[llvm] [AArch64][GlobalISel] Improve lowering of vector fp16 fptrunc (PR #163398)

[David Green via llvm-commits]

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@@ -2416,3 +2430,81 @@ bool AArch64LegalizerInfo::legalizePrefetch(MachineInstr &MI,
   MI.eraseFromParent();
   return true;
 }
+
+bool AArch64LegalizerInfo::legalizeFptrunc(MachineInstr &MI,
+                                           MachineIRBuilder &MIRBuilder,
+                                           MachineRegisterInfo &MRI) const {
+  auto [Dst, DstTy, Src, SrcTy] = MI.getFirst2RegLLTs();
+  assert(SrcTy.isFixedVector() && isPowerOf2_32(SrcTy.getNumElements()) &&
+         "Expected a power of 2 elements");
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davemgreen wrote:

No thats fine, we need to go through all of them I think.

https://github.com/llvm/llvm-project/pull/163398