[llvm] [Mips] Guard emission of CFI instructions by `MF.needsFrameMoves()` (PR #136108)

[Sergei Barannikov via llvm-commits]

================
@@ -20,7 +20,7 @@ entry:
 ; FIXME: We ought to be able to transform not+bnez -> beqz
 ; GPR:           not      $[[GPRCC]], $[[GPRCC]]
 ; 32-GPR:        bnez     $[[GPRCC]], $BB0_2
-; 64-GPR:        bnezc    $[[GPRCC]], .LBB0_2
+; 64-GPR:        bnez     $[[GPRCC]], .LBB0_2
----------------
s-barannikov wrote:

It appears it is the same delay slot filler optimization kicking in. The test doesn't show it, but the `bnez` instruction now has a store instruction in the delay slot. Before this patch, there was no delay slot candidate and the branch was transformed to the compact variant `bnezc` as explained in this comment:

```
    // For microMIPS if instruction is BEQ or BNE with one ZERO register, then
    // instead of adding NOP replace this instruction with the corresponding
    // compact branch instruction, i.e. BEQZC or BNEZC. Additionally
    // PseudoReturn and PseudoIndirectBranch are expanded to JR_MM, so they can
    // be replaced with JRC16_MM.

    // For MIPSR6 attempt to produce the corresponding compact (no delay slot)
    // form of the CTI. For indirect jumps this will not require inserting a
    // NOP and for branches will hopefully avoid requiring a NOP.
```


https://github.com/llvm/llvm-project/pull/136108