[llvm] [RISCV] LMUL lists for indexed and strided loads (PR #169756)

[Petr Penzin via llvm-commits]

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@@ -582,10 +582,8 @@ multiclass SiFive7WriteResBase<int VLEN,
       defm : LMULWriteResMX<"WriteVSTOX8", [VCQ, VS], mx, IsWorstCase>;
     }
   }
-  // TODO: The MxLists need to be filtered by EEW. We only need to support
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ppenzin wrote:

Maybe - I can probably revert that. If we try to implement this we would need to create a macro that takes EEW and returns a MxList, and this change doesn't quite get there.

https://github.com/llvm/llvm-project/pull/169756