[llvm] [AMDGPU] Add support for HW_REG_WAVE_SCHED_MODE (PR #169840)

[via llvm-commits]

https://github.com/lancesix updated https://github.com/llvm/llvm-project/pull/169840

>From 7859ef2da0853b16e1418ed1092c44e45ed4dd5c Mon Sep 17 00:00:00 2001
From: Lancelot SIX <lancelot.six at amd.com>
Date: Tue, 18 Nov 2025 21:15:17 +0000
Subject: [PATCH] [AMDGPU] Add support for HW_REG_WAVE_SCHED_MODE

Expose HW_REG_WAVE_SCHED_MODE to the s_getreg_b32, s_setreg_b32,
s_setreg_imm32_b32 instructions.
---
 llvm/lib/Target/AMDGPU/SIDefines.h                   | 1 +
 llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp      | 1 +
 llvm/test/MC/AMDGPU/gfx12_asm_sopk.s                 | 9 +++++++++
 llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopk.txt | 9 +++++++++
 4 files changed, 20 insertions(+)

diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h
index b7a92a0a1d634..192e1a0d7a812 100644
--- a/llvm/lib/Target/AMDGPU/SIDefines.h
+++ b/llvm/lib/Target/AMDGPU/SIDefines.h
@@ -541,6 +541,7 @@ enum Id { // HwRegCode, (6) [5:0]
   ID_EXCP_FLAG_PRIV = 17,
   ID_EXCP_FLAG_USER = 18,
   ID_TRAP_CTRL = 19,
+  ID_SCHED_MODE = 26,
 
   // GFX94* specific registers
   ID_XCC_ID = 20,
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
index 6489e63d4f6b8..24d139b73d2b1 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
@@ -208,6 +208,7 @@ static constexpr CustomOperand Operands[] = {
   {{"HW_REG_HW_ID"},                  ID_HW_ID1,                      isGFX10},
   {{"HW_REG_SQ_PERF_SNAPSHOT_PC_LO"}, ID_SQ_PERF_SNAPSHOT_PC_LO,      isGFX940},
   {{"HW_REG_WAVE_HW_ID2"},            ID_HW_ID2,                      isGFX12Plus},
+  {{"HW_REG_WAVE_SCHED_MODE"},        ID_SCHED_MODE,                  isGFX12Plus},
   {{"HW_REG_HW_ID2"},                 ID_HW_ID2,                      isGFX10Plus},
   {{"HW_REG_SQ_PERF_SNAPSHOT_PC_HI"}, ID_SQ_PERF_SNAPSHOT_PC_HI,      isGFX940},
   {{"HW_REG_POPS_PACKER"},            ID_POPS_PACKER,                 isGFX10},
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_sopk.s b/llvm/test/MC/AMDGPU/gfx12_asm_sopk.s
index 819ecb866c5ae..ba5159482df50 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_sopk.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_sopk.s
@@ -258,3 +258,12 @@ s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES_LO)
 
 s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES_HI)
 // GFX12: encoding: [0x1e,0xf8,0x80,0xb8]
+
+s_getreg_b32 s0, hwreg(HW_REG_WAVE_SCHED_MODE)
+// GFX12: encoding: [0x1a,0xf8,0x80,0xb8]
+
+s_setreg_b32 hwreg(HW_REG_WAVE_SCHED_MODE, 0, 2), s2
+// GFX12: encoding: [0x1a,0x08,0x02,0xb9]
+
+s_setreg_imm32_b32 hwreg(HW_REG_WAVE_SCHED_MODE), 0x2
+// GFX12: encoding: [0x1a,0xf8,0x80,0xb9,0x02,0x00,0x00,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopk.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopk.txt
index 41c5724a596f9..63ad07acee36f 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopk.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopk.txt
@@ -276,3 +276,12 @@
 
 # GFX12: s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES_HI) ; encoding: [0x1e,0xf8,0x80,0xb8]
 0x1e,0xf8,0x80,0xb8
+
+# GFX12: s_getreg_b32 s0, hwreg(HW_REG_WAVE_SCHED_MODE) ; encoding: [0x1a,0xf8,0x80,0xb8]
+0x1a,0xf8,0x80,0xb8
+
+# GFX12: s_setreg_b32 hwreg(HW_REG_WAVE_SCHED_MODE, 0, 2), s2 ; encoding: [0x1a,0x08,0x02,0xb9]
+0x1a,0x08,0x02,0xb9
+
+# GFX12: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_SCHED_MODE), 2 ; encoding: [0x1a,0xf8,0x80,0xb9,0x02,0x00,0x00,0x00]
+0x1a,0xf8,0x80,0xb9,0x02,0x00,0x00,0x00