[llvm] [AArch64]Enabled aggressive interleaving for A320 (PR #169825)

[Nashe Mncube via llvm-commits]

https://github.com/nasherm updated https://github.com/llvm/llvm-project/pull/169825

>From 7ca40572a3c10fcdb27160812ff3219642b4a9a5 Mon Sep 17 00:00:00 2001
From: nasmnc01 <nashe.mncube at arm.com>
Date: Thu, 27 Nov 2025 15:50:15 +0000
Subject: [PATCH 1/2] [AArch64]Enabled aggressive interleaving for A320

This patch makes use of aggressive interleaving options
for the A320 subtarget. This is done by adding a new local
parameter to the AArch64Subtarget class. With this flag
enabled we see an aggregate uplift of 0.7% on internal benchmark suites
with up to 51% uplift on individual benchmark workloads.

Change-Id: I53367df0aef299e0d02ce9150a105f12fa575b9d
---
 llvm/lib/Target/AArch64/AArch64Subtarget.cpp         | 6 ++++++
 llvm/lib/Target/AArch64/AArch64Subtarget.h           | 4 ++++
 llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h | 2 ++
 3 files changed, 12 insertions(+)

diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
index 53b00e83a36b3..8a43d0dc1652c 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -175,6 +175,12 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) {
     MaxBytesForLoopAlignment = 16;
     break;
   case CortexA320:
+    AggressiveInterleaving = true;
+    PrefFunctionAlignment = Align(16);
+    VScaleForTuning = 1;
+    PrefLoopAlignment = Align(16);
+    MaxBytesForLoopAlignment = 8;
+    break;
   case CortexA510:
   case CortexA520:
     PrefFunctionAlignment = Align(16);
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index 8974965c41fe3..53a497250b4f7 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -93,6 +93,8 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
 
   bool EnableSubregLiveness;
 
+  bool AggressiveInterleaving = false;
+
   /// TargetTriple - What processor and OS we're targeting.
   Triple TargetTriple;
 
@@ -469,6 +471,8 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
   /// a function.
   std::optional<uint16_t>
   getPtrAuthBlockAddressDiscriminatorIfEnabled(const Function &ParentFn) const;
+
+  bool enableAggressiveInterleaving() const { return AggressiveInterleaving; }
 };
 } // End llvm namespace
 
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
index 6cc4987428567..18521bb236d37 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
@@ -517,6 +517,8 @@ class AArch64TTIImpl final : public BasicTTIImplBase<AArch64TTIImpl> {
 
   bool isProfitableToSinkOperands(Instruction *I,
                                   SmallVectorImpl<Use *> &Ops) const override;
+
+  bool enableAggressiveInterleaving(bool) const override { return ST->enableAggressiveInterleaving(); }
   /// @}
 };
 

>From faefd59cc32796788e20f30986e72b1a6aeb2f53 Mon Sep 17 00:00:00 2001
From: nasmnc01 <nashe.mncube at arm.com>
Date: Thu, 27 Nov 2025 17:00:13 +0000
Subject: [PATCH 2/2] Code formatting

Change-Id: I6de3eec3da77cf211b060ed9541f1caee7fe0606
---
 llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
index 18521bb236d37..bfdb9fcf7d65d 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
@@ -518,7 +518,9 @@ class AArch64TTIImpl final : public BasicTTIImplBase<AArch64TTIImpl> {
   bool isProfitableToSinkOperands(Instruction *I,
                                   SmallVectorImpl<Use *> &Ops) const override;
 
-  bool enableAggressiveInterleaving(bool) const override { return ST->enableAggressiveInterleaving(); }
+  bool enableAggressiveInterleaving(bool) const override { 
+    return ST->enableAggressiveInterleaving(); 
+  }
   /// @}
 };