[llvm] [AArch64] Guard for 128bit vectors in mull combine. (PR #169839)

[Nathan Corbyn via llvm-commits]

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@@ -5795,8 +5795,10 @@ SDValue AArch64TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
   if (VT.is64BitVector()) {
     if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
         isNullConstant(N0.getOperand(1)) &&
+        N0.getOperand(0).getValueType().is128BitVector() &&
         N1.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
-        isNullConstant(N1.getOperand(1))) {
+        isNullConstant(N1.getOperand(1)) &&
+        N1.getOperand(0).getValueType().is128BitVector()) {
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cofibrant wrote:

Ahah--makes sense!

https://github.com/llvm/llvm-project/pull/169839