[llvm] [AArch64]Enabled aggressive interleaving for A320 (PR #169825)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-aarch64

Author: Nashe Mncube (nasherm)

<details>
<summary>Changes</summary>

This patch makes use of aggressive interleaving options for the A320 subtarget. This is done by adding a new local parameter to the AArch64Subtarget class. With this flag enabled we see an aggregate uplift of 0.7% on internal benchmark suites with up to 51% uplift on individual benchmark workloads.

---
Full diff: https://github.com/llvm/llvm-project/pull/169825.diff


3 Files Affected:

- (modified) llvm/lib/Target/AArch64/AArch64Subtarget.cpp (+6) 
- (modified) llvm/lib/Target/AArch64/AArch64Subtarget.h (+4) 
- (modified) llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h (+2) 


``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
index 53b00e83a36b3..8a43d0dc1652c 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -175,6 +175,12 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) {
     MaxBytesForLoopAlignment = 16;
     break;
   case CortexA320:
+    AggressiveInterleaving = true;
+    PrefFunctionAlignment = Align(16);
+    VScaleForTuning = 1;
+    PrefLoopAlignment = Align(16);
+    MaxBytesForLoopAlignment = 8;
+    break;
   case CortexA510:
   case CortexA520:
     PrefFunctionAlignment = Align(16);
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index 8974965c41fe3..53a497250b4f7 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -93,6 +93,8 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
 
   bool EnableSubregLiveness;
 
+  bool AggressiveInterleaving = false;
+
   /// TargetTriple - What processor and OS we're targeting.
   Triple TargetTriple;
 
@@ -469,6 +471,8 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
   /// a function.
   std::optional<uint16_t>
   getPtrAuthBlockAddressDiscriminatorIfEnabled(const Function &ParentFn) const;
+
+  bool enableAggressiveInterleaving() const { return AggressiveInterleaving; }
 };
 } // End llvm namespace
 
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
index 6cc4987428567..18521bb236d37 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
@@ -517,6 +517,8 @@ class AArch64TTIImpl final : public BasicTTIImplBase<AArch64TTIImpl> {
 
   bool isProfitableToSinkOperands(Instruction *I,
                                   SmallVectorImpl<Use *> &Ops) const override;
+
+  bool enableAggressiveInterleaving(bool) const override { return ST->enableAggressiveInterleaving(); }
   /// @}
 };
 

``````````

</details>


https://github.com/llvm/llvm-project/pull/169825