[llvm] [AArch64][GlobalISel] Improve lowering of vector fp16 fptrunc (PR #163398)

[David Green via llvm-commits]

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@@ -1464,6 +1474,10 @@ bool AArch64LegalizerInfo::legalizeCustom(
     return legalizeICMP(MI, MRI, MIRBuilder);
   case TargetOpcode::G_BITCAST:
     return legalizeBitcast(MI, Helper);
+  case TargetOpcode::G_FPTRUNC:
+    // In order to vectorise f16 to f64 properly, we need to use f32 as an
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davemgreen wrote:

vectorize -> lower?

https://github.com/llvm/llvm-project/pull/163398