[llvm] [AMDGPU] Verify dominance when rewriting spills to registers (PR #167347)

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ruiling wrote:

>just that all spills together jointly dominate it. But maybe that's a harder condition to check.

This can also be not true in case of register spill/reload. For SSA value, the def should dominates uses. But for memory store/load, there may be no dominance property. In this particular case. The register is spilled, so the stores does not jointly dominate loads anymore because there is `poison` incoming value in SSA form. Yes, aborting for such case is a solution. A better approach is to Insert `NewReg = IMPLICIT_DEF` at proper place, so we still benefit from not spill/reload the register. Now that we have `LiveStacks`, we can check the starting point of each segment, if there is no spill instruction, just insert an implicit_def there. But as the `LiveStacks` is conservatively correct, which means that the real spill instruction may appear a few instructions later. So we might need to scan forward a little bit from starting point of each live segment to do the check (maybe four instructions? I think it should be enough).

https://github.com/llvm/llvm-project/pull/167347