[llvm] [DAGCombiner, NVPTX] Port 'rem' custom combine from NVPTX to generic combiner (PR #167147)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 867f30985..899ae1453 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -900,40 +900,43 @@ namespace {
                          ISD::NodeType ExtType);
   };
 
-/// Generic remainder optimization : Folds a remainder operation (A % B) by reusing the computed quotient (A / B).
-static SDValue PerformREMCombineGeneric(SDNode *N, DAGCombiner &DC,
-                                        CodeGenOptLevel OptLevel) {
-  assert(N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM);
+  /// Generic remainder optimization : Folds a remainder operation (A % B) by
+  /// reusing the computed quotient (A / B).
+  static SDValue PerformREMCombineGeneric(SDNode *N, DAGCombiner &DC,
+                                          CodeGenOptLevel OptLevel) {
+    assert(N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM);
+
+    // Don't do anything at less than -O2.
+    if (OptLevel < CodeGenOptLevel::Default)
+      return SDValue();
 
-  // Don't do anything at less than -O2.
-  if (OptLevel < CodeGenOptLevel::Default)
-    return SDValue();
+    SelectionDAG &DAG = DC.getDAG();
+    SDLoc DL(N);
+    EVT VT = N->getValueType(0);
+    bool IsSigned = N->getOpcode() == ISD::SREM;
+    unsigned DivOpc = IsSigned ? ISD::SDIV : ISD::UDIV;
 
-  SelectionDAG &DAG = DC.getDAG();
-  SDLoc DL(N);
-  EVT VT = N->getValueType(0);
-  bool IsSigned = N->getOpcode() == ISD::SREM;
-  unsigned DivOpc = IsSigned ? ISD::SDIV : ISD::UDIV;
+    const SDValue &Num = N->getOperand(0);
+    const SDValue &Den = N->getOperand(1);
 
-  const SDValue &Num = N->getOperand(0);
-  const SDValue &Den = N->getOperand(1);
-  
-  AttributeList Attr = DC.getDAG().getMachineFunction().getFunction().getAttributes();
-  if (DC.getDAG().getTargetLoweringInfo().isIntDivCheap(N->getValueType(0), Attr))
-    return SDValue();
+    AttributeList Attr =
+        DC.getDAG().getMachineFunction().getFunction().getAttributes();
+    if (DC.getDAG().getTargetLoweringInfo().isIntDivCheap(N->getValueType(0),
+                                                          Attr))
+      return SDValue();
 
-  for (const SDNode *U : Num->users()) {
-    if (U->getOpcode() == DivOpc && U->getOperand(0) == Num &&
-        U->getOperand(1) == Den) {
-      // Num % Den -> Num - (Num / Den) * Den
-      return DAG.getNode(ISD::SUB, DL, VT, Num,
-                         DAG.getNode(ISD::MUL, DL, VT,
-                                     DAG.getNode(DivOpc, DL, VT, Num, Den),
-                                     Den));
+    for (const SDNode *U : Num->users()) {
+      if (U->getOpcode() == DivOpc && U->getOperand(0) == Num &&
+          U->getOperand(1) == Den) {
+        // Num % Den -> Num - (Num / Den) * Den
+        return DAG.getNode(ISD::SUB, DL, VT, Num,
+                           DAG.getNode(ISD::MUL, DL, VT,
+                                       DAG.getNode(DivOpc, DL, VT, Num, Den),
+                                       Den));
+      }
     }
+    return SDValue();
   }
-  return SDValue();
-}
 
 /// This class is a DAGUpdateListener that removes any deleted
 /// nodes from the worklist.
@@ -5437,7 +5440,7 @@ SDValue DAGCombiner::visitREM(SDNode *N) {
 
   if (SDValue V = PerformREMCombineGeneric(N, *this, OptLevel))
     return V;
-  
+
   if (isSigned) {
     // If we know the sign bits of both operands are zero, strength reduce to a
     // urem instead.  Handles (X & 0x0FFFFFFF) %s 16 -> X&15

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https://github.com/llvm/llvm-project/pull/167147