[llvm] 8401a8d - [NFC][LLVM] Add bitcode tests for llvm.aarch64.sve.rev

[Paul Walker via llvm-commits]

Author: Paul Walker
Date: 2025-11-27T10:42:29Z
New Revision: 8401a8d0be7671fb5089f850a34dc92ad4a2eb12

URL: https://github.com/llvm/llvm-project/commit/8401a8d0be7671fb5089f850a34dc92ad4a2eb12
DIFF: https://github.com/llvm/llvm-project/commit/8401a8d0be7671fb5089f850a34dc92ad4a2eb12.diff

LOG: [NFC][LLVM] Add bitcode tests for llvm.aarch64.sve.rev

Added: 
    llvm/test/Bitcode/aarch64-sve-rev-upgrade.ll
    llvm/test/Bitcode/aarch64-sve-rev-upgrade.ll.bc

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Bitcode/aarch64-sve-rev-upgrade.ll b/llvm/test/Bitcode/aarch64-sve-rev-upgrade.ll
new file mode 100644
index 0000000000000..6c7594f5d76b2
--- /dev/null
+++ b/llvm/test/Bitcode/aarch64-sve-rev-upgrade.ll
@@ -0,0 +1,111 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S < %s | FileCheck %s
+; RUN: llvm-dis < %s.bc | FileCheck %s
+
+define <vscale x 16 x i1> @rev_nxv16i1(<vscale x 16 x i1> %a) {
+; CHECK-LABEL: @rev_nxv16i1(
+; CHECK-NEXT:    [[RES:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.rev.nxv16i1(<vscale x 16 x i1> [[A:%.*]])
+; CHECK-NEXT:    ret <vscale x 16 x i1> [[RES]]
+;
+  %res = call <vscale x 16 x i1> @llvm.aarch64.sve.rev.nxv16i1(<vscale x 16 x i1> %a)
+  ret <vscale x 16 x i1> %res
+}
+
+define <vscale x 8 x i1> @rev_nxv8i1(<vscale x 8 x i1> %a) {
+; CHECK-LABEL: @rev_nxv8i1(
+; CHECK-NEXT:    [[RES:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.rev.nxv8i1(<vscale x 8 x i1> [[A:%.*]])
+; CHECK-NEXT:    ret <vscale x 8 x i1> [[RES]]
+;
+  %res = call <vscale x 8 x i1> @llvm.aarch64.sve.rev.nxv8i1(<vscale x 8 x i1> %a)
+  ret <vscale x 8 x i1> %res
+}
+
+define <vscale x 4 x i1> @rev_nxv4i1(<vscale x 4 x i1> %a) {
+; CHECK-LABEL: @rev_nxv4i1(
+; CHECK-NEXT:    [[RES:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.rev.nxv4i1(<vscale x 4 x i1> [[A:%.*]])
+; CHECK-NEXT:    ret <vscale x 4 x i1> [[RES]]
+;
+  %res = call <vscale x 4 x i1> @llvm.aarch64.sve.rev.nxv4i1(<vscale x 4 x i1> %a)
+  ret <vscale x 4 x i1> %res
+}
+
+define <vscale x 2 x i1> @rev_nxv2i1(<vscale x 2 x i1> %a) {
+; CHECK-LABEL: @rev_nxv2i1(
+; CHECK-NEXT:    [[RES:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.rev.nxv2i1(<vscale x 2 x i1> [[A:%.*]])
+; CHECK-NEXT:    ret <vscale x 2 x i1> [[RES]]
+;
+  %res = call <vscale x 2 x i1> @llvm.aarch64.sve.rev.nxv2i1(<vscale x 2 x i1> %a)
+  ret <vscale x 2 x i1> %res
+}
+
+define <vscale x 16 x i8> @rev_i8(<vscale x 16 x i8> %a) {
+; CHECK-LABEL: @rev_i8(
+; CHECK-NEXT:    [[RES:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.rev.nxv16i8(<vscale x 16 x i8> [[A:%.*]])
+; CHECK-NEXT:    ret <vscale x 16 x i8> [[RES]]
+;
+  %res = call <vscale x 16 x i8> @llvm.aarch64.sve.rev.nxv16i8(<vscale x 16 x i8> %a)
+  ret <vscale x 16 x i8> %res
+}
+
+define <vscale x 8 x i16> @rev_i16(<vscale x 8 x i16> %a) {
+; CHECK-LABEL: @rev_i16(
+; CHECK-NEXT:    [[RES:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.rev.nxv8i16(<vscale x 8 x i16> [[A:%.*]])
+; CHECK-NEXT:    ret <vscale x 8 x i16> [[RES]]
+;
+  %res = call <vscale x 8 x i16> @llvm.aarch64.sve.rev.nxv8i16(<vscale x 8 x i16> %a)
+  ret <vscale x 8 x i16> %res
+}
+
+define <vscale x 4 x i32> @rev_i32(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: @rev_i32(
+; CHECK-NEXT:    [[RES:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.rev.nxv4i32(<vscale x 4 x i32> [[A:%.*]])
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[RES]]
+;
+  %res = call <vscale x 4 x i32> @llvm.aarch64.sve.rev.nxv4i32(<vscale x 4 x i32> %a)
+  ret <vscale x 4 x i32> %res
+}
+
+define <vscale x 2 x i64> @rev_i64(<vscale x 2 x i64> %a) {
+; CHECK-LABEL: @rev_i64(
+; CHECK-NEXT:    [[RES:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.rev.nxv2i64(<vscale x 2 x i64> [[A:%.*]])
+; CHECK-NEXT:    ret <vscale x 2 x i64> [[RES]]
+;
+  %res = call <vscale x 2 x i64> @llvm.aarch64.sve.rev.nxv2i64(<vscale x 2 x i64> %a)
+  ret <vscale x 2 x i64> %res
+}
+
+define <vscale x 8 x half> @rev_f16(<vscale x 8 x half> %a) {
+; CHECK-LABEL: @rev_f16(
+; CHECK-NEXT:    [[RES:%.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.rev.nxv8f16(<vscale x 8 x half> [[A:%.*]])
+; CHECK-NEXT:    ret <vscale x 8 x half> [[RES]]
+;
+  %res = call <vscale x 8 x half> @llvm.aarch64.sve.rev.nxv8f16(<vscale x 8 x half> %a)
+  ret <vscale x 8 x half> %res
+}
+
+define <vscale x 4 x float> @rev_f32(<vscale x 4 x float> %a) {
+; CHECK-LABEL: @rev_f32(
+; CHECK-NEXT:    [[RES:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.rev.nxv4f32(<vscale x 4 x float> [[A:%.*]])
+; CHECK-NEXT:    ret <vscale x 4 x float> [[RES]]
+;
+  %res = call <vscale x 4 x float> @llvm.aarch64.sve.rev.nxv4f32(<vscale x 4 x float> %a)
+  ret <vscale x 4 x float> %res
+}
+
+define <vscale x 2 x double> @rev_f64(<vscale x 2 x double> %a) {
+; CHECK-LABEL: @rev_f64(
+; CHECK-NEXT:    [[RES:%.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.rev.nxv2f64(<vscale x 2 x double> [[A:%.*]])
+; CHECK-NEXT:    ret <vscale x 2 x double> [[RES]]
+;
+  %res = call <vscale x 2 x double> @llvm.aarch64.sve.rev.nxv2f64(<vscale x 2 x double> %a)
+  ret <vscale x 2 x double> %res
+}
+
+define <vscale x 8 x bfloat> @rev_bf16(<vscale x 8 x bfloat> %a) #0 {
+; CHECK-LABEL: @rev_bf16(
+; CHECK-NEXT:    [[RES:%.*]] = call <vscale x 8 x bfloat> @llvm.aarch64.sve.rev.nxv8bf16(<vscale x 8 x bfloat> [[A:%.*]])
+; CHECK-NEXT:    ret <vscale x 8 x bfloat> [[RES]]
+;
+  %res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.rev.nxv8bf16(<vscale x 8 x bfloat> %a)
+  ret <vscale x 8 x bfloat> %res
+}

diff  --git a/llvm/test/Bitcode/aarch64-sve-rev-upgrade.ll.bc b/llvm/test/Bitcode/aarch64-sve-rev-upgrade.ll.bc
new file mode 100644
index 0000000000000..fb8ba00e8039a
Binary files /dev/null and b/llvm/test/Bitcode/aarch64-sve-rev-upgrade.ll.bc 
diff er