[llvm] optimize `is_finite` assembly (PR #169402)
Folkert de Vries via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 27 01:44:33 PST 2025
https://github.com/folkertdev updated https://github.com/llvm/llvm-project/pull/169402
>From 66c7ffba0c01a61bc605bf18192496d91fd2dc93 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert at folkertdev.nl>
Date: Mon, 24 Nov 2025 21:06:52 +0100
Subject: [PATCH] optimize `is_finite` on floating points
---
.../CodeGen/SelectionDAG/TargetLowering.cpp | 11 +-
llvm/test/CodeGen/AArch64/is_fpclass.ll | 828 ++++++++++++++++++
llvm/test/CodeGen/AMDGPU/fp-classify.ll | 5 +-
.../CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll | 93 +-
.../CodeGen/AMDGPU/llvm.is.fpclass.f16.ll | 21 +-
.../CodeGen/AMDGPU/r600.llvm.is.fpclass.ll | 328 ++++---
llvm/test/CodeGen/PowerPC/fp-classify.ll | 34 +-
llvm/test/CodeGen/RISCV/float-intrinsics.ll | 24 +-
llvm/test/CodeGen/X86/is_fpclass.ll | 232 ++---
llvm/test/CodeGen/X86/isel-fpclass.ll | 44 +-
10 files changed, 1220 insertions(+), 400 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/is_fpclass.ll
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 920dff935daed..635ecbcf6e366 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -9122,8 +9122,15 @@ SDValue TargetLowering::expandIS_FPCLASS(EVT ResultVT, SDValue Op,
; // Detect finite numbers of f80 by checking individual classes because
// they have different settings of the explicit integer bit.
else if ((Test & fcFinite) == fcFinite) {
- // finite(V) ==> abs(V) < exp_mask
- PartialRes = DAG.getSetCC(DL, ResultVT, AbsV, ExpMaskV, ISD::SETLT);
+ // finite(V) ==> (a << 1) < (inf << 1)
+ //
+ // See https://github.com/llvm/llvm-project/issues/169270, this is slightly
+ // shorter than the `finite(V) ==> abs(V) < exp_mask` formula used before.
+ SDValue One = DAG.getShiftAmountConstant(1, IntVT, DL);
+ SDValue TwiceOp = DAG.getNode(ISD::SHL, DL, IntVT, OpAsInt, One);
+ SDValue TwiceInf = DAG.getNode(ISD::SHL, DL, IntVT, ExpMaskV, One);
+
+ PartialRes = DAG.getSetCC(DL, ResultVT, TwiceOp, TwiceInf, ISD::SETULT);
Test &= ~fcFinite;
} else if ((Test & fcFinite) == fcPosFinite) {
// finite(V) && V > 0 ==> V < exp_mask
diff --git a/llvm/test/CodeGen/AArch64/is_fpclass.ll b/llvm/test/CodeGen/AArch64/is_fpclass.ll
new file mode 100644
index 0000000000000..0c3fc9c7a1e53
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/is_fpclass.ll
@@ -0,0 +1,828 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -mtriple=aarch64 -global-isel=0 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+; RUN: llc -mtriple=armv6m-none-eabi -global-isel=0 < %s | FileCheck %s --check-prefixes=CHECK-SOFTFLOAT
+
+
+define i1 @isfinite_h(half %x) {
+; CHECK-LABEL: isfinite_h:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0
+; CHECK-NEXT: fmov w8, s0
+; CHECK-NEXT: ubfx w8, w8, #10, #5
+; CHECK-NEXT: cmp w8, #31
+; CHECK-NEXT: cset w0, lo
+; CHECK-NEXT: ret
+;
+; CHECK-SOFTFLOAT-LABEL: isfinite_h:
+; CHECK-SOFTFLOAT: @ %bb.0: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsls r0, r0, #17
+; CHECK-SOFTFLOAT-NEXT: lsrs r0, r0, #27
+; CHECK-SOFTFLOAT-NEXT: cmp r0, #31
+; CHECK-SOFTFLOAT-NEXT: blo .LBB0_2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.1: @ %entry
+; CHECK-SOFTFLOAT-NEXT: movs r0, #0
+; CHECK-SOFTFLOAT-NEXT: bx lr
+; CHECK-SOFTFLOAT-NEXT: .LBB0_2:
+; CHECK-SOFTFLOAT-NEXT: movs r0, #1
+; CHECK-SOFTFLOAT-NEXT: bx lr
+entry:
+ %0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 504) ; 0x1f8 = "finite"
+ ret i1 %0
+}
+
+define i1 @not_isfinite_h(half %x) {
+; CHECK-LABEL: not_isfinite_h:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0
+; CHECK-NEXT: fmov w8, s0
+; CHECK-NEXT: ubfx w8, w8, #10, #5
+; CHECK-NEXT: cmp w8, #30
+; CHECK-NEXT: cset w0, hi
+; CHECK-NEXT: ret
+;
+; CHECK-SOFTFLOAT-LABEL: not_isfinite_h:
+; CHECK-SOFTFLOAT: @ %bb.0: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsls r0, r0, #17
+; CHECK-SOFTFLOAT-NEXT: lsrs r0, r0, #27
+; CHECK-SOFTFLOAT-NEXT: cmp r0, #30
+; CHECK-SOFTFLOAT-NEXT: bhi .LBB1_2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.1: @ %entry
+; CHECK-SOFTFLOAT-NEXT: movs r0, #0
+; CHECK-SOFTFLOAT-NEXT: bx lr
+; CHECK-SOFTFLOAT-NEXT: .LBB1_2:
+; CHECK-SOFTFLOAT-NEXT: movs r0, #1
+; CHECK-SOFTFLOAT-NEXT: bx lr
+entry:
+ %0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 519) ; ~0x1f8 = "~finite"
+ ret i1 %0
+}
+
+define i1 @isfinite_f(float %x) {
+; CHECK-LABEL: isfinite_f:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fmov w8, s0
+; CHECK-NEXT: ubfx w8, w8, #23, #8
+; CHECK-NEXT: cmp w8, #255
+; CHECK-NEXT: cset w0, lo
+; CHECK-NEXT: ret
+;
+; CHECK-SOFTFLOAT-LABEL: isfinite_f:
+; CHECK-SOFTFLOAT: @ %bb.0: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsls r0, r0, #1
+; CHECK-SOFTFLOAT-NEXT: lsrs r0, r0, #24
+; CHECK-SOFTFLOAT-NEXT: cmp r0, #255
+; CHECK-SOFTFLOAT-NEXT: blo .LBB2_2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.1: @ %entry
+; CHECK-SOFTFLOAT-NEXT: movs r0, #0
+; CHECK-SOFTFLOAT-NEXT: bx lr
+; CHECK-SOFTFLOAT-NEXT: .LBB2_2:
+; CHECK-SOFTFLOAT-NEXT: movs r0, #1
+; CHECK-SOFTFLOAT-NEXT: bx lr
+entry:
+ %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 504) ; 0x1f8 = "finite"
+ ret i1 %0
+}
+
+define i1 @not_isfinite_f(float %x) {
+; CHECK-LABEL: not_isfinite_f:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fmov w8, s0
+; CHECK-NEXT: ubfx w8, w8, #23, #8
+; CHECK-NEXT: cmp w8, #254
+; CHECK-NEXT: cset w0, hi
+; CHECK-NEXT: ret
+;
+; CHECK-SOFTFLOAT-LABEL: not_isfinite_f:
+; CHECK-SOFTFLOAT: @ %bb.0: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsls r0, r0, #1
+; CHECK-SOFTFLOAT-NEXT: lsrs r0, r0, #24
+; CHECK-SOFTFLOAT-NEXT: cmp r0, #254
+; CHECK-SOFTFLOAT-NEXT: bhi .LBB3_2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.1: @ %entry
+; CHECK-SOFTFLOAT-NEXT: movs r0, #0
+; CHECK-SOFTFLOAT-NEXT: bx lr
+; CHECK-SOFTFLOAT-NEXT: .LBB3_2:
+; CHECK-SOFTFLOAT-NEXT: movs r0, #1
+; CHECK-SOFTFLOAT-NEXT: bx lr
+entry:
+ %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 519) ; ~0x1f8 = "~finite"
+ ret i1 %0
+}
+
+
+define i1 @isfinite_f_strictfp(float %x) strictfp {
+; CHECK-LABEL: isfinite_f_strictfp:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fmov w8, s0
+; CHECK-NEXT: ubfx w8, w8, #23, #8
+; CHECK-NEXT: cmp w8, #255
+; CHECK-NEXT: cset w0, lo
+; CHECK-NEXT: ret
+;
+; CHECK-SOFTFLOAT-LABEL: isfinite_f_strictfp:
+; CHECK-SOFTFLOAT: @ %bb.0: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsls r0, r0, #1
+; CHECK-SOFTFLOAT-NEXT: lsrs r0, r0, #24
+; CHECK-SOFTFLOAT-NEXT: cmp r0, #255
+; CHECK-SOFTFLOAT-NEXT: blo .LBB4_2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.1: @ %entry
+; CHECK-SOFTFLOAT-NEXT: movs r0, #0
+; CHECK-SOFTFLOAT-NEXT: bx lr
+; CHECK-SOFTFLOAT-NEXT: .LBB4_2:
+; CHECK-SOFTFLOAT-NEXT: movs r0, #1
+; CHECK-SOFTFLOAT-NEXT: bx lr
+entry:
+ %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 504) strictfp ; 0x1f8 = "finite"
+ ret i1 %0
+}
+
+define i1 @not_isfinite_f_strictfp(float %x) strictfp {
+; CHECK-LABEL: not_isfinite_f_strictfp:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fmov w8, s0
+; CHECK-NEXT: ubfx w8, w8, #23, #8
+; CHECK-NEXT: cmp w8, #254
+; CHECK-NEXT: cset w0, hi
+; CHECK-NEXT: ret
+;
+; CHECK-SOFTFLOAT-LABEL: not_isfinite_f_strictfp:
+; CHECK-SOFTFLOAT: @ %bb.0: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsls r0, r0, #1
+; CHECK-SOFTFLOAT-NEXT: lsrs r0, r0, #24
+; CHECK-SOFTFLOAT-NEXT: cmp r0, #254
+; CHECK-SOFTFLOAT-NEXT: bhi .LBB5_2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.1: @ %entry
+; CHECK-SOFTFLOAT-NEXT: movs r0, #0
+; CHECK-SOFTFLOAT-NEXT: bx lr
+; CHECK-SOFTFLOAT-NEXT: .LBB5_2:
+; CHECK-SOFTFLOAT-NEXT: movs r0, #1
+; CHECK-SOFTFLOAT-NEXT: bx lr
+entry:
+ %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 519) strictfp ; ~0x1f8 = ~"finite"
+ ret i1 %0
+}
+
+
+define i1 @isfinite_d(double %x) {
+; CHECK-LABEL: isfinite_d:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fmov x8, d0
+; CHECK-NEXT: ubfx x8, x8, #52, #11
+; CHECK-NEXT: cmp x8, #2047
+; CHECK-NEXT: cset w0, lo
+; CHECK-NEXT: ret
+;
+; CHECK-SOFTFLOAT-LABEL: isfinite_d:
+; CHECK-SOFTFLOAT: @ %bb.0: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsrs r0, r0, #31
+; CHECK-SOFTFLOAT-NEXT: lsls r1, r1, #1
+; CHECK-SOFTFLOAT-NEXT: adds r0, r1, r0
+; CHECK-SOFTFLOAT-NEXT: ldr r1, .LCPI6_0
+; CHECK-SOFTFLOAT-NEXT: cmp r0, r1
+; CHECK-SOFTFLOAT-NEXT: blo .LBB6_2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.1: @ %entry
+; CHECK-SOFTFLOAT-NEXT: movs r0, #0
+; CHECK-SOFTFLOAT-NEXT: bx lr
+; CHECK-SOFTFLOAT-NEXT: .LBB6_2:
+; CHECK-SOFTFLOAT-NEXT: movs r0, #1
+; CHECK-SOFTFLOAT-NEXT: bx lr
+; CHECK-SOFTFLOAT-NEXT: .p2align 2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.3:
+; CHECK-SOFTFLOAT-NEXT: .LCPI6_0:
+; CHECK-SOFTFLOAT-NEXT: .long 4292870144 @ 0xffe00000
+entry:
+ %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 504) ; 0x1f8 = "finite"
+ ret i1 %0
+}
+
+define i1 @not_isfinite_d(double %x) {
+; CHECK-LABEL: not_isfinite_d:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fmov x8, d0
+; CHECK-NEXT: ubfx x8, x8, #52, #11
+; CHECK-NEXT: cmp x8, #2046
+; CHECK-NEXT: cset w0, hi
+; CHECK-NEXT: ret
+;
+; CHECK-SOFTFLOAT-LABEL: not_isfinite_d:
+; CHECK-SOFTFLOAT: @ %bb.0: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsrs r0, r0, #31
+; CHECK-SOFTFLOAT-NEXT: lsls r1, r1, #1
+; CHECK-SOFTFLOAT-NEXT: adds r0, r1, r0
+; CHECK-SOFTFLOAT-NEXT: ldr r1, .LCPI7_0
+; CHECK-SOFTFLOAT-NEXT: cmp r0, r1
+; CHECK-SOFTFLOAT-NEXT: bhi .LBB7_2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.1: @ %entry
+; CHECK-SOFTFLOAT-NEXT: movs r0, #0
+; CHECK-SOFTFLOAT-NEXT: bx lr
+; CHECK-SOFTFLOAT-NEXT: .LBB7_2:
+; CHECK-SOFTFLOAT-NEXT: movs r0, #1
+; CHECK-SOFTFLOAT-NEXT: bx lr
+; CHECK-SOFTFLOAT-NEXT: .p2align 2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.3:
+; CHECK-SOFTFLOAT-NEXT: .LCPI7_0:
+; CHECK-SOFTFLOAT-NEXT: .long 4292870143 @ 0xffdfffff
+entry:
+ %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 519) ; ~0x1f8 = "~finite"
+ ret i1 %0
+}
+
+define i1 @isfinite_d_strictfp(double %x) {
+; CHECK-LABEL: isfinite_d_strictfp:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fmov x8, d0
+; CHECK-NEXT: ubfx x8, x8, #52, #11
+; CHECK-NEXT: cmp x8, #2047
+; CHECK-NEXT: cset w0, lo
+; CHECK-NEXT: ret
+;
+; CHECK-SOFTFLOAT-LABEL: isfinite_d_strictfp:
+; CHECK-SOFTFLOAT: @ %bb.0: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsrs r0, r0, #31
+; CHECK-SOFTFLOAT-NEXT: lsls r1, r1, #1
+; CHECK-SOFTFLOAT-NEXT: adds r0, r1, r0
+; CHECK-SOFTFLOAT-NEXT: ldr r1, .LCPI8_0
+; CHECK-SOFTFLOAT-NEXT: cmp r0, r1
+; CHECK-SOFTFLOAT-NEXT: blo .LBB8_2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.1: @ %entry
+; CHECK-SOFTFLOAT-NEXT: movs r0, #0
+; CHECK-SOFTFLOAT-NEXT: bx lr
+; CHECK-SOFTFLOAT-NEXT: .LBB8_2:
+; CHECK-SOFTFLOAT-NEXT: movs r0, #1
+; CHECK-SOFTFLOAT-NEXT: bx lr
+; CHECK-SOFTFLOAT-NEXT: .p2align 2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.3:
+; CHECK-SOFTFLOAT-NEXT: .LCPI8_0:
+; CHECK-SOFTFLOAT-NEXT: .long 4292870144 @ 0xffe00000
+entry:
+ %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 504) strictfp ; 0x1f8 = "finite"
+ ret i1 %0
+}
+
+define i1 @not_isfinite_d_strictfp(double %x) {
+; CHECK-LABEL: not_isfinite_d_strictfp:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fmov x8, d0
+; CHECK-NEXT: ubfx x8, x8, #52, #11
+; CHECK-NEXT: cmp x8, #2046
+; CHECK-NEXT: cset w0, hi
+; CHECK-NEXT: ret
+;
+; CHECK-SOFTFLOAT-LABEL: not_isfinite_d_strictfp:
+; CHECK-SOFTFLOAT: @ %bb.0: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsrs r0, r0, #31
+; CHECK-SOFTFLOAT-NEXT: lsls r1, r1, #1
+; CHECK-SOFTFLOAT-NEXT: adds r0, r1, r0
+; CHECK-SOFTFLOAT-NEXT: ldr r1, .LCPI9_0
+; CHECK-SOFTFLOAT-NEXT: cmp r0, r1
+; CHECK-SOFTFLOAT-NEXT: bhi .LBB9_2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.1: @ %entry
+; CHECK-SOFTFLOAT-NEXT: movs r0, #0
+; CHECK-SOFTFLOAT-NEXT: bx lr
+; CHECK-SOFTFLOAT-NEXT: .LBB9_2:
+; CHECK-SOFTFLOAT-NEXT: movs r0, #1
+; CHECK-SOFTFLOAT-NEXT: bx lr
+; CHECK-SOFTFLOAT-NEXT: .p2align 2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.3:
+; CHECK-SOFTFLOAT-NEXT: .LCPI9_0:
+; CHECK-SOFTFLOAT-NEXT: .long 4292870143 @ 0xffdfffff
+entry:
+ %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 519) strictfp ; ~0x1f8 = "~finite"
+ ret i1 %0
+}
+
+define i1 @isfinite_bf16(bfloat %x) {
+; CHECK-LABEL: isfinite_bf16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0
+; CHECK-NEXT: fmov w8, s0
+; CHECK-NEXT: ubfx w8, w8, #7, #8
+; CHECK-NEXT: cmp w8, #255
+; CHECK-NEXT: cset w0, lo
+; CHECK-NEXT: ret
+;
+; CHECK-SOFTFLOAT-LABEL: isfinite_bf16:
+; CHECK-SOFTFLOAT: @ %bb.0: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsrs r0, r0, #7
+; CHECK-SOFTFLOAT-NEXT: uxtb r0, r0
+; CHECK-SOFTFLOAT-NEXT: cmp r0, #255
+; CHECK-SOFTFLOAT-NEXT: blo .LBB10_2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.1: @ %entry
+; CHECK-SOFTFLOAT-NEXT: movs r0, #0
+; CHECK-SOFTFLOAT-NEXT: bx lr
+; CHECK-SOFTFLOAT-NEXT: .LBB10_2:
+; CHECK-SOFTFLOAT-NEXT: movs r0, #1
+; CHECK-SOFTFLOAT-NEXT: bx lr
+entry:
+ %0 = tail call i1 @llvm.is.fpclass.bf16(bfloat %x, i32 504) ; 0x1f8 = "finite"
+ ret i1 %0
+}
+
+define i1 @not_isfinite_bf16(bfloat %x) {
+; CHECK-LABEL: not_isfinite_bf16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0
+; CHECK-NEXT: fmov w8, s0
+; CHECK-NEXT: ubfx w8, w8, #7, #8
+; CHECK-NEXT: cmp w8, #254
+; CHECK-NEXT: cset w0, hi
+; CHECK-NEXT: ret
+;
+; CHECK-SOFTFLOAT-LABEL: not_isfinite_bf16:
+; CHECK-SOFTFLOAT: @ %bb.0: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsrs r0, r0, #7
+; CHECK-SOFTFLOAT-NEXT: uxtb r0, r0
+; CHECK-SOFTFLOAT-NEXT: cmp r0, #254
+; CHECK-SOFTFLOAT-NEXT: bhi .LBB11_2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.1: @ %entry
+; CHECK-SOFTFLOAT-NEXT: movs r0, #0
+; CHECK-SOFTFLOAT-NEXT: bx lr
+; CHECK-SOFTFLOAT-NEXT: .LBB11_2:
+; CHECK-SOFTFLOAT-NEXT: movs r0, #1
+; CHECK-SOFTFLOAT-NEXT: bx lr
+entry:
+ %0 = tail call i1 @llvm.is.fpclass.bf16(bfloat %x, i32 519) ; ~0x1f8 = "~finite"
+ ret i1 %0
+}
+
+define i1 @isfinite_f128(fp128 %x) {
+; CHECK-LABEL: isfinite_f128:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: str q0, [sp, #-16]!
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: ldp x8, x9, [sp], #16
+; CHECK-NEXT: extr x8, x9, x8, #63
+; CHECK-NEXT: mov x9, #-562949953421312 // =0xfffe000000000000
+; CHECK-NEXT: cmp x8, x9
+; CHECK-NEXT: cset w0, lo
+; CHECK-NEXT: ret
+;
+; CHECK-SOFTFLOAT-LABEL: isfinite_f128:
+; CHECK-SOFTFLOAT: @ %bb.0: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsrs r0, r2, #31
+; CHECK-SOFTFLOAT-NEXT: lsls r1, r3, #1
+; CHECK-SOFTFLOAT-NEXT: adds r0, r1, r0
+; CHECK-SOFTFLOAT-NEXT: ldr r1, .LCPI12_0
+; CHECK-SOFTFLOAT-NEXT: cmp r0, r1
+; CHECK-SOFTFLOAT-NEXT: blo .LBB12_2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.1: @ %entry
+; CHECK-SOFTFLOAT-NEXT: movs r0, #0
+; CHECK-SOFTFLOAT-NEXT: bx lr
+; CHECK-SOFTFLOAT-NEXT: .LBB12_2:
+; CHECK-SOFTFLOAT-NEXT: movs r0, #1
+; CHECK-SOFTFLOAT-NEXT: bx lr
+; CHECK-SOFTFLOAT-NEXT: .p2align 2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.3:
+; CHECK-SOFTFLOAT-NEXT: .LCPI12_0:
+; CHECK-SOFTFLOAT-NEXT: .long 4294836224 @ 0xfffe0000
+entry:
+ %0 = tail call i1 @llvm.is.fpclass.f128(fp128 %x, i32 504) ; 0x1f8 = "finite"
+ ret i1 %0
+}
+
+define i1 @not_isfinite_f128(fp128 %x) {
+; CHECK-LABEL: not_isfinite_f128:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: str q0, [sp, #-16]!
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: ldp x8, x9, [sp], #16
+; CHECK-NEXT: extr x8, x9, x8, #63
+; CHECK-NEXT: mov x9, #-562949953421313 // =0xfffdffffffffffff
+; CHECK-NEXT: cmp x8, x9
+; CHECK-NEXT: cset w0, hi
+; CHECK-NEXT: ret
+;
+; CHECK-SOFTFLOAT-LABEL: not_isfinite_f128:
+; CHECK-SOFTFLOAT: @ %bb.0: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsrs r0, r2, #31
+; CHECK-SOFTFLOAT-NEXT: lsls r1, r3, #1
+; CHECK-SOFTFLOAT-NEXT: adds r0, r1, r0
+; CHECK-SOFTFLOAT-NEXT: ldr r1, .LCPI13_0
+; CHECK-SOFTFLOAT-NEXT: cmp r0, r1
+; CHECK-SOFTFLOAT-NEXT: bhi .LBB13_2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.1: @ %entry
+; CHECK-SOFTFLOAT-NEXT: movs r0, #0
+; CHECK-SOFTFLOAT-NEXT: bx lr
+; CHECK-SOFTFLOAT-NEXT: .LBB13_2:
+; CHECK-SOFTFLOAT-NEXT: movs r0, #1
+; CHECK-SOFTFLOAT-NEXT: bx lr
+; CHECK-SOFTFLOAT-NEXT: .p2align 2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.3:
+; CHECK-SOFTFLOAT-NEXT: .LCPI13_0:
+; CHECK-SOFTFLOAT-NEXT: .long 4294836223 @ 0xfffdffff
+entry:
+ %0 = tail call i1 @llvm.is.fpclass.f128(fp128 %x, i32 519) ; ~0x1f8 = "~finite"
+ ret i1 %0
+}
+
+define <4 x i1> @isfinite_v4h(<4 x half> %x) {
+; CHECK-LABEL: isfinite_v4h:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.4h, #248, lsl #8
+; CHECK-NEXT: add v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: cmhi v0.4h, v1.4h, v0.4h
+; CHECK-NEXT: ret
+;
+; CHECK-SOFTFLOAT-LABEL: isfinite_v4h:
+; CHECK-SOFTFLOAT: @ %bb.0: @ %entry
+; CHECK-SOFTFLOAT-NEXT: .save {r4, r5, r7, lr}
+; CHECK-SOFTFLOAT-NEXT: push {r4, r5, r7, lr}
+; CHECK-SOFTFLOAT-NEXT: mov r4, r3
+; CHECK-SOFTFLOAT-NEXT: lsls r0, r0, #17
+; CHECK-SOFTFLOAT-NEXT: lsrs r0, r0, #27
+; CHECK-SOFTFLOAT-NEXT: movs r3, #1
+; CHECK-SOFTFLOAT-NEXT: movs r5, #0
+; CHECK-SOFTFLOAT-NEXT: cmp r0, #31
+; CHECK-SOFTFLOAT-NEXT: mov r0, r3
+; CHECK-SOFTFLOAT-NEXT: blo .LBB14_2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.1: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r0, r5
+; CHECK-SOFTFLOAT-NEXT: .LBB14_2: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsls r1, r1, #17
+; CHECK-SOFTFLOAT-NEXT: lsrs r1, r1, #27
+; CHECK-SOFTFLOAT-NEXT: cmp r1, #31
+; CHECK-SOFTFLOAT-NEXT: mov r1, r3
+; CHECK-SOFTFLOAT-NEXT: blo .LBB14_4
+; CHECK-SOFTFLOAT-NEXT: @ %bb.3: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r1, r5
+; CHECK-SOFTFLOAT-NEXT: .LBB14_4: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsls r2, r2, #17
+; CHECK-SOFTFLOAT-NEXT: lsrs r2, r2, #27
+; CHECK-SOFTFLOAT-NEXT: cmp r2, #31
+; CHECK-SOFTFLOAT-NEXT: mov r2, r3
+; CHECK-SOFTFLOAT-NEXT: blo .LBB14_6
+; CHECK-SOFTFLOAT-NEXT: @ %bb.5: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r2, r5
+; CHECK-SOFTFLOAT-NEXT: .LBB14_6: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsls r4, r4, #17
+; CHECK-SOFTFLOAT-NEXT: lsrs r4, r4, #27
+; CHECK-SOFTFLOAT-NEXT: cmp r4, #31
+; CHECK-SOFTFLOAT-NEXT: blo .LBB14_8
+; CHECK-SOFTFLOAT-NEXT: @ %bb.7: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r3, r5
+; CHECK-SOFTFLOAT-NEXT: .LBB14_8: @ %entry
+; CHECK-SOFTFLOAT-NEXT: pop {r4, r5, r7, pc}
+entry:
+ %0 = tail call <4 x i1> @llvm.is.fpclass.v4f16(<4 x half> %x, i32 504) ; 0x1f8 = "finite"
+ ret <4 x i1> %0
+}
+
+define <4 x i1> @not_isfinite_v4h(<4 x half> %x) {
+; CHECK-LABEL: not_isfinite_v4h:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.4h, #248, lsl #8
+; CHECK-NEXT: add v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: cmhs v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: ret
+;
+; CHECK-SOFTFLOAT-LABEL: not_isfinite_v4h:
+; CHECK-SOFTFLOAT: @ %bb.0: @ %entry
+; CHECK-SOFTFLOAT-NEXT: .save {r4, r5, r7, lr}
+; CHECK-SOFTFLOAT-NEXT: push {r4, r5, r7, lr}
+; CHECK-SOFTFLOAT-NEXT: mov r4, r3
+; CHECK-SOFTFLOAT-NEXT: lsls r0, r0, #17
+; CHECK-SOFTFLOAT-NEXT: lsrs r0, r0, #27
+; CHECK-SOFTFLOAT-NEXT: movs r3, #1
+; CHECK-SOFTFLOAT-NEXT: movs r5, #0
+; CHECK-SOFTFLOAT-NEXT: cmp r0, #30
+; CHECK-SOFTFLOAT-NEXT: mov r0, r3
+; CHECK-SOFTFLOAT-NEXT: bhi .LBB15_2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.1: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r0, r5
+; CHECK-SOFTFLOAT-NEXT: .LBB15_2: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsls r1, r1, #17
+; CHECK-SOFTFLOAT-NEXT: lsrs r1, r1, #27
+; CHECK-SOFTFLOAT-NEXT: cmp r1, #30
+; CHECK-SOFTFLOAT-NEXT: mov r1, r3
+; CHECK-SOFTFLOAT-NEXT: bhi .LBB15_4
+; CHECK-SOFTFLOAT-NEXT: @ %bb.3: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r1, r5
+; CHECK-SOFTFLOAT-NEXT: .LBB15_4: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsls r2, r2, #17
+; CHECK-SOFTFLOAT-NEXT: lsrs r2, r2, #27
+; CHECK-SOFTFLOAT-NEXT: cmp r2, #30
+; CHECK-SOFTFLOAT-NEXT: mov r2, r3
+; CHECK-SOFTFLOAT-NEXT: bhi .LBB15_6
+; CHECK-SOFTFLOAT-NEXT: @ %bb.5: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r2, r5
+; CHECK-SOFTFLOAT-NEXT: .LBB15_6: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsls r4, r4, #17
+; CHECK-SOFTFLOAT-NEXT: lsrs r4, r4, #27
+; CHECK-SOFTFLOAT-NEXT: cmp r4, #30
+; CHECK-SOFTFLOAT-NEXT: bhi .LBB15_8
+; CHECK-SOFTFLOAT-NEXT: @ %bb.7: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r3, r5
+; CHECK-SOFTFLOAT-NEXT: .LBB15_8: @ %entry
+; CHECK-SOFTFLOAT-NEXT: pop {r4, r5, r7, pc}
+entry:
+ %0 = tail call <4 x i1> @llvm.is.fpclass.v4f16(<4 x half> %x, i32 519) ; ~0x1f8 = "~finite"
+ ret <4 x i1> %0
+}
+
+define <4 x i1> @isfinite_v4f(<4 x float> %x) {
+; CHECK-LABEL: isfinite_v4f:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mvni v1.4s, #127, msl #16
+; CHECK-NEXT: fabs v0.4s, v0.4s
+; CHECK-NEXT: fneg v1.4s, v1.4s
+; CHECK-NEXT: fcmgt v2.4s, v0.4s, v1.4s
+; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
+;
+; CHECK-SOFTFLOAT-LABEL: isfinite_v4f:
+; CHECK-SOFTFLOAT: @ %bb.0: @ %entry
+; CHECK-SOFTFLOAT-NEXT: .save {r4, r5, r7, lr}
+; CHECK-SOFTFLOAT-NEXT: push {r4, r5, r7, lr}
+; CHECK-SOFTFLOAT-NEXT: mov r4, r3
+; CHECK-SOFTFLOAT-NEXT: lsls r0, r0, #1
+; CHECK-SOFTFLOAT-NEXT: lsrs r0, r0, #24
+; CHECK-SOFTFLOAT-NEXT: movs r3, #1
+; CHECK-SOFTFLOAT-NEXT: movs r5, #0
+; CHECK-SOFTFLOAT-NEXT: cmp r0, #255
+; CHECK-SOFTFLOAT-NEXT: mov r0, r3
+; CHECK-SOFTFLOAT-NEXT: blo .LBB16_2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.1: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r0, r5
+; CHECK-SOFTFLOAT-NEXT: .LBB16_2: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsls r1, r1, #1
+; CHECK-SOFTFLOAT-NEXT: lsrs r1, r1, #24
+; CHECK-SOFTFLOAT-NEXT: cmp r1, #255
+; CHECK-SOFTFLOAT-NEXT: mov r1, r3
+; CHECK-SOFTFLOAT-NEXT: blo .LBB16_4
+; CHECK-SOFTFLOAT-NEXT: @ %bb.3: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r1, r5
+; CHECK-SOFTFLOAT-NEXT: .LBB16_4: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsls r2, r2, #1
+; CHECK-SOFTFLOAT-NEXT: lsrs r2, r2, #24
+; CHECK-SOFTFLOAT-NEXT: cmp r2, #255
+; CHECK-SOFTFLOAT-NEXT: mov r2, r3
+; CHECK-SOFTFLOAT-NEXT: blo .LBB16_6
+; CHECK-SOFTFLOAT-NEXT: @ %bb.5: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r2, r5
+; CHECK-SOFTFLOAT-NEXT: .LBB16_6: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsls r4, r4, #1
+; CHECK-SOFTFLOAT-NEXT: lsrs r4, r4, #24
+; CHECK-SOFTFLOAT-NEXT: cmp r4, #255
+; CHECK-SOFTFLOAT-NEXT: blo .LBB16_8
+; CHECK-SOFTFLOAT-NEXT: @ %bb.7: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r3, r5
+; CHECK-SOFTFLOAT-NEXT: .LBB16_8: @ %entry
+; CHECK-SOFTFLOAT-NEXT: pop {r4, r5, r7, pc}
+entry:
+ %0 = tail call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %x, i32 504) ; 0x1f8 = "finite"
+ ret <4 x i1> %0
+}
+
+define <4 x i1> @not_isfinite_v4f(<4 x float> %x) {
+; CHECK-LABEL: not_isfinite_v4f:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.2d, #0xff000000ff000000
+; CHECK-NEXT: add v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: cmhs v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
+;
+; CHECK-SOFTFLOAT-LABEL: not_isfinite_v4f:
+; CHECK-SOFTFLOAT: @ %bb.0: @ %entry
+; CHECK-SOFTFLOAT-NEXT: .save {r4, r5, r7, lr}
+; CHECK-SOFTFLOAT-NEXT: push {r4, r5, r7, lr}
+; CHECK-SOFTFLOAT-NEXT: mov r4, r3
+; CHECK-SOFTFLOAT-NEXT: lsls r0, r0, #1
+; CHECK-SOFTFLOAT-NEXT: lsrs r0, r0, #24
+; CHECK-SOFTFLOAT-NEXT: movs r3, #1
+; CHECK-SOFTFLOAT-NEXT: movs r5, #0
+; CHECK-SOFTFLOAT-NEXT: cmp r0, #254
+; CHECK-SOFTFLOAT-NEXT: mov r0, r3
+; CHECK-SOFTFLOAT-NEXT: bhi .LBB17_2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.1: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r0, r5
+; CHECK-SOFTFLOAT-NEXT: .LBB17_2: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsls r1, r1, #1
+; CHECK-SOFTFLOAT-NEXT: lsrs r1, r1, #24
+; CHECK-SOFTFLOAT-NEXT: cmp r1, #254
+; CHECK-SOFTFLOAT-NEXT: mov r1, r3
+; CHECK-SOFTFLOAT-NEXT: bhi .LBB17_4
+; CHECK-SOFTFLOAT-NEXT: @ %bb.3: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r1, r5
+; CHECK-SOFTFLOAT-NEXT: .LBB17_4: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsls r2, r2, #1
+; CHECK-SOFTFLOAT-NEXT: lsrs r2, r2, #24
+; CHECK-SOFTFLOAT-NEXT: cmp r2, #254
+; CHECK-SOFTFLOAT-NEXT: mov r2, r3
+; CHECK-SOFTFLOAT-NEXT: bhi .LBB17_6
+; CHECK-SOFTFLOAT-NEXT: @ %bb.5: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r2, r5
+; CHECK-SOFTFLOAT-NEXT: .LBB17_6: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsls r4, r4, #1
+; CHECK-SOFTFLOAT-NEXT: lsrs r4, r4, #24
+; CHECK-SOFTFLOAT-NEXT: cmp r4, #254
+; CHECK-SOFTFLOAT-NEXT: bhi .LBB17_8
+; CHECK-SOFTFLOAT-NEXT: @ %bb.7: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r3, r5
+; CHECK-SOFTFLOAT-NEXT: .LBB17_8: @ %entry
+; CHECK-SOFTFLOAT-NEXT: pop {r4, r5, r7, pc}
+entry:
+ %0 = tail call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %x, i32 519) ; ~0x1f8 = "~finite"
+ ret <4 x i1> %0
+}
+
+define <2 x i1> @isfinite_v2d(<2 x double> %x) {
+; CHECK-LABEL: isfinite_v2d:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov x8, #9218868437227405312 // =0x7ff0000000000000
+; CHECK-NEXT: fabs v0.2d, v0.2d
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: fcmgt v2.2d, v0.2d, v1.2d
+; CHECK-NEXT: fcmgt v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
+;
+; CHECK-SOFTFLOAT-LABEL: isfinite_v2d:
+; CHECK-SOFTFLOAT: @ %bb.0: @ %entry
+; CHECK-SOFTFLOAT-NEXT: .save {r4, r5, r7, lr}
+; CHECK-SOFTFLOAT-NEXT: push {r4, r5, r7, lr}
+; CHECK-SOFTFLOAT-NEXT: lsrs r0, r0, #31
+; CHECK-SOFTFLOAT-NEXT: lsls r1, r1, #1
+; CHECK-SOFTFLOAT-NEXT: adds r0, r1, r0
+; CHECK-SOFTFLOAT-NEXT: movs r1, #1
+; CHECK-SOFTFLOAT-NEXT: movs r4, #0
+; CHECK-SOFTFLOAT-NEXT: ldr r5, .LCPI18_0
+; CHECK-SOFTFLOAT-NEXT: cmp r0, r5
+; CHECK-SOFTFLOAT-NEXT: mov r0, r1
+; CHECK-SOFTFLOAT-NEXT: blo .LBB18_2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.1: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r0, r4
+; CHECK-SOFTFLOAT-NEXT: .LBB18_2: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsrs r2, r2, #31
+; CHECK-SOFTFLOAT-NEXT: lsls r3, r3, #1
+; CHECK-SOFTFLOAT-NEXT: adds r2, r3, r2
+; CHECK-SOFTFLOAT-NEXT: cmp r2, r5
+; CHECK-SOFTFLOAT-NEXT: blo .LBB18_4
+; CHECK-SOFTFLOAT-NEXT: @ %bb.3: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r1, r4
+; CHECK-SOFTFLOAT-NEXT: .LBB18_4: @ %entry
+; CHECK-SOFTFLOAT-NEXT: pop {r4, r5, r7, pc}
+; CHECK-SOFTFLOAT-NEXT: .p2align 2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.5:
+; CHECK-SOFTFLOAT-NEXT: .LCPI18_0:
+; CHECK-SOFTFLOAT-NEXT: .long 4292870144 @ 0xffe00000
+entry:
+ %0 = tail call <2 x i1> @llvm.is.fpclass.v2f64(<2 x double> %x, i32 504) ; 0x1f8 = "finite"
+ ret <2 x i1> %0
+}
+
+define <2 x i1> @not_isfinite_v2d(<2 x double> %x) {
+; CHECK-LABEL: not_isfinite_v2d:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov x8, #-9007199254740992 // =0xffe0000000000000
+; CHECK-NEXT: add v0.2d, v0.2d, v0.2d
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmhs v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
+;
+; CHECK-SOFTFLOAT-LABEL: not_isfinite_v2d:
+; CHECK-SOFTFLOAT: @ %bb.0: @ %entry
+; CHECK-SOFTFLOAT-NEXT: .save {r4, r5, r7, lr}
+; CHECK-SOFTFLOAT-NEXT: push {r4, r5, r7, lr}
+; CHECK-SOFTFLOAT-NEXT: lsrs r0, r0, #31
+; CHECK-SOFTFLOAT-NEXT: lsls r1, r1, #1
+; CHECK-SOFTFLOAT-NEXT: adds r0, r1, r0
+; CHECK-SOFTFLOAT-NEXT: movs r1, #1
+; CHECK-SOFTFLOAT-NEXT: movs r4, #0
+; CHECK-SOFTFLOAT-NEXT: ldr r5, .LCPI19_0
+; CHECK-SOFTFLOAT-NEXT: cmp r0, r5
+; CHECK-SOFTFLOAT-NEXT: mov r0, r1
+; CHECK-SOFTFLOAT-NEXT: bhi .LBB19_2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.1: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r0, r4
+; CHECK-SOFTFLOAT-NEXT: .LBB19_2: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsrs r2, r2, #31
+; CHECK-SOFTFLOAT-NEXT: lsls r3, r3, #1
+; CHECK-SOFTFLOAT-NEXT: adds r2, r3, r2
+; CHECK-SOFTFLOAT-NEXT: cmp r2, r5
+; CHECK-SOFTFLOAT-NEXT: bhi .LBB19_4
+; CHECK-SOFTFLOAT-NEXT: @ %bb.3: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r1, r4
+; CHECK-SOFTFLOAT-NEXT: .LBB19_4: @ %entry
+; CHECK-SOFTFLOAT-NEXT: pop {r4, r5, r7, pc}
+; CHECK-SOFTFLOAT-NEXT: .p2align 2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.5:
+; CHECK-SOFTFLOAT-NEXT: .LCPI19_0:
+; CHECK-SOFTFLOAT-NEXT: .long 4292870143 @ 0xffdfffff
+entry:
+ %0 = tail call <2 x i1> @llvm.is.fpclass.v2f64(<2 x double> %x, i32 519) ; ~0x1f8 = "~finite"
+ ret <2 x i1> %0
+}
+
+define <4 x i1> @isfinite_v4bf16(<4 x bfloat> %x) {
+; CHECK-LABEL: isfinite_v4bf16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi d1, #0xff00ff00ff00ff00
+; CHECK-NEXT: add v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: cmhi v0.4h, v1.4h, v0.4h
+; CHECK-NEXT: ret
+;
+; CHECK-SOFTFLOAT-LABEL: isfinite_v4bf16:
+; CHECK-SOFTFLOAT: @ %bb.0: @ %entry
+; CHECK-SOFTFLOAT-NEXT: .save {r4, r5, r7, lr}
+; CHECK-SOFTFLOAT-NEXT: push {r4, r5, r7, lr}
+; CHECK-SOFTFLOAT-NEXT: mov r4, r3
+; CHECK-SOFTFLOAT-NEXT: lsls r0, r0, #17
+; CHECK-SOFTFLOAT-NEXT: lsrs r0, r0, #24
+; CHECK-SOFTFLOAT-NEXT: movs r3, #1
+; CHECK-SOFTFLOAT-NEXT: movs r5, #0
+; CHECK-SOFTFLOAT-NEXT: cmp r0, #255
+; CHECK-SOFTFLOAT-NEXT: mov r0, r3
+; CHECK-SOFTFLOAT-NEXT: blo .LBB20_2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.1: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r0, r5
+; CHECK-SOFTFLOAT-NEXT: .LBB20_2: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsls r1, r1, #17
+; CHECK-SOFTFLOAT-NEXT: lsrs r1, r1, #24
+; CHECK-SOFTFLOAT-NEXT: cmp r1, #255
+; CHECK-SOFTFLOAT-NEXT: mov r1, r3
+; CHECK-SOFTFLOAT-NEXT: blo .LBB20_4
+; CHECK-SOFTFLOAT-NEXT: @ %bb.3: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r1, r5
+; CHECK-SOFTFLOAT-NEXT: .LBB20_4: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsls r2, r2, #17
+; CHECK-SOFTFLOAT-NEXT: lsrs r2, r2, #24
+; CHECK-SOFTFLOAT-NEXT: cmp r2, #255
+; CHECK-SOFTFLOAT-NEXT: mov r2, r3
+; CHECK-SOFTFLOAT-NEXT: blo .LBB20_6
+; CHECK-SOFTFLOAT-NEXT: @ %bb.5: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r2, r5
+; CHECK-SOFTFLOAT-NEXT: .LBB20_6: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsls r4, r4, #17
+; CHECK-SOFTFLOAT-NEXT: lsrs r4, r4, #24
+; CHECK-SOFTFLOAT-NEXT: cmp r4, #255
+; CHECK-SOFTFLOAT-NEXT: blo .LBB20_8
+; CHECK-SOFTFLOAT-NEXT: @ %bb.7: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r3, r5
+; CHECK-SOFTFLOAT-NEXT: .LBB20_8: @ %entry
+; CHECK-SOFTFLOAT-NEXT: pop {r4, r5, r7, pc}
+entry:
+ %0 = tail call <4 x i1> @llvm.is.fpclass.v4bf16(<4 x bfloat> %x, i32 504) ; 0x1f8 = "finite"
+ ret <4 x i1> %0
+}
+
+define <4 x i1> @not_isfinite_v4bf16(<4 x bfloat> %x) {
+; CHECK-LABEL: not_isfinite_v4bf16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi d1, #0xff00ff00ff00ff00
+; CHECK-NEXT: add v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: cmhs v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: ret
+;
+; CHECK-SOFTFLOAT-LABEL: not_isfinite_v4bf16:
+; CHECK-SOFTFLOAT: @ %bb.0: @ %entry
+; CHECK-SOFTFLOAT-NEXT: .save {r4, r5, r7, lr}
+; CHECK-SOFTFLOAT-NEXT: push {r4, r5, r7, lr}
+; CHECK-SOFTFLOAT-NEXT: mov r4, r3
+; CHECK-SOFTFLOAT-NEXT: lsls r0, r0, #17
+; CHECK-SOFTFLOAT-NEXT: lsrs r0, r0, #24
+; CHECK-SOFTFLOAT-NEXT: movs r3, #1
+; CHECK-SOFTFLOAT-NEXT: movs r5, #0
+; CHECK-SOFTFLOAT-NEXT: cmp r0, #254
+; CHECK-SOFTFLOAT-NEXT: mov r0, r3
+; CHECK-SOFTFLOAT-NEXT: bhi .LBB21_2
+; CHECK-SOFTFLOAT-NEXT: @ %bb.1: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r0, r5
+; CHECK-SOFTFLOAT-NEXT: .LBB21_2: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsls r1, r1, #17
+; CHECK-SOFTFLOAT-NEXT: lsrs r1, r1, #24
+; CHECK-SOFTFLOAT-NEXT: cmp r1, #254
+; CHECK-SOFTFLOAT-NEXT: mov r1, r3
+; CHECK-SOFTFLOAT-NEXT: bhi .LBB21_4
+; CHECK-SOFTFLOAT-NEXT: @ %bb.3: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r1, r5
+; CHECK-SOFTFLOAT-NEXT: .LBB21_4: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsls r2, r2, #17
+; CHECK-SOFTFLOAT-NEXT: lsrs r2, r2, #24
+; CHECK-SOFTFLOAT-NEXT: cmp r2, #254
+; CHECK-SOFTFLOAT-NEXT: mov r2, r3
+; CHECK-SOFTFLOAT-NEXT: bhi .LBB21_6
+; CHECK-SOFTFLOAT-NEXT: @ %bb.5: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r2, r5
+; CHECK-SOFTFLOAT-NEXT: .LBB21_6: @ %entry
+; CHECK-SOFTFLOAT-NEXT: lsls r4, r4, #17
+; CHECK-SOFTFLOAT-NEXT: lsrs r4, r4, #24
+; CHECK-SOFTFLOAT-NEXT: cmp r4, #254
+; CHECK-SOFTFLOAT-NEXT: bhi .LBB21_8
+; CHECK-SOFTFLOAT-NEXT: @ %bb.7: @ %entry
+; CHECK-SOFTFLOAT-NEXT: mov r3, r5
+; CHECK-SOFTFLOAT-NEXT: .LBB21_8: @ %entry
+; CHECK-SOFTFLOAT-NEXT: pop {r4, r5, r7, pc}
+entry:
+ %0 = tail call <4 x i1> @llvm.is.fpclass.v4bf16(<4 x bfloat> %x, i32 519) ; ~0x1f8 = "~finite"
+ ret <4 x i1> %0
+}
+
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-GI: {{.*}}
+; CHECK-SD: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/fp-classify.ll b/llvm/test/CodeGen/AMDGPU/fp-classify.ll
index 4b800e4d47172..d62a7b7d7515d 100644
--- a/llvm/test/CodeGen/AMDGPU/fp-classify.ll
+++ b/llvm/test/CodeGen/AMDGPU/fp-classify.ll
@@ -699,8 +699,9 @@ define amdgpu_kernel void @test_isfinite_pattern_4_f16(ptr addrspace(1) nocaptur
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_and_b32 s4, s6, 0x7fff
-; SI-NEXT: s_cmpk_lt_i32 s4, 0x7c00
+; SI-NEXT: s_lshl_b32 s4, s6, 1
+; SI-NEXT: s_and_b32 s4, s4, 0xfffe
+; SI-NEXT: s_cmpk_lt_u32 s4, 0xf800
; SI-NEXT: s_cselect_b64 s[4:5], -1, 0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
index 956145fb24c4a..77d23aaff7f5e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
@@ -1342,51 +1342,52 @@ define i1 @isfinite_bf16(bfloat %x) nounwind {
; GFX7CHECK: ; %bb.0:
; GFX7CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7CHECK-NEXT: v_mul_f32_e32 v0, 1.0, v0
-; GFX7CHECK-NEXT: v_bfe_u32 v0, v0, 16, 15
-; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
-; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
+; GFX7CHECK-NEXT: v_lshrrev_b32_e32 v0, 15, v0
+; GFX7CHECK-NEXT: v_and_b32_e32 v0, 0xfffe, v0
+; GFX7CHECK-NEXT: s_mov_b32 s4, 0xff00
+; GFX7CHECK-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
; GFX7CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX7CHECK-NEXT: s_setpc_b64 s[30:31]
;
; GFX8CHECK-LABEL: isfinite_bf16:
; GFX8CHECK: ; %bb.0:
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8CHECK-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f80
-; GFX8CHECK-NEXT: v_cmp_gt_i16_e32 vcc, s4, v0
+; GFX8CHECK-NEXT: v_lshlrev_b16_e32 v0, 1, v0
+; GFX8CHECK-NEXT: s_movk_i32 s4, 0xff00
+; GFX8CHECK-NEXT: v_cmp_gt_u16_e32 vcc, s4, v0
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
;
; GFX9CHECK-LABEL: isfinite_bf16:
; GFX9CHECK: ; %bb.0:
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9CHECK-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f80
-; GFX9CHECK-NEXT: v_cmp_gt_i16_e32 vcc, s4, v0
+; GFX9CHECK-NEXT: v_lshlrev_b16_e32 v0, 1, v0
+; GFX9CHECK-NEXT: s_movk_i32 s4, 0xff00
+; GFX9CHECK-NEXT: v_cmp_gt_u16_e32 vcc, s4, v0
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
;
; GFX10CHECK-LABEL: isfinite_bf16:
; GFX10CHECK: ; %bb.0:
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10CHECK-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX10CHECK-NEXT: v_cmp_gt_i16_e32 vcc_lo, 0x7f80, v0
+; GFX10CHECK-NEXT: v_lshlrev_b16 v0, 1, v0
+; GFX10CHECK-NEXT: v_cmp_gt_u16_e32 vcc_lo, 0xff00, v0
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
;
; GFX11SELDAG-TRUE16-LABEL: isfinite_bf16:
; GFX11SELDAG-TRUE16: ; %bb.0:
; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11SELDAG-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v0.l
-; GFX11SELDAG-TRUE16-NEXT: v_cmp_gt_i16_e32 vcc_lo, 0x7f80, v0.l
+; GFX11SELDAG-TRUE16-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
+; GFX11SELDAG-TRUE16-NEXT: v_cmp_gt_u16_e32 vcc_lo, 0xff00, v0.l
; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11SELDAG-FAKE16-LABEL: isfinite_bf16:
; GFX11SELDAG-FAKE16: ; %bb.0:
; GFX11SELDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11SELDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX11SELDAG-FAKE16-NEXT: v_cmp_gt_i16_e32 vcc_lo, 0x7f80, v0
+; GFX11SELDAG-FAKE16-NEXT: v_lshlrev_b16 v0, 1, v0
+; GFX11SELDAG-FAKE16-NEXT: v_cmp_gt_u16_e32 vcc_lo, 0xff00, v0
; GFX11SELDAG-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11SELDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
%1 = call i1 @llvm.is.fpclass.bf16(bfloat %x, i32 504) ; 0x1f8 = "finite"
@@ -3130,51 +3131,52 @@ define i1 @isinf_or_nan_bf16(bfloat %x) {
; GFX7CHECK: ; %bb.0: ; %entry
; GFX7CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7CHECK-NEXT: v_mul_f32_e32 v0, 1.0, v0
-; GFX7CHECK-NEXT: v_bfe_u32 v0, v0, 16, 15
-; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f7f
-; GFX7CHECK-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
+; GFX7CHECK-NEXT: v_lshrrev_b32_e32 v0, 15, v0
+; GFX7CHECK-NEXT: v_and_b32_e32 v0, 0xfffe, v0
+; GFX7CHECK-NEXT: s_mov_b32 s4, 0xfeff
+; GFX7CHECK-NEXT: v_cmp_lt_u32_e32 vcc, s4, v0
; GFX7CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX7CHECK-NEXT: s_setpc_b64 s[30:31]
;
; GFX8CHECK-LABEL: isinf_or_nan_bf16:
; GFX8CHECK: ; %bb.0: ; %entry
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8CHECK-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f7f
-; GFX8CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v0
+; GFX8CHECK-NEXT: v_lshlrev_b16_e32 v0, 1, v0
+; GFX8CHECK-NEXT: s_movk_i32 s4, 0xfeff
+; GFX8CHECK-NEXT: v_cmp_lt_u16_e32 vcc, s4, v0
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
;
; GFX9CHECK-LABEL: isinf_or_nan_bf16:
; GFX9CHECK: ; %bb.0: ; %entry
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9CHECK-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f7f
-; GFX9CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v0
+; GFX9CHECK-NEXT: v_lshlrev_b16_e32 v0, 1, v0
+; GFX9CHECK-NEXT: s_movk_i32 s4, 0xfeff
+; GFX9CHECK-NEXT: v_cmp_lt_u16_e32 vcc, s4, v0
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
;
; GFX10CHECK-LABEL: isinf_or_nan_bf16:
; GFX10CHECK: ; %bb.0: ; %entry
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10CHECK-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX10CHECK-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f7f, v0
+; GFX10CHECK-NEXT: v_lshlrev_b16 v0, 1, v0
+; GFX10CHECK-NEXT: v_cmp_lt_u16_e32 vcc_lo, 0xfeff, v0
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
;
; GFX11SELDAG-TRUE16-LABEL: isinf_or_nan_bf16:
; GFX11SELDAG-TRUE16: ; %bb.0: ; %entry
; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11SELDAG-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v0.l
-; GFX11SELDAG-TRUE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f7f, v0.l
+; GFX11SELDAG-TRUE16-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
+; GFX11SELDAG-TRUE16-NEXT: v_cmp_lt_u16_e32 vcc_lo, 0xfeff, v0.l
; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11SELDAG-FAKE16-LABEL: isinf_or_nan_bf16:
; GFX11SELDAG-FAKE16: ; %bb.0: ; %entry
; GFX11SELDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11SELDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX11SELDAG-FAKE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f7f, v0
+; GFX11SELDAG-FAKE16-NEXT: v_lshlrev_b16 v0, 1, v0
+; GFX11SELDAG-FAKE16-NEXT: v_cmp_lt_u16_e32 vcc_lo, 0xfeff, v0
; GFX11SELDAG-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11SELDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -3187,51 +3189,52 @@ define i1 @not_isinf_or_nan_bf16(bfloat %x) {
; GFX7CHECK: ; %bb.0: ; %entry
; GFX7CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7CHECK-NEXT: v_mul_f32_e32 v0, 1.0, v0
-; GFX7CHECK-NEXT: v_bfe_u32 v0, v0, 16, 15
-; GFX7CHECK-NEXT: s_movk_i32 s4, 0x7f80
-; GFX7CHECK-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
+; GFX7CHECK-NEXT: v_lshrrev_b32_e32 v0, 15, v0
+; GFX7CHECK-NEXT: v_and_b32_e32 v0, 0xfffe, v0
+; GFX7CHECK-NEXT: s_mov_b32 s4, 0xff00
+; GFX7CHECK-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
; GFX7CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX7CHECK-NEXT: s_setpc_b64 s[30:31]
;
; GFX8CHECK-LABEL: not_isinf_or_nan_bf16:
; GFX8CHECK: ; %bb.0: ; %entry
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8CHECK-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f80
-; GFX8CHECK-NEXT: v_cmp_gt_i16_e32 vcc, s4, v0
+; GFX8CHECK-NEXT: v_lshlrev_b16_e32 v0, 1, v0
+; GFX8CHECK-NEXT: s_movk_i32 s4, 0xff00
+; GFX8CHECK-NEXT: v_cmp_gt_u16_e32 vcc, s4, v0
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
;
; GFX9CHECK-LABEL: not_isinf_or_nan_bf16:
; GFX9CHECK: ; %bb.0: ; %entry
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9CHECK-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f80
-; GFX9CHECK-NEXT: v_cmp_gt_i16_e32 vcc, s4, v0
+; GFX9CHECK-NEXT: v_lshlrev_b16_e32 v0, 1, v0
+; GFX9CHECK-NEXT: s_movk_i32 s4, 0xff00
+; GFX9CHECK-NEXT: v_cmp_gt_u16_e32 vcc, s4, v0
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
;
; GFX10CHECK-LABEL: not_isinf_or_nan_bf16:
; GFX10CHECK: ; %bb.0: ; %entry
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10CHECK-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX10CHECK-NEXT: v_cmp_gt_i16_e32 vcc_lo, 0x7f80, v0
+; GFX10CHECK-NEXT: v_lshlrev_b16 v0, 1, v0
+; GFX10CHECK-NEXT: v_cmp_gt_u16_e32 vcc_lo, 0xff00, v0
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
;
; GFX11SELDAG-TRUE16-LABEL: not_isinf_or_nan_bf16:
; GFX11SELDAG-TRUE16: ; %bb.0: ; %entry
; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11SELDAG-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v0.l
-; GFX11SELDAG-TRUE16-NEXT: v_cmp_gt_i16_e32 vcc_lo, 0x7f80, v0.l
+; GFX11SELDAG-TRUE16-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
+; GFX11SELDAG-TRUE16-NEXT: v_cmp_gt_u16_e32 vcc_lo, 0xff00, v0.l
; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11SELDAG-FAKE16-LABEL: not_isinf_or_nan_bf16:
; GFX11SELDAG-FAKE16: ; %bb.0: ; %entry
; GFX11SELDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11SELDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX11SELDAG-FAKE16-NEXT: v_cmp_gt_i16_e32 vcc_lo, 0x7f80, v0
+; GFX11SELDAG-FAKE16-NEXT: v_lshlrev_b16 v0, 1, v0
+; GFX11SELDAG-FAKE16-NEXT: v_cmp_gt_u16_e32 vcc_lo, 0xff00, v0
; GFX11SELDAG-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11SELDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
index 18c462ffd0ff5..ecfcbefc5d8d3 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
@@ -1879,9 +1879,10 @@ define i1 @isfinite_f16(half %x) nounwind {
; GFX7SELDAG: ; %bb.0:
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
-; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
+; GFX7SELDAG-NEXT: s_mov_b32 s4, 0xf800
+; GFX7SELDAG-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xfffe, v0
+; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3976,9 +3977,10 @@ define i1 @isinf_or_nan_f16(half %x) {
; GFX7SELDAG: ; %bb.0: ; %entry
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7bff
-; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
+; GFX7SELDAG-NEXT: s_mov_b32 s4, 0xf7ff
+; GFX7SELDAG-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xfffe, v0
+; GFX7SELDAG-NEXT: v_cmp_lt_u32_e32 vcc, s4, v0
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -4052,9 +4054,10 @@ define i1 @not_isinf_or_nan_f16(half %x) {
; GFX7SELDAG: ; %bb.0: ; %entry
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
-; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
+; GFX7SELDAG-NEXT: s_mov_b32 s4, 0xf800
+; GFX7SELDAG-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xfffe, v0
+; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/r600.llvm.is.fpclass.ll b/llvm/test/CodeGen/AMDGPU/r600.llvm.is.fpclass.ll
index 3116094fe1dfd..08039833e2a66 100644
--- a/llvm/test/CodeGen/AMDGPU/r600.llvm.is.fpclass.ll
+++ b/llvm/test/CodeGen/AMDGPU/r600.llvm.is.fpclass.ll
@@ -25,15 +25,14 @@ define amdgpu_kernel void @isnan_f32(ptr addrspace(1) %out, float %x) {
define amdgpu_kernel void @issue135083_f32(ptr addrspace(1) %out, float %x) {
; CM-LABEL: issue135083_f32:
; CM: ; %bb.0:
-; CM-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[]
+; CM-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
; CM-NEXT: CF_END
; CM-NEXT: PAD
; CM-NEXT: ALU clause starting at 4:
-; CM-NEXT: AND_INT * T0.W, KC0[2].Z, literal.x,
-; CM-NEXT: 2147483647(nan), 0(0.000000e+00)
-; CM-NEXT: SETGT_INT * T0.W, literal.x, PV.W,
-; CM-NEXT: 2139095040(INF), 0(0.000000e+00)
+; CM-NEXT: LSHL * T0.W, KC0[2].Z, 1,
+; CM-NEXT: SETGT_UINT * T0.W, literal.x, PV.W,
+; CM-NEXT: -16777216(-1.701412e+38), 0(0.000000e+00)
; CM-NEXT: AND_INT * T0.X, PV.W, 1,
; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
@@ -46,19 +45,18 @@ define amdgpu_kernel void @issue135083_f32(ptr addrspace(1) %out, float %x) {
define amdgpu_kernel void @issue135083_v2f32(ptr addrspace(1) %out, <2 x float> %x) {
; CM-LABEL: issue135083_v2f32:
; CM: ; %bb.0:
-; CM-NEXT: ALU 10, @4, KC0[CB0:0-32], KC1[]
+; CM-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X
; CM-NEXT: CF_END
; CM-NEXT: PAD
; CM-NEXT: ALU clause starting at 4:
-; CM-NEXT: AND_INT * T0.W, KC0[3].X, literal.x,
-; CM-NEXT: 2147483647(nan), 0(0.000000e+00)
-; CM-NEXT: AND_INT T0.Z, KC0[2].W, literal.x,
-; CM-NEXT: SETGT_INT * T0.W, PV.W, literal.y,
-; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)
+; CM-NEXT: LSHL * T0.W, KC0[3].X, 1,
+; CM-NEXT: LSHL T0.Z, KC0[2].W, 1,
+; CM-NEXT: SETGT_UINT * T0.W, PV.W, literal.x,
+; CM-NEXT: -16777217(-1.701412e+38), 0(0.000000e+00)
; CM-NEXT: CNDE_INT T0.Y, PV.W, 1, 0.0,
-; CM-NEXT: SETGT_INT * T0.W, PV.Z, literal.x,
-; CM-NEXT: 2139095039(3.402823e+38), 0(0.000000e+00)
+; CM-NEXT: SETGT_UINT * T0.W, PV.Z, literal.x,
+; CM-NEXT: -16777217(-1.701412e+38), 0(0.000000e+00)
; CM-NEXT: CNDE_INT * T0.X, PV.W, 1, 0.0,
; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
@@ -71,26 +69,24 @@ define amdgpu_kernel void @issue135083_v2f32(ptr addrspace(1) %out, <2 x float>
define amdgpu_kernel void @issue135083_v3f32(ptr addrspace(1) %out, <3 x float> %x) {
; CM-LABEL: issue135083_v3f32:
; CM: ; %bb.0:
-; CM-NEXT: ALU 17, @4, KC0[CB0:0-32], KC1[]
+; CM-NEXT: ALU 15, @4, KC0[CB0:0-32], KC1[]
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2, T3.X
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
; CM-NEXT: CF_END
; CM-NEXT: ALU clause starting at 4:
-; CM-NEXT: AND_INT * T0.W, KC0[3].W, literal.x,
-; CM-NEXT: 2147483647(nan), 0(0.000000e+00)
-; CM-NEXT: AND_INT T0.Z, KC0[3].Z, literal.x,
-; CM-NEXT: SETGT_INT * T0.W, PV.W, literal.y,
-; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)
+; CM-NEXT: LSHL * T0.W, KC0[3].W, 1,
+; CM-NEXT: LSHL T0.Z, KC0[3].Z, 1,
+; CM-NEXT: SETGT_UINT * T0.W, PV.W, literal.x,
+; CM-NEXT: -16777217(-1.701412e+38), 0(0.000000e+00)
; CM-NEXT: CNDE_INT T0.X, PV.W, 1, 0.0,
-; CM-NEXT: AND_INT T0.Y, KC0[3].Y, literal.x,
-; CM-NEXT: SETGT_INT T0.Z, PV.Z, literal.y,
-; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,
-; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)
-; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; CM-NEXT: LSHL T0.Y, KC0[3].Y, 1,
+; CM-NEXT: SETGT_UINT T0.Z, PV.Z, literal.x,
+; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; CM-NEXT: -16777217(-1.701412e+38), 8(1.121039e-44)
; CM-NEXT: LSHR T1.X, PV.W, literal.x,
; CM-NEXT: CNDE_INT T2.Y, PV.Z, 1, 0.0,
-; CM-NEXT: SETGT_INT * T0.W, PV.Y, literal.y,
-; CM-NEXT: 2(2.802597e-45), 2139095039(3.402823e+38)
+; CM-NEXT: SETGT_UINT * T0.W, PV.Y, literal.y,
+; CM-NEXT: 2(2.802597e-45), -16777217(-1.701412e+38)
; CM-NEXT: CNDE_INT * T2.X, PV.W, 1, 0.0,
; CM-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,
; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
@@ -103,27 +99,26 @@ define amdgpu_kernel void @issue135083_v3f32(ptr addrspace(1) %out, <3 x float>
define amdgpu_kernel void @issue135083_v4f32(ptr addrspace(1) %out, <4 x float> %x) {
; CM-LABEL: issue135083_v4f32:
; CM: ; %bb.0:
-; CM-NEXT: ALU 18, @4, KC0[CB0:0-32], KC1[]
+; CM-NEXT: ALU 17, @4, KC0[CB0:0-32], KC1[]
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X
; CM-NEXT: CF_END
; CM-NEXT: PAD
; CM-NEXT: ALU clause starting at 4:
-; CM-NEXT: AND_INT * T0.W, KC0[4].X, literal.x,
-; CM-NEXT: 2147483647(nan), 0(0.000000e+00)
-; CM-NEXT: SETGT_INT T0.Z, PV.W, literal.x,
-; CM-NEXT: AND_INT * T0.W, KC0[3].W, literal.y,
-; CM-NEXT: 2139095039(3.402823e+38), 2147483647(nan)
-; CM-NEXT: AND_INT T0.Y, KC0[3].Z, literal.x,
-; CM-NEXT: SETGT_INT T1.Z, PV.W, literal.y,
+; CM-NEXT: LSHL * T0.W, KC0[4].X, 1,
+; CM-NEXT: SETGT_UINT T0.Z, PV.W, literal.x,
+; CM-NEXT: LSHL * T0.W, KC0[3].W, 1,
+; CM-NEXT: -16777217(-1.701412e+38), 0(0.000000e+00)
+; CM-NEXT: LSHL T0.Y, KC0[3].Z, 1,
+; CM-NEXT: SETGT_UINT T1.Z, PV.W, literal.x,
; CM-NEXT: CNDE_INT * T0.W, PV.Z, 1, 0.0,
-; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)
-; CM-NEXT: AND_INT T1.Y, KC0[3].Y, literal.x,
+; CM-NEXT: -16777217(-1.701412e+38), 0(0.000000e+00)
+; CM-NEXT: LSHL T1.Y, KC0[3].Y, 1,
; CM-NEXT: CNDE_INT T0.Z, PV.Z, 1, 0.0,
-; CM-NEXT: SETGT_INT * T1.W, PV.Y, literal.y,
-; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)
+; CM-NEXT: SETGT_UINT * T1.W, PV.Y, literal.x,
+; CM-NEXT: -16777217(-1.701412e+38), 0(0.000000e+00)
; CM-NEXT: CNDE_INT T0.Y, PV.W, 1, 0.0,
-; CM-NEXT: SETGT_INT * T1.W, PV.Y, literal.x,
-; CM-NEXT: 2139095039(3.402823e+38), 0(0.000000e+00)
+; CM-NEXT: SETGT_UINT * T1.W, PV.Y, literal.x,
+; CM-NEXT: -16777217(-1.701412e+38), 0(0.000000e+00)
; CM-NEXT: CNDE_INT * T0.X, PV.W, 1, 0.0,
; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
@@ -136,32 +131,31 @@ define amdgpu_kernel void @issue135083_v4f32(ptr addrspace(1) %out, <4 x float>
define amdgpu_kernel void @issue135083_v5f32(ptr addrspace(1) %out, <5 x float> %x) {
; CM-LABEL: issue135083_v5f32:
; CM: ; %bb.0:
-; CM-NEXT: ALU 23, @4, KC0[CB0:0-32], KC1[]
+; CM-NEXT: ALU 22, @4, KC0[CB0:0-32], KC1[]
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T3.X
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2.X, T0.X
; CM-NEXT: CF_END
; CM-NEXT: ALU clause starting at 4:
-; CM-NEXT: AND_INT T0.Z, KC0[4].Y, literal.x,
-; CM-NEXT: AND_INT * T0.W, KC0[5].X, literal.x,
-; CM-NEXT: 2147483647(nan), 0(0.000000e+00)
-; CM-NEXT: SETGT_INT T0.Y, PV.W, literal.x,
-; CM-NEXT: AND_INT T1.Z, KC0[5].Y, literal.y,
-; CM-NEXT: AND_INT * T0.W, KC0[4].W, literal.y,
-; CM-NEXT: 2139095039(3.402823e+38), 2147483647(nan)
-; CM-NEXT: SETGT_INT T0.X, PV.W, literal.x,
-; CM-NEXT: AND_INT T1.Y, KC0[4].Z, literal.y,
-; CM-NEXT: SETGT_INT T1.Z, PV.Z, literal.x,
+; CM-NEXT: LSHL T0.Z, KC0[4].Y, 1,
+; CM-NEXT: LSHL * T0.W, KC0[5].X, 1,
+; CM-NEXT: SETGT_UINT T0.Y, PV.W, literal.x,
+; CM-NEXT: LSHL T1.Z, KC0[5].Y, 1,
+; CM-NEXT: LSHL * T0.W, KC0[4].W, 1,
+; CM-NEXT: -16777217(-1.701412e+38), 0(0.000000e+00)
+; CM-NEXT: SETGT_UINT T0.X, PV.W, literal.x,
+; CM-NEXT: LSHL T1.Y, KC0[4].Z, 1,
+; CM-NEXT: SETGT_UINT T1.Z, PV.Z, literal.x,
; CM-NEXT: CNDE_INT * T1.W, PV.Y, 1, 0.0,
-; CM-NEXT: 2139095039(3.402823e+38), 2147483647(nan)
+; CM-NEXT: -16777217(-1.701412e+38), 0(0.000000e+00)
; CM-NEXT: CNDE_INT T2.X, PV.Z, 1, 0.0,
-; CM-NEXT: SETGT_INT T0.Y, PV.Y, literal.x,
+; CM-NEXT: SETGT_UINT T0.Y, PV.Y, literal.x,
; CM-NEXT: CNDE_INT T1.Z, PV.X, 1, 0.0,
; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
-; CM-NEXT: 2139095039(3.402823e+38), 16(2.242078e-44)
+; CM-NEXT: -16777217(-1.701412e+38), 16(2.242078e-44)
; CM-NEXT: LSHR T0.X, PV.W, literal.x,
; CM-NEXT: CNDE_INT T1.Y, PV.Y, 1, 0.0,
-; CM-NEXT: SETGT_INT * T0.W, T0.Z, literal.y,
-; CM-NEXT: 2(2.802597e-45), 2139095039(3.402823e+38)
+; CM-NEXT: SETGT_UINT * T0.W, T0.Z, literal.y,
+; CM-NEXT: 2(2.802597e-45), -16777217(-1.701412e+38)
; CM-NEXT: CNDE_INT * T1.X, PV.W, 1, 0.0,
; CM-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,
; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
@@ -174,36 +168,34 @@ define amdgpu_kernel void @issue135083_v5f32(ptr addrspace(1) %out, <5 x float>
define amdgpu_kernel void @issue135083_v6f32(ptr addrspace(1) %out, <6 x float> %x) {
; CM-LABEL: issue135083_v6f32:
; CM: ; %bb.0:
-; CM-NEXT: ALU 27, @4, KC0[CB0:0-32], KC1[]
+; CM-NEXT: ALU 25, @4, KC0[CB0:0-32], KC1[]
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T3.X
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2, T0.X
; CM-NEXT: CF_END
; CM-NEXT: ALU clause starting at 4:
-; CM-NEXT: AND_INT T0.Z, KC0[4].Y, literal.x,
-; CM-NEXT: AND_INT * T0.W, KC0[5].Z, literal.x,
-; CM-NEXT: 2147483647(nan), 0(0.000000e+00)
-; CM-NEXT: AND_INT T1.Z, KC0[5].X, literal.x,
-; CM-NEXT: AND_INT * T1.W, KC0[4].W, literal.x,
-; CM-NEXT: 2147483647(nan), 0(0.000000e+00)
-; CM-NEXT: SETGT_INT T0.X, PV.W, literal.x,
-; CM-NEXT: SETGT_INT T0.Y, PV.Z, literal.x,
-; CM-NEXT: AND_INT T1.Z, KC0[5].Y, literal.y,
-; CM-NEXT: SETGT_INT * T0.W, T0.W, literal.x,
-; CM-NEXT: 2139095039(3.402823e+38), 2147483647(nan)
-; CM-NEXT: AND_INT T1.X, KC0[4].Z, literal.x,
+; CM-NEXT: LSHL T0.Z, KC0[4].Y, 1,
+; CM-NEXT: LSHL * T0.W, KC0[5].Z, 1,
+; CM-NEXT: LSHL T1.Z, KC0[5].X, 1,
+; CM-NEXT: LSHL * T1.W, KC0[4].W, 1,
+; CM-NEXT: SETGT_UINT T0.X, PV.W, literal.x,
+; CM-NEXT: SETGT_UINT T0.Y, PV.Z, literal.x,
+; CM-NEXT: LSHL T1.Z, KC0[5].Y, 1,
+; CM-NEXT: SETGT_UINT * T0.W, T0.W, literal.x,
+; CM-NEXT: -16777217(-1.701412e+38), 0(0.000000e+00)
+; CM-NEXT: LSHL T1.X, KC0[4].Z, 1,
; CM-NEXT: CNDE_INT T2.Y, PV.W, 1, 0.0,
-; CM-NEXT: SETGT_INT T1.Z, PV.Z, literal.y,
+; CM-NEXT: SETGT_UINT T1.Z, PV.Z, literal.x,
; CM-NEXT: CNDE_INT * T1.W, PV.Y, 1, 0.0,
-; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)
+; CM-NEXT: -16777217(-1.701412e+38), 0(0.000000e+00)
; CM-NEXT: CNDE_INT T2.X, PV.Z, 1, 0.0,
-; CM-NEXT: SETGT_INT T0.Y, PV.X, literal.x,
+; CM-NEXT: SETGT_UINT T0.Y, PV.X, literal.x,
; CM-NEXT: CNDE_INT T1.Z, T0.X, 1, 0.0,
; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
-; CM-NEXT: 2139095039(3.402823e+38), 16(2.242078e-44)
+; CM-NEXT: -16777217(-1.701412e+38), 16(2.242078e-44)
; CM-NEXT: LSHR T0.X, PV.W, literal.x,
; CM-NEXT: CNDE_INT T1.Y, PV.Y, 1, 0.0,
-; CM-NEXT: SETGT_INT * T0.W, T0.Z, literal.y,
-; CM-NEXT: 2(2.802597e-45), 2139095039(3.402823e+38)
+; CM-NEXT: SETGT_UINT * T0.W, T0.Z, literal.y,
+; CM-NEXT: 2(2.802597e-45), -16777217(-1.701412e+38)
; CM-NEXT: CNDE_INT * T1.X, PV.W, 1, 0.0,
; CM-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,
; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
@@ -216,45 +208,43 @@ define amdgpu_kernel void @issue135083_v6f32(ptr addrspace(1) %out, <6 x float>
define amdgpu_kernel void @issue135083_v7f32(ptr addrspace(1) %out, <7 x float> %x) {
; CM-LABEL: issue135083_v7f32:
; CM: ; %bb.0:
-; CM-NEXT: ALU 34, @6, KC0[CB0:0-32], KC1[]
+; CM-NEXT: ALU 32, @6, KC0[CB0:0-32], KC1[]
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T4, T5.X
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T3, T0.X
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T2.X
; CM-NEXT: CF_END
; CM-NEXT: PAD
; CM-NEXT: ALU clause starting at 6:
-; CM-NEXT: AND_INT T0.Z, KC0[4].Y, literal.x,
-; CM-NEXT: AND_INT * T0.W, KC0[4].W, literal.x,
-; CM-NEXT: 2147483647(nan), 0(0.000000e+00)
-; CM-NEXT: SETGT_INT T0.Y, PV.W, literal.x,
-; CM-NEXT: AND_INT T1.Z, KC0[5].W, literal.y,
-; CM-NEXT: AND_INT * T0.W, KC0[5].X, literal.y,
-; CM-NEXT: 2139095039(3.402823e+38), 2147483647(nan)
-; CM-NEXT: AND_INT T0.X, KC0[4].Z, literal.x,
-; CM-NEXT: SETGT_INT T1.Y, PV.W, literal.y,
-; CM-NEXT: AND_INT T2.Z, KC0[5].Z, literal.x,
-; CM-NEXT: SETGT_INT * T0.W, PV.Z, literal.y,
-; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)
+; CM-NEXT: LSHL T0.Z, KC0[4].Y, 1,
+; CM-NEXT: LSHL * T0.W, KC0[4].W, 1,
+; CM-NEXT: SETGT_UINT T0.Y, PV.W, literal.x,
+; CM-NEXT: LSHL T1.Z, KC0[5].W, 1,
+; CM-NEXT: LSHL * T0.W, KC0[5].X, 1,
+; CM-NEXT: -16777217(-1.701412e+38), 0(0.000000e+00)
+; CM-NEXT: LSHL T0.X, KC0[4].Z, 1,
+; CM-NEXT: SETGT_UINT T1.Y, PV.W, literal.x,
+; CM-NEXT: LSHL T2.Z, KC0[5].Z, 1,
+; CM-NEXT: SETGT_UINT * T0.W, PV.Z, literal.x,
+; CM-NEXT: -16777217(-1.701412e+38), 0(0.000000e+00)
; CM-NEXT: CNDE_INT T1.X, PV.W, 1, 0.0,
-; CM-NEXT: AND_INT T2.Y, KC0[5].Y, literal.x,
-; CM-NEXT: SETGT_INT T1.Z, PV.Z, literal.y,
-; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,
-; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)
-; CM-NEXT: 24(3.363116e-44), 0(0.000000e+00)
+; CM-NEXT: LSHL T2.Y, KC0[5].Y, 1,
+; CM-NEXT: SETGT_UINT T1.Z, PV.Z, literal.x,
+; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; CM-NEXT: -16777217(-1.701412e+38), 24(3.363116e-44)
; CM-NEXT: LSHR T2.X, PV.W, literal.x,
; CM-NEXT: CNDE_INT T3.Y, PV.Z, 1, 0.0,
-; CM-NEXT: SETGT_INT T1.Z, PV.Y, literal.y,
+; CM-NEXT: SETGT_UINT T1.Z, PV.Y, literal.y,
; CM-NEXT: CNDE_INT * T4.W, T1.Y, 1, 0.0,
-; CM-NEXT: 2(2.802597e-45), 2139095039(3.402823e+38)
+; CM-NEXT: 2(2.802597e-45), -16777217(-1.701412e+38)
; CM-NEXT: CNDE_INT T3.X, PV.Z, 1, 0.0,
-; CM-NEXT: SETGT_INT T1.Y, T0.X, literal.x,
+; CM-NEXT: SETGT_UINT T1.Y, T0.X, literal.x,
; CM-NEXT: CNDE_INT T4.Z, T0.Y, 1, 0.0,
; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
-; CM-NEXT: 2139095039(3.402823e+38), 16(2.242078e-44)
+; CM-NEXT: -16777217(-1.701412e+38), 16(2.242078e-44)
; CM-NEXT: LSHR T0.X, PV.W, literal.x,
; CM-NEXT: CNDE_INT T4.Y, PV.Y, 1, 0.0,
-; CM-NEXT: SETGT_INT * T0.W, T0.Z, literal.y,
-; CM-NEXT: 2(2.802597e-45), 2139095039(3.402823e+38)
+; CM-NEXT: SETGT_UINT * T0.W, T0.Z, literal.y,
+; CM-NEXT: 2(2.802597e-45), -16777217(-1.701412e+38)
; CM-NEXT: CNDE_INT * T4.X, PV.W, 1, 0.0,
; CM-NEXT: LSHR * T5.X, KC0[2].Y, literal.x,
; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
@@ -267,43 +257,42 @@ define amdgpu_kernel void @issue135083_v7f32(ptr addrspace(1) %out, <7 x float>
define amdgpu_kernel void @issue135083_v8f32(ptr addrspace(1) %out, <8 x float> %x) {
; CM-LABEL: issue135083_v8f32:
; CM: ; %bb.0:
-; CM-NEXT: ALU 34, @4, KC0[CB0:0-32], KC1[]
+; CM-NEXT: ALU 33, @4, KC0[CB0:0-32], KC1[]
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T3.X
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T2.X
; CM-NEXT: CF_END
; CM-NEXT: ALU clause starting at 4:
-; CM-NEXT: AND_INT T0.Z, KC0[6].X, literal.x,
-; CM-NEXT: AND_INT * T0.W, KC0[4].W, literal.x,
-; CM-NEXT: 2147483647(nan), 0(0.000000e+00)
-; CM-NEXT: AND_INT T0.X, KC0[4].Y, literal.x,
-; CM-NEXT: SETGT_INT T0.Y, PV.W, literal.y,
-; CM-NEXT: SETGT_INT T0.Z, PV.Z, literal.y,
-; CM-NEXT: AND_INT * T0.W, KC0[5].W, literal.x,
-; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)
-; CM-NEXT: AND_INT T1.X, KC0[5].Z, literal.x,
-; CM-NEXT: SETGT_INT T1.Y, PV.W, literal.y,
-; CM-NEXT: AND_INT T1.Z, KC0[5].X, literal.x,
+; CM-NEXT: LSHL T0.Z, KC0[6].X, 1,
+; CM-NEXT: LSHL * T0.W, KC0[4].W, 1,
+; CM-NEXT: LSHL T0.X, KC0[4].Y, 1,
+; CM-NEXT: SETGT_UINT T0.Y, PV.W, literal.x,
+; CM-NEXT: SETGT_UINT T0.Z, PV.Z, literal.x,
+; CM-NEXT: LSHL * T0.W, KC0[5].W, 1,
+; CM-NEXT: -16777217(-1.701412e+38), 0(0.000000e+00)
+; CM-NEXT: LSHL T1.X, KC0[5].Z, 1,
+; CM-NEXT: SETGT_UINT T1.Y, PV.W, literal.x,
+; CM-NEXT: LSHL T1.Z, KC0[5].X, 1,
; CM-NEXT: CNDE_INT * T1.W, PV.Z, 1, 0.0,
-; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)
-; CM-NEXT: SETGT_INT T2.X, PV.Z, literal.x,
-; CM-NEXT: AND_INT T2.Y, KC0[5].Y, literal.y,
+; CM-NEXT: -16777217(-1.701412e+38), 0(0.000000e+00)
+; CM-NEXT: SETGT_UINT T2.X, PV.Z, literal.x,
+; CM-NEXT: LSHL T2.Y, KC0[5].Y, 1,
; CM-NEXT: CNDE_INT T1.Z, PV.Y, 1, 0.0,
-; CM-NEXT: SETGT_INT * T0.W, PV.X, literal.x,
-; CM-NEXT: 2139095039(3.402823e+38), 2147483647(nan)
-; CM-NEXT: AND_INT T3.X, KC0[4].Z, literal.x,
+; CM-NEXT: SETGT_UINT * T0.W, PV.X, literal.x,
+; CM-NEXT: -16777217(-1.701412e+38), 0(0.000000e+00)
+; CM-NEXT: LSHL T3.X, KC0[4].Z, 1,
; CM-NEXT: CNDE_INT T1.Y, PV.W, 1, 0.0,
-; CM-NEXT: SETGT_INT T0.Z, PV.Y, literal.y,
+; CM-NEXT: SETGT_UINT T0.Z, PV.Y, literal.x,
; CM-NEXT: CNDE_INT * T0.W, PV.X, 1, 0.0,
-; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)
+; CM-NEXT: -16777217(-1.701412e+38), 0(0.000000e+00)
; CM-NEXT: CNDE_INT T1.X, PV.Z, 1, 0.0,
-; CM-NEXT: SETGT_INT T2.Y, PV.X, literal.x,
+; CM-NEXT: SETGT_UINT T2.Y, PV.X, literal.x,
; CM-NEXT: CNDE_INT T0.Z, T0.Y, 1, 0.0,
; CM-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.y,
-; CM-NEXT: 2139095039(3.402823e+38), 16(2.242078e-44)
+; CM-NEXT: -16777217(-1.701412e+38), 16(2.242078e-44)
; CM-NEXT: LSHR T2.X, PV.W, literal.x,
; CM-NEXT: CNDE_INT T0.Y, PV.Y, 1, 0.0,
-; CM-NEXT: SETGT_INT * T2.W, T0.X, literal.y,
-; CM-NEXT: 2(2.802597e-45), 2139095039(3.402823e+38)
+; CM-NEXT: SETGT_UINT * T2.W, T0.X, literal.y,
+; CM-NEXT: 2(2.802597e-45), -16777217(-1.701412e+38)
; CM-NEXT: CNDE_INT * T0.X, PV.W, 1, 0.0,
; CM-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,
; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
@@ -316,80 +305,79 @@ define amdgpu_kernel void @issue135083_v8f32(ptr addrspace(1) %out, <8 x float>
define amdgpu_kernel void @issue135083_v16f32(ptr addrspace(1) %out, <16 x float> %x) {
; CM-LABEL: issue135083_v16f32:
; CM: ; %bb.0:
-; CM-NEXT: ALU 69, @6, KC0[CB0:0-32], KC1[]
+; CM-NEXT: ALU 68, @6, KC0[CB0:0-32], KC1[]
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T7.X
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2, T0.X
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T3, T6.X
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T4, T5.X
; CM-NEXT: CF_END
; CM-NEXT: ALU clause starting at 6:
-; CM-NEXT: AND_INT T0.Z, KC0[6].Y, literal.x,
-; CM-NEXT: AND_INT * T0.W, KC0[6].W, literal.x,
-; CM-NEXT: 2147483647(nan), 0(0.000000e+00)
-; CM-NEXT: SETGT_INT T0.X, PV.W, literal.x,
-; CM-NEXT: AND_INT T0.Y, KC0[6].Z, literal.y,
-; CM-NEXT: AND_INT T1.Z, KC0[7].Y, literal.y,
-; CM-NEXT: AND_INT * T0.W, KC0[7].X, literal.y,
-; CM-NEXT: 2139095039(3.402823e+38), 2147483647(nan)
-; CM-NEXT: SETGT_INT T1.X, PV.W, literal.x,
-; CM-NEXT: AND_INT T1.Y, KC0[7].Z, literal.y,
-; CM-NEXT: AND_INT T2.Z, KC0[8].X, literal.y,
-; CM-NEXT: AND_INT * T0.W, KC0[7].W, literal.y,
-; CM-NEXT: 2139095039(3.402823e+38), 2147483647(nan)
-; CM-NEXT: SETGT_INT T2.X, PV.W, literal.x,
-; CM-NEXT: SETGT_INT T2.Y, PV.Z, literal.x,
-; CM-NEXT: AND_INT T2.Z, KC0[10].X, literal.y,
-; CM-NEXT: AND_INT * T0.W, KC0[8].W, literal.y,
-; CM-NEXT: 2139095039(3.402823e+38), 2147483647(nan)
-; CM-NEXT: AND_INT T3.X, KC0[8].Y, literal.x,
-; CM-NEXT: SETGT_INT T3.Y, PV.W, literal.y,
-; CM-NEXT: SETGT_INT T2.Z, PV.Z, literal.y,
-; CM-NEXT: AND_INT * T0.W, KC0[9].W, literal.x,
-; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)
-; CM-NEXT: AND_INT T4.X, KC0[9].Z, literal.x,
-; CM-NEXT: SETGT_INT T4.Y, PV.W, literal.y,
-; CM-NEXT: AND_INT T3.Z, KC0[9].X, literal.x,
+; CM-NEXT: LSHL T0.Z, KC0[6].Y, 1,
+; CM-NEXT: LSHL * T0.W, KC0[6].W, 1,
+; CM-NEXT: SETGT_UINT T0.X, PV.W, literal.x,
+; CM-NEXT: LSHL T0.Y, KC0[6].Z, 1,
+; CM-NEXT: LSHL T1.Z, KC0[7].Y, 1,
+; CM-NEXT: LSHL * T0.W, KC0[7].X, 1,
+; CM-NEXT: -16777217(-1.701412e+38), 0(0.000000e+00)
+; CM-NEXT: SETGT_UINT T1.X, PV.W, literal.x,
+; CM-NEXT: LSHL T1.Y, KC0[7].Z, 1,
+; CM-NEXT: LSHL T2.Z, KC0[8].X, 1,
+; CM-NEXT: LSHL * T0.W, KC0[7].W, 1,
+; CM-NEXT: -16777217(-1.701412e+38), 0(0.000000e+00)
+; CM-NEXT: SETGT_UINT T2.X, PV.W, literal.x,
+; CM-NEXT: SETGT_UINT T2.Y, PV.Z, literal.x,
+; CM-NEXT: LSHL T2.Z, KC0[10].X, 1,
+; CM-NEXT: LSHL * T0.W, KC0[8].W, 1,
+; CM-NEXT: -16777217(-1.701412e+38), 0(0.000000e+00)
+; CM-NEXT: LSHL T3.X, KC0[8].Y, 1,
+; CM-NEXT: SETGT_UINT T3.Y, PV.W, literal.x,
+; CM-NEXT: SETGT_UINT T2.Z, PV.Z, literal.x,
+; CM-NEXT: LSHL * T0.W, KC0[9].W, 1,
+; CM-NEXT: -16777217(-1.701412e+38), 0(0.000000e+00)
+; CM-NEXT: LSHL T4.X, KC0[9].Z, 1,
+; CM-NEXT: SETGT_UINT T4.Y, PV.W, literal.x,
+; CM-NEXT: LSHL T3.Z, KC0[9].X, 1,
; CM-NEXT: CNDE_INT * T4.W, PV.Z, 1, 0.0,
-; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)
-; CM-NEXT: SETGT_INT T5.X, PV.Z, literal.x,
-; CM-NEXT: AND_INT T5.Y, KC0[9].Y, literal.y,
+; CM-NEXT: -16777217(-1.701412e+38), 0(0.000000e+00)
+; CM-NEXT: SETGT_UINT T5.X, PV.Z, literal.x,
+; CM-NEXT: LSHL T5.Y, KC0[9].Y, 1,
; CM-NEXT: CNDE_INT T4.Z, PV.Y, 1, 0.0,
-; CM-NEXT: SETGT_INT * T0.W, PV.X, literal.x,
-; CM-NEXT: 2139095039(3.402823e+38), 2147483647(nan)
-; CM-NEXT: AND_INT T6.X, KC0[8].Z, literal.x,
+; CM-NEXT: SETGT_UINT * T0.W, PV.X, literal.x,
+; CM-NEXT: -16777217(-1.701412e+38), 0(0.000000e+00)
+; CM-NEXT: LSHL T6.X, KC0[8].Z, 1,
; CM-NEXT: CNDE_INT T4.Y, PV.W, 1, 0.0,
-; CM-NEXT: SETGT_INT T2.Z, PV.Y, literal.y,
+; CM-NEXT: SETGT_UINT T2.Z, PV.Y, literal.x,
; CM-NEXT: CNDE_INT * T3.W, PV.X, 1, 0.0,
-; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)
+; CM-NEXT: -16777217(-1.701412e+38), 0(0.000000e+00)
; CM-NEXT: CNDE_INT T4.X, PV.Z, 1, 0.0,
-; CM-NEXT: SETGT_INT T5.Y, PV.X, literal.x,
+; CM-NEXT: SETGT_UINT T5.Y, PV.X, literal.x,
; CM-NEXT: CNDE_INT T3.Z, T3.Y, 1, 0.0,
; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
-; CM-NEXT: 2139095039(3.402823e+38), 48(6.726233e-44)
+; CM-NEXT: -16777217(-1.701412e+38), 48(6.726233e-44)
; CM-NEXT: LSHR T5.X, PV.W, literal.x,
; CM-NEXT: CNDE_INT T3.Y, PV.Y, 1, 0.0,
-; CM-NEXT: SETGT_INT T2.Z, T3.X, literal.y,
+; CM-NEXT: SETGT_UINT T2.Z, T3.X, literal.y,
; CM-NEXT: CNDE_INT * T2.W, T2.Y, 1, 0.0,
-; CM-NEXT: 2(2.802597e-45), 2139095039(3.402823e+38)
+; CM-NEXT: 2(2.802597e-45), -16777217(-1.701412e+38)
; CM-NEXT: CNDE_INT T3.X, PV.Z, 1, 0.0,
-; CM-NEXT: SETGT_INT T1.Y, T1.Y, literal.x,
+; CM-NEXT: SETGT_UINT T1.Y, T1.Y, literal.x,
; CM-NEXT: CNDE_INT T2.Z, T2.X, 1, 0.0,
; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
-; CM-NEXT: 2139095039(3.402823e+38), 32(4.484155e-44)
+; CM-NEXT: -16777217(-1.701412e+38), 32(4.484155e-44)
; CM-NEXT: LSHR T6.X, PV.W, literal.x,
; CM-NEXT: CNDE_INT T2.Y, PV.Y, 1, 0.0,
-; CM-NEXT: SETGT_INT T1.Z, T1.Z, literal.y,
+; CM-NEXT: SETGT_UINT T1.Z, T1.Z, literal.y,
; CM-NEXT: CNDE_INT * T1.W, T1.X, 1, 0.0,
-; CM-NEXT: 2(2.802597e-45), 2139095039(3.402823e+38)
+; CM-NEXT: 2(2.802597e-45), -16777217(-1.701412e+38)
; CM-NEXT: CNDE_INT T2.X, PV.Z, 1, 0.0,
-; CM-NEXT: SETGT_INT T0.Y, T0.Y, literal.x,
+; CM-NEXT: SETGT_UINT T0.Y, T0.Y, literal.x,
; CM-NEXT: CNDE_INT T1.Z, T0.X, 1, 0.0,
; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
-; CM-NEXT: 2139095039(3.402823e+38), 16(2.242078e-44)
+; CM-NEXT: -16777217(-1.701412e+38), 16(2.242078e-44)
; CM-NEXT: LSHR T0.X, PV.W, literal.x,
; CM-NEXT: CNDE_INT T1.Y, PV.Y, 1, 0.0,
-; CM-NEXT: SETGT_INT * T0.W, T0.Z, literal.y,
-; CM-NEXT: 2(2.802597e-45), 2139095039(3.402823e+38)
+; CM-NEXT: SETGT_UINT * T0.W, T0.Z, literal.y,
+; CM-NEXT: 2(2.802597e-45), -16777217(-1.701412e+38)
; CM-NEXT: CNDE_INT * T1.X, PV.W, 1, 0.0,
; CM-NEXT: LSHR * T7.X, KC0[2].Y, literal.x,
; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
diff --git a/llvm/test/CodeGen/PowerPC/fp-classify.ll b/llvm/test/CodeGen/PowerPC/fp-classify.ll
index dc9853ff2e301..22b098dfc0df0 100644
--- a/llvm/test/CodeGen/PowerPC/fp-classify.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-classify.ll
@@ -88,11 +88,9 @@ define zeroext i1 @abs_isinfornanf(float %x) {
; P8-LABEL: abs_isinfornanf:
; P8: # %bb.0: # %entry
; P8-NEXT: xscvdpspn 0, 1
-; P8-NEXT: lis 4, 32639
-; P8-NEXT: ori 4, 4, 65535
; P8-NEXT: mffprwz 3, 0
-; P8-NEXT: clrlwi 3, 3, 1
-; P8-NEXT: sub 3, 4, 3
+; P8-NEXT: rlwinm 3, 3, 9, 24, 31
+; P8-NEXT: subfic 3, 3, 254
; P8-NEXT: rldicl 3, 3, 1, 63
; P8-NEXT: blr
;
@@ -113,14 +111,11 @@ define zeroext i1 @abs_isinfornan(double %x) {
; P8-LABEL: abs_isinfornan:
; P8: # %bb.0: # %entry
; P8-NEXT: mffprd 3, 1
-; P8-NEXT: li 4, -33
-; P8-NEXT: rldicl 4, 4, 47, 1
-; P8-NEXT: sradi 5, 4, 63
-; P8-NEXT: clrldi 3, 3, 1
-; P8-NEXT: rldicl 6, 3, 1, 63
-; P8-NEXT: subc 3, 4, 3
-; P8-NEXT: adde 3, 6, 5
-; P8-NEXT: xori 3, 3, 1
+; P8-NEXT: li 4, 2046
+; P8-NEXT: rldicl 3, 3, 12, 53
+; P8-NEXT: subfic 3, 3, 2046
+; P8-NEXT: subfe 3, 4, 4
+; P8-NEXT: neg 3, 3
; P8-NEXT: blr
;
; P9-LABEL: abs_isinfornan:
@@ -141,16 +136,13 @@ define zeroext i1 @abs_isinfornanq(fp128 %x) {
; P8: # %bb.0: # %entry
; P8-NEXT: xxswapd 0, 34
; P8-NEXT: addi 3, 1, -16
-; P8-NEXT: li 4, -3
+; P8-NEXT: li 4, 32766
; P8-NEXT: stxvd2x 0, 0, 3
-; P8-NEXT: rldicl 4, 4, 47, 1
-; P8-NEXT: ld 3, -8(1)
-; P8-NEXT: sradi 5, 4, 63
-; P8-NEXT: clrldi 3, 3, 1
-; P8-NEXT: rldicl 6, 3, 1, 63
-; P8-NEXT: subc 3, 4, 3
-; P8-NEXT: adde 3, 6, 5
-; P8-NEXT: xori 3, 3, 1
+; P8-NEXT: lhz 3, -2(1)
+; P8-NEXT: clrldi 3, 3, 49
+; P8-NEXT: subfic 3, 3, 32766
+; P8-NEXT: subfe 3, 4, 4
+; P8-NEXT: neg 3, 3
; P8-NEXT: blr
;
; P9-LABEL: abs_isinfornanq:
diff --git a/llvm/test/CodeGen/RISCV/float-intrinsics.ll b/llvm/test/CodeGen/RISCV/float-intrinsics.ll
index 5f673ac17d569..7298934367edf 100644
--- a/llvm/test/CodeGen/RISCV/float-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/float-intrinsics.ll
@@ -2280,17 +2280,15 @@ define i1 @isfinite_fpclass(float %x) {
; RV32I-LABEL: isfinite_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 1
-; RV32I-NEXT: srli a0, a0, 1
-; RV32I-NEXT: lui a1, 522240
-; RV32I-NEXT: slt a0, a0, a1
+; RV32I-NEXT: srli a0, a0, 24
+; RV32I-NEXT: sltiu a0, a0, 255
; RV32I-NEXT: ret
;
; RV64I-LABEL: isfinite_fpclass:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 33
-; RV64I-NEXT: srli a0, a0, 33
-; RV64I-NEXT: lui a1, 522240
-; RV64I-NEXT: slt a0, a0, a1
+; RV64I-NEXT: srli a0, a0, 56
+; RV64I-NEXT: sltiu a0, a0, 255
; RV64I-NEXT: ret
%1 = call i1 @llvm.is.fpclass.f32(float %x, i32 504) ; 0x1f8 = "finite"
ret i1 %1
@@ -2445,19 +2443,17 @@ define i1 @isnotfinite_fpclass(float %x) {
; RV32I-LABEL: isnotfinite_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 1
-; RV32I-NEXT: lui a1, 522240
-; RV32I-NEXT: srli a0, a0, 1
-; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: slt a0, a1, a0
+; RV32I-NEXT: srli a0, a0, 24
+; RV32I-NEXT: sltiu a0, a0, 255
+; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: isnotfinite_fpclass:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 33
-; RV64I-NEXT: lui a1, 522240
-; RV64I-NEXT: srli a0, a0, 33
-; RV64I-NEXT: addi a1, a1, -1
-; RV64I-NEXT: slt a0, a1, a0
+; RV64I-NEXT: srli a0, a0, 56
+; RV64I-NEXT: sltiu a0, a0, 255
+; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
%1 = call i1 @llvm.is.fpclass.f32(float %x, i32 519) ; ox207 = "inf|nan"
ret i1 %1
diff --git a/llvm/test/CodeGen/X86/is_fpclass.ll b/llvm/test/CodeGen/X86/is_fpclass.ll
index 97136dafa6c2c..ccf1893ce70dc 100644
--- a/llvm/test/CodeGen/X86/is_fpclass.ll
+++ b/llvm/test/CodeGen/X86/is_fpclass.ll
@@ -240,18 +240,18 @@ entry:
define i1 @isfinite_f(float %x) {
; X86-LABEL: isfinite_f:
; X86: # %bb.0: # %entry
-; X86-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
-; X86-NEXT: andl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X86-NEXT: setl %al
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: addl %eax, %eax
+; X86-NEXT: cmpl $-16777216, %eax # imm = 0xFF000000
+; X86-NEXT: setb %al
; X86-NEXT: retl
;
; X64-LABEL: isfinite_f:
; X64: # %bb.0: # %entry
; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: setl %al
+; X64-NEXT: addl %eax, %eax
+; X64-NEXT: cmpl $-16777216, %eax # imm = 0xFF000000
+; X64-NEXT: setb %al
; X64-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 504) ; 0x1f8 = "finite"
@@ -261,18 +261,18 @@ entry:
define i1 @not_isfinite_f(float %x) {
; X86-LABEL: not_isfinite_f:
; X86: # %bb.0: # %entry
-; X86-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
-; X86-NEXT: andl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X86-NEXT: setge %al
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: addl %eax, %eax
+; X86-NEXT: cmpl $-16777216, %eax # imm = 0xFF000000
+; X86-NEXT: setae %al
; X86-NEXT: retl
;
; X64-LABEL: not_isfinite_f:
; X64: # %bb.0: # %entry
; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: setge %al
+; X64-NEXT: addl %eax, %eax
+; X64-NEXT: cmpl $-16777216, %eax # imm = 0xFF000000
+; X64-NEXT: setae %al
; X64-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 519) ; ~0x1f8 = "~finite"
@@ -1017,18 +1017,18 @@ entry:
define i1 @isfinite_f_strictfp(float %x) strictfp {
; X86-LABEL: isfinite_f_strictfp:
; X86: # %bb.0: # %entry
-; X86-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
-; X86-NEXT: andl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X86-NEXT: setl %al
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: addl %eax, %eax
+; X86-NEXT: cmpl $-16777216, %eax # imm = 0xFF000000
+; X86-NEXT: setb %al
; X86-NEXT: retl
;
; X64-LABEL: isfinite_f_strictfp:
; X64: # %bb.0: # %entry
; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: setl %al
+; X64-NEXT: addl %eax, %eax
+; X64-NEXT: cmpl $-16777216, %eax # imm = 0xFF000000
+; X64-NEXT: setb %al
; X64-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 504) strictfp ; 0x1f8 = "finite"
@@ -1038,18 +1038,18 @@ entry:
define i1 @not_isfinite_f_strictfp(float %x) strictfp {
; X86-LABEL: not_isfinite_f_strictfp:
; X86: # %bb.0: # %entry
-; X86-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
-; X86-NEXT: andl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X86-NEXT: setge %al
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: addl %eax, %eax
+; X86-NEXT: cmpl $-16777216, %eax # imm = 0xFF000000
+; X86-NEXT: setae %al
; X86-NEXT: retl
;
; X64-LABEL: not_isfinite_f_strictfp:
; X64: # %bb.0: # %entry
; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: setge %al
+; X64-NEXT: addl %eax, %eax
+; X64-NEXT: cmpl $-16777216, %eax # imm = 0xFF000000
+; X64-NEXT: setae %al
; X64-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 519) strictfp ; ~0x1f8 = ~"finite"
@@ -1150,31 +1150,21 @@ entry:
define i1 @isfinite_d(double %x) {
; X86-LABEL: isfinite_d:
; X86: # %bb.0: # %entry
-; X86-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
-; X86-NEXT: andl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: cmpl $2146435072, %eax # imm = 0x7FF00000
-; X86-NEXT: setl %al
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: shrl $20, %eax
+; X86-NEXT: andl $2047, %eax # imm = 0x7FF
+; X86-NEXT: cmpl $2047, %eax # imm = 0x7FF
+; X86-NEXT: setb %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: isfinite_d:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movq %xmm0, %rax
-; X64-GENERIC-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
-; X64-GENERIC-NEXT: andq %rax, %rcx
-; X64-GENERIC-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
-; X64-GENERIC-NEXT: cmpq %rax, %rcx
-; X64-GENERIC-NEXT: setl %al
-; X64-GENERIC-NEXT: retq
-;
-; X64-NDD-LABEL: isfinite_d:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movq %xmm0, %rax
-; X64-NDD-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
-; X64-NDD-NEXT: andq %rcx, %rax
-; X64-NDD-NEXT: movabsq $9218868437227405312, %rcx # imm = 0x7FF0000000000000
-; X64-NDD-NEXT: cmpq %rcx, %rax
-; X64-NDD-NEXT: setl %al
-; X64-NDD-NEXT: retq
+; X64-LABEL: isfinite_d:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movq %xmm0, %rax
+; X64-NEXT: shrq $52, %rax
+; X64-NEXT: andl $2047, %eax # imm = 0x7FF
+; X64-NEXT: cmpl $2047, %eax # imm = 0x7FF
+; X64-NEXT: setb %al
+; X64-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 504) ; 0x1f8 = "finite"
ret i1 %0
@@ -2032,18 +2022,18 @@ entry:
define i1 @isinf_or_nan_f(float %x) {
; X86-LABEL: isinf_or_nan_f:
; X86: # %bb.0: # %entry
-; X86-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
-; X86-NEXT: andl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X86-NEXT: setge %al
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: addl %eax, %eax
+; X86-NEXT: cmpl $-16777216, %eax # imm = 0xFF000000
+; X86-NEXT: setae %al
; X86-NEXT: retl
;
; X64-LABEL: isinf_or_nan_f:
; X64: # %bb.0: # %entry
; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: setge %al
+; X64-NEXT: addl %eax, %eax
+; X64-NEXT: cmpl $-16777216, %eax # imm = 0xFF000000
+; X64-NEXT: setae %al
; X64-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 519) ; 0x204|0x3 = "inf|nan"
@@ -2053,18 +2043,18 @@ entry:
define i1 @not_isinf_or_nan_f(float %x) {
; X86-LABEL: not_isinf_or_nan_f:
; X86: # %bb.0: # %entry
-; X86-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
-; X86-NEXT: andl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X86-NEXT: setl %al
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: addl %eax, %eax
+; X86-NEXT: cmpl $-16777216, %eax # imm = 0xFF000000
+; X86-NEXT: setb %al
; X86-NEXT: retl
;
; X64-LABEL: not_isinf_or_nan_f:
; X64: # %bb.0: # %entry
; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: setl %al
+; X64-NEXT: addl %eax, %eax
+; X64-NEXT: cmpl $-16777216, %eax # imm = 0xFF000000
+; X64-NEXT: setb %al
; X64-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 504) ; ~(0x204|0x3) = "~(inf|nan)"
@@ -2277,10 +2267,11 @@ define i1 @not_is_plus_inf_or_snan_f(float %x) {
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
; X86-NEXT: sete %cl
-; X86-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X86-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X86-NEXT: setl %dl
+; X86-NEXT: leal (%eax,%eax), %edx
+; X86-NEXT: cmpl $-16777216, %edx # imm = 0xFF000000
+; X86-NEXT: setb %dl
; X86-NEXT: orb %cl, %dl
+; X86-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
; X86-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
; X86-NEXT: setge %al
; X86-NEXT: orb %dl, %al
@@ -2291,10 +2282,11 @@ define i1 @not_is_plus_inf_or_snan_f(float %x) {
; X64-GENERIC-NEXT: movd %xmm0, %eax
; X64-GENERIC-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
; X64-GENERIC-NEXT: sete %cl
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: setl %dl
+; X64-GENERIC-NEXT: leal (%rax,%rax), %edx
+; X64-GENERIC-NEXT: cmpl $-16777216, %edx # imm = 0xFF000000
+; X64-GENERIC-NEXT: setb %dl
; X64-GENERIC-NEXT: orb %cl, %dl
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
; X64-GENERIC-NEXT: setge %al
; X64-GENERIC-NEXT: orb %dl, %al
@@ -2305,10 +2297,11 @@ define i1 @not_is_plus_inf_or_snan_f(float %x) {
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
; X64-NDD-NEXT: sete %cl
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setl %dl
+; X64-NDD-NEXT: leal (%rax,%rax), %edx
+; X64-NDD-NEXT: cmpl $-16777216, %edx # imm = 0xFF000000
+; X64-NDD-NEXT: setb %dl
; X64-NDD-NEXT: orb %dl, %cl
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
; X64-NDD-NEXT: setge %al
; X64-NDD-NEXT: orb %cl, %al
@@ -2326,14 +2319,15 @@ define i1 @not_is_plus_inf_or_qnan_f(float %x) {
; X86-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
; X86-NEXT: setl %dl
; X86-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
-; X86-NEXT: setge %dh
-; X86-NEXT: andb %dl, %dh
+; X86-NEXT: setge %cl
+; X86-NEXT: andb %dl, %cl
; X86-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
; X86-NEXT: sete %dl
-; X86-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000
-; X86-NEXT: setl %al
+; X86-NEXT: addl %eax, %eax
+; X86-NEXT: cmpl $-16777216, %eax # imm = 0xFF000000
+; X86-NEXT: setb %al
; X86-NEXT: orb %dl, %al
-; X86-NEXT: orb %dh, %al
+; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
; X64-GENERIC-LABEL: not_is_plus_inf_or_qnan_f:
@@ -2344,14 +2338,15 @@ define i1 @not_is_plus_inf_or_qnan_f(float %x) {
; X64-GENERIC-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
; X64-GENERIC-NEXT: setl %dl
; X64-GENERIC-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
-; X64-GENERIC-NEXT: setge %sil
-; X64-GENERIC-NEXT: andb %dl, %sil
+; X64-GENERIC-NEXT: setge %cl
+; X64-GENERIC-NEXT: andb %dl, %cl
; X64-GENERIC-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
; X64-GENERIC-NEXT: sete %dl
-; X64-GENERIC-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000
-; X64-GENERIC-NEXT: setl %al
+; X64-GENERIC-NEXT: addl %eax, %eax
+; X64-GENERIC-NEXT: cmpl $-16777216, %eax # imm = 0xFF000000
+; X64-GENERIC-NEXT: setb %al
; X64-GENERIC-NEXT: orb %dl, %al
-; X64-GENERIC-NEXT: orb %sil, %al
+; X64-GENERIC-NEXT: orb %cl, %al
; X64-GENERIC-NEXT: retq
;
; X64-NDD-LABEL: not_is_plus_inf_or_qnan_f:
@@ -2361,14 +2356,15 @@ define i1 @not_is_plus_inf_or_qnan_f(float %x) {
; X64-NDD-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
; X64-NDD-NEXT: setl %dl
; X64-NDD-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
-; X64-NDD-NEXT: setge %sil
-; X64-NDD-NEXT: andb %sil, %dl
+; X64-NDD-NEXT: setge %cl
+; X64-NDD-NEXT: andb %dl, %cl
; X64-NDD-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
-; X64-NDD-NEXT: sete %al
-; X64-NDD-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000
-; X64-NDD-NEXT: setl %cl
-; X64-NDD-NEXT: orb %cl, %al
+; X64-NDD-NEXT: sete %dl
+; X64-NDD-NEXT: addl %eax, %eax
+; X64-NDD-NEXT: cmpl $-16777216, %eax # imm = 0xFF000000
+; X64-NDD-NEXT: setb %al
; X64-NDD-NEXT: orb %dl, %al
+; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 509) ; ~(+inf|qnan)
ret i1 %class
@@ -2454,10 +2450,11 @@ define i1 @not_is_minus_inf_or_snan_f(float %x) {
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
; X86-NEXT: sete %cl
-; X86-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X86-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X86-NEXT: setl %dl
+; X86-NEXT: leal (%eax,%eax), %edx
+; X86-NEXT: cmpl $-16777216, %edx # imm = 0xFF000000
+; X86-NEXT: setb %dl
; X86-NEXT: orb %cl, %dl
+; X86-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
; X86-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
; X86-NEXT: setge %al
; X86-NEXT: orb %dl, %al
@@ -2468,10 +2465,11 @@ define i1 @not_is_minus_inf_or_snan_f(float %x) {
; X64-GENERIC-NEXT: movd %xmm0, %eax
; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
; X64-GENERIC-NEXT: sete %cl
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: setl %dl
+; X64-GENERIC-NEXT: leal (%rax,%rax), %edx
+; X64-GENERIC-NEXT: cmpl $-16777216, %edx # imm = 0xFF000000
+; X64-GENERIC-NEXT: setb %dl
; X64-GENERIC-NEXT: orb %cl, %dl
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
; X64-GENERIC-NEXT: setge %al
; X64-GENERIC-NEXT: orb %dl, %al
@@ -2482,10 +2480,11 @@ define i1 @not_is_minus_inf_or_snan_f(float %x) {
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
; X64-NDD-NEXT: sete %cl
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setl %dl
+; X64-NDD-NEXT: leal (%rax,%rax), %edx
+; X64-NDD-NEXT: cmpl $-16777216, %edx # imm = 0xFF000000
+; X64-NDD-NEXT: setb %dl
; X64-NDD-NEXT: orb %dl, %cl
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
; X64-NDD-NEXT: setge %al
; X64-NDD-NEXT: orb %cl, %al
@@ -2503,14 +2502,15 @@ define i1 @not_is_minus_inf_or_qnan_f(float %x) {
; X86-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
; X86-NEXT: setl %dl
; X86-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
-; X86-NEXT: setge %dh
-; X86-NEXT: andb %dl, %dh
+; X86-NEXT: setge %cl
+; X86-NEXT: andb %dl, %cl
; X86-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
; X86-NEXT: sete %dl
-; X86-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000
-; X86-NEXT: setl %al
+; X86-NEXT: addl %eax, %eax
+; X86-NEXT: cmpl $-16777216, %eax # imm = 0xFF000000
+; X86-NEXT: setb %al
; X86-NEXT: orb %dl, %al
-; X86-NEXT: orb %dh, %al
+; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
; X64-GENERIC-LABEL: not_is_minus_inf_or_qnan_f:
@@ -2521,14 +2521,15 @@ define i1 @not_is_minus_inf_or_qnan_f(float %x) {
; X64-GENERIC-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
; X64-GENERIC-NEXT: setl %dl
; X64-GENERIC-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
-; X64-GENERIC-NEXT: setge %sil
-; X64-GENERIC-NEXT: andb %dl, %sil
+; X64-GENERIC-NEXT: setge %cl
+; X64-GENERIC-NEXT: andb %dl, %cl
; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
; X64-GENERIC-NEXT: sete %dl
-; X64-GENERIC-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000
-; X64-GENERIC-NEXT: setl %al
+; X64-GENERIC-NEXT: addl %eax, %eax
+; X64-GENERIC-NEXT: cmpl $-16777216, %eax # imm = 0xFF000000
+; X64-GENERIC-NEXT: setb %al
; X64-GENERIC-NEXT: orb %dl, %al
-; X64-GENERIC-NEXT: orb %sil, %al
+; X64-GENERIC-NEXT: orb %cl, %al
; X64-GENERIC-NEXT: retq
;
; X64-NDD-LABEL: not_is_minus_inf_or_qnan_f:
@@ -2538,14 +2539,15 @@ define i1 @not_is_minus_inf_or_qnan_f(float %x) {
; X64-NDD-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
; X64-NDD-NEXT: setl %dl
; X64-NDD-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
-; X64-NDD-NEXT: setge %sil
-; X64-NDD-NEXT: andb %sil, %dl
+; X64-NDD-NEXT: setge %cl
+; X64-NDD-NEXT: andb %dl, %cl
; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: sete %al
-; X64-NDD-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000
-; X64-NDD-NEXT: setl %cl
-; X64-NDD-NEXT: orb %cl, %al
+; X64-NDD-NEXT: sete %dl
+; X64-NDD-NEXT: addl %eax, %eax
+; X64-NDD-NEXT: cmpl $-16777216, %eax # imm = 0xFF000000
+; X64-NDD-NEXT: setb %al
; X64-NDD-NEXT: orb %dl, %al
+; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1017) ; "-inf|qnan"
ret i1 %class
diff --git a/llvm/test/CodeGen/X86/isel-fpclass.ll b/llvm/test/CodeGen/X86/isel-fpclass.ll
index df04b673d8223..25f76bb3efcc7 100644
--- a/llvm/test/CodeGen/X86/isel-fpclass.ll
+++ b/llvm/test/CodeGen/X86/isel-fpclass.ll
@@ -310,18 +310,18 @@ entry:
define i1 @isfinite_f(float %x) nounwind {
; X86-LABEL: isfinite_f:
; X86: # %bb.0: # %entry
-; X86-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
-; X86-NEXT: andl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X86-NEXT: setl %al
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: addl %eax, %eax
+; X86-NEXT: cmpl $-16777216, %eax # imm = 0xFF000000
+; X86-NEXT: setb %al
; X86-NEXT: retl
;
; X64-LABEL: isfinite_f:
; X64: # %bb.0: # %entry
; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: setl %al
+; X64-NEXT: addl %eax, %eax
+; X64-NEXT: cmpl $-16777216, %eax # imm = 0xFF000000
+; X64-NEXT: setb %al
; X64-NEXT: retq
;
; X86-FASTISEL-LABEL: isfinite_f:
@@ -329,10 +329,10 @@ define i1 @isfinite_f(float %x) nounwind {
; X86-FASTISEL-NEXT: pushl %eax
; X86-FASTISEL-NEXT: flds {{[0-9]+}}(%esp)
; X86-FASTISEL-NEXT: fstps (%esp)
-; X86-FASTISEL-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
-; X86-FASTISEL-NEXT: andl (%esp), %eax
-; X86-FASTISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X86-FASTISEL-NEXT: setl %al
+; X86-FASTISEL-NEXT: movl (%esp), %eax
+; X86-FASTISEL-NEXT: addl %eax, %eax
+; X86-FASTISEL-NEXT: cmpl $-16777216, %eax # imm = 0xFF000000
+; X86-FASTISEL-NEXT: setb %al
; X86-FASTISEL-NEXT: popl %ecx
; X86-FASTISEL-NEXT: retl
entry:
@@ -343,18 +343,18 @@ entry:
define i1 @not_isfinite_f(float %x) nounwind {
; X86-LABEL: not_isfinite_f:
; X86: # %bb.0: # %entry
-; X86-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
-; X86-NEXT: andl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X86-NEXT: setge %al
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: addl %eax, %eax
+; X86-NEXT: cmpl $-16777216, %eax # imm = 0xFF000000
+; X86-NEXT: setae %al
; X86-NEXT: retl
;
; X64-LABEL: not_isfinite_f:
; X64: # %bb.0: # %entry
; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: setge %al
+; X64-NEXT: addl %eax, %eax
+; X64-NEXT: cmpl $-16777216, %eax # imm = 0xFF000000
+; X64-NEXT: setae %al
; X64-NEXT: retq
;
; X86-FASTISEL-LABEL: not_isfinite_f:
@@ -362,10 +362,10 @@ define i1 @not_isfinite_f(float %x) nounwind {
; X86-FASTISEL-NEXT: pushl %eax
; X86-FASTISEL-NEXT: flds {{[0-9]+}}(%esp)
; X86-FASTISEL-NEXT: fstps (%esp)
-; X86-FASTISEL-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
-; X86-FASTISEL-NEXT: andl (%esp), %eax
-; X86-FASTISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X86-FASTISEL-NEXT: setge %al
+; X86-FASTISEL-NEXT: movl (%esp), %eax
+; X86-FASTISEL-NEXT: addl %eax, %eax
+; X86-FASTISEL-NEXT: cmpl $-16777216, %eax # imm = 0xFF000000
+; X86-FASTISEL-NEXT: setae %al
; X86-FASTISEL-NEXT: popl %ecx
; X86-FASTISEL-NEXT: retl
entry:
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