[clang] [llvm] [RISCV] Add Svrsw60t59b extension (PR #132321)
Mingzhu Yan via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 26 22:40:34 PST 2025
https://github.com/trdthg updated https://github.com/llvm/llvm-project/pull/132321
>From f9ad1edf3f00e858ae7da94edb4a4ecc4026b3a7 Mon Sep 17 00:00:00 2001
From: Mingzhu Yan <yanmingzhu at iscas.ac.cn>
Date: Thu, 27 Nov 2025 06:39:54 +0000
Subject: [PATCH] [RISCV] Add Svrsw60t59b extension
---
clang/test/Driver/print-supported-extensions-riscv.c | 1 +
clang/test/Preprocessor/riscv-target-features.c | 9 +++++++++
llvm/docs/RISCVUsage.rst | 1 +
llvm/lib/Target/RISCV/RISCVFeatures.td | 4 ++++
llvm/test/CodeGen/RISCV/attributes.ll | 8 ++++++--
llvm/test/CodeGen/RISCV/features-info.ll | 1 +
llvm/test/MC/RISCV/attribute-arch.s | 6 ++++++
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 1 +
8 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 7b4f46cdb4443..8b43b255864d0 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -156,6 +156,7 @@
// CHECK-NEXT: svinval 1.0 'Svinval' (Fine-Grained Address-Translation Cache Invalidation)
// CHECK-NEXT: svnapot 1.0 'Svnapot' (NAPOT Translation Contiguity)
// CHECK-NEXT: svpbmt 1.0 'Svpbmt' (Page-Based Memory Types)
+// CHECK-NEXT: svrsw60t59b 1.0 'Svrsw60t59b' (PTE Reserved-for-Software Bits 60-59)
// CHECK-NEXT: svvptc 1.0 'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
// CHECK-NEXT: xandesvdot 5.0 'XAndesVDot' (Andes Vector Dot Product Extension)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index e3b456e0245f7..ef56d0d8aea48 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -56,6 +56,7 @@
// CHECK-NOT: __riscv_svinval {{.*$}}
// CHECK-NOT: __riscv_svnapot {{.*$}}
// CHECK-NOT: __riscv_svpbmt {{.*$}}
+// CHECK-NOT: __riscv_svrsw60t59b {{.*$}}
// CHECK-NOT: __riscv_svvptc {{.*$}}
// CHECK-NOT: __riscv_v {{.*$}}
// CHECK-NOT: __riscv_v_elen {{.*$}}
@@ -546,6 +547,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SVVPTC-EXT %s
// CHECK-SVVPTC-EXT: __riscv_svvptc 1000000{{$}}
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32isvrsw60t59b -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SVRSW60T59B-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64isvrsw60t59b -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SVRSW60T59B-EXT %s
+// CHECK-SVRSW60T59B-EXT: __riscv_svrsw60t59b 1000000{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32iv1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 9ac21052eb66c..e5b3d4365e1d3 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -160,6 +160,7 @@ on support follow.
``Svinval`` Assembly Support
``Svnapot`` Assembly Support
``Svpbmt`` Supported
+ ``Svrsw60t59b`` Supported
``Svvptc`` Supported
``V`` Supported
``Za128rs`` Supported (`See note <#riscv-profiles-extensions-note>`__)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 86576ed190d14..50d2f33b59d86 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1009,6 +1009,10 @@ def FeatureStdExtSvnapot
def FeatureStdExtSvpbmt
: RISCVExtension<1, 0, "Page-Based Memory Types">;
+def FeatureStdExtSvrsw60t59b
+ : RISCVExtension<1, 0,
+ "PTE Reserved-for-Software Bits 60-59">;
+
def FeatureStdExtSvvptc
: RISCVExtension<1, 0,
"Obviating Memory-Management Instructions after Marking PTEs Valid">;
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 68b472936ecdf..35e963ec99893 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -64,11 +64,12 @@
; RUN: llc -mtriple=riscv32 -mattr=+svade %s -o - | FileCheck --check-prefixes=CHECK,RV32SVADE %s
; RUN: llc -mtriple=riscv32 -mattr=+svadu %s -o - | FileCheck --check-prefixes=CHECK,RV32SVADU %s
; RUN: llc -mtriple=riscv32 -mattr=+svbare %s -o - | FileCheck --check-prefixes=CHECK,RV32SVBARE %s
+; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV32SVINVAL %s
; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefixes=CHECK,RV32SVNAPOT %s
; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck --check-prefixes=CHECK,RV32SVPBMT %s
+; RUN: llc -mtriple=riscv32 -mattr=+svrsw60t59b %s -o - | FileCheck --check-prefixes=CHECK,RV32SVRSW60T59B %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-svukte %s -o - | FileCheck --check-prefixes=CHECK,RV32SVUKTE %s
; RUN: llc -mtriple=riscv32 -mattr=+svvptc %s -o - | FileCheck --check-prefixes=CHECK,RV32SVVPTC %s
-; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV32SVINVAL %s
; RUN: llc -mtriple=riscv32 -mattr=+xcvalu %s -o - | FileCheck --check-prefix=RV32XCVALU %s
; RUN: llc -mtriple=riscv32 -mattr=+xcvbitmanip %s -o - | FileCheck --check-prefix=RV32XCVBITMANIP %s
; RUN: llc -mtriple=riscv32 -mattr=+xcvelw %s -o - | FileCheck --check-prefix=RV32XCVELW %s
@@ -241,9 +242,10 @@
; RUN: llc -mtriple=riscv64 -mattr=+svbare %s -o - | FileCheck --check-prefixes=CHECK,RV64SVBARE %s
; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefixes=CHECK,RV64SVNAPOT %s
; RUN: llc -mtriple=riscv64 -mattr=+svpbmt %s -o - | FileCheck --check-prefixes=CHECK,RV64SVPBMT %s
+; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV64SVINVAL %s
+; RUN: llc -mtriple=riscv64 -mattr=+svrsw60t59b %s -o - | FileCheck --check-prefixes=CHECK,RV64SVRSW60T59B %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-svukte %s -o - | FileCheck --check-prefixes=CHECK,RV64SVUKTE %s
; RUN: llc -mtriple=riscv64 -mattr=+svvptc %s -o - | FileCheck --check-prefixes=CHECK,RV64SVVPTC %s
-; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV64SVINVAL %s
; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck --check-prefixes=CHECK,RV64XVENTANACONDOPS %s
; RUN: llc -mtriple=riscv64 -mattr=+xsfvfwmaccqqq %s -o - | FileCheck --check-prefix=RV64XSFVFWMACCQQQ %s
; RUN: llc -mtriple=riscv64 -mattr=+xtheadba %s -o - | FileCheck --check-prefixes=CHECK,RV64XTHEADBA %s
@@ -417,6 +419,7 @@
; RV32SVPBMT: .attribute 5, "rv32i2p1_svpbmt1p0"
; RV32SVUKTE: .attribute 5, "rv32i2p1_svukte0p3"
; RV32SVVPTC: .attribute 5, "rv32i2p1_svvptc1p0"
+; RV32SVRSW60T59B: .attribute 5, "rv32i2p1_svrsw60t59b1p0"
; RV32SVINVAL: .attribute 5, "rv32i2p1_svinval1p0"
; RV32XCVALU: .attribute 5, "rv32i2p1_xcvalu1p0"
; RV32XCVBITMANIP: .attribute 5, "rv32i2p1_xcvbitmanip1p0"
@@ -593,6 +596,7 @@
; RV64SVPBMT: .attribute 5, "rv64i2p1_svpbmt1p0"
; RV64SVUKTE: .attribute 5, "rv64i2p1_svukte0p3"
; RV64SVVPTC: .attribute 5, "rv64i2p1_svvptc1p0"
+; RV64SVRSW60T59B: .attribute 5, "rv64i2p1_svrsw60t59b1p0"
; RV64SVINVAL: .attribute 5, "rv64i2p1_svinval1p0"
; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p1_xventanacondops1p0"
; RV64XSFVFWMACCQQQ: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0_xsfvfwmaccqqq1p0"
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index 6c2b8af55acce..37c416d8a615b 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -163,6 +163,7 @@
; CHECK-NEXT: svinval - 'Svinval' (Fine-Grained Address-Translation Cache Invalidation).
; CHECK-NEXT: svnapot - 'Svnapot' (NAPOT Translation Contiguity).
; CHECK-NEXT: svpbmt - 'Svpbmt' (Page-Based Memory Types).
+; CHECK-NEXT: svrsw60t59b - 'Svrsw60t59b' (PTE Reserved-for-Software Bits 60-59).
; CHECK-NEXT: svvptc - 'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid).
; CHECK-NEXT: tagged-globals - Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits.
; CHECK-NEXT: unaligned-scalar-mem - Has reasonably performant unaligned scalar loads and stores.
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 202f54172ca74..5e19d800374eb 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -393,6 +393,12 @@
.attribute arch, "rv32i_svbare1p0"
# CHECK: attribute 5, "rv32i2p1_svbare1p0"
+.attribute arch, "rv32i_svrsw60t59b1p0"
+# CHECK: attribute 5, "rv32i2p1_svrsw60t59b1p0"
+
+.attribute arch, "rv64i_svrsw60t59b1p0"
+# CHECK: attribute 5, "rv64i2p1_svrsw60t59b1p0"
+
.attribute arch, "rv32i_svukte0p3"
# CHECK: attribute 5, "rv32i2p1_svukte0p3"
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 7a2539e80388c..9d3db7dbf9fbd 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1127,6 +1127,7 @@ R"(All available -march extensions for RISC-V
svinval 1.0
svnapot 1.0
svpbmt 1.0
+ svrsw60t59b 1.0
svvptc 1.0
xandesperf 5.0
xandesvdot 5.0
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