[llvm] [RISCV] Use vsetivli instead of `x0,x0` form to retain SEW/LMUL when AVL is imm (PR #169307)

[Pengcheng Wang via llvm-commits]

wangpc-pp wrote:

> > > vsetvli x0, x0 can't change vl. It can only change vtype and set vill. If the decoder was able to retrieve the vl from a vsetvli, it has to remember it for each subsequent vector instruction. Wouldn't it also remember it across the the vsetvli x0, x0?
> > 
> > 
> > Yes, that's correct for in-order, I understand that. Supposed that there is an OoO RVV implementation (like Xiangshan) and `vl` can be renamed, my motivation is that for `vsetivli` we can get `vl` in the decode stage, while for `vsetvli zero,zero`, the `vl` should be renamed and that will be 1 or more cycles later.
> 
> If vsetivli can get the vl in the decode stage, it needs to make it available to later vectors instructions in program order. The spec says you can assume that vsetvli x0, x0 doesn't change the VL. Wouldn't a vsetvli x0, x0 have access to the vl from an earlier vsetivli like any other vector instruction and not need to rename it?

You are right. I talked with some people and the conclusion is that there should be no big difference between `vsetvli x0, x0` and `vsetivli`. `vsetivli` will occupy a `vl` register file but the register files can be only `log_2(VLMAX_M8)` bits so the number of vl register files can be large. I would say there should be no uarch difference if the implementation is optimal. :-)

Is this PR still valuable from the perspective of reducing more `vtype` toggles? Or I will close it. WDYT?

https://github.com/llvm/llvm-project/pull/169307