[llvm] [Exegesis][RISCV] Support C_LDSP for llvm-exegesis (PR #169660)

[Min-Yih Hsu via llvm-commits]

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@@ -46,3 +46,12 @@ C_SRLI-NEXT: key:
 C_SRLI-NEXT:   instructions:
 C_SRLI-NEXT:     - 'C_SRLI [[REG101:X[0-9]+]] [[REG102:X[0-9]+]] [[IMM10:i_0x[0-9]+]]'
 C_SRLI-DAG: ...
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-name=C_LDSP -mattr=+c | FileCheck --check-prefix=C_LDSP %s
+
+C_LDSP:      ---
+C_LDSP-NEXT: mode: latency
+C_LDSP-NEXT: key:
+C_LDSP-NEXT:   instructions:
+C_LDSP-NEXT:     - 'C_LDSP [[REG111:X[0-9]+]] X2 [[IMM11:i_0x[0-9]+]]'
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mshockwave wrote:

so this will effectively generate sequence like
```
C_LDSP X10, X2, 0
C_LDSP X10, X2, 0
C_LDSP X10, X2, 0
...
```
But as you might also notice: this is not serial. Ideally it'll be great if we can generate
```
C_LDSP X2, X2, 0
C_LDSP X2, X2, 0
C_LDSP X2, X2, 0
...
```
To do this, we might need to teach it to use a different scratch memory register instead of X10.

https://github.com/llvm/llvm-project/pull/169660