[llvm] [AMDGPU] Sink uniform buffer address offsets into soffset (PR #169230)

[Krzysztof Drewniak via llvm-commits]

krzysz00 wrote:

(Noting that I have seen this PR and should be reminded to read it after Thanksgiving)

Also, re voffset/soffset/..., I'm just going to write out what I think might be a subtlety here around alignment.

```
let v0 = ...(align 4)
let s0 = ...(align 4)
let v1 = v0 + s0 + 4

I0: buffer_load_dword rsrc, (voffset = v1) 
<=>
I1: buffer_load_dword rsrc, (vOffset = v0, sOffset = s0, immOffset = 4)

;;; However?

let v2 = v0 + 3
let s1 = s0 + 1
I2: buffer_load_dword rsrc (voffset = v2, soffset = s1)
<?=>
I3: buffer_load_dword rsrc, (vOffset = v0, soffset = s0, immOffset = 4)
```

These are the bounds checking expressions for those four load instructions (on GCN) (as I understand them currently)

```
I0: (v0 + s0 + 4) +[unsigned,saturating] 4 >[unsigned] R
I1: v0 +[?] +[usat] 4 >[u] R -[unsigned,negative => 0] s0
I2: (v0 + 3) +[usat] 4 >[u] R -[u,clamping] (s0 + 1)
I3: v0 +[?] +[usat] 4 >[u] R -[u,clamping] s0
```

(I don't know and don't want to test right this second what the overflow behavior of VOFFSET + IMMOFFSET is, hence the `+[?]` syntax there - I suspect it's something that allows the existing VOFFSET => VOFFSET + IMMOFFSET transformation to take place ... unless it isn't)

I suspect this'll require a bit of testing just to make sure, because some of this shuffling around the inequality results in alive2 complaining once you try and leave the realm of pure integers.

(This also raises the possibility that going from `voffset = v0 + 4` to `voffset = v0, immOffset = 4` isn't correct, but ... it is, so I suspect I've got the problem modeled subtly wrong)

https://github.com/llvm/llvm-project/pull/169230