[llvm] [Exegesis][RISCV] Support C_LDSP for llvm-exegesis (PR #169660)

[Shaoce SUN via llvm-commits]

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@@ -819,6 +819,14 @@ void ExegesisRISCVTarget::fillMemoryOperands(InstructionTemplate &IT,
 
   assert(MemOp.isReg() && "Memory operand expected to be register");
 
+  unsigned Opcode = I.getOpcode();
+  if (Opcode == RISCV::C_LDSP || Opcode == RISCV::C_LWSP ||
+      Opcode == RISCV::C_SDSP || Opcode == RISCV::C_SWSP) {
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sunshaoce wrote:

I tested some instructions, but none of them can be measured:
```
C_FLDSP: No strategy found to make the execution serial
C_FSDSP: No strategy found to make the execution serial
C_FLWSP: No strategy found to make the execution serial
C_FSWSP: No strategy found to make the execution serial
```

https://github.com/llvm/llvm-project/pull/169660