[llvm] [AArch64] Lower v8bf16 FMUL to BFMLAL top/bottom with +sve (PR #169655)
Sam Tebbs via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 26 07:56:09 PST 2025
================
@@ -7697,37 +7701,59 @@ SDValue AArch64TargetLowering::LowerFMUL(SDValue Op, SelectionDAG &DAG) const {
};
};
- auto ReinterpretCast = [&](SDValue Value, EVT VT) {
- if (VT == Value.getValueType())
+ auto Reinterpret = [&](SDValue Value, EVT VT) {
+ EVT SrcVT = Value.getValueType();
+ if (VT == SrcVT)
return Value;
+ if (SrcVT.isFixedLengthVector())
+ return convertToScalableVector(DAG, VT, Value);
----------------
SamTebbs33 wrote:
Should this be `SrcVT` instead of `VT`? If so then it looks like we need some test coverage for this line.
https://github.com/llvm/llvm-project/pull/169655
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