[llvm] [LoadStoreVectorizer] Fill gaps in load/store chains to enable vectorization (PR #159388)

[Gang Chen via llvm-commits]

cmc-rep wrote:

> > It causes some assertion in llvm when compiling some AMD library.
> 
> Is there a reproducer? Stack trace pointing to the specific assertion? Anything else that we can use to figure out what went wrong?

This is the case causing problem for my change:
  %464 = load <1 x i32>, ptr addrspace(4) %coefficients_.i.i1034, align 4
  %394 = load i32, ptr addrspace(4) %coefficients_.i.i1034, align 4
Original chain element is <1 x i32>, new load is i32, it still tries to create suffle.


https://github.com/llvm/llvm-project/pull/159388