[llvm] [AArch64] Use umin for x != 0 when +cssc is enabled (PR #169159)

[via llvm-commits]

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@@ -11735,7 +11735,12 @@ SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
   }
 
   if (LHS.getValueType().isInteger()) {
-
+    if (Subtarget->hasCSSC() && CC == ISD::SETNE && isNullConstant(RHS)) {
+      SDValue One = DAG.getConstant(1, DL, LHS.getValueType());
+      auto UMin = DAG.getNode(ISD::UMIN, DL, LHS.getValueType(), LHS, One);
+      SDValue Res = DAG.getNode(ISD::TRUNCATE, DL, VT, UMin);
+      return IsStrict ? DAG.getMergeValues({Res, Chain}, DL) : Res;
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clingfei wrote:

This will cause a type mismatch between LHS.getValueType() and TVal.getValueType(), and between LHS.getValueType() and VT. Thus, the compiler will fail on the assert in 
```C++
SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
                              SDValue N1, SDValue N2, const SDNodeFlags Flags) {
    ...
  case ISD::UMIN:
    assert(VT.isInteger() && "This operator does not apply to FP types!");
    assert(N1.getValueType() == N2.getValueType() &&
           N1.getValueType() == VT && "Binary operator types must match!");
    ...
}

https://github.com/llvm/llvm-project/pull/169159