[llvm] [AArch64] Use umin for x != 0 when +cssc is enabled (PR #169159)

[via llvm-commits]

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@@ -26428,7 +26433,8 @@ performVecReduceBitwiseCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
 
 static SDValue performSETCCCombine(SDNode *N,
                                    TargetLowering::DAGCombinerInfo &DCI,
-                                   SelectionDAG &DAG) {
+                                   SelectionDAG &DAG,
+                                   const AArch64Subtarget *Subtarget) {
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clingfei wrote:

Removed. Thanks!

https://github.com/llvm/llvm-project/pull/169159