[llvm] [AArch64] Use umin for x != 0 when +cssc is enabled (PR #169159)

[Benjamin Maxwell via llvm-commits]

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@@ -26470,6 +26476,12 @@ static SDValue performSETCCCombine(SDNode *N,
       return DAG.getNode(ISD::SETCC, DL, VT, TST, RHS, N->getOperand(2));
     }
   }
+  if (Subtarget->hasCSSC() && Cond == ISD::SETNE && isNullConstant(RHS) &&
+      !VT.isVector() && DCI.getDAGCombineLevel() >= AfterLegalizeTypes) {
+    SDValue One = DAG.getConstant(1, DL, LHS.getValueType());
+    auto UMin = DAG.getNode(ISD::UMIN, DL, LHS.getValueType(), LHS, One);
+    return DAG.getNode(ISD::TRUNCATE, DL, VT, UMin);
+  }
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MacDue wrote:

Remove the change in  `performSETCCCombine`
```suggestion
```

https://github.com/llvm/llvm-project/pull/169159