[llvm] de674fb - [AArch64] Add vector tests for add(trunc(shift))

[David Green via llvm-commits]

Author: David Green
Date: 2025-11-26T09:37:35Z
New Revision: de674fb6c250608197a70ae3fdef5519597054f6

URL: https://github.com/llvm/llvm-project/commit/de674fb6c250608197a70ae3fdef5519597054f6
DIFF: https://github.com/llvm/llvm-project/commit/de674fb6c250608197a70ae3fdef5519597054f6.diff

LOG: [AArch64] Add vector tests for add(trunc(shift))

Added: 
    llvm/test/CodeGen/AArch64/addtruncshift.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AArch64/addtruncshift.ll b/llvm/test/CodeGen/AArch64/addtruncshift.ll
new file mode 100644
index 0000000000000..f3af50ec8cf3e
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/addtruncshift.ll
@@ -0,0 +1,96 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-none-elf < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -mtriple=aarch64-none-elf -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+define <2 x i32> @test_v2i64(<2 x i64> %n) {
+; CHECK-LABEL: test_v2i64:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushr v1.2d, v0.2d, #63
+; CHECK-NEXT:    sshr v0.2d, v0.2d, #35
+; CHECK-NEXT:    xtn v1.2s, v1.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
+; CHECK-NEXT:    add v0.2s, v1.2s, v0.2s
+; CHECK-NEXT:    ret
+entry:
+  %shr = lshr <2 x i64> %n, splat (i64 63)
+  %vmovn.i4 = trunc nuw nsw <2 x i64> %shr to <2 x i32>
+  %shr1 = ashr <2 x i64> %n, splat (i64 35)
+  %vmovn.i = trunc nsw <2 x i64> %shr1 to <2 x i32>
+  %add = add nsw <2 x i32> %vmovn.i4, %vmovn.i
+  ret <2 x i32> %add
+}
+
+define <4 x i16> @test_v4i32(<4 x i32> %n) {
+; CHECK-LABEL: test_v4i32:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushr v1.4s, v0.4s, #31
+; CHECK-NEXT:    sshr v0.4s, v0.4s, #17
+; CHECK-NEXT:    xtn v1.4h, v1.4s
+; CHECK-NEXT:    xtn v0.4h, v0.4s
+; CHECK-NEXT:    add v0.4h, v1.4h, v0.4h
+; CHECK-NEXT:    ret
+entry:
+  %shr = lshr <4 x i32> %n, splat (i32 31)
+  %vmovn.i4 = trunc nuw nsw <4 x i32> %shr to <4 x i16>
+  %shr1 = ashr <4 x i32> %n, splat (i32 17)
+  %vmovn.i = trunc nsw <4 x i32> %shr1 to <4 x i16>
+  %add = add nsw <4 x i16> %vmovn.i4, %vmovn.i
+  ret <4 x i16> %add
+}
+
+define <8 x i8> @test_v8i16(<8 x i16> %n) {
+; CHECK-LABEL: test_v8i16:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushr v1.8h, v0.8h, #15
+; CHECK-NEXT:    sshr v0.8h, v0.8h, #9
+; CHECK-NEXT:    xtn v1.8b, v1.8h
+; CHECK-NEXT:    xtn v0.8b, v0.8h
+; CHECK-NEXT:    add v0.8b, v1.8b, v0.8b
+; CHECK-NEXT:    ret
+entry:
+  %shr = lshr <8 x i16> %n, splat (i16 15)
+  %vmovn.i4 = trunc nuw nsw <8 x i16> %shr to <8 x i8>
+  %shr1 = ashr <8 x i16> %n, splat (i16 9)
+  %vmovn.i = trunc nsw <8 x i16> %shr1 to <8 x i8>
+  %add = add nsw <8 x i8> %vmovn.i4, %vmovn.i
+  ret <8 x i8> %add
+}
+
+define <2 x i32> @test_v2i64_smallsrl(<2 x i64> %n) {
+; CHECK-LABEL: test_v2i64_smallsrl:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushr v1.2d, v0.2d, #62
+; CHECK-NEXT:    sshr v0.2d, v0.2d, #35
+; CHECK-NEXT:    xtn v1.2s, v1.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
+; CHECK-NEXT:    add v0.2s, v1.2s, v0.2s
+; CHECK-NEXT:    ret
+entry:
+  %shr = lshr <2 x i64> %n, splat (i64 62)
+  %vmovn.i4 = trunc nuw nsw <2 x i64> %shr to <2 x i32>
+  %shr1 = ashr <2 x i64> %n, splat (i64 35)
+  %vmovn.i = trunc nsw <2 x i64> %shr1 to <2 x i32>
+  %add = add nsw <2 x i32> %vmovn.i4, %vmovn.i
+  ret <2 x i32> %add
+}
+
+define <2 x i32> @test_v2i64_smallsra(<2 x i64> %n) {
+; CHECK-LABEL: test_v2i64_smallsra:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushr v1.2d, v0.2d, #63
+; CHECK-NEXT:    shrn v0.2s, v0.2d, #27
+; CHECK-NEXT:    xtn v1.2s, v1.2d
+; CHECK-NEXT:    add v0.2s, v1.2s, v0.2s
+; CHECK-NEXT:    ret
+entry:
+  %shr = lshr <2 x i64> %n, splat (i64 63)
+  %vmovn.i4 = trunc nuw nsw <2 x i64> %shr to <2 x i32>
+  %shr1 = ashr <2 x i64> %n, splat (i64 27)
+  %vmovn.i = trunc nsw <2 x i64> %shr1 to <2 x i32>
+  %add = add nsw <2 x i32> %vmovn.i4, %vmovn.i
+  ret <2 x i32> %add
+}
+
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-GI: {{.*}}
+; CHECK-SD: {{.*}}