[llvm] [RISCV][ISelLowering] Use Zicond for FP selects on Zfinx/Zdinx (PR #169299)

[Sam Elliott via llvm-commits]

================
@@ -9555,6 +9555,54 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
   if (SDValue V = lowerSelectToBinOp(Op.getNode(), DAG, Subtarget))
     return V;
 
+  // When there is no cost for GPR <-> FGPR, we can use zicond select for
+  // floating value when CondV is int type
+  bool FPinGPR = Subtarget.hasStdExtZfinx();
+
+  // We can handle FGPR without spliting into hi/lo parts
+  bool FitsInGPR = TypeSize::isKnownLE(VT.getSizeInBits(),
+                                       Subtarget.getXLenVT().getSizeInBits());
+
+  bool UseZicondForFPSel = Subtarget.hasStdExtZicond() && FPinGPR &&
+                           VT.isFloatingPoint() && FitsInGPR;
+
+  if (UseZicondForFPSel) {
+    MVT XLenIntVT = Subtarget.getXLenVT();
+
+    auto CastToInt = [&](SDValue V) -> SDValue {
+      // Treat +0.0 as integer 0 to enable single 'czero' instruction
+      // generation.
+      if (auto *CFP = dyn_cast<ConstantFPSDNode>(V)) {
+        if (CFP->isZero() && !CFP->isNegative())
+          return DAG.getConstant(0, DL, XLenIntVT);
+      }
----------------
lenary wrote:

What happens for the following with zhinx:
```
define half @select_i1_half_0_add(i1 %cond, half %val) nounwind {
entry:
  %sel = select i1 %cond, half %val, half 0xH0000
  %add = fadd half %sel, 1.0
  ret half %add
}
```

Is the operand of the `fadd.h` correctly nan-boxed? (This wouldn't be dealt with in `splitValueIntoRegisterParts` because it's in the same basic block as the select).

You potentially have the same problem with `fadd.s` on rv64, for which I think you can make/adapt a testcase based on the above.

It may be simplest to push the `isNullFPConstant` check down to just above the `getBitcast` if these two examples are not correctly nan-boxed.

https://github.com/llvm/llvm-project/pull/169299