[llvm] [RISCV] Use vsetivli instead of `x0,x0` form to retain SEW/LMUL when AVL is imm (PR #169307)
Pengcheng Wang via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 25 22:51:04 PST 2025
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/169307
>From c1b62de029d313a782293c3157008b9cba7aa2a9 Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: Fri, 21 Nov 2025 17:47:44 +0800
Subject: [PATCH 1/5] [RISCV] Use vsetivli instead of `x0,x0` form to retain
SEW/LMUL when AVL is imm
Usually, the `vl` value of `vsetivli` form can be retrieved early
in the decoding stage of CPU pipeline. While for the `x0,x0` form
of `vsetvli`, the value of `vl` will be deferred to later stages.
So if the SEW/LMUL ratio doesn't change, we can use the `vsetivli`
form to replace the `x0,x0` form.
---
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 73 +-
llvm/test/CodeGen/RISCV/double_reduct.ll | 2 +-
.../early-clobber-tied-def-subreg-liveness.ll | 4 +-
.../test/CodeGen/RISCV/intrinsic-cttz-elts.ll | 4 +-
llvm/test/CodeGen/RISCV/pr94265.ll | 4 +-
.../RISCV/rvv/65704-illegal-instruction.ll | 2 +-
llvm/test/CodeGen/RISCV/rvv/compressstore.ll | 4 +-
.../RISCV/rvv/concat-vector-insert-elt.ll | 8 +-
.../RISCV/rvv/constant-folding-crash.ll | 20 +-
.../CodeGen/RISCV/rvv/constant-folding.ll | 2 +-
llvm/test/CodeGen/RISCV/rvv/expandload.ll | 8 +-
llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll | 6 +-
.../CodeGen/RISCV/rvv/fixed-vectors-abd.ll | 20 +-
.../CodeGen/RISCV/rvv/fixed-vectors-abs.ll | 6 +-
.../CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll | 12 +-
.../CodeGen/RISCV/rvv/fixed-vectors-cttz.ll | 36 +-
.../rvv/fixed-vectors-extload-truncstore.ll | 32 +-
.../RISCV/rvv/fixed-vectors-extract-i1.ll | 8 +-
.../RISCV/rvv/fixed-vectors-extract.ll | 24 +-
.../fixed-vectors-fceil-constrained-sdnode.ll | 72 +-
...fixed-vectors-ffloor-constrained-sdnode.ll | 72 +-
.../RISCV/rvv/fixed-vectors-fmaximum.ll | 64 +-
.../RISCV/rvv/fixed-vectors-fmaximumnum.ll | 20 +-
.../RISCV/rvv/fixed-vectors-fminimum.ll | 64 +-
.../RISCV/rvv/fixed-vectors-fminimumnum.ll | 20 +-
...d-vectors-fnearbyint-constrained-sdnode.ll | 56 +-
.../RISCV/rvv/fixed-vectors-fp-buildvec.ll | 12 +-
.../RISCV/rvv/fixed-vectors-fp-conv.ll | 8 +-
.../RISCV/rvv/fixed-vectors-fp-setcc.ll | 112 +-
.../CodeGen/RISCV/rvv/fixed-vectors-fp.ll | 594 ++++-----
.../RISCV/rvv/fixed-vectors-fp2i-sat.ll | 44 +-
.../CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll | 24 +-
...fixed-vectors-fround-constrained-sdnode.ll | 72 +-
.../CodeGen/RISCV/rvv/fixed-vectors-fround.ll | 82 +-
...d-vectors-froundeven-constrained-sdnode.ll | 72 +-
.../RISCV/rvv/fixed-vectors-froundeven.ll | 82 +-
...fixed-vectors-ftrunc-constrained-sdnode.ll | 72 +-
.../CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll | 36 +-
.../fixed-vectors-insert-subvector-shuffle.ll | 6 +-
.../rvv/fixed-vectors-insert-subvector.ll | 6 +-
.../CodeGen/RISCV/rvv/fixed-vectors-insert.ll | 12 +-
.../RISCV/rvv/fixed-vectors-int-buildvec.ll | 41 +-
.../RISCV/rvv/fixed-vectors-int-exttrunc.ll | 4 +-
.../CodeGen/RISCV/rvv/fixed-vectors-int.ll | 52 +-
.../rvv/fixed-vectors-interleaved-access.ll | 22 +-
.../CodeGen/RISCV/rvv/fixed-vectors-llrint.ll | 24 +-
.../RISCV/rvv/fixed-vectors-llround.ll | 24 +-
.../CodeGen/RISCV/rvv/fixed-vectors-lrint.ll | 76 +-
.../CodeGen/RISCV/rvv/fixed-vectors-lround.ll | 40 +-
.../RISCV/rvv/fixed-vectors-mask-buildvec.ll | 6 +-
.../RISCV/rvv/fixed-vectors-masked-gather.ll | 1095 +++++++----------
.../RISCV/rvv/fixed-vectors-masked-scatter.ll | 510 ++++----
.../rvv/fixed-vectors-reduction-fp-vp.ll | 4 +-
.../RISCV/rvv/fixed-vectors-reduction-fp.ll | 78 +-
.../rvv/fixed-vectors-reduction-int-vp.ll | 22 +-
.../RISCV/rvv/fixed-vectors-reduction-int.ll | 128 +-
.../CodeGen/RISCV/rvv/fixed-vectors-sad.ll | 24 +-
.../RISCV/rvv/fixed-vectors-select-bf16.ll | 16 +-
.../RISCV/rvv/fixed-vectors-select-fp.ll | 48 +-
.../RISCV/rvv/fixed-vectors-select-int.ll | 56 +-
.../fixed-vectors-shuffle-changes-length.ll | 14 +-
.../rvv/fixed-vectors-shuffle-deinterleave.ll | 20 +-
.../fixed-vectors-shuffle-deinterleave2.ll | 6 +-
.../rvv/fixed-vectors-shuffle-exact-vlen.ll | 6 +-
.../fixed-vectors-shuffle-fp-interleave.ll | 6 +-
.../RISCV/rvv/fixed-vectors-shuffle-fp.ll | 4 +-
.../fixed-vectors-shuffle-int-interleave.ll | 10 +-
.../RISCV/rvv/fixed-vectors-shuffle-int.ll | 26 +-
.../rvv/fixed-vectors-shuffle-reverse.ll | 6 +-
.../RISCV/rvv/fixed-vectors-shuffle-rotate.ll | 18 +-
.../rvv/fixed-vectors-shuffle-vslide1up.ll | 4 +-
.../CodeGen/RISCV/rvv/fixed-vectors-store.ll | 2 +-
.../RISCV/rvv/fixed-vectors-trunc-sat-clip.ll | 80 +-
.../RISCV/rvv/fixed-vectors-unaligned.ll | 70 +-
.../CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll | 8 +-
.../CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll | 48 +-
.../CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll | 48 +-
...fixed-vectors-vfpext-constrained-sdnode.ll | 12 +-
...fixed-vectors-vfptoi-constrained-sdnode.ll | 84 +-
...xed-vectors-vfptrunc-constrained-sdnode.ll | 12 +-
.../fixed-vectors-vfw-web-simplification.ll | 24 +-
.../RISCV/rvv/fixed-vectors-vfwmacc.ll | 80 +-
.../RISCV/rvv/fixed-vectors-vfwmaccbf16.ll | 26 +-
.../CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll | 2 +-
...fixed-vectors-vitofp-constrained-sdnode.ll | 16 +-
.../RISCV/rvv/fixed-vectors-vpscatter.ll | 16 +-
.../fixed-vectors-vreductions-fp-vp-bf16.ll | 12 +-
.../CodeGen/RISCV/rvv/fixed-vectors-vrol.ll | 12 +-
.../CodeGen/RISCV/rvv/fixed-vectors-vror.ll | 24 +-
.../RISCV/rvv/fixed-vectors-vselect.ll | 24 +-
.../fixed-vectors-vw-web-simplification.ll | 22 +-
.../RISCV/rvv/fixed-vectors-vwadd-mask.ll | 6 +-
.../CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll | 6 +-
.../CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll | 16 +-
.../CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll | 2 +-
.../CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll | 2 +-
.../CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll | 62 +-
.../RISCV/rvv/fixed-vectors-vwsub-mask.ll | 4 +-
.../CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll | 6 +-
.../CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll | 14 +-
.../RISCV/rvv/fixed-vectors-zvqdotq.ll | 69 +-
.../CodeGen/RISCV/rvv/fold-binary-reduce.ll | 4 +-
.../CodeGen/RISCV/rvv/fpclamptosat_vec.ll | 68 +-
llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll | 10 +-
llvm/test/CodeGen/RISCV/rvv/pr141907.ll | 2 +-
llvm/test/CodeGen/RISCV/rvv/pr165232.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/pr63459.ll | 2 +-
.../rvv/regcoal-liveinterval-pruning-crash.ll | 4 +-
.../RISCV/rvv/rvv-peephole-vmerge-vops.ll | 8 +-
.../CodeGen/RISCV/rvv/rvv-vmerge-to-vmv.ll | 2 +-
.../RISCV/rvv/trunc-select-to-max-usat.ll | 20 +-
.../RISCV/rvv/vector-deinterleave-fixed.ll | 6 +-
.../RISCV/rvv/vector-extract-last-active.ll | 27 +-
.../RISCV/rvv/vector-interleave-fixed.ll | 16 +-
llvm/test/CodeGen/RISCV/rvv/vl-opt.ll | 2 +-
.../RISCV/rvv/vsetvli-insert-crossbb.ll | 9 +-
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll | 4 +-
.../test/CodeGen/RISCV/rvv/vsetvli-insert.mir | 4 +-
.../CodeGen/RISCV/srem-seteq-illegal-types.ll | 2 +-
.../CodeGen/RISCV/urem-seteq-illegal-types.ll | 16 +-
120 files changed, 2550 insertions(+), 2744 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index e5819d90526d9..ead5eb9033285 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -47,6 +47,11 @@ static cl::opt<bool> EnsureWholeVectorRegisterMoveValidVTYPE(
"vill is cleared"),
cl::init(true));
+static cl::opt<bool> UseVsetivliForImmAVL(
+ DEBUG_TYPE "-use-vsetivli-for-imm-avl", cl::Hidden,
+ cl::desc("Use vsetivli to replace x0,x0 form when AVL is an immediate."),
+ cl::init(true));
+
namespace {
/// Given a virtual register \p Reg, return the corresponding VNInfo for it.
@@ -1167,7 +1172,13 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
// Use X0, X0 form if the AVL is the same and the SEW+LMUL gives the same
// VLMAX.
if (Info.hasSameAVL(PrevInfo) && Info.hasSameVLMAX(PrevInfo)) {
- auto MI = BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0X0))
+ auto MI =
+ UseVsetivliForImmAVL && Info.hasAVLImm()
+ ? BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETIVLI))
+ .addReg(RISCV::X0, RegState::Define | RegState::Dead)
+ .addImm(PrevInfo.getAVLImm())
+ .addImm(Info.encodeVTYPE())
+ : BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0X0))
.addReg(RISCV::X0, RegState::Define | RegState::Dead)
.addReg(RISCV::X0, RegState::Kill)
.addImm(Info.encodeVTYPE())
@@ -1734,35 +1745,47 @@ bool RISCVInsertVSETVLI::canMutatePriorConfig(
// demanded, or b) we can't rewrite the former to be the later for
// implementation reasons.
if (!RISCVInstrInfo::isVLPreservingConfig(MI)) {
- if (Used.VLAny)
- return false;
-
- if (Used.VLZeroness) {
- if (RISCVInstrInfo::isVLPreservingConfig(PrevMI))
- return false;
- if (!getInfoForVSETVLI(PrevMI).hasEquallyZeroAVL(getInfoForVSETVLI(MI),
- LIS))
- return false;
+ bool Skip = false;
+ if (MI.getOpcode() == RISCV::PseudoVSETIVLI &&
+ PrevMI.getOpcode() == RISCV::PseudoVSETIVLI &&
+ PrevMI.getOperand(0).isDead()) {
+ VSETVLIInfo PrevInfo = getInfoForVSETVLI(PrevMI);
+ VSETVLIInfo Info = getInfoForVSETVLI(MI);
+ if (PrevInfo.hasAVLImm() && Info.hasAVLImm() &&
+ PrevInfo.getAVLImm() == Info.getAVLImm())
+ Skip = true;
}
+ if (!Skip) {
+ if (Used.VLAny)
+ return false;
+
+ if (Used.VLZeroness) {
+ if (RISCVInstrInfo::isVLPreservingConfig(PrevMI))
+ return false;
+ if (!getInfoForVSETVLI(PrevMI).hasEquallyZeroAVL(getInfoForVSETVLI(MI),
+ LIS))
+ return false;
+ }
- auto &AVL = MI.getOperand(1);
+ auto &AVL = MI.getOperand(1);
- // If the AVL is a register, we need to make sure its definition is the same
- // at PrevMI as it was at MI.
- if (AVL.isReg() && AVL.getReg() != RISCV::X0) {
- VNInfo *VNI = getVNInfoFromReg(AVL.getReg(), MI, LIS);
- VNInfo *PrevVNI = getVNInfoFromReg(AVL.getReg(), PrevMI, LIS);
- if (!VNI || !PrevVNI || VNI != PrevVNI)
+ // If the AVL is a register, we need to make sure its definition is the
+ // same at PrevMI as it was at MI.
+ if (AVL.isReg() && AVL.getReg() != RISCV::X0) {
+ VNInfo *VNI = getVNInfoFromReg(AVL.getReg(), MI, LIS);
+ VNInfo *PrevVNI = getVNInfoFromReg(AVL.getReg(), PrevMI, LIS);
+ if (!VNI || !PrevVNI || VNI != PrevVNI)
+ return false;
+ }
+
+ // If we define VL and need to move the definition up, check we can extend
+ // the live interval upwards from MI to PrevMI.
+ Register VL = MI.getOperand(0).getReg();
+ if (VL.isVirtual() && LIS &&
+ LIS->getInterval(VL).overlaps(LIS->getInstructionIndex(PrevMI),
+ LIS->getInstructionIndex(MI)))
return false;
}
-
- // If we define VL and need to move the definition up, check we can extend
- // the live interval upwards from MI to PrevMI.
- Register VL = MI.getOperand(0).getReg();
- if (VL.isVirtual() && LIS &&
- LIS->getInterval(VL).overlaps(LIS->getInstructionIndex(PrevMI),
- LIS->getInstructionIndex(MI)))
- return false;
}
assert(PrevMI.getOperand(2).isImm() && MI.getOperand(2).isImm());
diff --git a/llvm/test/CodeGen/RISCV/double_reduct.ll b/llvm/test/CodeGen/RISCV/double_reduct.ll
index cecdd77a079e4..f4a0ab227edf4 100644
--- a/llvm/test/CodeGen/RISCV/double_reduct.ll
+++ b/llvm/test/CodeGen/RISCV/double_reduct.ll
@@ -90,7 +90,7 @@ define i16 @add_ext_i16(<16 x i8> %a, <16 x i8> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vwaddu.vv v10, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vmv.s.x v8, zero
; CHECK-NEXT: vredsum.vs v8, v10, v8
; CHECK-NEXT: vmv.x.s a0, v8
diff --git a/llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll b/llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
index 85867a4ab2c6f..42277a4ff6556 100644
--- a/llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
+++ b/llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
@@ -57,11 +57,11 @@ define void @_Z3foov() {
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v14, (a0) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, tu, mu
+; CHECK-NEXT: vsetivli zero, 2, e16, m2, tu, mu
; CHECK-NEXT: vsext.vf2 v8, v14, v0.t
; CHECK-NEXT: lui a0, %hi(.L__const._Z3foov.var_44)
; CHECK-NEXT: addi a0, a0, %lo(.L__const._Z3foov.var_44)
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, m2, ta, ma
; CHECK-NEXT: vle16.v v14, (a0)
; CHECK-NEXT: lui a0, %hi(var_47)
; CHECK-NEXT: addi a0, a0, %lo(var_47)
diff --git a/llvm/test/CodeGen/RISCV/intrinsic-cttz-elts.ll b/llvm/test/CodeGen/RISCV/intrinsic-cttz-elts.ll
index 1216d3000e8c8..b01edf4e3f182 100644
--- a/llvm/test/CodeGen/RISCV/intrinsic-cttz-elts.ll
+++ b/llvm/test/CodeGen/RISCV/intrinsic-cttz-elts.ll
@@ -9,7 +9,7 @@ define i16 @ctz_v4i32(<4 x i32> %a) {
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmsne.vi v0, v8, 0
-; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; RV32-NEXT: vmv.v.i v8, 0
; RV32-NEXT: vmerge.vim v8, v8, -1, v0
; RV32-NEXT: vid.v v9
@@ -26,7 +26,7 @@ define i16 @ctz_v4i32(<4 x i32> %a) {
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vmsne.vi v0, v8, 0
-; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; RV64-NEXT: vmv.v.i v8, 0
; RV64-NEXT: vmerge.vim v8, v8, -1, v0
; RV64-NEXT: vid.v v9
diff --git a/llvm/test/CodeGen/RISCV/pr94265.ll b/llvm/test/CodeGen/RISCV/pr94265.ll
index f92cdb4ca7395..e97f924d6ae4e 100644
--- a/llvm/test/CodeGen/RISCV/pr94265.ll
+++ b/llvm/test/CodeGen/RISCV/pr94265.ll
@@ -11,7 +11,7 @@ define <8 x i16> @PR94265(<8 x i32> %a0) #0 {
; RV32I-NEXT: vsra.vi v10, v8, 31
; RV32I-NEXT: vsrl.vi v10, v10, 26
; RV32I-NEXT: vadd.vv v8, v8, v10
-; RV32I-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV32I-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32I-NEXT: vnsrl.wi v10, v8, 6
; RV32I-NEXT: vsll.vi v8, v10, 10
; RV32I-NEXT: ret
@@ -22,7 +22,7 @@ define <8 x i16> @PR94265(<8 x i32> %a0) #0 {
; RV64I-NEXT: vsra.vi v10, v8, 31
; RV64I-NEXT: vsrl.vi v10, v10, 26
; RV64I-NEXT: vadd.vv v8, v8, v10
-; RV64I-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64I-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64I-NEXT: vnsrl.wi v10, v8, 6
; RV64I-NEXT: vsll.vi v8, v10, 10
; RV64I-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/65704-illegal-instruction.ll b/llvm/test/CodeGen/RISCV/rvv/65704-illegal-instruction.ll
index 44fd9046fa0e0..1a162cc160da7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/65704-illegal-instruction.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/65704-illegal-instruction.ll
@@ -26,7 +26,7 @@ define void @foo(<vscale x 8 x i8> %0) {
; CHECK-NEXT: vsetivli zero, 0, e8, m1, tu, ma
; CHECK-NEXT: vslideup.vi v9, v10, 0
; CHECK-NEXT: vslideup.vi v8, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; CHECK-NEXT: vsetivli zero, 0, e64, m8, ta, ma
; CHECK-NEXT: vmv.x.s s1, v9
; CHECK-NEXT: vmv.x.s s2, v8
; CHECK-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
diff --git a/llvm/test/CodeGen/RISCV/rvv/compressstore.ll b/llvm/test/CodeGen/RISCV/rvv/compressstore.ll
index 69822e9d9d2e3..50c51bfe62caf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/compressstore.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/compressstore.ll
@@ -797,7 +797,7 @@ define void @test_compresstore_v32i64(ptr %p, <32 x i1> %mask, <32 x i64> %data)
; RV64-NEXT: vse64.v v24, (a0)
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v24, v0, 2
-; RV64-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64-NEXT: vmv.x.s a1, v0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vcompress.vm v8, v16, v24
@@ -819,7 +819,7 @@ define void @test_compresstore_v32i64(ptr %p, <32 x i1> %mask, <32 x i64> %data)
; RV32-NEXT: vse64.v v24, (a0)
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v24, v0, 2
-; RV32-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV32-NEXT: vmv.x.s a1, v0
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vcompress.vm v8, v16, v24
diff --git a/llvm/test/CodeGen/RISCV/rvv/concat-vector-insert-elt.ll b/llvm/test/CodeGen/RISCV/rvv/concat-vector-insert-elt.ll
index 1343b64b876dc..6d60313bffc90 100644
--- a/llvm/test/CodeGen/RISCV/rvv/concat-vector-insert-elt.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/concat-vector-insert-elt.ll
@@ -10,7 +10,7 @@ define void @v4xi8_concat_vector_insert_idx0(ptr %a, ptr %b, i8 %x) {
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vle8.v v9, (a1)
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, tu, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, tu, ma
; CHECK-NEXT: vmv.s.x v8, a2
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v8, v9, 2
@@ -50,7 +50,7 @@ define void @v4xi8_concat_vector_insert_idx2(ptr %a, ptr %b, i8 %x) {
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vle8.v v8, (a1)
; CHECK-NEXT: vle8.v v9, (a0)
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, tu, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, tu, ma
; CHECK-NEXT: vmv.s.x v8, a2
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v9, v8, 2
@@ -103,7 +103,7 @@ define void @v4xi64_concat_vector_insert_idx0(ptr %a, ptr %b, i64 %x) {
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vle64.v v10, (a1)
-; RV64-NEXT: vsetvli zero, zero, e64, m1, tu, ma
+; RV64-NEXT: vsetivli zero, 2, e64, m1, tu, ma
; RV64-NEXT: vmv.s.x v8, a2
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64-NEXT: vslideup.vi v8, v10, 2
@@ -171,7 +171,7 @@ define void @v4xi64_concat_vector_insert_idx2(ptr %a, ptr %b, i64 %x) {
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a1)
; RV64-NEXT: vle64.v v10, (a0)
-; RV64-NEXT: vsetvli zero, zero, e64, m1, tu, ma
+; RV64-NEXT: vsetivli zero, 2, e64, m1, tu, ma
; RV64-NEXT: vmv.s.x v8, a2
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64-NEXT: vslideup.vi v10, v8, 2
diff --git a/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll b/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
index 593f8e2612fec..86e9eb2a42ab3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
@@ -25,18 +25,18 @@ define void @constant_folding_crash(ptr %v54, <4 x ptr> %lanes.a, <4 x ptr> %lan
; RV32-NEXT: seqz a0, a0
; RV32-NEXT: vmv.v.x v11, a0
; RV32-NEXT: vmsne.vi v0, v11, 0
-; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmerge.vvm v8, v9, v8, v0
-; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; RV32-NEXT: vmv.v.i v9, 0
-; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.i v11, 10
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; RV32-NEXT: vmerge.vim v9, v9, 1, v0
; RV32-NEXT: vrgather.vi v10, v9, 0
; RV32-NEXT: vmsne.vi v0, v10, 0
-; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: vse32.v v11, (a0), v0.t
; RV32-NEXT: ret
@@ -50,18 +50,18 @@ define void @constant_folding_crash(ptr %v54, <4 x ptr> %lanes.a, <4 x ptr> %lan
; RV64-NEXT: seqz a0, a0
; RV64-NEXT: vmv.v.x v13, a0
; RV64-NEXT: vmsne.vi v0, v13, 0
-; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64-NEXT: vmerge.vvm v8, v10, v8, v0
-; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; RV64-NEXT: vmv.v.i v9, 0
-; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vmv.v.i v10, 10
; RV64-NEXT: vmv1r.v v0, v12
-; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; RV64-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-NEXT: vrgather.vi v11, v9, 0
; RV64-NEXT: vmsne.vi v0, v11, 0
-; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: vse32.v v10, (a0), v0.t
; RV64-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/constant-folding.ll b/llvm/test/CodeGen/RISCV/rvv/constant-folding.ll
index 05747ff0d049a..68f5a0b580c3c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/constant-folding.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/constant-folding.ll
@@ -18,7 +18,7 @@ define <2 x i16> @fixedlen(<2 x i32> %x) {
; CHECK-NEXT: vsrl.vi v8, v8, 16
; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: vand.vx v8, v8, a0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%v43 = lshr <2 x i32> %x, splat (i32 16)
diff --git a/llvm/test/CodeGen/RISCV/rvv/expandload.ll b/llvm/test/CodeGen/RISCV/rvv/expandload.ll
index cc1282a9119da..76e1692bd2acc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/expandload.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/expandload.ll
@@ -657,7 +657,7 @@ define <128 x i16> @test_expandload_v128i16(ptr %base, <128 x i1> %mask, <128 x
; CHECK-RV32-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-RV32-NEXT: vslidedown.vi v7, v0, 8
; CHECK-RV32-NEXT: li a2, 32
-; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; CHECK-RV32-NEXT: vsetivli zero, 8, e64, m8, ta, ma
; CHECK-RV32-NEXT: vmv.x.s a3, v0
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-RV32-NEXT: vcpop.m a4, v0
@@ -1091,7 +1091,7 @@ define <64 x i32> @test_expandload_v64i32(ptr %base, <64 x i1> %mask, <64 x i32>
; CHECK-RV64-NEXT: li a1, 32
; CHECK-RV64-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-RV64-NEXT: vslidedown.vi v7, v0, 4
-; CHECK-RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-RV64-NEXT: vsetivli zero, 4, e32, m2, ta, ma
; CHECK-RV64-NEXT: vmv.x.s a2, v0
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vcpop.m a3, v0
@@ -3907,7 +3907,7 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV32-NEXT: .LBB61_544: # %cond.load
; CHECK-RV32-NEXT: lbu a1, 0(a0)
; CHECK-RV32-NEXT: vmv8r.v v16, v8
-; CHECK-RV32-NEXT: vsetvli zero, zero, e8, mf8, tu, ma
+; CHECK-RV32-NEXT: vsetivli zero, 1, e8, mf8, tu, ma
; CHECK-RV32-NEXT: vmv.s.x v8, a1
; CHECK-RV32-NEXT: addi a0, a0, 1
; CHECK-RV32-NEXT: vmv1r.v v16, v8
@@ -12760,7 +12760,7 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, <
; CHECK-RV64-NEXT: .LBB61_527: # %cond.load
; CHECK-RV64-NEXT: lbu a1, 0(a0)
; CHECK-RV64-NEXT: vmv8r.v v16, v8
-; CHECK-RV64-NEXT: vsetvli zero, zero, e8, mf8, tu, ma
+; CHECK-RV64-NEXT: vsetivli zero, 1, e8, mf8, tu, ma
; CHECK-RV64-NEXT: vmv.s.x v8, a1
; CHECK-RV64-NEXT: addi a0, a0, 1
; CHECK-RV64-NEXT: vmv1r.v v16, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
index 903c0dcaba2d8..b8aceb5cc3db3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
@@ -338,7 +338,7 @@ define bfloat @extractelt_nxv8bf16_idx(<vscale x 8 x bfloat> %v, i32 zeroext %id
; ZVFBFA: # %bb.0:
; ZVFBFA-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; ZVFBFA-NEXT: vslidedown.vx v8, v8, a0
-; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m2, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 1, e16alt, m2, ta, ma
; ZVFBFA-NEXT: vfmv.f.s fa0, v8
; ZVFBFA-NEXT: ret
%r = extractelement <vscale x 8 x bfloat> %v, i32 %idx
@@ -423,7 +423,7 @@ define bfloat @extractelt_nxv16bf16_idx(<vscale x 16 x bfloat> %v, i32 zeroext %
; ZVFBFA: # %bb.0:
; ZVFBFA-NEXT: vsetivli zero, 1, e16, m4, ta, ma
; ZVFBFA-NEXT: vslidedown.vx v8, v8, a0
-; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 1, e16alt, m4, ta, ma
; ZVFBFA-NEXT: vfmv.f.s fa0, v8
; ZVFBFA-NEXT: ret
%r = extractelement <vscale x 16 x bfloat> %v, i32 %idx
@@ -508,7 +508,7 @@ define bfloat @extractelt_nxv32bf16_idx(<vscale x 32 x bfloat> %v, i32 zeroext %
; ZVFBFA: # %bb.0:
; ZVFBFA-NEXT: vsetivli zero, 1, e16, m8, ta, ma
; ZVFBFA-NEXT: vslidedown.vx v8, v8, a0
-; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m8, ta, ma
+; ZVFBFA-NEXT: vsetivli zero, 1, e16alt, m8, ta, ma
; ZVFBFA-NEXT: vfmv.f.s fa0, v8
; ZVFBFA-NEXT: ret
%r = extractelement <vscale x 32 x bfloat> %v, i32 %idx
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll
index bd1209a17b534..b8ff35c2c1ac2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll
@@ -81,7 +81,7 @@ define <4 x i16> @sabd_4h_promoted_ops(<4 x i8> %a, <4 x i8> %b) {
; CHECK-NEXT: vmin.vv v10, v8, v9
; CHECK-NEXT: vmax.vv v8, v8, v9
; CHECK-NEXT: vsub.vv v9, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vzext.vf2 v8, v9
; CHECK-NEXT: ret
%a.sext = sext <4 x i8> %a to <4 x i16>
@@ -116,7 +116,7 @@ define <8 x i16> @sabd_8h_promoted_ops(<8 x i8> %a, <8 x i8> %b) {
; CHECK-NEXT: vmin.vv v10, v8, v9
; CHECK-NEXT: vmax.vv v8, v8, v9
; CHECK-NEXT: vsub.vv v9, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vzext.vf2 v8, v9
; CHECK-NEXT: ret
%a.sext = sext <8 x i8> %a to <8 x i16>
@@ -151,7 +151,7 @@ define <2 x i32> @sabd_2s_promoted_ops(<2 x i16> %a, <2 x i16> %b) {
; CHECK-NEXT: vmin.vv v10, v8, v9
; CHECK-NEXT: vmax.vv v8, v8, v9
; CHECK-NEXT: vsub.vv v9, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vzext.vf2 v8, v9
; CHECK-NEXT: ret
%a.sext = sext <2 x i16> %a to <2 x i32>
@@ -186,7 +186,7 @@ define <4 x i32> @sabd_4s_promoted_ops(<4 x i16> %a, <4 x i16> %b) {
; CHECK-NEXT: vmin.vv v10, v8, v9
; CHECK-NEXT: vmax.vv v8, v8, v9
; CHECK-NEXT: vsub.vv v9, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vzext.vf2 v8, v9
; CHECK-NEXT: ret
%a.sext = sext <4 x i16> %a to <4 x i32>
@@ -220,7 +220,7 @@ define <2 x i64> @sabd_2d_promoted_ops(<2 x i32> %a, <2 x i32> %b) {
; CHECK-NEXT: vmin.vv v10, v8, v9
; CHECK-NEXT: vmax.vv v8, v8, v9
; CHECK-NEXT: vsub.vv v9, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vzext.vf2 v8, v9
; CHECK-NEXT: ret
%a.sext = sext <2 x i32> %a to <2 x i64>
@@ -293,7 +293,7 @@ define <4 x i16> @uabd_4h_promoted_ops(<4 x i8> %a, <4 x i8> %b) {
; CHECK-NEXT: vminu.vv v10, v8, v9
; CHECK-NEXT: vmaxu.vv v8, v8, v9
; CHECK-NEXT: vsub.vv v9, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vzext.vf2 v8, v9
; CHECK-NEXT: ret
%a.zext = zext <4 x i8> %a to <4 x i16>
@@ -328,7 +328,7 @@ define <8 x i16> @uabd_8h_promoted_ops(<8 x i8> %a, <8 x i8> %b) {
; CHECK-NEXT: vminu.vv v10, v8, v9
; CHECK-NEXT: vmaxu.vv v8, v8, v9
; CHECK-NEXT: vsub.vv v9, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vzext.vf2 v8, v9
; CHECK-NEXT: ret
%a.zext = zext <8 x i8> %a to <8 x i16>
@@ -363,7 +363,7 @@ define <2 x i32> @uabd_2s_promoted_ops(<2 x i16> %a, <2 x i16> %b) {
; CHECK-NEXT: vminu.vv v10, v8, v9
; CHECK-NEXT: vmaxu.vv v8, v8, v9
; CHECK-NEXT: vsub.vv v9, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vzext.vf2 v8, v9
; CHECK-NEXT: ret
%a.zext = zext <2 x i16> %a to <2 x i32>
@@ -398,7 +398,7 @@ define <4 x i32> @uabd_4s_promoted_ops(<4 x i16> %a, <4 x i16> %b) {
; CHECK-NEXT: vminu.vv v10, v8, v9
; CHECK-NEXT: vmaxu.vv v8, v8, v9
; CHECK-NEXT: vsub.vv v9, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vzext.vf2 v8, v9
; CHECK-NEXT: ret
%a.zext = zext <4 x i16> %a to <4 x i32>
@@ -432,7 +432,7 @@ define <2 x i64> @uabd_2d_promoted_ops(<2 x i32> %a, <2 x i32> %b) {
; CHECK-NEXT: vminu.vv v10, v8, v9
; CHECK-NEXT: vmaxu.vv v8, v8, v9
; CHECK-NEXT: vsub.vv v9, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vzext.vf2 v8, v9
; CHECK-NEXT: ret
%a.zext = zext <2 x i32> %a to <2 x i64>
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
index 2356237d790b6..a53c5b1252a4f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
@@ -154,7 +154,7 @@ define void @abs_v4i64_of_sext_v4i8(ptr %x) {
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vmax.vv v10, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vzext.vf8 v8, v10
; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
@@ -172,7 +172,7 @@ define void @abs_v4i64_of_sext_v4i16(ptr %x) {
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vmax.vv v10, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vzext.vf4 v8, v10
; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
@@ -190,7 +190,7 @@ define void @abs_v4i64_of_sext_v4i32(ptr %x) {
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vrsub.vi v9, v8, 0
; CHECK-NEXT: vmax.vv v10, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v8, v10
; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
index 61730b87c5517..e1a6e02748aa2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
@@ -43,7 +43,7 @@ define void @ctlz_v16i8(ptr %x, ptr %y) nounwind {
; RVF-NEXT: vzext.vf2 v12, v8
; RVF-NEXT: vfwcvt.f.xu.v v8, v12
; RVF-NEXT: vnsrl.wi v12, v8, 23
-; RVF-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RVF-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RVF-NEXT: vnsrl.wi v8, v12, 0
; RVF-NEXT: vrsub.vx v8, v8, a1
; RVF-NEXT: li a1, 8
@@ -59,7 +59,7 @@ define void @ctlz_v16i8(ptr %x, ptr %y) nounwind {
; RVD-NEXT: vzext.vf2 v12, v8
; RVD-NEXT: vfwcvt.f.xu.v v8, v12
; RVD-NEXT: vnsrl.wi v12, v8, 23
-; RVD-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RVD-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RVD-NEXT: vnsrl.wi v8, v12, 0
; RVD-NEXT: vrsub.vx v8, v8, a1
; RVD-NEXT: li a1, 8
@@ -359,7 +359,7 @@ define void @ctlz_v2i64(ptr %x, ptr %y) nounwind {
; RVF-NEXT: vsrl.vi v8, v10, 23
; RVF-NEXT: vwsubu.vv v10, v9, v8
; RVF-NEXT: li a1, 64
-; RVF-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RVF-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RVF-NEXT: vminu.vx v8, v10, a1
; RVF-NEXT: vse64.v v8, (a0)
; RVF-NEXT: ret
@@ -750,7 +750,7 @@ define void @ctlz_v4i64(ptr %x, ptr %y) nounwind {
; RVF-NEXT: vsrl.vi v11, v11, 23
; RVF-NEXT: vwsubu.vv v8, v10, v11
; RVF-NEXT: li a1, 64
-; RVF-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RVF-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RVF-NEXT: vminu.vx v8, v8, a1
; RVF-NEXT: vse64.v v8, (a0)
; RVF-NEXT: ret
@@ -820,7 +820,7 @@ define void @ctlz_zero_undef_v16i8(ptr %x, ptr %y) nounwind {
; RVF-NEXT: vzext.vf2 v12, v8
; RVF-NEXT: vfwcvt.f.xu.v v8, v12
; RVF-NEXT: vnsrl.wi v12, v8, 23
-; RVF-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RVF-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RVF-NEXT: vnsrl.wi v8, v12, 0
; RVF-NEXT: li a1, 134
; RVF-NEXT: vrsub.vx v8, v8, a1
@@ -834,7 +834,7 @@ define void @ctlz_zero_undef_v16i8(ptr %x, ptr %y) nounwind {
; RVD-NEXT: vzext.vf2 v12, v8
; RVD-NEXT: vfwcvt.f.xu.v v8, v12
; RVD-NEXT: vnsrl.wi v12, v8, 23
-; RVD-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RVD-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RVD-NEXT: vnsrl.wi v8, v12, 0
; RVD-NEXT: li a1, 134
; RVD-NEXT: vrsub.vx v8, v8, a1
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
index 307b143f4449f..e45e97a941f2d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
@@ -38,11 +38,11 @@ define void @cttz_v16i8(ptr %x, ptr %y) nounwind {
; RVF-NEXT: li a1, 127
; RVF-NEXT: vrsub.vi v8, v14, 0
; RVF-NEXT: vand.vv v8, v14, v8
-; RVF-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RVF-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RVF-NEXT: vzext.vf2 v12, v8
; RVF-NEXT: vfwcvt.f.xu.v v8, v12
; RVF-NEXT: vnsrl.wi v12, v8, 23
-; RVF-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RVF-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RVF-NEXT: vnsrl.wi v8, v12, 0
; RVF-NEXT: vmseq.vi v0, v14, 0
; RVF-NEXT: vsub.vx v8, v8, a1
@@ -57,11 +57,11 @@ define void @cttz_v16i8(ptr %x, ptr %y) nounwind {
; RVD-NEXT: li a1, 127
; RVD-NEXT: vrsub.vi v8, v14, 0
; RVD-NEXT: vand.vv v8, v14, v8
-; RVD-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RVD-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RVD-NEXT: vzext.vf2 v12, v8
; RVD-NEXT: vfwcvt.f.xu.v v8, v12
; RVD-NEXT: vnsrl.wi v12, v8, 23
-; RVD-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RVD-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RVD-NEXT: vnsrl.wi v8, v12, 0
; RVD-NEXT: vmseq.vi v0, v14, 0
; RVD-NEXT: vsub.vx v8, v8, a1
@@ -332,17 +332,17 @@ define void @cttz_v2i64(ptr %x, ptr %y) nounwind {
; RVF-NEXT: fsrmi a1, 1
; RVF-NEXT: vrsub.vi v9, v8, 0
; RVF-NEXT: vand.vv v9, v8, v9
-; RVF-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RVF-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RVF-NEXT: vfncvt.f.xu.w v10, v9
; RVF-NEXT: fsrm a1
; RVF-NEXT: li a1, 127
-; RVF-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RVF-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RVF-NEXT: vmseq.vi v0, v8, 0
-; RVF-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RVF-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RVF-NEXT: vsrl.vi v8, v10, 23
; RVF-NEXT: vwsubu.vx v9, v8, a1
; RVF-NEXT: li a1, 64
-; RVF-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RVF-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RVF-NEXT: vmerge.vxm v8, v9, a1, v0
; RVF-NEXT: vse64.v v8, (a0)
; RVF-NEXT: ret
@@ -709,17 +709,17 @@ define void @cttz_v4i64(ptr %x, ptr %y) nounwind {
; RVF-NEXT: fsrmi a1, 1
; RVF-NEXT: vrsub.vi v10, v8, 0
; RVF-NEXT: vand.vv v10, v8, v10
-; RVF-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RVF-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RVF-NEXT: vfncvt.f.xu.w v12, v10
; RVF-NEXT: fsrm a1
; RVF-NEXT: li a1, 127
-; RVF-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RVF-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RVF-NEXT: vmseq.vi v0, v8, 0
-; RVF-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RVF-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RVF-NEXT: vsrl.vi v10, v12, 23
; RVF-NEXT: vwsubu.vx v8, v10, a1
; RVF-NEXT: li a1, 64
-; RVF-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RVF-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RVF-NEXT: vmerge.vxm v8, v8, a1, v0
; RVF-NEXT: vse64.v v8, (a0)
; RVF-NEXT: ret
@@ -787,11 +787,11 @@ define void @cttz_zero_undef_v16i8(ptr %x, ptr %y) nounwind {
; RVF-NEXT: vle8.v v8, (a0)
; RVF-NEXT: vrsub.vi v9, v8, 0
; RVF-NEXT: vand.vv v8, v8, v9
-; RVF-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RVF-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RVF-NEXT: vzext.vf2 v12, v8
; RVF-NEXT: vfwcvt.f.xu.v v8, v12
; RVF-NEXT: vnsrl.wi v12, v8, 23
-; RVF-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RVF-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RVF-NEXT: vnsrl.wi v8, v12, 0
; RVF-NEXT: li a1, 127
; RVF-NEXT: vsub.vx v8, v8, a1
@@ -804,11 +804,11 @@ define void @cttz_zero_undef_v16i8(ptr %x, ptr %y) nounwind {
; RVD-NEXT: vle8.v v8, (a0)
; RVD-NEXT: vrsub.vi v9, v8, 0
; RVD-NEXT: vand.vv v8, v8, v9
-; RVD-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RVD-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RVD-NEXT: vzext.vf2 v12, v8
; RVD-NEXT: vfwcvt.f.xu.v v8, v12
; RVD-NEXT: vnsrl.wi v12, v8, 23
-; RVD-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RVD-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RVD-NEXT: vnsrl.wi v8, v12, 0
; RVD-NEXT: li a1, 127
; RVD-NEXT: vsub.vx v8, v8, a1
@@ -1063,7 +1063,7 @@ define void @cttz_zero_undef_v2i64(ptr %x, ptr %y) nounwind {
; RVF-NEXT: fsrmi a1, 1
; RVF-NEXT: vrsub.vi v9, v8, 0
; RVF-NEXT: vand.vv v8, v8, v9
-; RVF-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RVF-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RVF-NEXT: vfncvt.f.xu.w v9, v8
; RVF-NEXT: fsrm a1
; RVF-NEXT: vsrl.vi v8, v9, 23
@@ -1411,7 +1411,7 @@ define void @cttz_zero_undef_v4i64(ptr %x, ptr %y) nounwind {
; RVF-NEXT: fsrmi a1, 1
; RVF-NEXT: vrsub.vi v10, v8, 0
; RVF-NEXT: vand.vv v8, v8, v10
-; RVF-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RVF-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RVF-NEXT: vfncvt.f.xu.w v10, v8
; RVF-NEXT: fsrm a1
; RVF-NEXT: vsrl.vi v10, v10, 23
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
index bb2b57fbcc3b7..74cf6240408fa 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
@@ -569,7 +569,7 @@ define void @truncstore_v2i32_v2i8(<2 x i32> %x, ptr %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
@@ -619,7 +619,7 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, ptr %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
@@ -669,7 +669,7 @@ define void @truncstore_v8i32_v8i8(<8 x i32> %x, ptr %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
@@ -719,7 +719,7 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, ptr %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v12, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
@@ -769,9 +769,9 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, ptr %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
@@ -785,7 +785,7 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, ptr %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
@@ -811,9 +811,9 @@ define void @truncstore_v4i64_v4i8(<4 x i64> %x, ptr %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
@@ -827,7 +827,7 @@ define void @truncstore_v4i64_v4i16(<4 x i64> %x, ptr %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
@@ -853,9 +853,9 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, ptr %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v12, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
@@ -869,7 +869,7 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, ptr %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v12, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
@@ -895,9 +895,9 @@ define void @truncstore_v16i64_v16i8(<16 x i64> %x, ptr %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v16, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v16, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vse8.v v10, (a0)
; CHECK-NEXT: ret
@@ -911,7 +911,7 @@ define void @truncstore_v16i64_v16i16(<16 x i64> %x, ptr %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v16, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v16, 0
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
index fb070b24a4f34..862bcb0f27877 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
@@ -106,7 +106,7 @@ define i1 @extractelt_v16i1(ptr %x, i64 %idx) nounwind {
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vle8.v v8, (a0)
; RV32-NEXT: vmseq.vi v8, v8, 0
-; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: srl a0, a0, a1
; RV32-NEXT: andi a0, a0, 1
@@ -117,7 +117,7 @@ define i1 @extractelt_v16i1(ptr %x, i64 %idx) nounwind {
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vle8.v v8, (a0)
; RV64-NEXT: vmseq.vi v8, v8, 0
-; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: srl a0, a0, a1
; RV64-NEXT: andi a0, a0, 1
@@ -128,7 +128,7 @@ define i1 @extractelt_v16i1(ptr %x, i64 %idx) nounwind {
; RV32ZBS-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32ZBS-NEXT: vle8.v v8, (a0)
; RV32ZBS-NEXT: vmseq.vi v8, v8, 0
-; RV32ZBS-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32ZBS-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV32ZBS-NEXT: vmv.x.s a0, v8
; RV32ZBS-NEXT: bext a0, a0, a1
; RV32ZBS-NEXT: ret
@@ -138,7 +138,7 @@ define i1 @extractelt_v16i1(ptr %x, i64 %idx) nounwind {
; RV64ZBS-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64ZBS-NEXT: vle8.v v8, (a0)
; RV64ZBS-NEXT: vmseq.vi v8, v8, 0
-; RV64ZBS-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZBS-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV64ZBS-NEXT: vmv.x.s a0, v8
; RV64ZBS-NEXT: bext a0, a0, a1
; RV64ZBS-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
index dba5d26c216fa..b58fab42b9f51 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
@@ -540,9 +540,9 @@ define bfloat @extractelt_v8bf16_idx(<8 x bfloat> %a, i32 zeroext %idx) nounwind
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfadd.vv v8, v10, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vslidedown.vx v8, v10, a0
; CHECK-NEXT: vmv.x.s a0, v8
@@ -553,9 +553,9 @@ define bfloat @extractelt_v8bf16_idx(<8 x bfloat> %a, i32 zeroext %idx) nounwind
; VISNI: # %bb.0:
; VISNI-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; VISNI-NEXT: vfwcvtbf16.f.f.v v10, v8
-; VISNI-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; VISNI-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; VISNI-NEXT: vfadd.vv v8, v10, v10
-; VISNI-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; VISNI-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; VISNI-NEXT: vfncvtbf16.f.f.w v10, v8
; VISNI-NEXT: vslidedown.vx v8, v10, a0
; VISNI-NEXT: vmv.x.s a0, v8
@@ -579,9 +579,9 @@ define half @extractelt_v8f16_idx(<8 x half> %a, i32 zeroext %idx) nounwind {
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfadd.vv v8, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vslidedown.vx v8, v10, a0
; ZVFHMIN-NEXT: vmv.x.s a0, v8
@@ -737,9 +737,9 @@ define bfloat @extractelt_v16bf16_idx(<16 x bfloat> %a, i32 zeroext %idx) nounwi
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfadd.vv v8, v12, v12
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v8
; CHECK-NEXT: vslidedown.vx v8, v12, a0
; CHECK-NEXT: vmv.x.s a0, v8
@@ -750,9 +750,9 @@ define bfloat @extractelt_v16bf16_idx(<16 x bfloat> %a, i32 zeroext %idx) nounwi
; VISNI: # %bb.0:
; VISNI-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; VISNI-NEXT: vfwcvtbf16.f.f.v v12, v8
-; VISNI-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; VISNI-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; VISNI-NEXT: vfadd.vv v8, v12, v12
-; VISNI-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; VISNI-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; VISNI-NEXT: vfncvtbf16.f.f.w v12, v8
; VISNI-NEXT: vslidedown.vx v8, v12, a0
; VISNI-NEXT: vmv.x.s a0, v8
@@ -776,9 +776,9 @@ define half @extractelt_v16f16_idx(<16 x half> %a, i32 zeroext %idx) nounwind {
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfadd.vv v8, v12, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v8
; ZVFHMIN-NEXT: vslidedown.vx v8, v12, a0
; ZVFHMIN-NEXT: vmv.x.s a0, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
index 71b0624d91f22..79b2bc7014b31 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
@@ -16,11 +16,11 @@ define <1 x half> @ceil_v1f16(<1 x half> %x) strictfp {
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 3
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <1 x half> @llvm.experimental.constrained.ceil.v1f16(<1 x half> %x, metadata !"fpexcept.strict")
@@ -40,11 +40,11 @@ define <2 x half> @ceil_v2f16(<2 x half> %x) strictfp {
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 3
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <2 x half> @llvm.experimental.constrained.ceil.v2f16(<2 x half> %x, metadata !"fpexcept.strict")
@@ -64,11 +64,11 @@ define <4 x half> @ceil_v4f16(<4 x half> %x) strictfp {
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 3
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <4 x half> @llvm.experimental.constrained.ceil.v4f16(<4 x half> %x, metadata !"fpexcept.strict")
@@ -88,11 +88,11 @@ define <8 x half> @ceil_v8f16(<8 x half> %x) strictfp {
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 3
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <8 x half> @llvm.experimental.constrained.ceil.v8f16(<8 x half> %x, metadata !"fpexcept.strict")
@@ -112,11 +112,11 @@ define <16 x half> @ceil_v16f16(<16 x half> %x) strictfp {
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 3
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
%a = call <16 x half> @llvm.experimental.constrained.ceil.v16f16(<16 x half> %x, metadata !"fpexcept.strict")
@@ -160,11 +160,11 @@ define <1 x float> @ceil_v1f32(<1 x float> %x) strictfp {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 3
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <1 x float> @llvm.experimental.constrained.ceil.v1f32(<1 x float> %x, metadata !"fpexcept.strict")
@@ -183,11 +183,11 @@ define <2 x float> @ceil_v2f32(<2 x float> %x) strictfp {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 3
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <2 x float> @llvm.experimental.constrained.ceil.v2f32(<2 x float> %x, metadata !"fpexcept.strict")
@@ -206,11 +206,11 @@ define <4 x float> @ceil_v4f32(<4 x float> %x) strictfp {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 3
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <4 x float> @llvm.experimental.constrained.ceil.v4f32(<4 x float> %x, metadata !"fpexcept.strict")
@@ -229,11 +229,11 @@ define <8 x float> @ceil_v8f32(<8 x float> %x) strictfp {
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 3
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
%a = call <8 x float> @llvm.experimental.constrained.ceil.v8f32(<8 x float> %x, metadata !"fpexcept.strict")
@@ -252,11 +252,11 @@ define <16 x float> @ceil_v16f32(<16 x float> %x) strictfp {
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 3
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret
%a = call <16 x float> @llvm.experimental.constrained.ceil.v16f32(<16 x float> %x, metadata !"fpexcept.strict")
@@ -275,11 +275,11 @@ define <1 x double> @ceil_v1f64(<1 x double> %x) strictfp {
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32-NEXT: ret
;
@@ -294,11 +294,11 @@ define <1 x double> @ceil_v1f64(<1 x double> %x) strictfp {
; RV64-NEXT: fmv.d.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64-NEXT: ret
%a = call <1 x double> @llvm.experimental.constrained.ceil.v1f64(<1 x double> %x, metadata !"fpexcept.strict")
@@ -317,11 +317,11 @@ define <2 x double> @ceil_v2f64(<2 x double> %x) strictfp {
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32-NEXT: ret
;
@@ -336,11 +336,11 @@ define <2 x double> @ceil_v2f64(<2 x double> %x) strictfp {
; RV64-NEXT: fmv.d.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64-NEXT: ret
%a = call <2 x double> @llvm.experimental.constrained.ceil.v2f64(<2 x double> %x, metadata !"fpexcept.strict")
@@ -359,11 +359,11 @@ define <4 x double> @ceil_v4f64(<4 x double> %x) strictfp {
; RV32-NEXT: vfabs.v v10, v8
; RV32-NEXT: vmflt.vf v0, v10, fa5
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; RV32-NEXT: ret
;
@@ -378,11 +378,11 @@ define <4 x double> @ceil_v4f64(<4 x double> %x) strictfp {
; RV64-NEXT: fmv.d.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v10, fa5
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; RV64-NEXT: ret
%a = call <4 x double> @llvm.experimental.constrained.ceil.v4f64(<4 x double> %x, metadata !"fpexcept.strict")
@@ -401,11 +401,11 @@ define <8 x double> @ceil_v8f64(<8 x double> %x) strictfp {
; RV32-NEXT: vfabs.v v12, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; RV32-NEXT: ret
;
@@ -420,11 +420,11 @@ define <8 x double> @ceil_v8f64(<8 x double> %x) strictfp {
; RV64-NEXT: fmv.d.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; RV64-NEXT: ret
%a = call <8 x double> @llvm.experimental.constrained.ceil.v8f64(<8 x double> %x, metadata !"fpexcept.strict")
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
index 9eca66eea865c..590ca0f9a4901 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
@@ -16,11 +16,11 @@ define <1 x half> @floor_v1f16(<1 x half> %x) strictfp {
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 2
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <1 x half> @llvm.experimental.constrained.floor.v1f16(<1 x half> %x, metadata !"fpexcept.strict")
@@ -40,11 +40,11 @@ define <2 x half> @floor_v2f16(<2 x half> %x) strictfp {
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 2
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <2 x half> @llvm.experimental.constrained.floor.v2f16(<2 x half> %x, metadata !"fpexcept.strict")
@@ -64,11 +64,11 @@ define <4 x half> @floor_v4f16(<4 x half> %x) strictfp {
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 2
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <4 x half> @llvm.experimental.constrained.floor.v4f16(<4 x half> %x, metadata !"fpexcept.strict")
@@ -88,11 +88,11 @@ define <8 x half> @floor_v8f16(<8 x half> %x) strictfp {
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 2
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <8 x half> @llvm.experimental.constrained.floor.v8f16(<8 x half> %x, metadata !"fpexcept.strict")
@@ -112,11 +112,11 @@ define <16 x half> @floor_v16f16(<16 x half> %x) strictfp {
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 2
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
%a = call <16 x half> @llvm.experimental.constrained.floor.v16f16(<16 x half> %x, metadata !"fpexcept.strict")
@@ -160,11 +160,11 @@ define <1 x float> @floor_v1f32(<1 x float> %x) strictfp {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 2
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <1 x float> @llvm.experimental.constrained.floor.v1f32(<1 x float> %x, metadata !"fpexcept.strict")
@@ -183,11 +183,11 @@ define <2 x float> @floor_v2f32(<2 x float> %x) strictfp {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 2
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <2 x float> @llvm.experimental.constrained.floor.v2f32(<2 x float> %x, metadata !"fpexcept.strict")
@@ -206,11 +206,11 @@ define <4 x float> @floor_v4f32(<4 x float> %x) strictfp {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 2
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <4 x float> @llvm.experimental.constrained.floor.v4f32(<4 x float> %x, metadata !"fpexcept.strict")
@@ -229,11 +229,11 @@ define <8 x float> @floor_v8f32(<8 x float> %x) strictfp {
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 2
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
%a = call <8 x float> @llvm.experimental.constrained.floor.v8f32(<8 x float> %x, metadata !"fpexcept.strict")
@@ -252,11 +252,11 @@ define <16 x float> @floor_v16f32(<16 x float> %x) strictfp {
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 2
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret
%a = call <16 x float> @llvm.experimental.constrained.floor.v16f32(<16 x float> %x, metadata !"fpexcept.strict")
@@ -275,11 +275,11 @@ define <1 x double> @floor_v1f64(<1 x double> %x) strictfp {
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
; RV32-NEXT: fsrmi a0, 2
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32-NEXT: ret
;
@@ -294,11 +294,11 @@ define <1 x double> @floor_v1f64(<1 x double> %x) strictfp {
; RV64-NEXT: fmv.d.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: fsrmi a0, 2
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64-NEXT: ret
%a = call <1 x double> @llvm.experimental.constrained.floor.v1f64(<1 x double> %x, metadata !"fpexcept.strict")
@@ -317,11 +317,11 @@ define <2 x double> @floor_v2f64(<2 x double> %x) strictfp {
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
; RV32-NEXT: fsrmi a0, 2
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32-NEXT: ret
;
@@ -336,11 +336,11 @@ define <2 x double> @floor_v2f64(<2 x double> %x) strictfp {
; RV64-NEXT: fmv.d.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: fsrmi a0, 2
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64-NEXT: ret
%a = call <2 x double> @llvm.experimental.constrained.floor.v2f64(<2 x double> %x, metadata !"fpexcept.strict")
@@ -359,11 +359,11 @@ define <4 x double> @floor_v4f64(<4 x double> %x) strictfp {
; RV32-NEXT: vfabs.v v10, v8
; RV32-NEXT: vmflt.vf v0, v10, fa5
; RV32-NEXT: fsrmi a0, 2
-; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; RV32-NEXT: ret
;
@@ -378,11 +378,11 @@ define <4 x double> @floor_v4f64(<4 x double> %x) strictfp {
; RV64-NEXT: fmv.d.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v10, fa5
; RV64-NEXT: fsrmi a0, 2
-; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; RV64-NEXT: ret
%a = call <4 x double> @llvm.experimental.constrained.floor.v4f64(<4 x double> %x, metadata !"fpexcept.strict")
@@ -401,11 +401,11 @@ define <8 x double> @floor_v8f64(<8 x double> %x) strictfp {
; RV32-NEXT: vfabs.v v12, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
; RV32-NEXT: fsrmi a0, 2
-; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; RV32-NEXT: ret
;
@@ -420,11 +420,11 @@ define <8 x double> @floor_v8f64(<8 x double> %x) strictfp {
; RV64-NEXT: fmv.d.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: fsrmi a0, 2
-; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; RV64-NEXT: ret
%a = call <8 x double> @llvm.experimental.constrained.floor.v8f64(<8 x double> %x, metadata !"fpexcept.strict")
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
index e2cbdd3911ad5..ea2e8e3742400 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
@@ -25,16 +25,16 @@ define <2 x half> @vfmax_v2f16_vv(<2 x half> %a, <2 x half> %b) {
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
; ZVFHMIN-NEXT: vfmax.vv v9, v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%v = call <2 x half> @llvm.maximum.v2f16(<2 x half> %a, <2 x half> %b)
@@ -58,16 +58,16 @@ define <4 x half> @vfmax_v4f16_vv(<4 x half> %a, <4 x half> %b) {
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
; ZVFHMIN-NEXT: vfmax.vv v9, v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%v = call <4 x half> @llvm.maximum.v4f16(<4 x half> %a, <4 x half> %b)
@@ -91,16 +91,16 @@ define <8 x half> @vfmax_v8f16_vv(<8 x half> %a, <8 x half> %b) {
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v12, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
; ZVFHMIN-NEXT: vmerge.vvm v10, v12, v10, v0
; ZVFHMIN-NEXT: vfmax.vv v10, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
; ZVFHMIN-NEXT: ret
%v = call <8 x half> @llvm.maximum.v8f16(<8 x half> %a, <8 x half> %b)
@@ -124,16 +124,16 @@ define <16 x half> @vfmax_v16f16_vv(<16 x half> %a, <16 x half> %b) {
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v16, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
; ZVFHMIN-NEXT: vmerge.vvm v12, v16, v12, v0
; ZVFHMIN-NEXT: vfmax.vv v12, v12, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: ret
%v = call <16 x half> @llvm.maximum.v16f16(<16 x half> %a, <16 x half> %b)
@@ -281,9 +281,9 @@ define <2 x half> @vfmax_v2f16_vv_nnan(<2 x half> %a, <2 x half> %b) {
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfmax.vv v9, v9, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%v = call nnan <2 x half> @llvm.maximum.v2f16(<2 x half> %a, <2 x half> %b)
@@ -305,18 +305,18 @@ define <2 x half> @vfmax_v2f16_vv_nnana(<2 x half> %a, <2 x half> %b) {
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfadd.vv v9, v10, v10
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vmerge.vvm v10, v8, v9, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
; ZVFHMIN-NEXT: vfmax.vv v9, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%c = fadd nnan <2 x half> %a, %a
@@ -339,18 +339,18 @@ define <2 x half> @vfmax_v2f16_vv_nnanb(<2 x half> %a, <2 x half> %b) {
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfadd.vv v8, v10, v10
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vmerge.vvm v10, v9, v8, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0
; ZVFHMIN-NEXT: vfmax.vv v9, v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%c = fadd nnan <2 x half> %b, %b
@@ -378,25 +378,25 @@ define <4 x half> @vfmax_v2f16_vv_nnan_insert_subvector(<2 x half> %a, <2 x half
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfadd.vv v9, v11, v11
; ZVFHMIN-NEXT: vfadd.vv v8, v8, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v9
; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v8
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vslideup.vi v11, v9, 2
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFHMIN-NEXT: vmerge.vvm v10, v8, v9, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
; ZVFHMIN-NEXT: vfmax.vv v9, v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%d = fadd nnan <2 x half> %a, %a
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximumnum.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximumnum.ll
index c8cea368f905e..394e60c2923c7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximumnum.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximumnum.ll
@@ -102,9 +102,9 @@ define <2 x half> @max_v2f16(<2 x half> %a, <2 x half> %b) {
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfmax.vv v9, v9, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
entry:
@@ -124,9 +124,9 @@ define <4 x half> @max_v4f16(<4 x half> %a, <4 x half> %b) {
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfmax.vv v9, v9, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
entry:
@@ -146,9 +146,9 @@ define <8 x half> @max_v8f16(<8 x half> %a, <8 x half> %b) {
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmax.vv v10, v12, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
; ZVFHMIN-NEXT: ret
entry:
@@ -168,9 +168,9 @@ define <9 x half> @max_v9f16(<9 x half> %a, <9 x half> %b) {
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfmax.vv v12, v16, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: ret
entry:
@@ -190,9 +190,9 @@ define <16 x half> @max_v16f16(<16 x half> %a, <16 x half> %b) {
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfmax.vv v12, v16, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
index 9c75af359a4cb..1e84a2d69a555 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
@@ -25,16 +25,16 @@ define <2 x half> @vfmin_v2f16_vv(<2 x half> %a, <2 x half> %b) {
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
; ZVFHMIN-NEXT: vfmin.vv v9, v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%v = call <2 x half> @llvm.minimum.v2f16(<2 x half> %a, <2 x half> %b)
@@ -58,16 +58,16 @@ define <4 x half> @vfmin_v4f16_vv(<4 x half> %a, <4 x half> %b) {
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
; ZVFHMIN-NEXT: vfmin.vv v9, v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%v = call <4 x half> @llvm.minimum.v4f16(<4 x half> %a, <4 x half> %b)
@@ -91,16 +91,16 @@ define <8 x half> @vfmin_v8f16_vv(<8 x half> %a, <8 x half> %b) {
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v12, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
; ZVFHMIN-NEXT: vmerge.vvm v10, v12, v10, v0
; ZVFHMIN-NEXT: vfmin.vv v10, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
; ZVFHMIN-NEXT: ret
%v = call <8 x half> @llvm.minimum.v8f16(<8 x half> %a, <8 x half> %b)
@@ -124,16 +124,16 @@ define <16 x half> @vfmin_v16f16_vv(<16 x half> %a, <16 x half> %b) {
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v16, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
; ZVFHMIN-NEXT: vmerge.vvm v12, v16, v12, v0
; ZVFHMIN-NEXT: vfmin.vv v12, v12, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: ret
%v = call <16 x half> @llvm.minimum.v16f16(<16 x half> %a, <16 x half> %b)
@@ -281,9 +281,9 @@ define <2 x half> @vfmin_v2f16_vv_nnan(<2 x half> %a, <2 x half> %b) {
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfmin.vv v9, v9, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%v = call nnan <2 x half> @llvm.minimum.v2f16(<2 x half> %a, <2 x half> %b)
@@ -305,18 +305,18 @@ define <2 x half> @vfmin_v2f16_vv_nnana(<2 x half> %a, <2 x half> %b) {
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfadd.vv v9, v10, v10
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vmerge.vvm v10, v8, v9, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
; ZVFHMIN-NEXT: vfmin.vv v9, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%c = fadd nnan <2 x half> %a, %a
@@ -339,18 +339,18 @@ define <2 x half> @vfmin_v2f16_vv_nnanb(<2 x half> %a, <2 x half> %b) {
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfadd.vv v8, v10, v10
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vmerge.vvm v10, v9, v8, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0
; ZVFHMIN-NEXT: vfmin.vv v9, v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%c = fadd nnan <2 x half> %b, %b
@@ -378,25 +378,25 @@ define <4 x half> @vfmin_v2f16_vv_nnan_insert_subvector(<2 x half> %a, <2 x half
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfadd.vv v9, v11, v11
; ZVFHMIN-NEXT: vfadd.vv v8, v8, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v9
; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v8
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vslideup.vi v11, v9, 2
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFHMIN-NEXT: vmerge.vvm v10, v8, v9, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
; ZVFHMIN-NEXT: vfmin.vv v9, v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%d = fadd nnan <2 x half> %a, %a
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimumnum.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimumnum.ll
index 36114d56aa0d6..e13836f17e0ea 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimumnum.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimumnum.ll
@@ -102,9 +102,9 @@ define <2 x half> @min_v2f16(<2 x half> %a, <2 x half> %b) {
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfmin.vv v9, v9, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
entry:
@@ -124,9 +124,9 @@ define <4 x half> @min_v4f16(<4 x half> %a, <4 x half> %b) {
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfmin.vv v9, v9, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
entry:
@@ -146,9 +146,9 @@ define <8 x half> @min_v8f16(<8 x half> %a, <8 x half> %b) {
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmin.vv v10, v12, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
; ZVFHMIN-NEXT: ret
entry:
@@ -168,9 +168,9 @@ define <9 x half> @min_v9f16(<9 x half> %a, <9 x half> %b) {
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfmin.vv v12, v16, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: ret
entry:
@@ -190,9 +190,9 @@ define <16 x half> @min_v16f16(<16 x half> %a, <16 x half> %b) {
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfmin.vv v12, v16, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll
index dd1b99bee6d55..81eb57fd48a7e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll
@@ -18,10 +18,10 @@ define <2 x half> @nearbyint_v2f16(<2 x half> %v) strictfp {
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: frflags a0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: fsflags a0
; CHECK-NEXT: ret
@@ -43,10 +43,10 @@ define <4 x half> @nearbyint_v4f16(<4 x half> %v) strictfp {
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: frflags a0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: fsflags a0
; CHECK-NEXT: ret
@@ -68,10 +68,10 @@ define <8 x half> @nearbyint_v8f16(<8 x half> %v) strictfp {
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: frflags a0
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: fsflags a0
; CHECK-NEXT: ret
@@ -93,10 +93,10 @@ define <16 x half> @nearbyint_v16f16(<16 x half> %v) strictfp {
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: frflags a0
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; CHECK-NEXT: fsflags a0
; CHECK-NEXT: ret
@@ -143,10 +143,10 @@ define <2 x float> @nearbyint_v2f32(<2 x float> %v) strictfp {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: frflags a0
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: fsflags a0
; CHECK-NEXT: ret
@@ -167,10 +167,10 @@ define <4 x float> @nearbyint_v4f32(<4 x float> %v) strictfp {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: frflags a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: fsflags a0
; CHECK-NEXT: ret
@@ -191,10 +191,10 @@ define <8 x float> @nearbyint_v8f32(<8 x float> %v) strictfp {
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: frflags a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; CHECK-NEXT: fsflags a0
; CHECK-NEXT: ret
@@ -215,10 +215,10 @@ define <16 x float> @nearbyint_v16f32(<16 x float> %v) strictfp {
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: frflags a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; CHECK-NEXT: fsflags a0
; CHECK-NEXT: ret
@@ -239,10 +239,10 @@ define <2 x double> @nearbyint_v2f64(<2 x double> %v) strictfp {
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
; RV32-NEXT: frflags a0
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32-NEXT: fsflags a0
; RV32-NEXT: ret
@@ -258,10 +258,10 @@ define <2 x double> @nearbyint_v2f64(<2 x double> %v) strictfp {
; RV64-NEXT: fmv.d.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: frflags a0
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64-NEXT: fsflags a0
; RV64-NEXT: ret
@@ -282,10 +282,10 @@ define <4 x double> @nearbyint_v4f64(<4 x double> %v) strictfp {
; RV32-NEXT: vfabs.v v10, v8
; RV32-NEXT: vmflt.vf v0, v10, fa5
; RV32-NEXT: frflags a0
-; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; RV32-NEXT: fsflags a0
; RV32-NEXT: ret
@@ -301,10 +301,10 @@ define <4 x double> @nearbyint_v4f64(<4 x double> %v) strictfp {
; RV64-NEXT: fmv.d.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v10, fa5
; RV64-NEXT: frflags a0
-; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; RV64-NEXT: fsflags a0
; RV64-NEXT: ret
@@ -325,10 +325,10 @@ define <8 x double> @nearbyint_v8f64(<8 x double> %v) strictfp {
; RV32-NEXT: vfabs.v v12, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
; RV32-NEXT: frflags a0
-; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; RV32-NEXT: fsflags a0
; RV32-NEXT: ret
@@ -344,10 +344,10 @@ define <8 x double> @nearbyint_v8f64(<8 x double> %v) strictfp {
; RV64-NEXT: fmv.d.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: frflags a0
-; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; RV64-NEXT: fsflags a0
; RV64-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
index 248ec1369076b..dee780903a5e7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
@@ -1863,11 +1863,11 @@ define <8 x float> @buildvec_vfredusum_slideup_leading_undef(float %start, <8 x
; CHECK-NEXT: vfredusum.vs v8, v10, v17
; CHECK-NEXT: vfredusum.vs v10, v12, v17
; CHECK-NEXT: vfredusum.vs v12, v14, v17
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, tu, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, tu, ma
; CHECK-NEXT: vslideup.vi v10, v12, 1
; CHECK-NEXT: vslideup.vi v8, v10, 1
; CHECK-NEXT: vslideup.vi v16, v8, 1
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v16, 4
; CHECK-NEXT: ret
%252 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg1)
@@ -1890,7 +1890,7 @@ define <8 x float> @buildvec_vfredusum_slideup_trailing_undef(float %start, <8 x
; CHECK-NEXT: vfredusum.vs v10, v10, v16
; CHECK-NEXT: vfredusum.vs v12, v12, v16
; CHECK-NEXT: vfredusum.vs v14, v14, v16
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, tu, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, tu, ma
; CHECK-NEXT: vslideup.vi v12, v14, 1
; CHECK-NEXT: vslideup.vi v10, v12, 1
; CHECK-NEXT: vslideup.vi v8, v10, 1
@@ -1942,11 +1942,11 @@ define <8 x float> @buildvec_vfredusum_slideup_mid_undef(float %start, <8 x floa
; CHECK-NEXT: vfredusum.vs v10, v10, v16
; CHECK-NEXT: vfredusum.vs v12, v12, v16
; CHECK-NEXT: vfredusum.vs v14, v14, v16
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, tu, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, tu, ma
; CHECK-NEXT: vslideup.vi v12, v14, 1
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vslideup.vi v14, v12, 4
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, tu, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, tu, ma
; CHECK-NEXT: vslideup.vi v10, v14, 1
; CHECK-NEXT: vslideup.vi v8, v10, 1
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
index 78ad10033feaa..1199278ab2f80 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
@@ -22,7 +22,7 @@ define void @fpext_v2f16_v2f64(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfwcvt.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v8, v9
; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret
@@ -52,7 +52,7 @@ define void @fpext_v8f16_v8f64(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfwcvt.f.f.v v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v8, v12
; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret
@@ -82,7 +82,7 @@ define void @fpround_v2f64_v2f16(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfncvt.rod.f.f.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfncvt.f.f.w v8, v9
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
@@ -112,7 +112,7 @@ define void @fpround_v8f64_v8f16(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfncvt.rod.f.f.w v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvt.f.f.w v8, v12
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
index e256ba9dd5997..25c1ecf3dffb3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
@@ -21,7 +21,7 @@ define void @fcmp_oeq_vv_v8f16(ptr %x, ptr %y, ptr %z) {
; ZVFHMIN-NEXT: vle16.v v12, (a0)
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v12, v10, v8
; ZVFHMIN-NEXT: vsm.v v12, (a2)
; ZVFHMIN-NEXT: ret
@@ -49,7 +49,7 @@ define void @fcmp_oeq_vv_v8f16_nonans(ptr %x, ptr %y, ptr %z) {
; ZVFHMIN-NEXT: vle16.v v12, (a0)
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v12, v10, v8
; ZVFHMIN-NEXT: vsm.v v12, (a2)
; ZVFHMIN-NEXT: ret
@@ -67,7 +67,7 @@ define void @fcmp_une_vv_v4f32(ptr %x, ptr %y, ptr %z) {
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vle32.v v9, (a1)
; CHECK-NEXT: vmfne.vv v0, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -92,7 +92,7 @@ define void @fcmp_une_vv_v4f32_nonans(ptr %x, ptr %y, ptr %z) {
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vle32.v v9, (a1)
; CHECK-NEXT: vmfne.vv v0, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -117,7 +117,7 @@ define void @fcmp_ogt_vv_v2f64(ptr %x, ptr %y, ptr %z) {
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vle64.v v9, (a1)
; CHECK-NEXT: vmflt.vv v0, v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -142,7 +142,7 @@ define void @fcmp_ogt_vv_v2f64_nonans(ptr %x, ptr %y, ptr %z) {
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vle64.v v9, (a1)
; CHECK-NEXT: vmflt.vv v0, v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -177,7 +177,7 @@ define void @fcmp_olt_vv_v16f16(ptr %x, ptr %y, ptr %z) {
; ZVFHMIN-NEXT: vle16.v v16, (a0)
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v16
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vmflt.vv v16, v12, v8
; ZVFHMIN-NEXT: vsm.v v16, (a2)
; ZVFHMIN-NEXT: ret
@@ -205,7 +205,7 @@ define void @fcmp_olt_vv_v16f16_nonans(ptr %x, ptr %y, ptr %z) {
; ZVFHMIN-NEXT: vle16.v v16, (a0)
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v16
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vmflt.vv v16, v12, v8
; ZVFHMIN-NEXT: vsm.v v16, (a2)
; ZVFHMIN-NEXT: ret
@@ -255,7 +255,7 @@ define void @fcmp_ole_vv_v4f64(ptr %x, ptr %y, ptr %z) {
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vle64.v v10, (a1)
; CHECK-NEXT: vmfle.vv v0, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -280,7 +280,7 @@ define void @fcmp_ole_vv_v4f64_nonans(ptr %x, ptr %y, ptr %z) {
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vle64.v v10, (a1)
; CHECK-NEXT: vmfle.vv v0, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -2472,7 +2472,7 @@ define void @fcmp_ord_vv_v4f16(ptr %x, ptr %y, ptr %z) {
; ZVFH-NEXT: vmfeq.vv v8, v8, v8
; ZVFH-NEXT: vmfeq.vv v9, v9, v9
; ZVFH-NEXT: vmand.mm v0, v9, v8
-; ZVFH-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; ZVFH-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; ZVFH-NEXT: vmv.v.i v8, 0
; ZVFH-NEXT: vmerge.vim v8, v8, 1, v0
; ZVFH-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -2491,11 +2491,11 @@ define void @fcmp_ord_vv_v4f16(ptr %x, ptr %y, ptr %z) {
; ZVFHMIN-NEXT: vle16.v v9, (a0)
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v9, v10, v10
; ZVFHMIN-NEXT: vmfeq.vv v8, v8, v8
; ZVFHMIN-NEXT: vmand.mm v0, v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; ZVFHMIN-NEXT: vmv.v.i v8, 0
; ZVFHMIN-NEXT: vmerge.vim v8, v8, 1, v0
; ZVFHMIN-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -2522,7 +2522,7 @@ define void @fcmp_uno_vv_v4f16(ptr %x, ptr %y, ptr %z) {
; ZVFH-NEXT: vmfne.vv v8, v8, v8
; ZVFH-NEXT: vmfne.vv v9, v9, v9
; ZVFH-NEXT: vmor.mm v0, v9, v8
-; ZVFH-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; ZVFH-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; ZVFH-NEXT: vmv.v.i v8, 0
; ZVFH-NEXT: vmerge.vim v8, v8, 1, v0
; ZVFH-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -2541,11 +2541,11 @@ define void @fcmp_uno_vv_v4f16(ptr %x, ptr %y, ptr %z) {
; ZVFHMIN-NEXT: vle16.v v9, (a0)
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vmfne.vv v9, v10, v10
; ZVFHMIN-NEXT: vmfne.vv v8, v8, v8
; ZVFHMIN-NEXT: vmor.mm v0, v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; ZVFHMIN-NEXT: vmv.v.i v8, 0
; ZVFHMIN-NEXT: vmerge.vim v8, v8, 1, v0
; ZVFHMIN-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -2580,7 +2580,7 @@ define void @fcmp_oeq_vf_v8f16(ptr %x, half %y, ptr %z) {
; ZVFHMIN-NEXT: vmv.v.x v12, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v12, v8, v10
; ZVFHMIN-NEXT: vsm.v v12, (a1)
; ZVFHMIN-NEXT: ret
@@ -2609,7 +2609,7 @@ define void @fcmp_oeq_vf_v8f16_nonans(ptr %x, half %y, ptr %z) {
; ZVFHMIN-NEXT: vmv.v.x v12, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v12, v8, v10
; ZVFHMIN-NEXT: vsm.v v12, (a1)
; ZVFHMIN-NEXT: ret
@@ -2627,7 +2627,7 @@ define void @fcmp_une_vf_v4f32(ptr %x, float %y, ptr %z) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -2652,7 +2652,7 @@ define void @fcmp_une_vf_v4f32_nonans(ptr %x, float %y, ptr %z) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -2677,7 +2677,7 @@ define void @fcmp_ogt_vf_v2f64(ptr %x, double %y, ptr %z) {
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -2702,7 +2702,7 @@ define void @fcmp_ogt_vf_v2f64_nonans(ptr %x, double %y, ptr %z) {
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -2738,7 +2738,7 @@ define void @fcmp_olt_vf_v16f16(ptr %x, half %y, ptr %z) {
; ZVFHMIN-NEXT: vmv.v.x v16, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v16
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vmflt.vv v16, v8, v12
; ZVFHMIN-NEXT: vsm.v v16, (a1)
; ZVFHMIN-NEXT: ret
@@ -2767,7 +2767,7 @@ define void @fcmp_olt_vf_v16f16_nonans(ptr %x, half %y, ptr %z) {
; ZVFHMIN-NEXT: vmv.v.x v16, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v16
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vmflt.vv v16, v8, v12
; ZVFHMIN-NEXT: vsm.v v16, (a1)
; ZVFHMIN-NEXT: ret
@@ -2817,7 +2817,7 @@ define void @fcmp_ole_vf_v4f64(ptr %x, double %y, ptr %z) {
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -2842,7 +2842,7 @@ define void @fcmp_ole_vf_v4f64_nonans(ptr %x, double %y, ptr %z) {
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -4453,7 +4453,7 @@ define void @fcmp_ord_vf_v4f16(ptr %x, half %y, ptr %z) {
; ZVFH-NEXT: vmfeq.vf v9, v9, fa0
; ZVFH-NEXT: vmfeq.vv v8, v8, v8
; ZVFH-NEXT: vmand.mm v0, v8, v9
-; ZVFH-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; ZVFH-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; ZVFH-NEXT: vmv.v.i v8, 0
; ZVFH-NEXT: vmerge.vim v8, v8, 1, v0
; ZVFH-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -4472,14 +4472,14 @@ define void @fcmp_ord_vf_v4f16(ptr %x, half %y, ptr %z) {
; ZVFHMIN-NEXT: fmv.x.h a0, fa0
; ZVFHMIN-NEXT: vmv.v.x v9, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v9, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v8, v10, v10
; ZVFHMIN-NEXT: vmand.mm v0, v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; ZVFHMIN-NEXT: vmv.v.i v8, 0
; ZVFHMIN-NEXT: vmerge.vim v8, v8, 1, v0
; ZVFHMIN-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -4507,7 +4507,7 @@ define void @fcmp_uno_vf_v4f16(ptr %x, half %y, ptr %z) {
; ZVFH-NEXT: vmfne.vf v9, v9, fa0
; ZVFH-NEXT: vmfne.vv v8, v8, v8
; ZVFH-NEXT: vmor.mm v0, v8, v9
-; ZVFH-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; ZVFH-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; ZVFH-NEXT: vmv.v.i v8, 0
; ZVFH-NEXT: vmerge.vim v8, v8, 1, v0
; ZVFH-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -4526,14 +4526,14 @@ define void @fcmp_uno_vf_v4f16(ptr %x, half %y, ptr %z) {
; ZVFHMIN-NEXT: fmv.x.h a0, fa0
; ZVFHMIN-NEXT: vmv.v.x v9, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vmfne.vv v9, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vmfne.vv v8, v10, v10
; ZVFHMIN-NEXT: vmor.mm v0, v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; ZVFHMIN-NEXT: vmv.v.i v8, 0
; ZVFHMIN-NEXT: vmerge.vim v8, v8, 1, v0
; ZVFHMIN-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -4569,7 +4569,7 @@ define void @fcmp_oeq_fv_v8f16(ptr %x, half %y, ptr %z) {
; ZVFHMIN-NEXT: vmv.v.x v12, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v12, v10, v8
; ZVFHMIN-NEXT: vsm.v v12, (a1)
; ZVFHMIN-NEXT: ret
@@ -4598,7 +4598,7 @@ define void @fcmp_oeq_fv_v8f16_nonans(ptr %x, half %y, ptr %z) {
; ZVFHMIN-NEXT: vmv.v.x v12, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v12, v10, v8
; ZVFHMIN-NEXT: vsm.v v12, (a1)
; ZVFHMIN-NEXT: ret
@@ -4616,7 +4616,7 @@ define void @fcmp_une_fv_v4f32(ptr %x, float %y, ptr %z) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -4641,7 +4641,7 @@ define void @fcmp_une_fv_v4f32_nonans(ptr %x, float %y, ptr %z) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -4666,7 +4666,7 @@ define void @fcmp_ogt_fv_v2f64(ptr %x, double %y, ptr %z) {
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -4691,7 +4691,7 @@ define void @fcmp_ogt_fv_v2f64_nonans(ptr %x, double %y, ptr %z) {
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -4727,7 +4727,7 @@ define void @fcmp_olt_fv_v16f16(ptr %x, half %y, ptr %z) {
; ZVFHMIN-NEXT: vmv.v.x v16, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v16
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vmflt.vv v16, v12, v8
; ZVFHMIN-NEXT: vsm.v v16, (a1)
; ZVFHMIN-NEXT: ret
@@ -4756,7 +4756,7 @@ define void @fcmp_olt_fv_v16f16_nonans(ptr %x, half %y, ptr %z) {
; ZVFHMIN-NEXT: vmv.v.x v16, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v16
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vmflt.vv v16, v12, v8
; ZVFHMIN-NEXT: vsm.v v16, (a1)
; ZVFHMIN-NEXT: ret
@@ -4806,7 +4806,7 @@ define void @fcmp_ole_fv_v4f64(ptr %x, double %y, ptr %z) {
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -4831,7 +4831,7 @@ define void @fcmp_ole_fv_v4f64_nonans(ptr %x, double %y, ptr %z) {
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -6442,7 +6442,7 @@ define void @fcmp_ord_fv_v4f16(ptr %x, half %y, ptr %z) {
; ZVFH-NEXT: vmfeq.vf v9, v9, fa0
; ZVFH-NEXT: vmfeq.vv v8, v8, v8
; ZVFH-NEXT: vmand.mm v0, v9, v8
-; ZVFH-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; ZVFH-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; ZVFH-NEXT: vmv.v.i v8, 0
; ZVFH-NEXT: vmerge.vim v8, v8, 1, v0
; ZVFH-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -6461,14 +6461,14 @@ define void @fcmp_ord_fv_v4f16(ptr %x, half %y, ptr %z) {
; ZVFHMIN-NEXT: fmv.x.h a0, fa0
; ZVFHMIN-NEXT: vmv.v.x v9, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v9, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v8, v10, v10
; ZVFHMIN-NEXT: vmand.mm v0, v9, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; ZVFHMIN-NEXT: vmv.v.i v8, 0
; ZVFHMIN-NEXT: vmerge.vim v8, v8, 1, v0
; ZVFHMIN-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -6496,7 +6496,7 @@ define void @fcmp_uno_fv_v4f16(ptr %x, half %y, ptr %z) {
; ZVFH-NEXT: vmfne.vf v9, v9, fa0
; ZVFH-NEXT: vmfne.vv v8, v8, v8
; ZVFH-NEXT: vmor.mm v0, v9, v8
-; ZVFH-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; ZVFH-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; ZVFH-NEXT: vmv.v.i v8, 0
; ZVFH-NEXT: vmerge.vim v8, v8, 1, v0
; ZVFH-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -6515,14 +6515,14 @@ define void @fcmp_uno_fv_v4f16(ptr %x, half %y, ptr %z) {
; ZVFHMIN-NEXT: fmv.x.h a0, fa0
; ZVFHMIN-NEXT: vmv.v.x v9, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vmfne.vv v9, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vmfne.vv v8, v10, v10
; ZVFHMIN-NEXT: vmor.mm v0, v9, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; ZVFHMIN-NEXT: vmv.v.i v8, 0
; ZVFHMIN-NEXT: vmerge.vim v8, v8, 1, v0
; ZVFHMIN-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
index dd415116c2327..100b7cf0d82e7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
@@ -13,9 +13,9 @@ define void @fadd_v8bf16(ptr %x, ptr %y) {
; CHECK-NEXT: vle16.v v12, (a0)
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfadd.vv v8, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -34,9 +34,9 @@ define void @fadd_v6bf16(ptr %x, ptr %y) {
; CHECK-NEXT: vle16.v v12, (a0)
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vfadd.vv v8, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -64,9 +64,9 @@ define void @fadd_v8f16(ptr %x, ptr %y) {
; ZVFHMIN-NEXT: vle16.v v12, (a0)
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfadd.vv v8, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -94,9 +94,9 @@ define void @fadd_v6f16(ptr %x, ptr %y) {
; ZVFHMIN-NEXT: vle16.v v12, (a0)
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfadd.vv v8, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -147,9 +147,9 @@ define void @fsub_v8bf16(ptr %x, ptr %y) {
; CHECK-NEXT: vle16.v v12, (a0)
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfsub.vv v8, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -168,9 +168,9 @@ define void @fsub_v6bf16(ptr %x, ptr %y) {
; CHECK-NEXT: vle16.v v12, (a0)
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vfsub.vv v8, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -198,9 +198,9 @@ define void @fsub_v8f16(ptr %x, ptr %y) {
; ZVFHMIN-NEXT: vle16.v v12, (a0)
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfsub.vv v8, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -228,9 +228,9 @@ define void @fsub_v6f16(ptr %x, ptr %y) {
; ZVFHMIN-NEXT: vle16.v v12, (a0)
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfsub.vv v8, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -281,9 +281,9 @@ define void @fmul_v8bf16(ptr %x, ptr %y) {
; CHECK-NEXT: vle16.v v12, (a0)
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfmul.vv v8, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -302,9 +302,9 @@ define void @fmul_v6bf16(ptr %x, ptr %y) {
; CHECK-NEXT: vle16.v v12, (a0)
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vfmul.vv v8, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -332,9 +332,9 @@ define void @fmul_v8f16(ptr %x, ptr %y) {
; ZVFHMIN-NEXT: vle16.v v12, (a0)
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmul.vv v8, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -362,9 +362,9 @@ define void @fmul_v6f16(ptr %x, ptr %y) {
; ZVFHMIN-NEXT: vle16.v v12, (a0)
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmul.vv v8, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -415,9 +415,9 @@ define void @fdiv_v8bf16(ptr %x, ptr %y) {
; CHECK-NEXT: vle16.v v12, (a0)
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfdiv.vv v8, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -436,9 +436,9 @@ define void @fdiv_v6bf16(ptr %x, ptr %y) {
; CHECK-NEXT: vle16.v v12, (a0)
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vfdiv.vv v8, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -466,9 +466,9 @@ define void @fdiv_v8f16(ptr %x, ptr %y) {
; ZVFHMIN-NEXT: vle16.v v12, (a0)
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfdiv.vv v8, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -496,9 +496,9 @@ define void @fdiv_v6f16(ptr %x, ptr %y) {
; ZVFHMIN-NEXT: vle16.v v12, (a0)
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfdiv.vv v8, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -1282,7 +1282,7 @@ define void @copysign_neg_ext_v2f64_v2f32(ptr %x, ptr %y) {
; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: vle64.v v9, (a0)
; CHECK-NEXT: vfwcvt.f.f.v v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vfsgnjn.vv v8, v9, v10
; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
@@ -1301,9 +1301,9 @@ define void @sqrt_v8bf16(ptr %x) {
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v10, (a0)
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfsqrt.v v8, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -1319,9 +1319,9 @@ define void @sqrt_v6bf16(ptr %x) {
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v10, (a0)
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vfsqrt.v v8, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -1345,9 +1345,9 @@ define void @sqrt_v8f16(ptr %x) {
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vle16.v v10, (a0)
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfsqrt.v v8, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -1371,9 +1371,9 @@ define void @sqrt_v6f16(ptr %x) {
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vle16.v v10, (a0)
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfsqrt.v v8, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -1421,9 +1421,9 @@ define void @fma_v8bf16(ptr %x, ptr %y, ptr %z) {
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v14
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfmadd.vv v12, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
@@ -1445,9 +1445,9 @@ define void @fma_v6bf16(ptr %x, ptr %y, ptr %z) {
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v14
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vfmadd.vv v12, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
@@ -1479,9 +1479,9 @@ define void @fma_v8f16(ptr %x, ptr %y, ptr %z) {
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v14
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v12, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: vse16.v v8, (a0)
; ZVFHMIN-NEXT: ret
@@ -1513,9 +1513,9 @@ define void @fma_v6f16(ptr %x, ptr %y, ptr %z) {
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v14
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v12, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: vse16.v v8, (a0)
; ZVFHMIN-NEXT: ret
@@ -1575,9 +1575,9 @@ define void @fmsub_v8bf16(ptr %x, ptr %y, ptr %z) {
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v14
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfmadd.vv v12, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
@@ -1602,9 +1602,9 @@ define void @fmsub_v6bf16(ptr %x, ptr %y, ptr %z) {
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v14
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vfmadd.vv v12, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
@@ -1639,9 +1639,9 @@ define void @fmsub_v8f16(ptr %x, ptr %y, ptr %z) {
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v14
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v12, v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: vse16.v v8, (a0)
; ZVFHMIN-NEXT: ret
@@ -1676,9 +1676,9 @@ define void @fmsub_v6f16(ptr %x, ptr %y, ptr %z) {
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v14
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v12, v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: vse16.v v8, (a0)
; ZVFHMIN-NEXT: ret
@@ -1738,9 +1738,9 @@ define void @fadd_v16bf16(ptr %x, ptr %y) {
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v12
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v16
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfadd.vv v8, v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v8
; CHECK-NEXT: vse16.v v12, (a0)
; CHECK-NEXT: ret
@@ -1768,9 +1768,9 @@ define void @fadd_v16f16(ptr %x, ptr %y) {
; ZVFHMIN-NEXT: vle16.v v16, (a0)
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v16
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfadd.vv v8, v12, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v8
; ZVFHMIN-NEXT: vse16.v v12, (a0)
; ZVFHMIN-NEXT: ret
@@ -1821,9 +1821,9 @@ define void @fsub_v16bf16(ptr %x, ptr %y) {
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v12
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v16
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfsub.vv v8, v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v8
; CHECK-NEXT: vse16.v v12, (a0)
; CHECK-NEXT: ret
@@ -1851,9 +1851,9 @@ define void @fsub_v16f16(ptr %x, ptr %y) {
; ZVFHMIN-NEXT: vle16.v v16, (a0)
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v16
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfsub.vv v8, v12, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v8
; ZVFHMIN-NEXT: vse16.v v12, (a0)
; ZVFHMIN-NEXT: ret
@@ -1904,9 +1904,9 @@ define void @fmul_v16bf16(ptr %x, ptr %y) {
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v12
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v16
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfmul.vv v8, v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v8
; CHECK-NEXT: vse16.v v12, (a0)
; CHECK-NEXT: ret
@@ -1934,9 +1934,9 @@ define void @fmul_v16f16(ptr %x, ptr %y) {
; ZVFHMIN-NEXT: vle16.v v16, (a0)
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v16
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfmul.vv v8, v12, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v8
; ZVFHMIN-NEXT: vse16.v v12, (a0)
; ZVFHMIN-NEXT: ret
@@ -1987,9 +1987,9 @@ define void @fdiv_v16bf16(ptr %x, ptr %y) {
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v12
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v16
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfdiv.vv v8, v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v8
; CHECK-NEXT: vse16.v v12, (a0)
; CHECK-NEXT: ret
@@ -2017,9 +2017,9 @@ define void @fdiv_v16f16(ptr %x, ptr %y) {
; ZVFHMIN-NEXT: vle16.v v16, (a0)
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v16
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfdiv.vv v8, v12, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v8
; ZVFHMIN-NEXT: vse16.v v12, (a0)
; ZVFHMIN-NEXT: ret
@@ -2138,9 +2138,9 @@ define void @fma_v16bf16(ptr %x, ptr %y, ptr %z) {
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v12
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v16
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v20
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfmadd.vv v16, v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
@@ -2172,9 +2172,9 @@ define void @fma_v16f16(ptr %x, ptr %y, ptr %z) {
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v16
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v20
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v16, v12, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: vse16.v v8, (a0)
; ZVFHMIN-NEXT: ret
@@ -2231,9 +2231,9 @@ define void @fadd_vf_v8bf16(ptr %x, bfloat %y) {
; CHECK-NEXT: vmv.v.x v12, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfadd.vv v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -2254,9 +2254,9 @@ define void @fadd_vf_v6bf16(ptr %x, bfloat %y) {
; CHECK-NEXT: vmv.v.x v12, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vfadd.vv v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -2285,9 +2285,9 @@ define void @fadd_vf_v8f16(ptr %x, half %y) {
; ZVFHMIN-NEXT: vmv.v.x v12, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfadd.vv v8, v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -2316,9 +2316,9 @@ define void @fadd_vf_v6f16(ptr %x, half %y) {
; ZVFHMIN-NEXT: vmv.v.x v12, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfadd.vv v8, v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -2371,9 +2371,9 @@ define void @fadd_fv_v8bf16(ptr %x, bfloat %y) {
; CHECK-NEXT: vmv.v.x v12, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfadd.vv v8, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -2394,9 +2394,9 @@ define void @fadd_fv_v6bf16(ptr %x, bfloat %y) {
; CHECK-NEXT: vmv.v.x v12, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vfadd.vv v8, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -2425,9 +2425,9 @@ define void @fadd_fv_v8f16(ptr %x, half %y) {
; ZVFHMIN-NEXT: vmv.v.x v12, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfadd.vv v8, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -2456,9 +2456,9 @@ define void @fadd_fv_v6f16(ptr %x, half %y) {
; ZVFHMIN-NEXT: vmv.v.x v12, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfadd.vv v8, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -2511,9 +2511,9 @@ define void @fsub_vf_v8bf16(ptr %x, bfloat %y) {
; CHECK-NEXT: vmv.v.x v12, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfsub.vv v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -2534,9 +2534,9 @@ define void @fsub_vf_v6bf16(ptr %x, bfloat %y) {
; CHECK-NEXT: vmv.v.x v12, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vfsub.vv v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -2565,9 +2565,9 @@ define void @fsub_vf_v8f16(ptr %x, half %y) {
; ZVFHMIN-NEXT: vmv.v.x v12, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfsub.vv v8, v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -2596,9 +2596,9 @@ define void @fsub_vf_v6f16(ptr %x, half %y) {
; ZVFHMIN-NEXT: vmv.v.x v12, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfsub.vv v8, v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -2651,9 +2651,9 @@ define void @fsub_fv_v8bf16(ptr %x, bfloat %y) {
; CHECK-NEXT: vmv.v.x v12, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfsub.vv v8, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -2674,9 +2674,9 @@ define void @fsub_fv_v6bf16(ptr %x, bfloat %y) {
; CHECK-NEXT: vmv.v.x v12, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vfsub.vv v8, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -2705,9 +2705,9 @@ define void @fsub_fv_v8f16(ptr %x, half %y) {
; ZVFHMIN-NEXT: vmv.v.x v12, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfsub.vv v8, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -2736,9 +2736,9 @@ define void @fsub_fv_v6f16(ptr %x, half %y) {
; ZVFHMIN-NEXT: vmv.v.x v12, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfsub.vv v8, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -2791,9 +2791,9 @@ define void @fmul_vf_v8bf16(ptr %x, bfloat %y) {
; CHECK-NEXT: vmv.v.x v12, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfmul.vv v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -2814,9 +2814,9 @@ define void @fmul_vf_v6bf16(ptr %x, bfloat %y) {
; CHECK-NEXT: vmv.v.x v12, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vfmul.vv v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -2845,9 +2845,9 @@ define void @fmul_vf_v8f16(ptr %x, half %y) {
; ZVFHMIN-NEXT: vmv.v.x v12, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmul.vv v8, v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -2876,9 +2876,9 @@ define void @fmul_vf_v6f16(ptr %x, half %y) {
; ZVFHMIN-NEXT: vmv.v.x v12, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmul.vv v8, v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -2931,9 +2931,9 @@ define void @fmul_fv_v8bf16(ptr %x, bfloat %y) {
; CHECK-NEXT: vmv.v.x v12, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfmul.vv v8, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -2954,9 +2954,9 @@ define void @fmul_fv_v6bf16(ptr %x, bfloat %y) {
; CHECK-NEXT: vmv.v.x v12, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vfmul.vv v8, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -2985,9 +2985,9 @@ define void @fmul_fv_v8f16(ptr %x, half %y) {
; ZVFHMIN-NEXT: vmv.v.x v12, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmul.vv v8, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -3016,9 +3016,9 @@ define void @fmul_fv_v6f16(ptr %x, half %y) {
; ZVFHMIN-NEXT: vmv.v.x v12, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmul.vv v8, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -3071,9 +3071,9 @@ define void @fdiv_vf_v8bf16(ptr %x, bfloat %y) {
; CHECK-NEXT: vmv.v.x v12, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfdiv.vv v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -3094,9 +3094,9 @@ define void @fdiv_vf_v6bf16(ptr %x, bfloat %y) {
; CHECK-NEXT: vmv.v.x v12, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vfdiv.vv v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -3125,9 +3125,9 @@ define void @fdiv_vf_v8f16(ptr %x, half %y) {
; ZVFHMIN-NEXT: vmv.v.x v12, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfdiv.vv v8, v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -3156,9 +3156,9 @@ define void @fdiv_vf_v6f16(ptr %x, half %y) {
; ZVFHMIN-NEXT: vmv.v.x v12, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfdiv.vv v8, v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -3211,9 +3211,9 @@ define void @fdiv_fv_v8bf16(ptr %x, bfloat %y) {
; CHECK-NEXT: vmv.v.x v12, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfdiv.vv v8, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -3234,9 +3234,9 @@ define void @fdiv_fv_v6bf16(ptr %x, bfloat %y) {
; CHECK-NEXT: vmv.v.x v12, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vfdiv.vv v8, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -3265,9 +3265,9 @@ define void @fdiv_fv_v8f16(ptr %x, half %y) {
; ZVFHMIN-NEXT: vmv.v.x v12, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfdiv.vv v8, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -3296,9 +3296,9 @@ define void @fdiv_fv_v6f16(ptr %x, half %y) {
; ZVFHMIN-NEXT: vmv.v.x v12, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfdiv.vv v8, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -3353,9 +3353,9 @@ define void @fma_vf_v8bf16(ptr %x, ptr %y, bfloat %z) {
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v14
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfmadd.vv v12, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
@@ -3379,9 +3379,9 @@ define void @fma_vf_v6bf16(ptr %x, ptr %y, bfloat %z) {
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v14
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vfmadd.vv v12, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
@@ -3414,9 +3414,9 @@ define void @fma_vf_v8f16(ptr %x, ptr %y, half %z) {
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v14
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v12, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: vse16.v v8, (a0)
; ZVFHMIN-NEXT: ret
@@ -3449,9 +3449,9 @@ define void @fma_vf_v6f16(ptr %x, ptr %y, half %z) {
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v14
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v12, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: vse16.v v8, (a0)
; ZVFHMIN-NEXT: ret
@@ -3511,9 +3511,9 @@ define void @fma_fv_v8bf16(ptr %x, ptr %y, bfloat %z) {
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v14
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfmadd.vv v12, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
@@ -3537,9 +3537,9 @@ define void @fma_fv_v6bf16(ptr %x, ptr %y, bfloat %z) {
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v14
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vfmadd.vv v12, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
@@ -3572,9 +3572,9 @@ define void @fma_fv_v8f16(ptr %x, ptr %y, half %z) {
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v14
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v12, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: vse16.v v8, (a0)
; ZVFHMIN-NEXT: ret
@@ -3607,9 +3607,9 @@ define void @fma_fv_v6f16(ptr %x, ptr %y, half %z) {
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v14
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v12, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: vse16.v v8, (a0)
; ZVFHMIN-NEXT: ret
@@ -3671,9 +3671,9 @@ define void @fmsub_vf_v8bf16(ptr %x, ptr %y, bfloat %z) {
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v14
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfmadd.vv v12, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
@@ -3700,9 +3700,9 @@ define void @fmsub_vf_v6bf16(ptr %x, ptr %y, bfloat %z) {
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v14
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vfmadd.vv v12, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
@@ -3738,9 +3738,9 @@ define void @fmsub_vf_v8f16(ptr %x, ptr %y, half %z) {
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v14
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v12, v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: vse16.v v8, (a0)
; ZVFHMIN-NEXT: ret
@@ -3776,9 +3776,9 @@ define void @fmsub_vf_v6f16(ptr %x, ptr %y, half %z) {
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v14
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v12, v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: vse16.v v8, (a0)
; ZVFHMIN-NEXT: ret
@@ -3878,14 +3878,14 @@ define void @trunc_v8bf16(ptr %x) {
; CHECK-NEXT: lui a1, 307200
; CHECK-NEXT: fmv.w.x fa5, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -3903,14 +3903,14 @@ define void @trunc_v6bf16(ptr %x) {
; CHECK-NEXT: lui a1, 307200
; CHECK-NEXT: fmv.w.x fa5, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -3932,7 +3932,7 @@ define void @trunc_v8f16(ptr %x) {
; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; ZVFH-NEXT: vse16.v v8, (a0)
; ZVFH-NEXT: ret
@@ -3944,14 +3944,14 @@ define void @trunc_v8f16(ptr %x) {
; ZVFHMIN-NEXT: lui a1, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v10, v8
; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -3973,7 +3973,7 @@ define void @trunc_v6f16(ptr %x) {
; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, mu
; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; ZVFH-NEXT: vse16.v v8, (a0)
; ZVFH-NEXT: ret
@@ -3985,14 +3985,14 @@ define void @trunc_v6f16(ptr %x) {
; ZVFHMIN-NEXT: lui a1, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v10, v8
; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -4013,7 +4013,7 @@ define void @trunc_v4f32(ptr %x) {
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
@@ -4034,7 +4034,7 @@ define void @trunc_v2f64(ptr %x) {
; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32ZVFH-NEXT: vse64.v v8, (a0)
; RV32ZVFH-NEXT: ret
@@ -4050,7 +4050,7 @@ define void @trunc_v2f64(ptr %x) {
; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64ZVFH-NEXT: vse64.v v8, (a0)
; RV64ZVFH-NEXT: ret
@@ -4065,7 +4065,7 @@ define void @trunc_v2f64(ptr %x) {
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32ZVFHMIN-NEXT: vse64.v v8, (a0)
; RV32ZVFHMIN-NEXT: ret
@@ -4081,7 +4081,7 @@ define void @trunc_v2f64(ptr %x) {
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64ZVFHMIN-NEXT: vse64.v v8, (a0)
; RV64ZVFHMIN-NEXT: ret
@@ -4099,16 +4099,16 @@ define void @ceil_v8bf16(ptr %x) {
; CHECK-NEXT: lui a1, 307200
; CHECK-NEXT: fmv.w.x fa5, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a1, 3
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -4126,16 +4126,16 @@ define void @ceil_v6bf16(ptr %x) {
; CHECK-NEXT: lui a1, 307200
; CHECK-NEXT: fmv.w.x fa5, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a1, 3
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -4159,7 +4159,7 @@ define void @ceil_v8f16(ptr %x) {
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a1
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; ZVFH-NEXT: vse16.v v8, (a0)
; ZVFH-NEXT: ret
@@ -4171,16 +4171,16 @@ define void @ceil_v8f16(ptr %x) {
; ZVFHMIN-NEXT: lui a1, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v10, v8
; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; ZVFHMIN-NEXT: fsrmi a1, 3
; ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: fsrm a1
; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -4204,7 +4204,7 @@ define void @ceil_v6f16(ptr %x) {
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a1
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, mu
; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; ZVFH-NEXT: vse16.v v8, (a0)
; ZVFH-NEXT: ret
@@ -4216,16 +4216,16 @@ define void @ceil_v6f16(ptr %x) {
; ZVFHMIN-NEXT: lui a1, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v10, v8
; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; ZVFHMIN-NEXT: fsrmi a1, 3
; ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: fsrm a1
; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -4248,7 +4248,7 @@ define void @ceil_v4f32(ptr %x) {
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
@@ -4271,7 +4271,7 @@ define void @ceil_v2f64(ptr %x) {
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a1
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32ZVFH-NEXT: vse64.v v8, (a0)
; RV32ZVFH-NEXT: ret
@@ -4289,7 +4289,7 @@ define void @ceil_v2f64(ptr %x) {
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a1
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64ZVFH-NEXT: vse64.v v8, (a0)
; RV64ZVFH-NEXT: ret
@@ -4306,7 +4306,7 @@ define void @ceil_v2f64(ptr %x) {
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a1
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32ZVFHMIN-NEXT: vse64.v v8, (a0)
; RV32ZVFHMIN-NEXT: ret
@@ -4324,7 +4324,7 @@ define void @ceil_v2f64(ptr %x) {
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a1
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64ZVFHMIN-NEXT: vse64.v v8, (a0)
; RV64ZVFHMIN-NEXT: ret
@@ -4342,16 +4342,16 @@ define void @floor_v8bf16(ptr %x) {
; CHECK-NEXT: lui a1, 307200
; CHECK-NEXT: fmv.w.x fa5, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a1, 2
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -4369,16 +4369,16 @@ define void @floor_v6bf16(ptr %x) {
; CHECK-NEXT: lui a1, 307200
; CHECK-NEXT: fmv.w.x fa5, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a1, 2
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -4402,7 +4402,7 @@ define void @floor_v8f16(ptr %x) {
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a1
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; ZVFH-NEXT: vse16.v v8, (a0)
; ZVFH-NEXT: ret
@@ -4414,16 +4414,16 @@ define void @floor_v8f16(ptr %x) {
; ZVFHMIN-NEXT: lui a1, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v10, v8
; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; ZVFHMIN-NEXT: fsrmi a1, 2
; ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: fsrm a1
; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -4447,7 +4447,7 @@ define void @floor_v6f16(ptr %x) {
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a1
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, mu
; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; ZVFH-NEXT: vse16.v v8, (a0)
; ZVFH-NEXT: ret
@@ -4459,16 +4459,16 @@ define void @floor_v6f16(ptr %x) {
; ZVFHMIN-NEXT: lui a1, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v10, v8
; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; ZVFHMIN-NEXT: fsrmi a1, 2
; ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: fsrm a1
; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -4491,7 +4491,7 @@ define void @floor_v4f32(ptr %x) {
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
@@ -4514,7 +4514,7 @@ define void @floor_v2f64(ptr %x) {
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a1
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32ZVFH-NEXT: vse64.v v8, (a0)
; RV32ZVFH-NEXT: ret
@@ -4532,7 +4532,7 @@ define void @floor_v2f64(ptr %x) {
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a1
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64ZVFH-NEXT: vse64.v v8, (a0)
; RV64ZVFH-NEXT: ret
@@ -4549,7 +4549,7 @@ define void @floor_v2f64(ptr %x) {
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a1
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32ZVFHMIN-NEXT: vse64.v v8, (a0)
; RV32ZVFHMIN-NEXT: ret
@@ -4567,7 +4567,7 @@ define void @floor_v2f64(ptr %x) {
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a1
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64ZVFHMIN-NEXT: vse64.v v8, (a0)
; RV64ZVFHMIN-NEXT: ret
@@ -4585,16 +4585,16 @@ define void @round_v8bf16(ptr %x) {
; CHECK-NEXT: lui a1, 307200
; CHECK-NEXT: fmv.w.x fa5, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a1, 4
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -4612,16 +4612,16 @@ define void @round_v6bf16(ptr %x) {
; CHECK-NEXT: lui a1, 307200
; CHECK-NEXT: fmv.w.x fa5, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a1, 4
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -4645,7 +4645,7 @@ define void @round_v8f16(ptr %x) {
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a1
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; ZVFH-NEXT: vse16.v v8, (a0)
; ZVFH-NEXT: ret
@@ -4657,16 +4657,16 @@ define void @round_v8f16(ptr %x) {
; ZVFHMIN-NEXT: lui a1, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v10, v8
; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; ZVFHMIN-NEXT: fsrmi a1, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: fsrm a1
; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -4690,7 +4690,7 @@ define void @round_v6f16(ptr %x) {
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a1
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, mu
; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; ZVFH-NEXT: vse16.v v8, (a0)
; ZVFH-NEXT: ret
@@ -4702,16 +4702,16 @@ define void @round_v6f16(ptr %x) {
; ZVFHMIN-NEXT: lui a1, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v10, v8
; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; ZVFHMIN-NEXT: fsrmi a1, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: fsrm a1
; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -4734,7 +4734,7 @@ define void @round_v4f32(ptr %x) {
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
@@ -4757,7 +4757,7 @@ define void @round_v2f64(ptr %x) {
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a1
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32ZVFH-NEXT: vse64.v v8, (a0)
; RV32ZVFH-NEXT: ret
@@ -4775,7 +4775,7 @@ define void @round_v2f64(ptr %x) {
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a1
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64ZVFH-NEXT: vse64.v v8, (a0)
; RV64ZVFH-NEXT: ret
@@ -4792,7 +4792,7 @@ define void @round_v2f64(ptr %x) {
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a1
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32ZVFHMIN-NEXT: vse64.v v8, (a0)
; RV32ZVFHMIN-NEXT: ret
@@ -4810,7 +4810,7 @@ define void @round_v2f64(ptr %x) {
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a1
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64ZVFHMIN-NEXT: vse64.v v8, (a0)
; RV64ZVFHMIN-NEXT: ret
@@ -4828,14 +4828,14 @@ define void @rint_v8bf16(ptr %x) {
; CHECK-NEXT: lui a1, 307200
; CHECK-NEXT: fmv.w.x fa5, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -4857,7 +4857,7 @@ define void @rint_v8f16(ptr %x) {
; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; ZVFH-NEXT: vse16.v v8, (a0)
; ZVFH-NEXT: ret
@@ -4869,14 +4869,14 @@ define void @rint_v8f16(ptr %x) {
; ZVFHMIN-NEXT: lui a1, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v10, v8
; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -4897,7 +4897,7 @@ define void @rint_v4f32(ptr %x) {
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
@@ -4918,7 +4918,7 @@ define void @rint_v2f64(ptr %x) {
; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32ZVFH-NEXT: vse64.v v8, (a0)
; RV32ZVFH-NEXT: ret
@@ -4934,7 +4934,7 @@ define void @rint_v2f64(ptr %x) {
; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64ZVFH-NEXT: vse64.v v8, (a0)
; RV64ZVFH-NEXT: ret
@@ -4949,7 +4949,7 @@ define void @rint_v2f64(ptr %x) {
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32ZVFHMIN-NEXT: vse64.v v8, (a0)
; RV32ZVFHMIN-NEXT: ret
@@ -4965,7 +4965,7 @@ define void @rint_v2f64(ptr %x) {
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64ZVFHMIN-NEXT: vse64.v v8, (a0)
; RV64ZVFHMIN-NEXT: ret
@@ -4983,16 +4983,16 @@ define void @nearbyint_v8bf16(ptr %x) {
; CHECK-NEXT: lui a1, 307200
; CHECK-NEXT: fmv.w.x fa5, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: frflags a1
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
; CHECK-NEXT: fsflags a1
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -5016,7 +5016,7 @@ define void @nearbyint_v8f16(ptr %x) {
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
; ZVFH-NEXT: fsflags a1
-; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; ZVFH-NEXT: vse16.v v8, (a0)
; ZVFH-NEXT: ret
@@ -5028,16 +5028,16 @@ define void @nearbyint_v8f16(ptr %x) {
; ZVFHMIN-NEXT: lui a1, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v10, v8
; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; ZVFHMIN-NEXT: frflags a1
; ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
; ZVFHMIN-NEXT: fsflags a1
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -5060,7 +5060,7 @@ define void @nearbyint_v4f32(ptr %x) {
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
; CHECK-NEXT: fsflags a1
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
@@ -5083,7 +5083,7 @@ define void @nearbyint_v2f64(ptr %x) {
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
; RV32ZVFH-NEXT: fsflags a1
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32ZVFH-NEXT: vse64.v v8, (a0)
; RV32ZVFH-NEXT: ret
@@ -5101,7 +5101,7 @@ define void @nearbyint_v2f64(ptr %x) {
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
; RV64ZVFH-NEXT: fsflags a1
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64ZVFH-NEXT: vse64.v v8, (a0)
; RV64ZVFH-NEXT: ret
@@ -5118,7 +5118,7 @@ define void @nearbyint_v2f64(ptr %x) {
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
; RV32ZVFHMIN-NEXT: fsflags a1
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32ZVFHMIN-NEXT: vse64.v v8, (a0)
; RV32ZVFHMIN-NEXT: ret
@@ -5136,7 +5136,7 @@ define void @nearbyint_v2f64(ptr %x) {
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
; RV64ZVFHMIN-NEXT: fsflags a1
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64ZVFHMIN-NEXT: vse64.v v8, (a0)
; RV64ZVFHMIN-NEXT: ret
@@ -5155,15 +5155,15 @@ define void @fmuladd_v8bf16(ptr %x, ptr %y, ptr %z) {
; CHECK-NEXT: vle16.v v13, (a2)
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfmul.vv v8, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v13
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfadd.vv v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -5184,15 +5184,15 @@ define void @fmuladd_v6bf16(ptr %x, ptr %y, ptr %z) {
; CHECK-NEXT: vle16.v v13, (a2)
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vfmul.vv v8, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v13
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vfadd.vv v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -5223,15 +5223,15 @@ define void @fmuladd_v8f16(ptr %x, ptr %y, ptr %z) {
; ZVFHMIN-NEXT: vle16.v v13, (a2)
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmul.vv v8, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v13
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfadd.vv v8, v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -5262,15 +5262,15 @@ define void @fmuladd_v6f16(ptr %x, ptr %y, ptr %z) {
; ZVFHMIN-NEXT: vle16.v v13, (a2)
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmul.vv v8, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v13
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfadd.vv v8, v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -5327,15 +5327,15 @@ define void @fmsub_fmuladd_v8bf16(ptr %x, ptr %y, ptr %z) {
; CHECK-NEXT: vle16.v v13, (a2)
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfmul.vv v8, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v13
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfsub.vv v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -5357,15 +5357,15 @@ define void @fmsub_fmuladd_v6bf16(ptr %x, ptr %y, ptr %z) {
; CHECK-NEXT: vle16.v v13, (a2)
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vfmul.vv v8, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v13
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vfsub.vv v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret
@@ -5397,15 +5397,15 @@ define void @fmsub_fmuladd_v8f16(ptr %x, ptr %y, ptr %z) {
; ZVFHMIN-NEXT: vle16.v v13, (a2)
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmul.vv v8, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v13
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfsub.vv v8, v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
@@ -5437,15 +5437,15 @@ define void @fmsub_fmuladd_v6f16(ptr %x, ptr %y, ptr %z) {
; ZVFHMIN-NEXT: vle16.v v13, (a2)
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmul.vv v8, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v13
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfsub.vv v8, v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vse16.v v10, (a0)
; ZVFHMIN-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
index 1f9a8bf8133c8..80be8f211f7e0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
@@ -79,7 +79,7 @@ define void @fp2si_v2f32_v2i64(ptr %x, ptr %y) {
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vmerge.vim v8, v9, 0, v0
; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret
@@ -97,7 +97,7 @@ define void @fp2ui_v2f32_v2i64(ptr %x, ptr %y) {
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vmerge.vim v8, v9, 0, v0
; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret
@@ -116,7 +116,7 @@ define void @fp2si_v8f32_v8i64(ptr %x, ptr %y) {
; CHECK-NEXT: vle32.v v12, (a0)
; CHECK-NEXT: vmfne.vv v0, v12, v12
; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v12
-; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret
@@ -135,7 +135,7 @@ define void @fp2ui_v8f32_v8i64(ptr %x, ptr %y) {
; CHECK-NEXT: vle32.v v12, (a0)
; CHECK-NEXT: vmfne.vv v0, v12, v12
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v12
-; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret
@@ -153,9 +153,9 @@ define void @fp2si_v2f16_v2i64(ptr %x, ptr %y) {
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret
@@ -173,9 +173,9 @@ define void @fp2ui_v2f16_v2i64(ptr %x, ptr %y) {
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret
@@ -192,11 +192,11 @@ define void @fp2si_v2f64_v2i8(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfne.vv v0, v8, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vnclip.wi v8, v9, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vnclip.wi v8, v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
; CHECK-NEXT: vse8.v v8, (a1)
@@ -214,11 +214,11 @@ define void @fp2ui_v2f64_v2i8(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfne.vv v0, v8, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v9, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
; CHECK-NEXT: vse8.v v8, (a1)
@@ -237,11 +237,11 @@ define void @fp2si_v8f64_v8i8(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfne.vv v0, v8, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vnclip.wi v8, v12, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vnclip.wi v8, v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
; CHECK-NEXT: vse8.v v8, (a1)
@@ -260,11 +260,11 @@ define void @fp2ui_v8f64_v8i8(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfne.vv v0, v8, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v12, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
; CHECK-NEXT: vse8.v v8, (a1)
@@ -282,7 +282,7 @@ define void @fp2si_v2f64_v2i32(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfne.vv v0, v8, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-NEXT: vmerge.vim v8, v9, 0, v0
; CHECK-NEXT: vse32.v v8, (a1)
@@ -300,7 +300,7 @@ define void @fp2ui_v2f64_v2i32(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfne.vv v0, v8, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
; CHECK-NEXT: vmerge.vim v8, v9, 0, v0
; CHECK-NEXT: vse32.v v8, (a1)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
index 9be93d5209121..63d1a043b2537 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
@@ -430,7 +430,7 @@ define void @fp2si_v2bf16_v2i64(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v9
; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret
@@ -446,7 +446,7 @@ define void @fp2ui_v2bf16_v2i64(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v9
; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret
@@ -488,7 +488,7 @@ define void @fp2si_v2f16_v2i64(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfwcvt.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v9
; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret
@@ -504,7 +504,7 @@ define void @fp2ui_v2f16_v2i64(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfwcvt.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v9
; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret
@@ -562,9 +562,9 @@ define void @fp2si_v2f64_v2i8(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v9, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
@@ -580,9 +580,9 @@ define void @fp2ui_v2f64_v2i8(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v9, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
@@ -622,9 +622,9 @@ define void @fp2si_v8f64_v8i8(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
@@ -640,9 +640,9 @@ define void @fp2ui_v8f64_v8i8(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll
index c0b67dd603ebb..59f651613e7b9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll
@@ -18,11 +18,11 @@ define <1 x half> @round_v1f16(<1 x half> %x) strictfp {
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 4
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <1 x half> @llvm.experimental.constrained.round.v1f16(<1 x half> %x, metadata !"fpexcept.strict")
@@ -42,11 +42,11 @@ define <2 x half> @round_v2f16(<2 x half> %x) strictfp {
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 4
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <2 x half> @llvm.experimental.constrained.round.v2f16(<2 x half> %x, metadata !"fpexcept.strict")
@@ -66,11 +66,11 @@ define <4 x half> @round_v4f16(<4 x half> %x) strictfp {
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 4
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <4 x half> @llvm.experimental.constrained.round.v4f16(<4 x half> %x, metadata !"fpexcept.strict")
@@ -90,11 +90,11 @@ define <8 x half> @round_v8f16(<8 x half> %x) strictfp {
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 4
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <8 x half> @llvm.experimental.constrained.round.v8f16(<8 x half> %x, metadata !"fpexcept.strict")
@@ -114,11 +114,11 @@ define <16 x half> @round_v16f16(<16 x half> %x) strictfp {
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 4
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
%a = call <16 x half> @llvm.experimental.constrained.round.v16f16(<16 x half> %x, metadata !"fpexcept.strict")
@@ -162,11 +162,11 @@ define <1 x float> @round_v1f32(<1 x float> %x) strictfp {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 4
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <1 x float> @llvm.experimental.constrained.round.v1f32(<1 x float> %x, metadata !"fpexcept.strict")
@@ -185,11 +185,11 @@ define <2 x float> @round_v2f32(<2 x float> %x) strictfp {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 4
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <2 x float> @llvm.experimental.constrained.round.v2f32(<2 x float> %x, metadata !"fpexcept.strict")
@@ -208,11 +208,11 @@ define <4 x float> @round_v4f32(<4 x float> %x) strictfp {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 4
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <4 x float> @llvm.experimental.constrained.round.v4f32(<4 x float> %x, metadata !"fpexcept.strict")
@@ -231,11 +231,11 @@ define <8 x float> @round_v8f32(<8 x float> %x) strictfp {
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 4
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
%a = call <8 x float> @llvm.experimental.constrained.round.v8f32(<8 x float> %x, metadata !"fpexcept.strict")
@@ -254,11 +254,11 @@ define <16 x float> @round_v16f32(<16 x float> %x) strictfp {
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 4
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret
%a = call <16 x float> @llvm.experimental.constrained.round.v16f32(<16 x float> %x, metadata !"fpexcept.strict")
@@ -277,11 +277,11 @@ define <1 x double> @round_v1f64(<1 x double> %x) strictfp {
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
; RV32-NEXT: fsrmi a0, 4
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32-NEXT: ret
;
@@ -296,11 +296,11 @@ define <1 x double> @round_v1f64(<1 x double> %x) strictfp {
; RV64-NEXT: fmv.d.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: fsrmi a0, 4
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64-NEXT: ret
%a = call <1 x double> @llvm.experimental.constrained.round.v1f64(<1 x double> %x, metadata !"fpexcept.strict")
@@ -319,11 +319,11 @@ define <2 x double> @round_v2f64(<2 x double> %x) strictfp {
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
; RV32-NEXT: fsrmi a0, 4
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32-NEXT: ret
;
@@ -338,11 +338,11 @@ define <2 x double> @round_v2f64(<2 x double> %x) strictfp {
; RV64-NEXT: fmv.d.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: fsrmi a0, 4
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64-NEXT: ret
%a = call <2 x double> @llvm.experimental.constrained.round.v2f64(<2 x double> %x, metadata !"fpexcept.strict")
@@ -361,11 +361,11 @@ define <4 x double> @round_v4f64(<4 x double> %x) strictfp {
; RV32-NEXT: vfabs.v v10, v8
; RV32-NEXT: vmflt.vf v0, v10, fa5
; RV32-NEXT: fsrmi a0, 4
-; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; RV32-NEXT: ret
;
@@ -380,11 +380,11 @@ define <4 x double> @round_v4f64(<4 x double> %x) strictfp {
; RV64-NEXT: fmv.d.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v10, fa5
; RV64-NEXT: fsrmi a0, 4
-; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; RV64-NEXT: ret
%a = call <4 x double> @llvm.experimental.constrained.round.v4f64(<4 x double> %x, metadata !"fpexcept.strict")
@@ -403,11 +403,11 @@ define <8 x double> @round_v8f64(<8 x double> %x) strictfp {
; RV32-NEXT: vfabs.v v12, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
; RV32-NEXT: fsrmi a0, 4
-; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; RV32-NEXT: ret
;
@@ -422,11 +422,11 @@ define <8 x double> @round_v8f64(<8 x double> %x) strictfp {
; RV64-NEXT: fmv.d.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: fsrmi a0, 4
-; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; RV64-NEXT: ret
%a = call <8 x double> @llvm.experimental.constrained.round.v8f64(<8 x double> %x, metadata !"fpexcept.strict")
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
index 455dc0b83c03d..69593e42eff75 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
@@ -23,7 +23,7 @@ define <1 x half> @round_v1f16(<1 x half> %x) {
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
+; ZVFH-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; ZVFH-NEXT: ret
;
@@ -32,7 +32,7 @@ define <1 x half> @round_v1f16(<1 x half> %x) {
; ZVFHMIN-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -40,9 +40,9 @@ define <1 x half> @round_v1f16(<1 x half> %x) {
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; ZVFHMIN-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%a = call <1 x half> @llvm.round.v1f16(<1 x half> %x)
@@ -63,7 +63,7 @@ define <2 x half> @round_v2f16(<2 x half> %x) {
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
+; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; ZVFH-NEXT: ret
;
@@ -72,7 +72,7 @@ define <2 x half> @round_v2f16(<2 x half> %x) {
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -80,9 +80,9 @@ define <2 x half> @round_v2f16(<2 x half> %x) {
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%a = call <2 x half> @llvm.round.v2f16(<2 x half> %x)
@@ -103,7 +103,7 @@ define <4 x half> @round_v4f16(<4 x half> %x) {
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
+; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; ZVFH-NEXT: ret
;
@@ -112,7 +112,7 @@ define <4 x half> @round_v4f16(<4 x half> %x) {
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -120,9 +120,9 @@ define <4 x half> @round_v4f16(<4 x half> %x) {
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%a = call <4 x half> @llvm.round.v4f16(<4 x half> %x)
@@ -143,7 +143,7 @@ define <8 x half> @round_v8f16(<8 x half> %x) {
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; ZVFH-NEXT: ret
;
@@ -152,7 +152,7 @@ define <8 x half> @round_v8f16(<8 x half> %x) {
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -160,9 +160,9 @@ define <8 x half> @round_v8f16(<8 x half> %x) {
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v10, v8, v10, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
; ZVFHMIN-NEXT: ret
%a = call <8 x half> @llvm.round.v8f16(<8 x half> %x)
@@ -183,7 +183,7 @@ define <16 x half> @round_v16f16(<16 x half> %x) {
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu
+; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; ZVFH-NEXT: ret
;
@@ -192,7 +192,7 @@ define <16 x half> @round_v16f16(<16 x half> %x) {
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -200,9 +200,9 @@ define <16 x half> @round_v16f16(<16 x half> %x) {
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v12, v8, v12, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: ret
%a = call <16 x half> @llvm.round.v16f16(<16 x half> %x)
@@ -264,7 +264,7 @@ define <1 x float> @round_v1f32(<1 x float> %x) {
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <1 x float> @llvm.round.v1f32(<1 x float> %x)
@@ -284,7 +284,7 @@ define <2 x float> @round_v2f32(<2 x float> %x) {
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <2 x float> @llvm.round.v2f32(<2 x float> %x)
@@ -304,7 +304,7 @@ define <4 x float> @round_v4f32(<4 x float> %x) {
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <4 x float> @llvm.round.v4f32(<4 x float> %x)
@@ -324,7 +324,7 @@ define <8 x float> @round_v8f32(<8 x float> %x) {
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
%a = call <8 x float> @llvm.round.v8f32(<8 x float> %x)
@@ -344,7 +344,7 @@ define <16 x float> @round_v16f32(<16 x float> %x) {
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret
%a = call <16 x float> @llvm.round.v16f32(<16 x float> %x)
@@ -364,7 +364,7 @@ define <1 x double> @round_v1f64(<1 x double> %x) {
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32ZVFH-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32ZVFH-NEXT: ret
;
@@ -380,7 +380,7 @@ define <1 x double> @round_v1f64(<1 x double> %x) {
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64ZVFH-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64ZVFH-NEXT: ret
;
@@ -395,7 +395,7 @@ define <1 x double> @round_v1f64(<1 x double> %x) {
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32ZVFHMIN-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32ZVFHMIN-NEXT: ret
;
@@ -411,7 +411,7 @@ define <1 x double> @round_v1f64(<1 x double> %x) {
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64ZVFHMIN-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64ZVFHMIN-NEXT: ret
%a = call <1 x double> @llvm.round.v1f64(<1 x double> %x)
@@ -431,7 +431,7 @@ define <2 x double> @round_v2f64(<2 x double> %x) {
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32ZVFH-NEXT: ret
;
@@ -447,7 +447,7 @@ define <2 x double> @round_v2f64(<2 x double> %x) {
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64ZVFH-NEXT: ret
;
@@ -462,7 +462,7 @@ define <2 x double> @round_v2f64(<2 x double> %x) {
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32ZVFHMIN-NEXT: ret
;
@@ -478,7 +478,7 @@ define <2 x double> @round_v2f64(<2 x double> %x) {
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64ZVFHMIN-NEXT: ret
%a = call <2 x double> @llvm.round.v2f64(<2 x double> %x)
@@ -498,7 +498,7 @@ define <4 x double> @round_v4f64(<4 x double> %x) {
; RV32ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu
+; RV32ZVFH-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; RV32ZVFH-NEXT: ret
;
@@ -514,7 +514,7 @@ define <4 x double> @round_v4f64(<4 x double> %x) {
; RV64ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu
+; RV64ZVFH-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; RV64ZVFH-NEXT: ret
;
@@ -529,7 +529,7 @@ define <4 x double> @round_v4f64(<4 x double> %x) {
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu
+; RV32ZVFHMIN-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; RV32ZVFHMIN-NEXT: ret
;
@@ -545,7 +545,7 @@ define <4 x double> @round_v4f64(<4 x double> %x) {
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu
+; RV64ZVFHMIN-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; RV64ZVFHMIN-NEXT: ret
%a = call <4 x double> @llvm.round.v4f64(<4 x double> %x)
@@ -565,7 +565,7 @@ define <8 x double> @round_v8f64(<8 x double> %x) {
; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32ZVFH-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; RV32ZVFH-NEXT: ret
;
@@ -581,7 +581,7 @@ define <8 x double> @round_v8f64(<8 x double> %x) {
; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV64ZVFH-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; RV64ZVFH-NEXT: ret
;
@@ -596,7 +596,7 @@ define <8 x double> @round_v8f64(<8 x double> %x) {
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32ZVFHMIN-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; RV32ZVFHMIN-NEXT: ret
;
@@ -612,7 +612,7 @@ define <8 x double> @round_v8f64(<8 x double> %x) {
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV64ZVFHMIN-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; RV64ZVFHMIN-NEXT: ret
%a = call <8 x double> @llvm.round.v8f64(<8 x double> %x)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
index b1d35d3bcdc1d..b971a29fb2a06 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
@@ -18,11 +18,11 @@ define <1 x half> @roundeven_v1f16(<1 x half> %x) strictfp {
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <1 x half> @llvm.experimental.constrained.roundeven.v1f16(<1 x half> %x, metadata !"fpexcept.strict")
@@ -42,11 +42,11 @@ define <2 x half> @roundeven_v2f16(<2 x half> %x) strictfp {
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <2 x half> @llvm.experimental.constrained.roundeven.v2f16(<2 x half> %x, metadata !"fpexcept.strict")
@@ -66,11 +66,11 @@ define <4 x half> @roundeven_v4f16(<4 x half> %x) strictfp {
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <4 x half> @llvm.experimental.constrained.roundeven.v4f16(<4 x half> %x, metadata !"fpexcept.strict")
@@ -90,11 +90,11 @@ define <8 x half> @roundeven_v8f16(<8 x half> %x) strictfp {
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <8 x half> @llvm.experimental.constrained.roundeven.v8f16(<8 x half> %x, metadata !"fpexcept.strict")
@@ -114,11 +114,11 @@ define <16 x half> @roundeven_v16f16(<16 x half> %x) strictfp {
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
%a = call <16 x half> @llvm.experimental.constrained.roundeven.v16f16(<16 x half> %x, metadata !"fpexcept.strict")
@@ -162,11 +162,11 @@ define <1 x float> @roundeven_v1f32(<1 x float> %x) strictfp {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 0
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <1 x float> @llvm.experimental.constrained.roundeven.v1f32(<1 x float> %x, metadata !"fpexcept.strict")
@@ -185,11 +185,11 @@ define <2 x float> @roundeven_v2f32(<2 x float> %x) strictfp {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 0
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <2 x float> @llvm.experimental.constrained.roundeven.v2f32(<2 x float> %x, metadata !"fpexcept.strict")
@@ -208,11 +208,11 @@ define <4 x float> @roundeven_v4f32(<4 x float> %x) strictfp {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <4 x float> @llvm.experimental.constrained.roundeven.v4f32(<4 x float> %x, metadata !"fpexcept.strict")
@@ -231,11 +231,11 @@ define <8 x float> @roundeven_v8f32(<8 x float> %x) strictfp {
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 0
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
%a = call <8 x float> @llvm.experimental.constrained.roundeven.v8f32(<8 x float> %x, metadata !"fpexcept.strict")
@@ -254,11 +254,11 @@ define <16 x float> @roundeven_v16f32(<16 x float> %x) strictfp {
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 0
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret
%a = call <16 x float> @llvm.experimental.constrained.roundeven.v16f32(<16 x float> %x, metadata !"fpexcept.strict")
@@ -277,11 +277,11 @@ define <1 x double> @roundeven_v1f64(<1 x double> %x) strictfp {
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
; RV32-NEXT: fsrmi a0, 0
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32-NEXT: ret
;
@@ -296,11 +296,11 @@ define <1 x double> @roundeven_v1f64(<1 x double> %x) strictfp {
; RV64-NEXT: fmv.d.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: fsrmi a0, 0
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64-NEXT: ret
%a = call <1 x double> @llvm.experimental.constrained.roundeven.v1f64(<1 x double> %x, metadata !"fpexcept.strict")
@@ -319,11 +319,11 @@ define <2 x double> @roundeven_v2f64(<2 x double> %x) strictfp {
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
; RV32-NEXT: fsrmi a0, 0
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32-NEXT: ret
;
@@ -338,11 +338,11 @@ define <2 x double> @roundeven_v2f64(<2 x double> %x) strictfp {
; RV64-NEXT: fmv.d.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: fsrmi a0, 0
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64-NEXT: ret
%a = call <2 x double> @llvm.experimental.constrained.roundeven.v2f64(<2 x double> %x, metadata !"fpexcept.strict")
@@ -361,11 +361,11 @@ define <4 x double> @roundeven_v4f64(<4 x double> %x) strictfp {
; RV32-NEXT: vfabs.v v10, v8
; RV32-NEXT: vmflt.vf v0, v10, fa5
; RV32-NEXT: fsrmi a0, 0
-; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; RV32-NEXT: ret
;
@@ -380,11 +380,11 @@ define <4 x double> @roundeven_v4f64(<4 x double> %x) strictfp {
; RV64-NEXT: fmv.d.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v10, fa5
; RV64-NEXT: fsrmi a0, 0
-; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; RV64-NEXT: ret
%a = call <4 x double> @llvm.experimental.constrained.roundeven.v4f64(<4 x double> %x, metadata !"fpexcept.strict")
@@ -403,11 +403,11 @@ define <8 x double> @roundeven_v8f64(<8 x double> %x) strictfp {
; RV32-NEXT: vfabs.v v12, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
; RV32-NEXT: fsrmi a0, 0
-; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; RV32-NEXT: ret
;
@@ -422,11 +422,11 @@ define <8 x double> @roundeven_v8f64(<8 x double> %x) strictfp {
; RV64-NEXT: fmv.d.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: fsrmi a0, 0
-; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; RV64-NEXT: ret
%a = call <8 x double> @llvm.experimental.constrained.roundeven.v8f64(<8 x double> %x, metadata !"fpexcept.strict")
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
index f8b3cb5897dfa..7f824995ae8a1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
@@ -23,7 +23,7 @@ define <1 x half> @roundeven_v1f16(<1 x half> %x) {
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
+; ZVFH-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; ZVFH-NEXT: ret
;
@@ -32,7 +32,7 @@ define <1 x half> @roundeven_v1f16(<1 x half> %x) {
; ZVFHMIN-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -40,9 +40,9 @@ define <1 x half> @roundeven_v1f16(<1 x half> %x) {
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; ZVFHMIN-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%a = call <1 x half> @llvm.roundeven.v1f16(<1 x half> %x)
@@ -63,7 +63,7 @@ define <2 x half> @roundeven_v2f16(<2 x half> %x) {
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
+; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; ZVFH-NEXT: ret
;
@@ -72,7 +72,7 @@ define <2 x half> @roundeven_v2f16(<2 x half> %x) {
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -80,9 +80,9 @@ define <2 x half> @roundeven_v2f16(<2 x half> %x) {
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%a = call <2 x half> @llvm.roundeven.v2f16(<2 x half> %x)
@@ -103,7 +103,7 @@ define <4 x half> @roundeven_v4f16(<4 x half> %x) {
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
+; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; ZVFH-NEXT: ret
;
@@ -112,7 +112,7 @@ define <4 x half> @roundeven_v4f16(<4 x half> %x) {
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -120,9 +120,9 @@ define <4 x half> @roundeven_v4f16(<4 x half> %x) {
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%a = call <4 x half> @llvm.roundeven.v4f16(<4 x half> %x)
@@ -143,7 +143,7 @@ define <8 x half> @roundeven_v8f16(<8 x half> %x) {
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; ZVFH-NEXT: ret
;
@@ -152,7 +152,7 @@ define <8 x half> @roundeven_v8f16(<8 x half> %x) {
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -160,9 +160,9 @@ define <8 x half> @roundeven_v8f16(<8 x half> %x) {
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v10, v8, v10, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
; ZVFHMIN-NEXT: ret
%a = call <8 x half> @llvm.roundeven.v8f16(<8 x half> %x)
@@ -183,7 +183,7 @@ define <16 x half> @roundeven_v16f16(<16 x half> %x) {
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu
+; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; ZVFH-NEXT: ret
;
@@ -192,7 +192,7 @@ define <16 x half> @roundeven_v16f16(<16 x half> %x) {
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
@@ -200,9 +200,9 @@ define <16 x half> @roundeven_v16f16(<16 x half> %x) {
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v12, v8, v12, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: ret
%a = call <16 x half> @llvm.roundeven.v16f16(<16 x half> %x)
@@ -264,7 +264,7 @@ define <1 x float> @roundeven_v1f32(<1 x float> %x) {
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <1 x float> @llvm.roundeven.v1f32(<1 x float> %x)
@@ -284,7 +284,7 @@ define <2 x float> @roundeven_v2f32(<2 x float> %x) {
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %x)
@@ -304,7 +304,7 @@ define <4 x float> @roundeven_v4f32(<4 x float> %x) {
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %x)
@@ -324,7 +324,7 @@ define <8 x float> @roundeven_v8f32(<8 x float> %x) {
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
%a = call <8 x float> @llvm.roundeven.v8f32(<8 x float> %x)
@@ -344,7 +344,7 @@ define <16 x float> @roundeven_v16f32(<16 x float> %x) {
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret
%a = call <16 x float> @llvm.roundeven.v16f32(<16 x float> %x)
@@ -364,7 +364,7 @@ define <1 x double> @roundeven_v1f64(<1 x double> %x) {
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32ZVFH-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32ZVFH-NEXT: ret
;
@@ -380,7 +380,7 @@ define <1 x double> @roundeven_v1f64(<1 x double> %x) {
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64ZVFH-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64ZVFH-NEXT: ret
;
@@ -395,7 +395,7 @@ define <1 x double> @roundeven_v1f64(<1 x double> %x) {
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32ZVFHMIN-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32ZVFHMIN-NEXT: ret
;
@@ -411,7 +411,7 @@ define <1 x double> @roundeven_v1f64(<1 x double> %x) {
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64ZVFHMIN-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64ZVFHMIN-NEXT: ret
%a = call <1 x double> @llvm.roundeven.v1f64(<1 x double> %x)
@@ -431,7 +431,7 @@ define <2 x double> @roundeven_v2f64(<2 x double> %x) {
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32ZVFH-NEXT: ret
;
@@ -447,7 +447,7 @@ define <2 x double> @roundeven_v2f64(<2 x double> %x) {
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64ZVFH-NEXT: ret
;
@@ -462,7 +462,7 @@ define <2 x double> @roundeven_v2f64(<2 x double> %x) {
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32ZVFHMIN-NEXT: ret
;
@@ -478,7 +478,7 @@ define <2 x double> @roundeven_v2f64(<2 x double> %x) {
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64ZVFHMIN-NEXT: ret
%a = call <2 x double> @llvm.roundeven.v2f64(<2 x double> %x)
@@ -498,7 +498,7 @@ define <4 x double> @roundeven_v4f64(<4 x double> %x) {
; RV32ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu
+; RV32ZVFH-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; RV32ZVFH-NEXT: ret
;
@@ -514,7 +514,7 @@ define <4 x double> @roundeven_v4f64(<4 x double> %x) {
; RV64ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu
+; RV64ZVFH-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; RV64ZVFH-NEXT: ret
;
@@ -529,7 +529,7 @@ define <4 x double> @roundeven_v4f64(<4 x double> %x) {
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu
+; RV32ZVFHMIN-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; RV32ZVFHMIN-NEXT: ret
;
@@ -545,7 +545,7 @@ define <4 x double> @roundeven_v4f64(<4 x double> %x) {
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m2, ta, mu
+; RV64ZVFHMIN-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; RV64ZVFHMIN-NEXT: ret
%a = call <4 x double> @llvm.roundeven.v4f64(<4 x double> %x)
@@ -565,7 +565,7 @@ define <8 x double> @roundeven_v8f64(<8 x double> %x) {
; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32ZVFH-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; RV32ZVFH-NEXT: ret
;
@@ -581,7 +581,7 @@ define <8 x double> @roundeven_v8f64(<8 x double> %x) {
; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV64ZVFH-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; RV64ZVFH-NEXT: ret
;
@@ -596,7 +596,7 @@ define <8 x double> @roundeven_v8f64(<8 x double> %x) {
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32ZVFHMIN-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; RV32ZVFHMIN-NEXT: ret
;
@@ -612,7 +612,7 @@ define <8 x double> @roundeven_v8f64(<8 x double> %x) {
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV64ZVFHMIN-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; RV64ZVFHMIN-NEXT: ret
%a = call <8 x double> @llvm.roundeven.v8f64(<8 x double> %x)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll
index b7cf84fba4210..2fe64497511db 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll
@@ -15,10 +15,10 @@ define <1 x half> @trunc_v1f16(<1 x half> %x) strictfp {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <1 x half> @llvm.experimental.constrained.trunc.v1f16(<1 x half> %x, metadata !"fpexcept.strict")
@@ -37,10 +37,10 @@ define <2 x half> @trunc_v2f16(<2 x half> %x) strictfp {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <2 x half> @llvm.experimental.constrained.trunc.v2f16(<2 x half> %x, metadata !"fpexcept.strict")
@@ -59,10 +59,10 @@ define <4 x half> @trunc_v4f16(<4 x half> %x) strictfp {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <4 x half> @llvm.experimental.constrained.trunc.v4f16(<4 x half> %x, metadata !"fpexcept.strict")
@@ -81,10 +81,10 @@ define <8 x half> @trunc_v8f16(<8 x half> %x) strictfp {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <8 x half> @llvm.experimental.constrained.trunc.v8f16(<8 x half> %x, metadata !"fpexcept.strict")
@@ -103,10 +103,10 @@ define <16 x half> @trunc_v16f16(<16 x half> %x) strictfp {
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: fmv.h.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
%a = call <16 x half> @llvm.experimental.constrained.trunc.v16f16(<16 x half> %x, metadata !"fpexcept.strict")
@@ -147,10 +147,10 @@ define <1 x float> @trunc_v1f32(<1 x float> %x) strictfp {
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <1 x float> @llvm.experimental.constrained.trunc.v1f32(<1 x float> %x, metadata !"fpexcept.strict")
@@ -168,10 +168,10 @@ define <2 x float> @trunc_v2f32(<2 x float> %x) strictfp {
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <2 x float> @llvm.experimental.constrained.trunc.v2f32(<2 x float> %x, metadata !"fpexcept.strict")
@@ -189,10 +189,10 @@ define <4 x float> @trunc_v4f32(<4 x float> %x) strictfp {
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
%a = call <4 x float> @llvm.experimental.constrained.trunc.v4f32(<4 x float> %x, metadata !"fpexcept.strict")
@@ -210,10 +210,10 @@ define <8 x float> @trunc_v8f32(<8 x float> %x) strictfp {
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
%a = call <8 x float> @llvm.experimental.constrained.trunc.v8f32(<8 x float> %x, metadata !"fpexcept.strict")
@@ -231,10 +231,10 @@ define <16 x float> @trunc_v16f32(<16 x float> %x) strictfp {
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret
%a = call <16 x float> @llvm.experimental.constrained.trunc.v16f32(<16 x float> %x, metadata !"fpexcept.strict")
@@ -252,10 +252,10 @@ define <1 x double> @trunc_v1f64(<1 x double> %x) strictfp {
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32-NEXT: ret
;
@@ -269,10 +269,10 @@ define <1 x double> @trunc_v1f64(<1 x double> %x) strictfp {
; RV64-NEXT: vfabs.v v9, v8
; RV64-NEXT: fmv.d.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v9, fa5
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64-NEXT: ret
%a = call <1 x double> @llvm.experimental.constrained.trunc.v1f64(<1 x double> %x, metadata !"fpexcept.strict")
@@ -290,10 +290,10 @@ define <2 x double> @trunc_v2f64(<2 x double> %x) strictfp {
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV32-NEXT: ret
;
@@ -307,10 +307,10 @@ define <2 x double> @trunc_v2f64(<2 x double> %x) strictfp {
; RV64-NEXT: vfabs.v v9, v8
; RV64-NEXT: fmv.d.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v9, fa5
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; RV64-NEXT: ret
%a = call <2 x double> @llvm.experimental.constrained.trunc.v2f64(<2 x double> %x, metadata !"fpexcept.strict")
@@ -328,10 +328,10 @@ define <4 x double> @trunc_v4f64(<4 x double> %x) strictfp {
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV32-NEXT: vfabs.v v10, v8
; RV32-NEXT: vmflt.vf v0, v10, fa5
-; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t
; RV32-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; RV32-NEXT: ret
;
@@ -345,10 +345,10 @@ define <4 x double> @trunc_v4f64(<4 x double> %x) strictfp {
; RV64-NEXT: vfabs.v v10, v8
; RV64-NEXT: fmv.d.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v10, fa5
-; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t
; RV64-NEXT: vfcvt.f.x.v v10, v10, v0.t
-; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; RV64-NEXT: ret
%a = call <4 x double> @llvm.experimental.constrained.trunc.v4f64(<4 x double> %x, metadata !"fpexcept.strict")
@@ -366,10 +366,10 @@ define <8 x double> @trunc_v8f64(<8 x double> %x) strictfp {
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV32-NEXT: vfabs.v v12, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
-; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t
; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; RV32-NEXT: ret
;
@@ -383,10 +383,10 @@ define <8 x double> @trunc_v8f64(<8 x double> %x) strictfp {
; RV64-NEXT: vfabs.v v12, v8
; RV64-NEXT: fmv.d.x fa5, a0
; RV64-NEXT: vmflt.vf v0, v12, fa5
-; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t
; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t
-; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; RV64-NEXT: ret
%a = call <8 x double> @llvm.experimental.constrained.trunc.v8f64(<8 x double> %x, metadata !"fpexcept.strict")
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
index b52b082282ec4..a005aa1970e85 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
@@ -50,7 +50,7 @@ define <2 x float> @si2fp_v2i7_v2f32(<2 x i7> %x) {
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: vsra.vi v8, v8, 1
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vsext.vf2 v9, v8
; CHECK-NEXT: vfwcvt.f.x.v v8, v9
; CHECK-NEXT: ret
@@ -64,7 +64,7 @@ define <2 x float> @ui2fp_v2i7_v2f32(<2 x i7> %x) {
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vand.vx v8, v8, a0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vzext.vf2 v9, v8
; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
; CHECK-NEXT: ret
@@ -138,7 +138,7 @@ define <3 x float> @si2fp_v3i7_v3f32(<3 x i7> %x) {
; ZVFH32-NEXT: vslidedown.vi v8, v8, 1
; ZVFH32-NEXT: vadd.vv v8, v8, v8
; ZVFH32-NEXT: vsra.vi v8, v8, 1
-; ZVFH32-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFH32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFH32-NEXT: vsext.vf2 v9, v8
; ZVFH32-NEXT: vfwcvt.f.x.v v8, v9
; ZVFH32-NEXT: ret
@@ -155,7 +155,7 @@ define <3 x float> @si2fp_v3i7_v3f32(<3 x i7> %x) {
; ZVFH64-NEXT: vslidedown.vi v8, v8, 1
; ZVFH64-NEXT: vadd.vv v8, v8, v8
; ZVFH64-NEXT: vsra.vi v8, v8, 1
-; ZVFH64-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFH64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFH64-NEXT: vsext.vf2 v9, v8
; ZVFH64-NEXT: vfwcvt.f.x.v v8, v9
; ZVFH64-NEXT: ret
@@ -172,7 +172,7 @@ define <3 x float> @si2fp_v3i7_v3f32(<3 x i7> %x) {
; ZVFHMIN32-NEXT: vslidedown.vi v8, v8, 1
; ZVFHMIN32-NEXT: vadd.vv v8, v8, v8
; ZVFHMIN32-NEXT: vsra.vi v8, v8, 1
-; ZVFHMIN32-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN32-NEXT: vsext.vf2 v9, v8
; ZVFHMIN32-NEXT: vfwcvt.f.x.v v8, v9
; ZVFHMIN32-NEXT: ret
@@ -189,7 +189,7 @@ define <3 x float> @si2fp_v3i7_v3f32(<3 x i7> %x) {
; ZVFHMIN64-NEXT: vslidedown.vi v8, v8, 1
; ZVFHMIN64-NEXT: vadd.vv v8, v8, v8
; ZVFHMIN64-NEXT: vsra.vi v8, v8, 1
-; ZVFHMIN64-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN64-NEXT: vsext.vf2 v9, v8
; ZVFHMIN64-NEXT: vfwcvt.f.x.v v8, v9
; ZVFHMIN64-NEXT: ret
@@ -211,7 +211,7 @@ define <3 x float> @ui2fp_v3i7_v3f32(<3 x i7> %x) {
; ZVFH32-NEXT: vslidedown.vi v8, v8, 1
; ZVFH32-NEXT: li a0, 127
; ZVFH32-NEXT: vand.vx v8, v8, a0
-; ZVFH32-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFH32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFH32-NEXT: vzext.vf2 v9, v8
; ZVFH32-NEXT: vfwcvt.f.xu.v v8, v9
; ZVFH32-NEXT: ret
@@ -228,7 +228,7 @@ define <3 x float> @ui2fp_v3i7_v3f32(<3 x i7> %x) {
; ZVFH64-NEXT: vslidedown.vi v8, v8, 1
; ZVFH64-NEXT: li a0, 127
; ZVFH64-NEXT: vand.vx v8, v8, a0
-; ZVFH64-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFH64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFH64-NEXT: vzext.vf2 v9, v8
; ZVFH64-NEXT: vfwcvt.f.xu.v v8, v9
; ZVFH64-NEXT: ret
@@ -245,7 +245,7 @@ define <3 x float> @ui2fp_v3i7_v3f32(<3 x i7> %x) {
; ZVFHMIN32-NEXT: vslidedown.vi v8, v8, 1
; ZVFHMIN32-NEXT: li a0, 127
; ZVFHMIN32-NEXT: vand.vx v8, v8, a0
-; ZVFHMIN32-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN32-NEXT: vzext.vf2 v9, v8
; ZVFHMIN32-NEXT: vfwcvt.f.xu.v v8, v9
; ZVFHMIN32-NEXT: ret
@@ -262,7 +262,7 @@ define <3 x float> @ui2fp_v3i7_v3f32(<3 x i7> %x) {
; ZVFHMIN64-NEXT: vslidedown.vi v8, v8, 1
; ZVFHMIN64-NEXT: li a0, 127
; ZVFHMIN64-NEXT: vand.vx v8, v8, a0
-; ZVFHMIN64-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN64-NEXT: vzext.vf2 v9, v8
; ZVFHMIN64-NEXT: vfwcvt.f.xu.v v8, v9
; ZVFHMIN64-NEXT: ret
@@ -424,7 +424,7 @@ define void @si2fp_v2i64_v2bf16(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfncvt.f.x.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
@@ -440,7 +440,7 @@ define void @ui2fp_v2i64_v2bf16(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfncvt.f.xu.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
@@ -482,7 +482,7 @@ define void @si2fp_v8i64_v8bf16(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfncvt.f.x.w v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
@@ -498,7 +498,7 @@ define void @ui2fp_v8i64_v8bf16(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfncvt.f.xu.w v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
@@ -540,7 +540,7 @@ define void @si2fp_v2i64_v2f16(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfncvt.f.x.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfncvt.f.f.w v8, v9
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
@@ -556,7 +556,7 @@ define void @ui2fp_v2i64_v2f16(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfncvt.f.xu.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfncvt.f.f.w v8, v9
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
@@ -614,7 +614,7 @@ define void @si2fp_v8i64_v8f16(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfncvt.f.x.w v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvt.f.f.w v8, v12
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
@@ -630,7 +630,7 @@ define void @ui2fp_v8i64_v8f16(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfncvt.f.xu.w v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvt.f.f.w v8, v12
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll
index a99efc97f7e63..7faca86175444 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll
@@ -32,7 +32,7 @@ define <4 x i32> @insert_subvector_load_unfoldable_passthru_v4i32_v4i32(<4 x i32
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v9, (a0), v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
%v2 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %p, i32 4, <4 x i1> %mask, <4 x i32> %passthru)
@@ -57,7 +57,7 @@ define <4 x i32> @insert_subvector_add_v4i32_v4i32(<4 x i32> %v1, <4 x i32> %v2)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; CHECK-NEXT: vid.v v10
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; CHECK-NEXT: vadd.vv v8, v9, v10
; CHECK-NEXT: ret
%v3 = add <4 x i32> %v2, <i32 0, i32 1, i32 2, i32 3>
@@ -168,7 +168,7 @@ define <4 x i32> @insert_subvector_add_v4i32_v8i32(<4 x i32> %v1, <8 x i32> %v2)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; CHECK-NEXT: vid.v v9
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; CHECK-NEXT: vadd.vv v8, v10, v9
; CHECK-NEXT: ret
%v3 = add <8 x i32> %v2, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
index 00328f9d33d3e..5ba759ff4aece 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
@@ -554,7 +554,7 @@ define <vscale x 2 x i1> @insert_nxv2i1_v4i1_0(<vscale x 2 x i1> %v, ptr %svp) {
; VLA-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; VLA-NEXT: vmv.v.i v10, 0
; VLA-NEXT: vmv1r.v v0, v8
-; VLA-NEXT: vsetvli zero, zero, e8, mf4, tu, ma
+; VLA-NEXT: vsetivli zero, 4, e8, mf4, tu, ma
; VLA-NEXT: vmerge.vim v9, v10, 1, v0
; VLA-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; VLA-NEXT: vmsne.vi v0, v9, 0
@@ -567,9 +567,9 @@ define <vscale x 2 x i1> @insert_nxv2i1_v4i1_0(<vscale x 2 x i1> %v, ptr %svp) {
; VLS-NEXT: vmv.v.i v9, 0
; VLS-NEXT: vmerge.vim v10, v9, 1, v0
; VLS-NEXT: vmv1r.v v0, v8
-; VLS-NEXT: vsetvli zero, zero, e8, mf4, tu, ma
+; VLS-NEXT: vsetivli zero, 4, e8, mf4, tu, ma
; VLS-NEXT: vmerge.vim v10, v9, 1, v0
-; VLS-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; VLS-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; VLS-NEXT: vmsne.vi v0, v10, 0
; VLS-NEXT: ret
%sv = load <4 x i1>, ptr %svp
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
index 79286c0304e0c..95f3f6eecef8d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
@@ -789,9 +789,9 @@ define void @insertelt_c6_v8i64_0_add(ptr %x, ptr %y) {
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vle64.v v12, (a1)
; CHECK-NEXT: li a1, 6
-; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, ma
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, tu, ma
; CHECK-NEXT: vmv.s.x v8, a1
-; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vadd.vv v8, v8, v12
; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
@@ -802,9 +802,9 @@ define void @insertelt_c6_v8i64_0_add(ptr %x, ptr %y) {
; VISNI-NEXT: vle64.v v8, (a0)
; VISNI-NEXT: vle64.v v12, (a1)
; VISNI-NEXT: li a1, 6
-; VISNI-NEXT: vsetvli zero, zero, e64, m4, tu, ma
+; VISNI-NEXT: vsetivli zero, 8, e64, m4, tu, ma
; VISNI-NEXT: vmv.s.x v8, a1
-; VISNI-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; VISNI-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; VISNI-NEXT: vadd.vv v8, v8, v12
; VISNI-NEXT: vse64.v v8, (a0)
; VISNI-NEXT: ret
@@ -1149,7 +1149,7 @@ define <2 x i8> @pr169017(<4 x i16> %vecinit, <2 x i8> %dst_vec) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, tu, ma
+; CHECK-NEXT: vsetivli zero, 1, e8, mf8, tu, ma
; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
@@ -1158,7 +1158,7 @@ define <2 x i8> @pr169017(<4 x i16> %vecinit, <2 x i8> %dst_vec) {
; VISNI: # %bb.0: # %entry
; VISNI-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; VISNI-NEXT: vmv.x.s a0, v8
-; VISNI-NEXT: vsetvli zero, zero, e8, mf8, tu, ma
+; VISNI-NEXT: vsetivli zero, 1, e8, mf8, tu, ma
; VISNI-NEXT: vmv.s.x v9, a0
; VISNI-NEXT: vmv1r.v v8, v9
; VISNI-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
index ca72905a0f39b..884a772a166fc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
@@ -528,7 +528,7 @@ define void @buildvec_dominant0_v2i32(ptr %x) {
; RV64V-NEXT: ld a1, %lo(.LCPI40_0)(a1)
; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64V-NEXT: vmv.v.i v8, -1
-; RV64V-NEXT: vsetvli zero, zero, e64, m1, tu, ma
+; RV64V-NEXT: vsetivli zero, 2, e64, m1, tu, ma
; RV64V-NEXT: vmv.s.x v8, a1
; RV64V-NEXT: vse64.v v8, (a0)
; RV64V-NEXT: ret
@@ -693,14 +693,14 @@ define void @buildvec_seq_v9i8(ptr %x) {
; CHECK-NEXT: li a1, 73
; CHECK-NEXT: vsetivli zero, 9, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.i v8, 3
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 9, e16, m2, ta, ma
; CHECK-NEXT: vmv.s.x v0, a1
; CHECK-NEXT: li a1, 146
-; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 9, e8, m1, ta, ma
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 9, e16, m2, ta, ma
; CHECK-NEXT: vmv.s.x v0, a1
-; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 9, e8, m1, ta, ma
; CHECK-NEXT: vmerge.vim v8, v8, 2, v0
; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
@@ -1055,10 +1055,9 @@ define <512 x i8> @buildvec_not_vid_v512i8_indices_overflow_2() vscale_range(16,
define <8 x i32> @prefix_overwrite(<8 x i32> %vin, i32 %a, i32 %b, i32 %c, i32 %d) {
; CHECK-LABEL: prefix_overwrite:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e32, m1, tu, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; CHECK-NEXT: vmv.s.x v10, a1
; CHECK-NEXT: vmv.s.x v8, a0
-; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; CHECK-NEXT: vslideup.vi v8, v10, 1
; CHECK-NEXT: vmv.s.x v10, a2
; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, ma
@@ -3391,7 +3390,7 @@ define <4 x i32> @buildvec_vslide1up(i32 %e1, i32 %e2) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.x v8, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma
; CHECK-NEXT: vmv.s.x v8, a1
; CHECK-NEXT: ret
%v1 = insertelement <4 x i32> poison, i32 %e2, i32 0
@@ -3622,10 +3621,9 @@ define <16 x i16> @PR159294(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
; RV32VB-NEXT: vmv.x.s a1, v9
; RV32VB-NEXT: vmv.v.i v8, 0
; RV32VB-NEXT: zext.h a1, a1
-; RV32VB-NEXT: vsetvli zero, zero, e32, m2, tu, ma
+; RV32VB-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; RV32VB-NEXT: vmv.s.x v8, a0
; RV32VB-NEXT: vmv.s.x v10, a1
-; RV32VB-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; RV32VB-NEXT: vslideup.vi v8, v10, 1
; RV32VB-NEXT: ret
;
@@ -3639,10 +3637,9 @@ define <16 x i16> @PR159294(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
; RV32VB-PACK-NEXT: pack a1, a0, a0
; RV32VB-PACK-NEXT: vmv.v.x v8, a1
; RV32VB-PACK-NEXT: pack a1, a2, a0
-; RV32VB-PACK-NEXT: vsetvli zero, zero, e32, m2, tu, ma
+; RV32VB-PACK-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; RV32VB-PACK-NEXT: vmv.s.x v8, a0
; RV32VB-PACK-NEXT: vmv.s.x v10, a1
-; RV32VB-PACK-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; RV32VB-PACK-NEXT: vslideup.vi v8, v10, 1
; RV32VB-PACK-NEXT: ret
;
@@ -3670,10 +3667,9 @@ define <16 x i16> @PR159294(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
; RVA22U64-NEXT: vmv.x.s a1, v9
; RVA22U64-NEXT: vmv.v.i v8, 0
; RVA22U64-NEXT: zext.h a1, a1
-; RVA22U64-NEXT: vsetvli zero, zero, e32, m2, tu, ma
+; RVA22U64-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; RVA22U64-NEXT: vmv.s.x v8, a0
; RVA22U64-NEXT: vmv.s.x v10, a1
-; RVA22U64-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; RVA22U64-NEXT: vslideup.vi v8, v10, 1
; RVA22U64-NEXT: ret
;
@@ -3687,10 +3683,9 @@ define <16 x i16> @PR159294(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
; RVA22U64-PACK-NEXT: packw a1, a0, a0
; RVA22U64-PACK-NEXT: vmv.v.x v8, a1
; RVA22U64-PACK-NEXT: packw a1, a2, a0
-; RVA22U64-PACK-NEXT: vsetvli zero, zero, e32, m2, tu, ma
+; RVA22U64-PACK-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; RVA22U64-PACK-NEXT: vmv.s.x v8, a0
; RVA22U64-PACK-NEXT: vmv.s.x v10, a1
-; RVA22U64-PACK-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; RVA22U64-PACK-NEXT: vslideup.vi v8, v10, 1
; RVA22U64-PACK-NEXT: ret
;
@@ -3767,10 +3762,9 @@ define <16 x i32> @PR159294_zext(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {
; RVA22U64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RVA22U64-NEXT: vmv.v.i v8, 0
; RVA22U64-NEXT: zext.h a1, a1
-; RVA22U64-NEXT: vsetvli zero, zero, e64, m4, tu, ma
+; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, tu, ma
; RVA22U64-NEXT: vmv.s.x v8, a0
; RVA22U64-NEXT: vmv.s.x v12, a1
-; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, tu, ma
; RVA22U64-NEXT: vslideup.vi v8, v12, 1
; RVA22U64-NEXT: ret
;
@@ -3783,17 +3777,16 @@ define <16 x i32> @PR159294_zext(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {
; RVA22U64-PACK-NEXT: pack a2, a0, a0
; RVA22U64-PACK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RVA22U64-PACK-NEXT: vmv.v.x v8, a2
-; RVA22U64-PACK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RVA22U64-PACK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RVA22U64-PACK-NEXT: vmv.x.s a2, v12
; RVA22U64-PACK-NEXT: zext.h a0, a0
; RVA22U64-PACK-NEXT: zext.h a1, a1
; RVA22U64-PACK-NEXT: zext.h a2, a2
; RVA22U64-PACK-NEXT: pack a0, a1, a0
; RVA22U64-PACK-NEXT: pack a1, a2, a0
-; RVA22U64-PACK-NEXT: vsetvli zero, zero, e64, m4, tu, ma
+; RVA22U64-PACK-NEXT: vsetivli zero, 2, e64, m1, tu, ma
; RVA22U64-PACK-NEXT: vmv.s.x v8, a0
; RVA22U64-PACK-NEXT: vmv.s.x v12, a1
-; RVA22U64-PACK-NEXT: vsetivli zero, 2, e64, m1, tu, ma
; RVA22U64-PACK-NEXT: vslideup.vi v8, v12, 1
; RVA22U64-PACK-NEXT: ret
;
@@ -3865,10 +3858,9 @@ define <16 x i32> @PR159294_sext(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {
; RVA22U64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RVA22U64-NEXT: vmv.v.i v8, 0
; RVA22U64-NEXT: zext.w a1, a1
-; RVA22U64-NEXT: vsetvli zero, zero, e64, m4, tu, ma
+; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, tu, ma
; RVA22U64-NEXT: vmv.s.x v8, a0
; RVA22U64-NEXT: vmv.s.x v12, a1
-; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, tu, ma
; RVA22U64-NEXT: vslideup.vi v8, v12, 1
; RVA22U64-NEXT: ret
;
@@ -3883,10 +3875,9 @@ define <16 x i32> @PR159294_sext(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {
; RVA22U64-PACK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RVA22U64-PACK-NEXT: vmv.v.x v8, a1
; RVA22U64-PACK-NEXT: pack a1, a2, a0
-; RVA22U64-PACK-NEXT: vsetvli zero, zero, e64, m4, tu, ma
+; RVA22U64-PACK-NEXT: vsetivli zero, 2, e64, m1, tu, ma
; RVA22U64-PACK-NEXT: vmv.s.x v8, a0
; RVA22U64-PACK-NEXT: vmv.s.x v12, a1
-; RVA22U64-PACK-NEXT: vsetivli zero, 2, e64, m1, tu, ma
; RVA22U64-PACK-NEXT: vslideup.vi v8, v12, 1
; RVA22U64-PACK-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
index 970f4b04e919a..ca90220ecf48b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
@@ -65,7 +65,7 @@ define void @trunc_v4i8_v4i32(ptr %x, ptr %z) {
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vnsrl.wi v8, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
@@ -81,7 +81,7 @@ define void @trunc_v8i8_v8i32(ptr %x, ptr %z) {
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vnsrl.wi v10, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
index 9df71cfc96cc7..4f71c0cec4ef7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
@@ -1054,36 +1054,36 @@ define void @mulhu_v16i8(ptr %x) {
; CHECK-NEXT: vle8.v v10, (a2)
; CHECK-NEXT: li a2, -128
; CHECK-NEXT: addi a1, a1, -2044
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vmv.s.x v0, a1
; CHECK-NEXT: lui a1, 1
-; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmerge.vxm v11, v9, a2, v0
; CHECK-NEXT: addi a2, a1, 32
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vmv.s.x v0, a2
; CHECK-NEXT: li a2, 513
-; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.i v12, 4
; CHECK-NEXT: addi a1, a1, 78
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vmv.s.x v0, a2
-; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vsrl.vv v9, v8, v9
; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vmv.s.x v0, a1
-; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmulhu.vv v9, v9, v10
; CHECK-NEXT: vmerge.vim v10, v12, 3, v0
; CHECK-NEXT: lui a1, 8
; CHECK-NEXT: addi a1, a1, 304
; CHECK-NEXT: vsub.vv v8, v8, v9
; CHECK-NEXT: vmulhu.vv v8, v8, v11
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vmv.s.x v0, a1
-; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vmerge.vim v9, v10, 2, v0
; CHECK-NEXT: vsrl.vv v8, v8, v9
@@ -1118,9 +1118,9 @@ define void @mulhu_v8i16(ptr %x) {
; CHECK-NEXT: vsrl.vv v9, v8, v9
; CHECK-NEXT: vmulhu.vv v9, v9, v12
; CHECK-NEXT: lui a1, 1048568
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, tu, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, tu, ma
; CHECK-NEXT: vmv.s.x v13, a1
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vsub.vv v8, v8, v9
; CHECK-NEXT: vmulhu.vv v8, v8, v13
; CHECK-NEXT: vadd.vv v8, v8, v9
@@ -1214,9 +1214,9 @@ define void @mulhu_v2i64(ptr %x) {
; RV64-NEXT: slli a3, a2, 32
; RV64-NEXT: add a2, a2, a3
; RV64-NEXT: vmv.v.x v9, a1
-; RV64-NEXT: vsetvli zero, zero, e64, m1, tu, ma
+; RV64-NEXT: vsetivli zero, 2, e64, m1, tu, ma
; RV64-NEXT: vmv.s.x v9, a2
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vmulhu.vv v8, v8, v9
; RV64-NEXT: vid.v v9
; RV64-NEXT: vadd.vi v9, v9, 1
@@ -1238,10 +1238,10 @@ define void @mulhs_v16i8(ptr %x) {
; CHECK-NEXT: vmv.v.x v9, a1
; CHECK-NEXT: lui a1, 5
; CHECK-NEXT: addi a1, a1, -1452
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vmv.s.x v0, a1
; CHECK-NEXT: li a1, 57
-; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmerge.vxm v9, v9, a1, v0
; CHECK-NEXT: vmv.v.i v10, 7
; CHECK-NEXT: vmulhu.vv v8, v8, v9
@@ -1352,9 +1352,9 @@ define void @mulhs_v2i64(ptr %x) {
; RV32-NEXT: addi a1, a1, 1366
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vrsub.vi v11, v9, 0
-; RV32-NEXT: vsetvli zero, zero, e32, mf2, tu, ma
+; RV32-NEXT: vsetivli zero, 2, e32, mf2, tu, ma
; RV32-NEXT: vmv.s.x v10, a1
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vmulh.vv v10, v8, v10
; RV32-NEXT: vmadd.vv v11, v8, v10
; RV32-NEXT: vsrl.vx v8, v11, a2
@@ -1377,9 +1377,9 @@ define void @mulhs_v2i64(ptr %x) {
; RV64-NEXT: vmv.v.x v10, a1
; RV64-NEXT: li a1, 63
; RV64-NEXT: vrsub.vi v11, v9, 0
-; RV64-NEXT: vsetvli zero, zero, e64, m1, tu, ma
+; RV64-NEXT: vsetivli zero, 2, e64, m1, tu, ma
; RV64-NEXT: vmv.s.x v10, a2
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vmulh.vv v10, v8, v10
; RV64-NEXT: vmadd.vv v11, v8, v10
; RV64-NEXT: vsrl.vx v8, v11, a1
@@ -3206,27 +3206,27 @@ define void @mulhu_v16i16(ptr %x) {
; RV32-NEXT: lui a1, 1048568
; RV32-NEXT: vmerge.vxm v12, v8, a1, v0
; RV32-NEXT: lui a1, 4
-; RV32-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: addi a1, a1, 64
-; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV32-NEXT: vmv.s.x v8, a1
; RV32-NEXT: lui a1, 2
; RV32-NEXT: addi a1, a1, 289
; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmerge.vim v16, v9, 1, v0
-; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV32-NEXT: vmv.s.x v0, a1
; RV32-NEXT: lui a1, %hi(.LCPI182_0)
; RV32-NEXT: addi a1, a1, %lo(.LCPI182_0)
-; RV32-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmv.v.i v9, 3
; RV32-NEXT: vmerge.vim v9, v9, 2, v0
; RV32-NEXT: vle16.v v14, (a1)
; RV32-NEXT: vmv1r.v v0, v8
; RV32-NEXT: vmerge.vim v17, v9, 1, v0
-; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV32-NEXT: vsext.vf2 v8, v16
; RV32-NEXT: vsrl.vv v8, v10, v8
; RV32-NEXT: vmulhu.vv v8, v8, v14
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
index 5567310bb2a61..7d3f359f14f99 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
@@ -584,8 +584,9 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV32-NEXT: vle16.v v28, (a7)
+; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vmv.s.x v0, a6
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 6
@@ -598,7 +599,6 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vmerge.vvm v16, v8, v16, v0
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vrgatherei16.vv v0, v16, v28
@@ -608,7 +608,7 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
+; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; RV32-NEXT: vslideup.vi v8, v24, 2
; RV32-NEXT: vmv1r.v v0, v30
; RV32-NEXT: csrr a1, vlenb
@@ -790,7 +790,7 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vmerge.vvm v8, v24, v8, v0
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a3, 92
@@ -803,7 +803,7 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vrgatherei16.vv v24, v8, v2
; RV32-NEXT: lui a1, %hi(.LCPI27_2)
; RV32-NEXT: addi a1, a1, %lo(.LCPI27_2)
@@ -2030,10 +2030,9 @@ define {<4 x i32>, <4 x i32>, <4 x i32>} @invalid_vp_mask(ptr %ptr) {
; RV32-NEXT: lui a1, 1
; RV32-NEXT: vmv.v.i v10, 8
; RV32-NEXT: addi a1, a1, -43
-; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 12, e32, m4, ta, ma
; RV32-NEXT: vmv.s.x v0, a1
; RV32-NEXT: li a1, 146
-; RV32-NEXT: vsetivli zero, 12, e32, m4, ta, ma
; RV32-NEXT: vle32.v v12, (a0), v0.t
; RV32-NEXT: li a0, 36
; RV32-NEXT: vmv.s.x v20, a1
@@ -2065,10 +2064,9 @@ define {<4 x i32>, <4 x i32>, <4 x i32>} @invalid_vp_mask(ptr %ptr) {
; RV64-NEXT: lui a1, 1
; RV64-NEXT: vmv.v.i v10, 8
; RV64-NEXT: addi a1, a1, -43
-; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 12, e32, m4, ta, ma
; RV64-NEXT: vmv.s.x v0, a1
; RV64-NEXT: li a1, 36
-; RV64-NEXT: vsetivli zero, 12, e32, m4, ta, ma
; RV64-NEXT: vle32.v v12, (a0), v0.t
; RV64-NEXT: li a0, 3
; RV64-NEXT: slli a0, a0, 32
@@ -2373,10 +2371,9 @@ define {<4 x i32>, <4 x i32>, <4 x i32>} @maskedload_factor3_invalid_skip_field(
; RV32-NEXT: lui a1, 1
; RV32-NEXT: vmv.v.i v10, 8
; RV32-NEXT: addi a1, a1, -1171
-; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 12, e32, m4, ta, ma
; RV32-NEXT: vmv.s.x v0, a1
; RV32-NEXT: li a1, 146
-; RV32-NEXT: vsetivli zero, 12, e32, m4, ta, ma
; RV32-NEXT: vle32.v v12, (a0), v0.t
; RV32-NEXT: li a0, 36
; RV32-NEXT: vmv.s.x v20, a1
@@ -2408,10 +2405,9 @@ define {<4 x i32>, <4 x i32>, <4 x i32>} @maskedload_factor3_invalid_skip_field(
; RV64-NEXT: lui a1, 1
; RV64-NEXT: vmv.v.i v10, 8
; RV64-NEXT: addi a1, a1, -1171
-; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 12, e32, m4, ta, ma
; RV64-NEXT: vmv.s.x v0, a1
; RV64-NEXT: li a1, 36
-; RV64-NEXT: vsetivli zero, 12, e32, m4, ta, ma
; RV64-NEXT: vle32.v v12, (a0), v0.t
; RV64-NEXT: li a0, 3
; RV64-NEXT: slli a0, a0, 32
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
index b9a84ff9b07b9..63fb8202b1885 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
@@ -125,7 +125,7 @@ define <1 x i64> @llrint_v1i64_v1f16(<1 x half> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfwcvt.x.f.v v8, v9
; CHECK-NEXT: ret
%a = call <1 x i64> @llvm.llrint.v1i64.v1f16(<1 x half> %x)
@@ -138,7 +138,7 @@ define <2 x i64> @llrint_v2i64_v2f16(<2 x half> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwcvt.x.f.v v8, v9
; CHECK-NEXT: ret
%a = call <2 x i64> @llvm.llrint.v2i64.v2f16(<2 x half> %x)
@@ -151,7 +151,7 @@ define <3 x i64> @llrint_v3i64_v3f16(<3 x half> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfwcvt.x.f.v v8, v10
; CHECK-NEXT: ret
%a = call <3 x i64> @llvm.llrint.v3i64.v3f16(<3 x half> %x)
@@ -164,7 +164,7 @@ define <4 x i64> @llrint_v4i64_v4f16(<4 x half> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfwcvt.x.f.v v8, v10
; CHECK-NEXT: ret
%a = call <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half> %x)
@@ -177,7 +177,7 @@ define <8 x i64> @llrint_v8i64_v8f16(<8 x half> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfwcvt.x.f.v v8, v12
; CHECK-NEXT: ret
%a = call <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half> %x)
@@ -190,7 +190,7 @@ define <16 x i64> @llrint_v16i64_v16f16(<16 x half> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v16, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfwcvt.x.f.v v8, v16
; CHECK-NEXT: ret
%a = call <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half> %x)
@@ -203,7 +203,7 @@ define <1 x i64> @llrint_v1i64_v1bf16(<1 x bfloat> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfwcvt.x.f.v v8, v9
; CHECK-NEXT: ret
%a = call <1 x i64> @llvm.llrint.v1i64.v1bf16(<1 x bfloat> %x)
@@ -216,7 +216,7 @@ define <2 x i64> @llrint_v2i64_v2bf16(<2 x bfloat> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwcvt.x.f.v v8, v9
; CHECK-NEXT: ret
%a = call <2 x i64> @llvm.llrint.v2i64.v2bf16(<2 x bfloat> %x)
@@ -229,7 +229,7 @@ define <3 x i64> @llrint_v3i64_v3bf16(<3 x bfloat> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfwcvt.x.f.v v8, v10
; CHECK-NEXT: ret
%a = call <3 x i64> @llvm.llrint.v3i64.v3bf16(<3 x bfloat> %x)
@@ -242,7 +242,7 @@ define <4 x i64> @llrint_v4i64_v4bf16(<4 x bfloat> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfwcvt.x.f.v v8, v10
; CHECK-NEXT: ret
%a = call <4 x i64> @llvm.llrint.v4i64.v4bf16(<4 x bfloat> %x)
@@ -255,7 +255,7 @@ define <8 x i64> @llrint_v8i64_v8bf16(<8 x bfloat> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfwcvt.x.f.v v8, v12
; CHECK-NEXT: ret
%a = call <8 x i64> @llvm.llrint.v8i64.v8bf16(<8 x bfloat> %x)
@@ -268,7 +268,7 @@ define <16 x i64> @llrint_v16i64_v16bf16(<16 x bfloat> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfwcvt.x.f.v v8, v16
; CHECK-NEXT: ret
%a = call <16 x i64> @llvm.llrint.v16i64.v16bf16(<16 x bfloat> %x)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llround.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llround.ll
index 5751759ddd9cb..e2001c8ee0baa 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llround.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llround.ll
@@ -10,7 +10,7 @@ define <1 x i64> @llround_v1f16(<1 x half> %x) nounwind {
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vfwcvt.f.f.v v9, v8
; RV32-NEXT: fsrmi a0, 4
-; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: vfwcvt.x.f.v v8, v9
; RV32-NEXT: fsrm a0
; RV32-NEXT: ret
@@ -20,7 +20,7 @@ define <1 x i64> @llround_v1f16(<1 x half> %x) nounwind {
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-NEXT: vfwcvt.f.f.v v9, v8
; RV64-NEXT: fsrmi a0, 4
-; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV64-NEXT: vfwcvt.x.f.v v8, v9
; RV64-NEXT: fsrm a0
; RV64-NEXT: ret
@@ -35,7 +35,7 @@ define <2 x i64> @llround_v2f16(<2 x half> %x) nounwind {
; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV32-NEXT: vfwcvt.f.f.v v9, v8
; RV32-NEXT: fsrmi a0, 4
-; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV32-NEXT: vfwcvt.x.f.v v8, v9
; RV32-NEXT: fsrm a0
; RV32-NEXT: ret
@@ -45,7 +45,7 @@ define <2 x i64> @llround_v2f16(<2 x half> %x) nounwind {
; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV64-NEXT: vfwcvt.f.f.v v9, v8
; RV64-NEXT: fsrmi a0, 4
-; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64-NEXT: vfwcvt.x.f.v v8, v9
; RV64-NEXT: fsrm a0
; RV64-NEXT: ret
@@ -60,7 +60,7 @@ define <3 x i64> @llround_v3f16(<3 x half> %x) nounwind {
; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV32-NEXT: vfwcvt.f.f.v v10, v8
; RV32-NEXT: fsrmi a0, 4
-; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vfwcvt.x.f.v v8, v10
; RV32-NEXT: fsrm a0
; RV32-NEXT: ret
@@ -70,7 +70,7 @@ define <3 x i64> @llround_v3f16(<3 x half> %x) nounwind {
; RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV64-NEXT: vfwcvt.f.f.v v10, v8
; RV64-NEXT: fsrmi a0, 4
-; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vfwcvt.x.f.v v8, v10
; RV64-NEXT: fsrm a0
; RV64-NEXT: ret
@@ -85,7 +85,7 @@ define <4 x i64> @llround_v4f16(<4 x half> %x) nounwind {
; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV32-NEXT: vfwcvt.f.f.v v10, v8
; RV32-NEXT: fsrmi a0, 4
-; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vfwcvt.x.f.v v8, v10
; RV32-NEXT: fsrm a0
; RV32-NEXT: ret
@@ -95,7 +95,7 @@ define <4 x i64> @llround_v4f16(<4 x half> %x) nounwind {
; RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV64-NEXT: vfwcvt.f.f.v v10, v8
; RV64-NEXT: fsrmi a0, 4
-; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vfwcvt.x.f.v v8, v10
; RV64-NEXT: fsrm a0
; RV64-NEXT: ret
@@ -110,7 +110,7 @@ define <8 x i64> @llround_v8f16(<8 x half> %x) nounwind {
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vfwcvt.f.f.v v12, v8
; RV32-NEXT: fsrmi a0, 4
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vfwcvt.x.f.v v8, v12
; RV32-NEXT: fsrm a0
; RV32-NEXT: ret
@@ -120,7 +120,7 @@ define <8 x i64> @llround_v8f16(<8 x half> %x) nounwind {
; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64-NEXT: vfwcvt.f.f.v v12, v8
; RV64-NEXT: fsrmi a0, 4
-; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64-NEXT: vfwcvt.x.f.v v8, v12
; RV64-NEXT: fsrm a0
; RV64-NEXT: ret
@@ -135,7 +135,7 @@ define <16 x i64> @llround_v16f16(<16 x half> %x) nounwind {
; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV32-NEXT: vfwcvt.f.f.v v16, v8
; RV32-NEXT: fsrmi a0, 4
-; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vfwcvt.x.f.v v8, v16
; RV32-NEXT: fsrm a0
; RV32-NEXT: ret
@@ -145,7 +145,7 @@ define <16 x i64> @llround_v16f16(<16 x half> %x) nounwind {
; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV64-NEXT: vfwcvt.f.f.v v16, v8
; RV64-NEXT: fsrmi a0, 4
-; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV64-NEXT: vfwcvt.x.f.v v8, v16
; RV64-NEXT: fsrm a0
; RV64-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
index a52290072c540..47b903034fbf4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
@@ -255,7 +255,7 @@ define <1 x iXLen> @lrint_v1f16(<1 x half> %x) {
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vfwcvt.f.f.v v9, v8
-; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: vfcvt.x.f.v v8, v9
; RV32-NEXT: ret
;
@@ -263,7 +263,7 @@ define <1 x iXLen> @lrint_v1f16(<1 x half> %x) {
; RV64-i32: # %bb.0:
; RV64-i32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-i32-NEXT: vfwcvt.f.f.v v9, v8
-; RV64-i32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-i32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV64-i32-NEXT: vfcvt.x.f.v v8, v9
; RV64-i32-NEXT: ret
;
@@ -271,7 +271,7 @@ define <1 x iXLen> @lrint_v1f16(<1 x half> %x) {
; RV64-i64: # %bb.0:
; RV64-i64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-i64-NEXT: vfwcvt.f.f.v v9, v8
-; RV64-i64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-i64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV64-i64-NEXT: vfwcvt.x.f.v v8, v9
; RV64-i64-NEXT: ret
%a = call <1 x iXLen> @llvm.lrint.v1iXLen.v1f16(<1 x half> %x)
@@ -284,7 +284,7 @@ define <2 x iXLen> @lrint_v2f16(<2 x half> %x) {
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV32-NEXT: vfwcvt.f.f.v v9, v8
-; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV32-NEXT: vfcvt.x.f.v v8, v9
; RV32-NEXT: ret
;
@@ -292,7 +292,7 @@ define <2 x iXLen> @lrint_v2f16(<2 x half> %x) {
; RV64-i32: # %bb.0:
; RV64-i32-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV64-i32-NEXT: vfwcvt.f.f.v v9, v8
-; RV64-i32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-i32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64-i32-NEXT: vfcvt.x.f.v v8, v9
; RV64-i32-NEXT: ret
;
@@ -300,7 +300,7 @@ define <2 x iXLen> @lrint_v2f16(<2 x half> %x) {
; RV64-i64: # %bb.0:
; RV64-i64-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV64-i64-NEXT: vfwcvt.f.f.v v9, v8
-; RV64-i64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-i64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64-i64-NEXT: vfwcvt.x.f.v v8, v9
; RV64-i64-NEXT: ret
%a = call <2 x iXLen> @llvm.lrint.v2iXLen.v2f16(<2 x half> %x)
@@ -313,7 +313,7 @@ define <3 x iXLen> @lrint_v3f16(<3 x half> %x) {
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV32-NEXT: vfwcvt.f.f.v v9, v8
-; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v8, v9
; RV32-NEXT: ret
;
@@ -321,7 +321,7 @@ define <3 x iXLen> @lrint_v3f16(<3 x half> %x) {
; RV64-i32: # %bb.0:
; RV64-i32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV64-i32-NEXT: vfwcvt.f.f.v v9, v8
-; RV64-i32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-i32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-i32-NEXT: vfcvt.x.f.v v8, v9
; RV64-i32-NEXT: ret
;
@@ -329,7 +329,7 @@ define <3 x iXLen> @lrint_v3f16(<3 x half> %x) {
; RV64-i64: # %bb.0:
; RV64-i64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV64-i64-NEXT: vfwcvt.f.f.v v10, v8
-; RV64-i64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-i64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10
; RV64-i64-NEXT: ret
%a = call <3 x iXLen> @llvm.lrint.v3iXLen.v3f16(<3 x half> %x)
@@ -342,7 +342,7 @@ define <4 x iXLen> @lrint_v4f16(<4 x half> %x) {
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV32-NEXT: vfwcvt.f.f.v v9, v8
-; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v8, v9
; RV32-NEXT: ret
;
@@ -350,7 +350,7 @@ define <4 x iXLen> @lrint_v4f16(<4 x half> %x) {
; RV64-i32: # %bb.0:
; RV64-i32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV64-i32-NEXT: vfwcvt.f.f.v v9, v8
-; RV64-i32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-i32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-i32-NEXT: vfcvt.x.f.v v8, v9
; RV64-i32-NEXT: ret
;
@@ -358,7 +358,7 @@ define <4 x iXLen> @lrint_v4f16(<4 x half> %x) {
; RV64-i64: # %bb.0:
; RV64-i64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV64-i64-NEXT: vfwcvt.f.f.v v10, v8
-; RV64-i64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-i64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10
; RV64-i64-NEXT: ret
%a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4f16(<4 x half> %x)
@@ -371,7 +371,7 @@ define <8 x iXLen> @lrint_v8f16(<8 x half> %x) {
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vfwcvt.f.f.v v10, v8
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vfcvt.x.f.v v8, v10
; RV32-NEXT: ret
;
@@ -379,7 +379,7 @@ define <8 x iXLen> @lrint_v8f16(<8 x half> %x) {
; RV64-i32: # %bb.0:
; RV64-i32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64-i32-NEXT: vfwcvt.f.f.v v10, v8
-; RV64-i32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64-i32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64-i32-NEXT: vfcvt.x.f.v v8, v10
; RV64-i32-NEXT: ret
;
@@ -387,7 +387,7 @@ define <8 x iXLen> @lrint_v8f16(<8 x half> %x) {
; RV64-i64: # %bb.0:
; RV64-i64-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64-i64-NEXT: vfwcvt.f.f.v v12, v8
-; RV64-i64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64-i64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64-i64-NEXT: vfwcvt.x.f.v v8, v12
; RV64-i64-NEXT: ret
%a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8f16(<8 x half> %x)
@@ -400,7 +400,7 @@ define <16 x iXLen> @lrint_v16f16(<16 x half> %x) {
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV32-NEXT: vfwcvt.f.f.v v12, v8
-; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vfcvt.x.f.v v8, v12
; RV32-NEXT: ret
;
@@ -408,7 +408,7 @@ define <16 x iXLen> @lrint_v16f16(<16 x half> %x) {
; RV64-i32: # %bb.0:
; RV64-i32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV64-i32-NEXT: vfwcvt.f.f.v v12, v8
-; RV64-i32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64-i32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV64-i32-NEXT: vfcvt.x.f.v v8, v12
; RV64-i32-NEXT: ret
;
@@ -416,7 +416,7 @@ define <16 x iXLen> @lrint_v16f16(<16 x half> %x) {
; RV64-i64: # %bb.0:
; RV64-i64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV64-i64-NEXT: vfwcvt.f.f.v v16, v8
-; RV64-i64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64-i64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16
; RV64-i64-NEXT: ret
%a = call <16 x iXLen> @llvm.lrint.v16iXLen.v16f16(<16 x half> %x)
@@ -429,7 +429,7 @@ define <1 x iXLen> @lrint_v1bf16(<1 x bfloat> %x) {
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vfwcvtbf16.f.f.v v9, v8
-; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: vfcvt.x.f.v v8, v9
; RV32-NEXT: ret
;
@@ -437,7 +437,7 @@ define <1 x iXLen> @lrint_v1bf16(<1 x bfloat> %x) {
; RV64-i32: # %bb.0:
; RV64-i32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-i32-NEXT: vfwcvtbf16.f.f.v v9, v8
-; RV64-i32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-i32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV64-i32-NEXT: vfcvt.x.f.v v8, v9
; RV64-i32-NEXT: ret
;
@@ -445,7 +445,7 @@ define <1 x iXLen> @lrint_v1bf16(<1 x bfloat> %x) {
; RV64-i64: # %bb.0:
; RV64-i64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-i64-NEXT: vfwcvtbf16.f.f.v v9, v8
-; RV64-i64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-i64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV64-i64-NEXT: vfwcvt.x.f.v v8, v9
; RV64-i64-NEXT: ret
%a = call <1 x iXLen> @llvm.lrint.v1iXLen.v1bf16(<1 x bfloat> %x)
@@ -458,7 +458,7 @@ define <2 x iXLen> @lrint_v2bf16(<2 x bfloat> %x) {
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV32-NEXT: vfwcvtbf16.f.f.v v9, v8
-; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV32-NEXT: vfcvt.x.f.v v8, v9
; RV32-NEXT: ret
;
@@ -466,7 +466,7 @@ define <2 x iXLen> @lrint_v2bf16(<2 x bfloat> %x) {
; RV64-i32: # %bb.0:
; RV64-i32-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV64-i32-NEXT: vfwcvtbf16.f.f.v v9, v8
-; RV64-i32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-i32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64-i32-NEXT: vfcvt.x.f.v v8, v9
; RV64-i32-NEXT: ret
;
@@ -474,7 +474,7 @@ define <2 x iXLen> @lrint_v2bf16(<2 x bfloat> %x) {
; RV64-i64: # %bb.0:
; RV64-i64-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV64-i64-NEXT: vfwcvtbf16.f.f.v v9, v8
-; RV64-i64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-i64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64-i64-NEXT: vfwcvt.x.f.v v8, v9
; RV64-i64-NEXT: ret
%a = call <2 x iXLen> @llvm.lrint.v2iXLen.v2bf16(<2 x bfloat> %x)
@@ -487,7 +487,7 @@ define <3 x iXLen> @lrint_v3bf16(<3 x bfloat> %x) {
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV32-NEXT: vfwcvtbf16.f.f.v v9, v8
-; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v8, v9
; RV32-NEXT: ret
;
@@ -495,7 +495,7 @@ define <3 x iXLen> @lrint_v3bf16(<3 x bfloat> %x) {
; RV64-i32: # %bb.0:
; RV64-i32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV64-i32-NEXT: vfwcvtbf16.f.f.v v9, v8
-; RV64-i32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-i32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-i32-NEXT: vfcvt.x.f.v v8, v9
; RV64-i32-NEXT: ret
;
@@ -503,7 +503,7 @@ define <3 x iXLen> @lrint_v3bf16(<3 x bfloat> %x) {
; RV64-i64: # %bb.0:
; RV64-i64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV64-i64-NEXT: vfwcvtbf16.f.f.v v10, v8
-; RV64-i64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-i64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10
; RV64-i64-NEXT: ret
%a = call <3 x iXLen> @llvm.lrint.v3iXLen.v3bf16(<3 x bfloat> %x)
@@ -516,7 +516,7 @@ define <4 x iXLen> @lrint_v4bf16(<4 x bfloat> %x) {
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV32-NEXT: vfwcvtbf16.f.f.v v9, v8
-; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v8, v9
; RV32-NEXT: ret
;
@@ -524,7 +524,7 @@ define <4 x iXLen> @lrint_v4bf16(<4 x bfloat> %x) {
; RV64-i32: # %bb.0:
; RV64-i32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV64-i32-NEXT: vfwcvtbf16.f.f.v v9, v8
-; RV64-i32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-i32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-i32-NEXT: vfcvt.x.f.v v8, v9
; RV64-i32-NEXT: ret
;
@@ -532,7 +532,7 @@ define <4 x iXLen> @lrint_v4bf16(<4 x bfloat> %x) {
; RV64-i64: # %bb.0:
; RV64-i64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV64-i64-NEXT: vfwcvtbf16.f.f.v v10, v8
-; RV64-i64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-i64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10
; RV64-i64-NEXT: ret
%a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4bf16(<4 x bfloat> %x)
@@ -545,7 +545,7 @@ define <8 x iXLen> @lrint_v8bf16(<8 x bfloat> %x) {
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vfwcvtbf16.f.f.v v10, v8
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vfcvt.x.f.v v8, v10
; RV32-NEXT: ret
;
@@ -553,7 +553,7 @@ define <8 x iXLen> @lrint_v8bf16(<8 x bfloat> %x) {
; RV64-i32: # %bb.0:
; RV64-i32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64-i32-NEXT: vfwcvtbf16.f.f.v v10, v8
-; RV64-i32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64-i32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64-i32-NEXT: vfcvt.x.f.v v8, v10
; RV64-i32-NEXT: ret
;
@@ -561,7 +561,7 @@ define <8 x iXLen> @lrint_v8bf16(<8 x bfloat> %x) {
; RV64-i64: # %bb.0:
; RV64-i64-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64-i64-NEXT: vfwcvtbf16.f.f.v v12, v8
-; RV64-i64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64-i64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64-i64-NEXT: vfwcvt.x.f.v v8, v12
; RV64-i64-NEXT: ret
%a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8bf16(<8 x bfloat> %x)
@@ -574,7 +574,7 @@ define <16 x iXLen> @lrint_v16bf16(<16 x bfloat> %x) {
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV32-NEXT: vfwcvtbf16.f.f.v v12, v8
-; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vfcvt.x.f.v v8, v12
; RV32-NEXT: ret
;
@@ -582,7 +582,7 @@ define <16 x iXLen> @lrint_v16bf16(<16 x bfloat> %x) {
; RV64-i32: # %bb.0:
; RV64-i32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV64-i32-NEXT: vfwcvtbf16.f.f.v v12, v8
-; RV64-i32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64-i32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV64-i32-NEXT: vfcvt.x.f.v v8, v12
; RV64-i32-NEXT: ret
;
@@ -590,7 +590,7 @@ define <16 x iXLen> @lrint_v16bf16(<16 x bfloat> %x) {
; RV64-i64: # %bb.0:
; RV64-i64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV64-i64-NEXT: vfwcvtbf16.f.f.v v16, v8
-; RV64-i64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64-i64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16
; RV64-i64-NEXT: ret
%a = call <16 x iXLen> @llvm.lrint.v16iXLen.v16bf16(<16 x bfloat> %x)
@@ -625,9 +625,9 @@ define <32 x iXLen> @lrint_v32bf16(<32 x bfloat> %x) {
; RV64-i64-NEXT: vslidedown.vi v20, v8, 16
; RV64-i64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16
-; RV64-i64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64-i64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV64-i64-NEXT: vfwcvtbf16.f.f.v v24, v20
-; RV64-i64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64-i64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV64-i64-NEXT: vfwcvt.x.f.v v16, v24
; RV64-i64-NEXT: ret
%a = call <32 x iXLen> @llvm.lrint.v32iXLen.v32bf16(<32 x bfloat> %x)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lround.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lround.ll
index 64b3b7912ed32..21ea8fbf20097 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lround.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lround.ll
@@ -12,7 +12,7 @@ define <1 x iXLen> @lround_v1f16(<1 x half> %x) nounwind {
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vfwcvt.f.f.v v9, v8
; RV32-NEXT: fsrmi a0, 4
-; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: vfcvt.x.f.v v8, v9
; RV32-NEXT: fsrm a0
; RV32-NEXT: ret
@@ -22,7 +22,7 @@ define <1 x iXLen> @lround_v1f16(<1 x half> %x) nounwind {
; RV64-i32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-i32-NEXT: vfwcvt.f.f.v v9, v8
; RV64-i32-NEXT: fsrmi a0, 4
-; RV64-i32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-i32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV64-i32-NEXT: vfcvt.x.f.v v8, v9
; RV64-i32-NEXT: fsrm a0
; RV64-i32-NEXT: ret
@@ -32,7 +32,7 @@ define <1 x iXLen> @lround_v1f16(<1 x half> %x) nounwind {
; RV64-i64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-i64-NEXT: vfwcvt.f.f.v v9, v8
; RV64-i64-NEXT: fsrmi a0, 4
-; RV64-i64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-i64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV64-i64-NEXT: vfwcvt.x.f.v v8, v9
; RV64-i64-NEXT: fsrm a0
; RV64-i64-NEXT: ret
@@ -47,7 +47,7 @@ define <2 x iXLen> @lround_v2f16(<2 x half> %x) nounwind {
; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV32-NEXT: vfwcvt.f.f.v v9, v8
; RV32-NEXT: fsrmi a0, 4
-; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV32-NEXT: vfcvt.x.f.v v8, v9
; RV32-NEXT: fsrm a0
; RV32-NEXT: ret
@@ -57,7 +57,7 @@ define <2 x iXLen> @lround_v2f16(<2 x half> %x) nounwind {
; RV64-i32-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV64-i32-NEXT: vfwcvt.f.f.v v9, v8
; RV64-i32-NEXT: fsrmi a0, 4
-; RV64-i32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-i32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64-i32-NEXT: vfcvt.x.f.v v8, v9
; RV64-i32-NEXT: fsrm a0
; RV64-i32-NEXT: ret
@@ -67,7 +67,7 @@ define <2 x iXLen> @lround_v2f16(<2 x half> %x) nounwind {
; RV64-i64-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV64-i64-NEXT: vfwcvt.f.f.v v9, v8
; RV64-i64-NEXT: fsrmi a0, 4
-; RV64-i64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-i64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64-i64-NEXT: vfwcvt.x.f.v v8, v9
; RV64-i64-NEXT: fsrm a0
; RV64-i64-NEXT: ret
@@ -82,7 +82,7 @@ define <3 x iXLen> @lround_v3f16(<3 x half> %x) nounwind {
; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV32-NEXT: vfwcvt.f.f.v v9, v8
; RV32-NEXT: fsrmi a0, 4
-; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v8, v9
; RV32-NEXT: fsrm a0
; RV32-NEXT: ret
@@ -92,7 +92,7 @@ define <3 x iXLen> @lround_v3f16(<3 x half> %x) nounwind {
; RV64-i32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV64-i32-NEXT: vfwcvt.f.f.v v9, v8
; RV64-i32-NEXT: fsrmi a0, 4
-; RV64-i32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-i32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-i32-NEXT: vfcvt.x.f.v v8, v9
; RV64-i32-NEXT: fsrm a0
; RV64-i32-NEXT: ret
@@ -102,7 +102,7 @@ define <3 x iXLen> @lround_v3f16(<3 x half> %x) nounwind {
; RV64-i64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV64-i64-NEXT: vfwcvt.f.f.v v10, v8
; RV64-i64-NEXT: fsrmi a0, 4
-; RV64-i64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-i64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10
; RV64-i64-NEXT: fsrm a0
; RV64-i64-NEXT: ret
@@ -117,7 +117,7 @@ define <4 x iXLen> @lround_v4f16(<4 x half> %x) nounwind {
; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV32-NEXT: vfwcvt.f.f.v v9, v8
; RV32-NEXT: fsrmi a0, 4
-; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v8, v9
; RV32-NEXT: fsrm a0
; RV32-NEXT: ret
@@ -127,7 +127,7 @@ define <4 x iXLen> @lround_v4f16(<4 x half> %x) nounwind {
; RV64-i32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV64-i32-NEXT: vfwcvt.f.f.v v9, v8
; RV64-i32-NEXT: fsrmi a0, 4
-; RV64-i32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-i32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-i32-NEXT: vfcvt.x.f.v v8, v9
; RV64-i32-NEXT: fsrm a0
; RV64-i32-NEXT: ret
@@ -137,7 +137,7 @@ define <4 x iXLen> @lround_v4f16(<4 x half> %x) nounwind {
; RV64-i64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV64-i64-NEXT: vfwcvt.f.f.v v10, v8
; RV64-i64-NEXT: fsrmi a0, 4
-; RV64-i64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-i64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10
; RV64-i64-NEXT: fsrm a0
; RV64-i64-NEXT: ret
@@ -152,7 +152,7 @@ define <8 x iXLen> @lround_v8f16(<8 x half> %x) nounwind {
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vfwcvt.f.f.v v10, v8
; RV32-NEXT: fsrmi a0, 4
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vfcvt.x.f.v v8, v10
; RV32-NEXT: fsrm a0
; RV32-NEXT: ret
@@ -162,7 +162,7 @@ define <8 x iXLen> @lround_v8f16(<8 x half> %x) nounwind {
; RV64-i32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64-i32-NEXT: vfwcvt.f.f.v v10, v8
; RV64-i32-NEXT: fsrmi a0, 4
-; RV64-i32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64-i32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64-i32-NEXT: vfcvt.x.f.v v8, v10
; RV64-i32-NEXT: fsrm a0
; RV64-i32-NEXT: ret
@@ -172,7 +172,7 @@ define <8 x iXLen> @lround_v8f16(<8 x half> %x) nounwind {
; RV64-i64-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64-i64-NEXT: vfwcvt.f.f.v v12, v8
; RV64-i64-NEXT: fsrmi a0, 4
-; RV64-i64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64-i64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64-i64-NEXT: vfwcvt.x.f.v v8, v12
; RV64-i64-NEXT: fsrm a0
; RV64-i64-NEXT: ret
@@ -187,7 +187,7 @@ define <16 x iXLen> @lround_v16f16(<16 x half> %x) nounwind {
; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV32-NEXT: vfwcvt.f.f.v v12, v8
; RV32-NEXT: fsrmi a0, 4
-; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vfcvt.x.f.v v8, v12
; RV32-NEXT: fsrm a0
; RV32-NEXT: ret
@@ -197,7 +197,7 @@ define <16 x iXLen> @lround_v16f16(<16 x half> %x) nounwind {
; RV64-i32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV64-i32-NEXT: vfwcvt.f.f.v v12, v8
; RV64-i32-NEXT: fsrmi a0, 4
-; RV64-i32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64-i32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV64-i32-NEXT: vfcvt.x.f.v v8, v12
; RV64-i32-NEXT: fsrm a0
; RV64-i32-NEXT: ret
@@ -207,7 +207,7 @@ define <16 x iXLen> @lround_v16f16(<16 x half> %x) nounwind {
; RV64-i64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV64-i64-NEXT: vfwcvt.f.f.v v16, v8
; RV64-i64-NEXT: fsrmi a0, 4
-; RV64-i64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64-i64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16
; RV64-i64-NEXT: fsrm a0
; RV64-i64-NEXT: ret
@@ -552,9 +552,9 @@ define <32 x iXLen> @lround_v32bf16(<32 x bfloat> %x) {
; RV64-i64-NEXT: vslidedown.vi v20, v8, 16
; RV64-i64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16
-; RV64-i64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64-i64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV64-i64-NEXT: vfwcvtbf16.f.f.v v24, v20
-; RV64-i64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64-i64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV64-i64-NEXT: vfwcvt.x.f.v v16, v24
; RV64-i64-NEXT: fsrm a0
; RV64-i64-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
index 8027b911a0933..33f51dfc80b59 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
@@ -489,7 +489,7 @@ define <64 x i1> @buildvec_mask_v64i1() {
; RV32-NEXT: vmv.v.x v0, a0
; RV32-NEXT: lui a0, 748384
; RV32-NEXT: addi a0, a0, 1776
-; RV32-NEXT: vsetvli zero, zero, e32, mf2, tu, ma
+; RV32-NEXT: vsetivli zero, 2, e32, mf2, tu, ma
; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: ret
;
@@ -509,7 +509,7 @@ define <64 x i1> @buildvec_mask_v64i1() {
; ZVE32F-NEXT: vmv.v.x v0, a0
; ZVE32F-NEXT: lui a0, 748384
; ZVE32F-NEXT: addi a0, a0, 1776
-; ZVE32F-NEXT: vsetvli zero, zero, e32, m1, tu, ma
+; ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; ZVE32F-NEXT: vmv.s.x v0, a0
; ZVE32F-NEXT: ret
ret <64 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1>
@@ -532,7 +532,7 @@ define <128 x i1> @buildvec_mask_v128i1() {
; RV64-NEXT: ld a1, %lo(.LCPI20_1)(a1)
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vmv.v.x v0, a0
-; RV64-NEXT: vsetvli zero, zero, e64, m1, tu, ma
+; RV64-NEXT: vsetivli zero, 2, e64, m1, tu, ma
; RV64-NEXT: vmv.s.x v0, a1
; RV64-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
index 7e6f2c76e5881..fed7739f85176 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
@@ -92,15 +92,14 @@ define <2 x i8> @mgather_v2i8(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i8> %passthru)
; RV64ZVE32F-NEXT: ret
; RV64ZVE32F-NEXT: .LBB1_3: # %cond.load
; RV64ZVE32F-NEXT: lbu a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: andi a2, a2, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB1_2
; RV64ZVE32F-NEXT: .LBB1_4: # %cond.load1
; RV64ZVE32F-NEXT: lbu a0, 0(a1)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: ret
%v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru)
@@ -112,7 +111,7 @@ define <2 x i16> @mgather_v2i8_sextload_v2i16(<2 x ptr> %ptrs, <2 x i1> %m, <2 x
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32V-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; RV32V-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV32V-NEXT: vsext.vf2 v8, v9
; RV32V-NEXT: ret
;
@@ -120,7 +119,7 @@ define <2 x i16> @mgather_v2i8_sextload_v2i16(<2 x ptr> %ptrs, <2 x i1> %m, <2 x
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t
-; RV64V-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; RV64V-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV64V-NEXT: vsext.vf2 v8, v9
; RV64V-NEXT: ret
;
@@ -128,7 +127,7 @@ define <2 x i16> @mgather_v2i8_sextload_v2i16(<2 x ptr> %ptrs, <2 x i1> %m, <2 x
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV32ZVE32F-NEXT: vsext.vf2 v8, v9
; RV32ZVE32F-NEXT: ret
;
@@ -140,16 +139,15 @@ define <2 x i16> @mgather_v2i8_sextload_v2i16(<2 x ptr> %ptrs, <2 x i1> %m, <2 x
; RV64ZVE32F-NEXT: beqz a3, .LBB2_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: lbu a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: .LBB2_2: # %else
; RV64ZVE32F-NEXT: andi a2, a2, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB2_4
; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
; RV64ZVE32F-NEXT: lbu a0, 0(a1)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: .LBB2_4: # %else2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
@@ -166,7 +164,7 @@ define <2 x i16> @mgather_v2i8_zextload_v2i16(<2 x ptr> %ptrs, <2 x i1> %m, <2 x
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32V-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; RV32V-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV32V-NEXT: vzext.vf2 v8, v9
; RV32V-NEXT: ret
;
@@ -174,7 +172,7 @@ define <2 x i16> @mgather_v2i8_zextload_v2i16(<2 x ptr> %ptrs, <2 x i1> %m, <2 x
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t
-; RV64V-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; RV64V-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV64V-NEXT: vzext.vf2 v8, v9
; RV64V-NEXT: ret
;
@@ -182,7 +180,7 @@ define <2 x i16> @mgather_v2i8_zextload_v2i16(<2 x ptr> %ptrs, <2 x i1> %m, <2 x
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV32ZVE32F-NEXT: vzext.vf2 v8, v9
; RV32ZVE32F-NEXT: ret
;
@@ -194,16 +192,15 @@ define <2 x i16> @mgather_v2i8_zextload_v2i16(<2 x ptr> %ptrs, <2 x i1> %m, <2 x
; RV64ZVE32F-NEXT: beqz a3, .LBB3_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: lbu a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: .LBB3_2: # %else
; RV64ZVE32F-NEXT: andi a2, a2, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB3_4
; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
; RV64ZVE32F-NEXT: lbu a0, 0(a1)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: .LBB3_4: # %else2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
@@ -220,7 +217,7 @@ define <2 x i32> @mgather_v2i8_sextload_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, <2 x
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV32V-NEXT: vsext.vf4 v8, v9
; RV32V-NEXT: ret
;
@@ -228,7 +225,7 @@ define <2 x i32> @mgather_v2i8_sextload_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, <2 x
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t
-; RV64V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64V-NEXT: vsext.vf4 v8, v9
; RV64V-NEXT: ret
;
@@ -236,7 +233,7 @@ define <2 x i32> @mgather_v2i8_sextload_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, <2 x
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV32ZVE32F-NEXT: vsext.vf4 v8, v9
; RV32ZVE32F-NEXT: ret
;
@@ -248,16 +245,15 @@ define <2 x i32> @mgather_v2i8_sextload_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, <2 x
; RV64ZVE32F-NEXT: beqz a3, .LBB4_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: lbu a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: .LBB4_2: # %else
; RV64ZVE32F-NEXT: andi a2, a2, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB4_4
; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
; RV64ZVE32F-NEXT: lbu a0, 0(a1)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: .LBB4_4: # %else2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
@@ -274,7 +270,7 @@ define <2 x i32> @mgather_v2i8_zextload_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, <2 x
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV32V-NEXT: vzext.vf4 v8, v9
; RV32V-NEXT: ret
;
@@ -282,7 +278,7 @@ define <2 x i32> @mgather_v2i8_zextload_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, <2 x
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t
-; RV64V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64V-NEXT: vzext.vf4 v8, v9
; RV64V-NEXT: ret
;
@@ -290,7 +286,7 @@ define <2 x i32> @mgather_v2i8_zextload_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, <2 x
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV32ZVE32F-NEXT: vzext.vf4 v8, v9
; RV32ZVE32F-NEXT: ret
;
@@ -302,16 +298,15 @@ define <2 x i32> @mgather_v2i8_zextload_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, <2 x
; RV64ZVE32F-NEXT: beqz a3, .LBB5_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: lbu a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: .LBB5_2: # %else
; RV64ZVE32F-NEXT: andi a2, a2, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB5_4
; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
; RV64ZVE32F-NEXT: lbu a0, 0(a1)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: .LBB5_4: # %else2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
@@ -328,7 +323,7 @@ define <2 x i64> @mgather_v2i8_sextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2 x
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32V-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32V-NEXT: vsext.vf8 v8, v9
; RV32V-NEXT: ret
;
@@ -336,7 +331,7 @@ define <2 x i64> @mgather_v2i8_sextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2 x
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t
-; RV64V-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64V-NEXT: vsext.vf8 v8, v9
; RV64V-NEXT: ret
;
@@ -363,16 +358,15 @@ define <2 x i64> @mgather_v2i8_sextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2 x
; RV64ZVE32F-NEXT: beqz a3, .LBB6_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: lbu a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: .LBB6_2: # %else
; RV64ZVE32F-NEXT: andi a2, a2, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB6_4
; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
; RV64ZVE32F-NEXT: lbu a0, 0(a1)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: .LBB6_4: # %else2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
@@ -390,7 +384,7 @@ define <2 x i64> @mgather_v2i8_zextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2 x
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32V-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32V-NEXT: vzext.vf8 v8, v9
; RV32V-NEXT: ret
;
@@ -398,7 +392,7 @@ define <2 x i64> @mgather_v2i8_zextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2 x
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t
-; RV64V-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64V-NEXT: vzext.vf8 v8, v9
; RV64V-NEXT: ret
;
@@ -425,16 +419,15 @@ define <2 x i64> @mgather_v2i8_zextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2 x
; RV64ZVE32F-NEXT: beqz a3, .LBB7_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: lbu a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: .LBB7_2: # %else
; RV64ZVE32F-NEXT: andi a2, a2, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB7_4
; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
; RV64ZVE32F-NEXT: lbu a0, 0(a1)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: .LBB7_4: # %else2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
@@ -486,16 +479,15 @@ define <4 x i8> @mgather_v4i8(<4 x ptr> %ptrs, <4 x i1> %m, <4 x i8> %passthru)
; RV64ZVE32F-NEXT: .LBB8_5: # %cond.load
; RV64ZVE32F-NEXT: ld a2, 0(a0)
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v8, a2
; RV64ZVE32F-NEXT: andi a2, a1, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB8_2
; RV64ZVE32F-NEXT: .LBB8_6: # %cond.load1
; RV64ZVE32F-NEXT: ld a2, 8(a0)
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: andi a2, a1, 4
; RV64ZVE32F-NEXT: beqz a2, .LBB8_3
@@ -622,16 +614,15 @@ define <8 x i8> @mgather_v8i8(<8 x ptr> %ptrs, <8 x i1> %m, <8 x i8> %passthru)
; RV64ZVE32F-NEXT: .LBB11_9: # %cond.load
; RV64ZVE32F-NEXT: ld a2, 0(a0)
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v8, a2
; RV64ZVE32F-NEXT: andi a2, a1, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB11_2
; RV64ZVE32F-NEXT: .LBB11_10: # %cond.load1
; RV64ZVE32F-NEXT: ld a2, 8(a0)
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: andi a2, a1, 4
; RV64ZVE32F-NEXT: beqz a2, .LBB11_3
@@ -691,7 +682,7 @@ define <8 x i8> @mgather_baseidx_v8i8(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vsext.vf4 v10, v8
-; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
+; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
@@ -700,7 +691,7 @@ define <8 x i8> @mgather_baseidx_v8i8(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf8 v12, v8
-; RV64V-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64V-NEXT: vluxei64.v v9, (a0), v12, v0.t
; RV64V-NEXT: vmv1r.v v8, v9
; RV64V-NEXT: ret
@@ -715,7 +706,7 @@ define <8 x i8> @mgather_baseidx_v8i8(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: .LBB12_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
@@ -885,15 +876,14 @@ define <2 x i16> @mgather_v2i16(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i16> %passthr
; RV64ZVE32F-NEXT: ret
; RV64ZVE32F-NEXT: .LBB14_3: # %cond.load
; RV64ZVE32F-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: andi a2, a2, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB14_2
; RV64ZVE32F-NEXT: .LBB14_4: # %cond.load1
; RV64ZVE32F-NEXT: lh a0, 0(a1)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: ret
%v = call <2 x i16> @llvm.masked.gather.v2i16.v2p0(<2 x ptr> %ptrs, i32 2, <2 x i1> %m, <2 x i16> %passthru)
@@ -905,7 +895,7 @@ define <2 x i32> @mgather_v2i16_sextload_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, <2
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV32V-NEXT: vsext.vf2 v8, v9
; RV32V-NEXT: ret
;
@@ -913,7 +903,7 @@ define <2 x i32> @mgather_v2i16_sextload_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, <2
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t
-; RV64V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64V-NEXT: vsext.vf2 v8, v9
; RV64V-NEXT: ret
;
@@ -921,7 +911,7 @@ define <2 x i32> @mgather_v2i16_sextload_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, <2
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV32ZVE32F-NEXT: vsext.vf2 v8, v9
; RV32ZVE32F-NEXT: ret
;
@@ -933,16 +923,15 @@ define <2 x i32> @mgather_v2i16_sextload_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, <2
; RV64ZVE32F-NEXT: beqz a3, .LBB15_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: .LBB15_2: # %else
; RV64ZVE32F-NEXT: andi a2, a2, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB15_4
; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
; RV64ZVE32F-NEXT: lh a0, 0(a1)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: .LBB15_4: # %else2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
@@ -959,7 +948,7 @@ define <2 x i32> @mgather_v2i16_zextload_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, <2
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV32V-NEXT: vzext.vf2 v8, v9
; RV32V-NEXT: ret
;
@@ -967,7 +956,7 @@ define <2 x i32> @mgather_v2i16_zextload_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, <2
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t
-; RV64V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64V-NEXT: vzext.vf2 v8, v9
; RV64V-NEXT: ret
;
@@ -975,7 +964,7 @@ define <2 x i32> @mgather_v2i16_zextload_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, <2
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV32ZVE32F-NEXT: vzext.vf2 v8, v9
; RV32ZVE32F-NEXT: ret
;
@@ -987,16 +976,15 @@ define <2 x i32> @mgather_v2i16_zextload_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, <2
; RV64ZVE32F-NEXT: beqz a3, .LBB16_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: .LBB16_2: # %else
; RV64ZVE32F-NEXT: andi a2, a2, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB16_4
; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
; RV64ZVE32F-NEXT: lh a0, 0(a1)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: .LBB16_4: # %else2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
@@ -1013,7 +1001,7 @@ define <2 x i64> @mgather_v2i16_sextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32V-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32V-NEXT: vsext.vf4 v8, v9
; RV32V-NEXT: ret
;
@@ -1021,7 +1009,7 @@ define <2 x i64> @mgather_v2i16_sextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t
-; RV64V-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64V-NEXT: vsext.vf4 v8, v9
; RV64V-NEXT: ret
;
@@ -1048,16 +1036,15 @@ define <2 x i64> @mgather_v2i16_sextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2
; RV64ZVE32F-NEXT: beqz a3, .LBB17_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: .LBB17_2: # %else
; RV64ZVE32F-NEXT: andi a2, a2, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB17_4
; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
; RV64ZVE32F-NEXT: lh a0, 0(a1)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: .LBB17_4: # %else2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
@@ -1075,7 +1062,7 @@ define <2 x i64> @mgather_v2i16_zextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32V-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32V-NEXT: vzext.vf4 v8, v9
; RV32V-NEXT: ret
;
@@ -1083,7 +1070,7 @@ define <2 x i64> @mgather_v2i16_zextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t
-; RV64V-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64V-NEXT: vzext.vf4 v8, v9
; RV64V-NEXT: ret
;
@@ -1112,16 +1099,15 @@ define <2 x i64> @mgather_v2i16_zextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2
; RV64ZVE32F-NEXT: beqz a3, .LBB18_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: .LBB18_2: # %else
; RV64ZVE32F-NEXT: andi a2, a2, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB18_4
; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
; RV64ZVE32F-NEXT: lh a0, 0(a1)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: .LBB18_4: # %else2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
@@ -1175,16 +1161,15 @@ define <4 x i16> @mgather_v4i16(<4 x ptr> %ptrs, <4 x i1> %m, <4 x i16> %passthr
; RV64ZVE32F-NEXT: .LBB19_5: # %cond.load
; RV64ZVE32F-NEXT: ld a2, 0(a0)
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v8, a2
; RV64ZVE32F-NEXT: andi a2, a1, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB19_2
; RV64ZVE32F-NEXT: .LBB19_6: # %cond.load1
; RV64ZVE32F-NEXT: ld a2, 8(a0)
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: andi a2, a1, 4
; RV64ZVE32F-NEXT: beqz a2, .LBB19_3
@@ -1311,16 +1296,15 @@ define <8 x i16> @mgather_v8i16(<8 x ptr> %ptrs, <8 x i1> %m, <8 x i16> %passthr
; RV64ZVE32F-NEXT: .LBB22_9: # %cond.load
; RV64ZVE32F-NEXT: ld a2, 0(a0)
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v8, a2
; RV64ZVE32F-NEXT: andi a2, a1, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB22_2
; RV64ZVE32F-NEXT: .LBB22_10: # %cond.load1
; RV64ZVE32F-NEXT: ld a2, 8(a0)
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: andi a2, a1, 4
; RV64ZVE32F-NEXT: beqz a2, .LBB22_3
@@ -1381,7 +1365,7 @@ define <8 x i16> @mgather_baseidx_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vsext.vf4 v10, v8
; RV32-NEXT: vadd.vv v10, v10, v10
-; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t
; RV32-NEXT: vmv.v.v v8, v9
; RV32-NEXT: ret
@@ -1391,7 +1375,7 @@ define <8 x i16> @mgather_baseidx_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf8 v12, v8
; RV64V-NEXT: vadd.vv v12, v12, v12
-; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV64V-NEXT: vluxei64.v v9, (a0), v12, v0.t
; RV64V-NEXT: vmv.v.v v8, v9
; RV64V-NEXT: ret
@@ -1407,7 +1391,7 @@ define <8 x i16> @mgather_baseidx_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: .LBB23_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
@@ -1419,9 +1403,8 @@ define <8 x i16> @mgather_baseidx_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 1
; RV64ZVE32F-NEXT: .LBB23_4: # %else2
; RV64ZVE32F-NEXT: andi a2, a1, 4
@@ -1433,9 +1416,8 @@ define <8 x i16> @mgather_baseidx_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v11, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v11, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 2
; RV64ZVE32F-NEXT: .LBB23_6: # %else5
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -1447,9 +1429,8 @@ define <8 x i16> @mgather_baseidx_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
; RV64ZVE32F-NEXT: .LBB23_8: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 16
@@ -1461,9 +1442,8 @@ define <8 x i16> @mgather_baseidx_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 4
; RV64ZVE32F-NEXT: .LBB23_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
@@ -1475,9 +1455,8 @@ define <8 x i16> @mgather_baseidx_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 5
; RV64ZVE32F-NEXT: .LBB23_12: # %else14
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -1489,9 +1468,8 @@ define <8 x i16> @mgather_baseidx_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 6
; RV64ZVE32F-NEXT: .LBB23_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
@@ -1503,9 +1481,8 @@ define <8 x i16> @mgather_baseidx_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: slli a1, a1, 1
; RV64ZVE32F-NEXT: add a0, a0, a1
; RV64ZVE32F-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7
; RV64ZVE32F-NEXT: .LBB23_16: # %else20
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
@@ -1522,7 +1499,7 @@ define <8 x i16> @mgather_baseidx_sext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vsext.vf4 v10, v8
; RV32-NEXT: vadd.vv v10, v10, v10
-; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t
; RV32-NEXT: vmv.v.v v8, v9
; RV32-NEXT: ret
@@ -1532,7 +1509,7 @@ define <8 x i16> @mgather_baseidx_sext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf8 v12, v8
; RV64V-NEXT: vadd.vv v12, v12, v12
-; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV64V-NEXT: vluxei64.v v9, (a0), v12, v0.t
; RV64V-NEXT: vmv.v.v v8, v9
; RV64V-NEXT: ret
@@ -1548,7 +1525,7 @@ define <8 x i16> @mgather_baseidx_sext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: .LBB24_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
@@ -1560,9 +1537,8 @@ define <8 x i16> @mgather_baseidx_sext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 1
; RV64ZVE32F-NEXT: .LBB24_4: # %else2
; RV64ZVE32F-NEXT: andi a2, a1, 4
@@ -1574,9 +1550,8 @@ define <8 x i16> @mgather_baseidx_sext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v11, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v11, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 2
; RV64ZVE32F-NEXT: .LBB24_6: # %else5
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -1588,9 +1563,8 @@ define <8 x i16> @mgather_baseidx_sext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
; RV64ZVE32F-NEXT: .LBB24_8: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 16
@@ -1602,9 +1576,8 @@ define <8 x i16> @mgather_baseidx_sext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 4
; RV64ZVE32F-NEXT: .LBB24_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
@@ -1616,9 +1589,8 @@ define <8 x i16> @mgather_baseidx_sext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 5
; RV64ZVE32F-NEXT: .LBB24_12: # %else14
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -1630,9 +1602,8 @@ define <8 x i16> @mgather_baseidx_sext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 6
; RV64ZVE32F-NEXT: .LBB24_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
@@ -1644,9 +1615,8 @@ define <8 x i16> @mgather_baseidx_sext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a1, a1, 1
; RV64ZVE32F-NEXT: add a0, a0, a1
; RV64ZVE32F-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7
; RV64ZVE32F-NEXT: .LBB24_16: # %else20
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
@@ -1663,7 +1633,7 @@ define <8 x i16> @mgather_baseidx_zext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vwaddu.vv v10, v8, v8
-; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV32-NEXT: vluxei16.v v9, (a0), v10, v0.t
; RV32-NEXT: vmv.v.v v8, v9
; RV32-NEXT: ret
@@ -1672,7 +1642,7 @@ define <8 x i16> @mgather_baseidx_zext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64V-NEXT: vwaddu.vv v10, v8, v8
-; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV64V-NEXT: vluxei16.v v9, (a0), v10, v0.t
; RV64V-NEXT: vmv.v.v v8, v9
; RV64V-NEXT: ret
@@ -1689,7 +1659,7 @@ define <8 x i16> @mgather_baseidx_zext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: .LBB25_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
@@ -1702,9 +1672,8 @@ define <8 x i16> @mgather_baseidx_zext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 1
; RV64ZVE32F-NEXT: .LBB25_4: # %else2
; RV64ZVE32F-NEXT: andi a2, a1, 4
@@ -1717,9 +1686,8 @@ define <8 x i16> @mgather_baseidx_zext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v11, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v11, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 2
; RV64ZVE32F-NEXT: .LBB25_6: # %else5
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -1732,9 +1700,8 @@ define <8 x i16> @mgather_baseidx_zext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
; RV64ZVE32F-NEXT: .LBB25_8: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 16
@@ -1747,9 +1714,8 @@ define <8 x i16> @mgather_baseidx_zext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 4
; RV64ZVE32F-NEXT: .LBB25_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
@@ -1762,9 +1728,8 @@ define <8 x i16> @mgather_baseidx_zext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 5
; RV64ZVE32F-NEXT: .LBB25_12: # %else14
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -1777,9 +1742,8 @@ define <8 x i16> @mgather_baseidx_zext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 6
; RV64ZVE32F-NEXT: .LBB25_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
@@ -1792,9 +1756,8 @@ define <8 x i16> @mgather_baseidx_zext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a1, a1, 1
; RV64ZVE32F-NEXT: add a0, a0, a1
; RV64ZVE32F-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7
; RV64ZVE32F-NEXT: .LBB25_16: # %else20
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
@@ -1820,7 +1783,7 @@ define <8 x i16> @mgather_baseidx_v8i16(ptr %base, <8 x i16> %idxs, <8 x i1> %m,
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf4 v12, v8
; RV64V-NEXT: vadd.vv v12, v12, v12
-; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV64V-NEXT: vluxei64.v v9, (a0), v12, v0.t
; RV64V-NEXT: vmv.v.v v8, v9
; RV64V-NEXT: ret
@@ -1832,7 +1795,7 @@ define <8 x i16> @mgather_baseidx_v8i16(ptr %base, <8 x i16> %idxs, <8 x i1> %m,
; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB26_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -2013,15 +1976,14 @@ define <2 x i32> @mgather_v2i32(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i32> %passthr
; RV64ZVE32F-NEXT: ret
; RV64ZVE32F-NEXT: .LBB28_3: # %cond.load
; RV64ZVE32F-NEXT: lw a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: andi a2, a2, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB28_2
; RV64ZVE32F-NEXT: .LBB28_4: # %cond.load1
; RV64ZVE32F-NEXT: lw a0, 0(a1)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: ret
%v = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %m, <2 x i32> %passthru)
@@ -2033,7 +1995,7 @@ define <2 x i64> @mgather_v2i32_sextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32V-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32V-NEXT: vsext.vf2 v8, v9
; RV32V-NEXT: ret
;
@@ -2041,7 +2003,7 @@ define <2 x i64> @mgather_v2i32_sextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t
-; RV64V-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64V-NEXT: vsext.vf2 v8, v9
; RV64V-NEXT: ret
;
@@ -2068,16 +2030,15 @@ define <2 x i64> @mgather_v2i32_sextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2
; RV64ZVE32F-NEXT: beqz a3, .LBB29_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: lw a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: .LBB29_2: # %else
; RV64ZVE32F-NEXT: andi a2, a2, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB29_4
; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
; RV64ZVE32F-NEXT: lw a0, 0(a1)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: .LBB29_4: # %else2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
@@ -2095,7 +2056,7 @@ define <2 x i64> @mgather_v2i32_zextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32V-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32V-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32V-NEXT: vzext.vf2 v8, v9
; RV32V-NEXT: ret
;
@@ -2103,7 +2064,7 @@ define <2 x i64> @mgather_v2i32_zextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64V-NEXT: vluxei64.v v9, (zero), v8, v0.t
-; RV64V-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64V-NEXT: vzext.vf2 v8, v9
; RV64V-NEXT: ret
;
@@ -2128,16 +2089,15 @@ define <2 x i64> @mgather_v2i32_zextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2
; RV64ZVE32F-NEXT: beqz a3, .LBB30_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: lw a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: .LBB30_2: # %else
; RV64ZVE32F-NEXT: andi a2, a2, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB30_4
; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
; RV64ZVE32F-NEXT: lw a0, 0(a1)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: .LBB30_4: # %else2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
@@ -2191,16 +2151,15 @@ define <4 x i32> @mgather_v4i32(<4 x ptr> %ptrs, <4 x i1> %m, <4 x i32> %passthr
; RV64ZVE32F-NEXT: .LBB31_5: # %cond.load
; RV64ZVE32F-NEXT: ld a2, 0(a0)
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v8, a2
; RV64ZVE32F-NEXT: andi a2, a1, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB31_2
; RV64ZVE32F-NEXT: .LBB31_6: # %cond.load1
; RV64ZVE32F-NEXT: ld a2, 8(a0)
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: andi a2, a1, 4
; RV64ZVE32F-NEXT: beqz a2, .LBB31_3
@@ -2326,16 +2285,15 @@ define <8 x i32> @mgather_v8i32(<8 x ptr> %ptrs, <8 x i1> %m, <8 x i32> %passthr
; RV64ZVE32F-NEXT: .LBB34_9: # %cond.load
; RV64ZVE32F-NEXT: ld a2, 0(a0)
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v8, a2
; RV64ZVE32F-NEXT: andi a2, a1, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB34_2
; RV64ZVE32F-NEXT: .LBB34_10: # %cond.load1
; RV64ZVE32F-NEXT: ld a2, 8(a0)
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v8, v10, 1
; RV64ZVE32F-NEXT: andi a2, a1, 4
; RV64ZVE32F-NEXT: beqz a2, .LBB34_3
@@ -2405,7 +2363,7 @@ define <8 x i32> @mgather_baseidx_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf8 v12, v8
; RV64V-NEXT: vsll.vi v12, v12, 2
-; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV64V-NEXT: vluxei64.v v10, (a0), v12, v0.t
; RV64V-NEXT: vmv.v.v v8, v10
; RV64V-NEXT: ret
@@ -2421,7 +2379,7 @@ define <8 x i32> @mgather_baseidx_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: .LBB35_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
@@ -2433,9 +2391,8 @@ define <8 x i32> @mgather_baseidx_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 1
; RV64ZVE32F-NEXT: .LBB35_4: # %else2
; RV64ZVE32F-NEXT: andi a2, a1, 4
@@ -2447,9 +2404,8 @@ define <8 x i32> @mgather_baseidx_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
; RV64ZVE32F-NEXT: .LBB35_6: # %else5
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -2461,9 +2417,8 @@ define <8 x i32> @mgather_baseidx_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
; RV64ZVE32F-NEXT: .LBB35_8: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 16
@@ -2475,9 +2430,8 @@ define <8 x i32> @mgather_baseidx_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
; RV64ZVE32F-NEXT: .LBB35_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
@@ -2489,9 +2443,8 @@ define <8 x i32> @mgather_baseidx_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
; RV64ZVE32F-NEXT: .LBB35_12: # %else14
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -2503,9 +2456,8 @@ define <8 x i32> @mgather_baseidx_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 6
; RV64ZVE32F-NEXT: .LBB35_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
@@ -2517,9 +2469,8 @@ define <8 x i32> @mgather_baseidx_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: slli a1, a1, 2
; RV64ZVE32F-NEXT: add a0, a0, a1
; RV64ZVE32F-NEXT: lw a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
; RV64ZVE32F-NEXT: .LBB35_16: # %else20
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
@@ -2545,7 +2496,7 @@ define <8 x i32> @mgather_baseidx_sext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf8 v12, v8
; RV64V-NEXT: vsll.vi v12, v12, 2
-; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV64V-NEXT: vluxei64.v v10, (a0), v12, v0.t
; RV64V-NEXT: vmv.v.v v8, v10
; RV64V-NEXT: ret
@@ -2561,7 +2512,7 @@ define <8 x i32> @mgather_baseidx_sext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: .LBB36_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
@@ -2573,9 +2524,8 @@ define <8 x i32> @mgather_baseidx_sext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 1
; RV64ZVE32F-NEXT: .LBB36_4: # %else2
; RV64ZVE32F-NEXT: andi a2, a1, 4
@@ -2587,9 +2537,8 @@ define <8 x i32> @mgather_baseidx_sext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
; RV64ZVE32F-NEXT: .LBB36_6: # %else5
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -2601,9 +2550,8 @@ define <8 x i32> @mgather_baseidx_sext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
; RV64ZVE32F-NEXT: .LBB36_8: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 16
@@ -2615,9 +2563,8 @@ define <8 x i32> @mgather_baseidx_sext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
; RV64ZVE32F-NEXT: .LBB36_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
@@ -2629,9 +2576,8 @@ define <8 x i32> @mgather_baseidx_sext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
; RV64ZVE32F-NEXT: .LBB36_12: # %else14
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -2643,9 +2589,8 @@ define <8 x i32> @mgather_baseidx_sext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 6
; RV64ZVE32F-NEXT: .LBB36_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
@@ -2657,9 +2602,8 @@ define <8 x i32> @mgather_baseidx_sext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a1, a1, 2
; RV64ZVE32F-NEXT: add a0, a0, a1
; RV64ZVE32F-NEXT: lw a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
; RV64ZVE32F-NEXT: .LBB36_16: # %else20
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
@@ -2677,7 +2621,7 @@ define <8 x i32> @mgather_baseidx_zext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV32-NEXT: li a1, 4
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vwmulu.vx v9, v8, a1
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV32-NEXT: vluxei16.v v10, (a0), v9, v0.t
; RV32-NEXT: vmv.v.v v8, v10
; RV32-NEXT: ret
@@ -2687,7 +2631,7 @@ define <8 x i32> @mgather_baseidx_zext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64V-NEXT: li a1, 4
; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64V-NEXT: vwmulu.vx v9, v8, a1
-; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV64V-NEXT: vluxei16.v v10, (a0), v9, v0.t
; RV64V-NEXT: vmv.v.v v8, v10
; RV64V-NEXT: ret
@@ -2704,7 +2648,7 @@ define <8 x i32> @mgather_baseidx_zext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: .LBB37_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
@@ -2717,9 +2661,8 @@ define <8 x i32> @mgather_baseidx_zext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 1
; RV64ZVE32F-NEXT: .LBB37_4: # %else2
; RV64ZVE32F-NEXT: andi a2, a1, 4
@@ -2732,9 +2675,8 @@ define <8 x i32> @mgather_baseidx_zext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
; RV64ZVE32F-NEXT: .LBB37_6: # %else5
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -2747,9 +2689,8 @@ define <8 x i32> @mgather_baseidx_zext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
; RV64ZVE32F-NEXT: .LBB37_8: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 16
@@ -2762,9 +2703,8 @@ define <8 x i32> @mgather_baseidx_zext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
; RV64ZVE32F-NEXT: .LBB37_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
@@ -2777,9 +2717,8 @@ define <8 x i32> @mgather_baseidx_zext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
; RV64ZVE32F-NEXT: .LBB37_12: # %else14
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -2792,9 +2731,8 @@ define <8 x i32> @mgather_baseidx_zext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 6
; RV64ZVE32F-NEXT: .LBB37_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
@@ -2807,9 +2745,8 @@ define <8 x i32> @mgather_baseidx_zext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a1, a1, 2
; RV64ZVE32F-NEXT: add a0, a0, a1
; RV64ZVE32F-NEXT: lw a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
; RV64ZVE32F-NEXT: .LBB37_16: # %else20
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
@@ -2827,7 +2764,7 @@ define <8 x i32> @mgather_baseidx_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <8 x i
; RV32-NEXT: li a1, 4
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vwmulsu.vx v12, v8, a1
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV32-NEXT: vluxei32.v v10, (a0), v12, v0.t
; RV32-NEXT: vmv.v.v v8, v10
; RV32-NEXT: ret
@@ -2837,7 +2774,7 @@ define <8 x i32> @mgather_baseidx_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <8 x i
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf4 v12, v8
; RV64V-NEXT: vsll.vi v12, v12, 2
-; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV64V-NEXT: vluxei64.v v10, (a0), v12, v0.t
; RV64V-NEXT: vmv.v.v v8, v10
; RV64V-NEXT: ret
@@ -2849,12 +2786,12 @@ define <8 x i32> @mgather_baseidx_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB38_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: .LBB38_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
@@ -2866,9 +2803,8 @@ define <8 x i32> @mgather_baseidx_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 1
; RV64ZVE32F-NEXT: .LBB38_4: # %else2
; RV64ZVE32F-NEXT: andi a2, a1, 4
@@ -2880,9 +2816,8 @@ define <8 x i32> @mgather_baseidx_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
; RV64ZVE32F-NEXT: .LBB38_6: # %else5
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -2894,9 +2829,8 @@ define <8 x i32> @mgather_baseidx_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
; RV64ZVE32F-NEXT: .LBB38_8: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 16
@@ -2908,9 +2842,8 @@ define <8 x i32> @mgather_baseidx_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
; RV64ZVE32F-NEXT: .LBB38_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
@@ -2922,9 +2855,8 @@ define <8 x i32> @mgather_baseidx_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
; RV64ZVE32F-NEXT: .LBB38_12: # %else14
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -2936,9 +2868,8 @@ define <8 x i32> @mgather_baseidx_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 6
; RV64ZVE32F-NEXT: .LBB38_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
@@ -2950,9 +2881,8 @@ define <8 x i32> @mgather_baseidx_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli a1, a1, 2
; RV64ZVE32F-NEXT: add a0, a0, a1
; RV64ZVE32F-NEXT: lw a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
; RV64ZVE32F-NEXT: .LBB38_16: # %else20
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
@@ -2969,7 +2899,7 @@ define <8 x i32> @mgather_baseidx_sext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV32-NEXT: li a1, 4
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vwmulsu.vx v12, v8, a1
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV32-NEXT: vluxei32.v v10, (a0), v12, v0.t
; RV32-NEXT: vmv.v.v v8, v10
; RV32-NEXT: ret
@@ -2979,7 +2909,7 @@ define <8 x i32> @mgather_baseidx_sext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf4 v12, v8
; RV64V-NEXT: vsll.vi v12, v12, 2
-; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV64V-NEXT: vluxei64.v v10, (a0), v12, v0.t
; RV64V-NEXT: vmv.v.v v8, v10
; RV64V-NEXT: ret
@@ -2991,12 +2921,12 @@ define <8 x i32> @mgather_baseidx_sext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB39_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: .LBB39_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
@@ -3008,9 +2938,8 @@ define <8 x i32> @mgather_baseidx_sext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 1
; RV64ZVE32F-NEXT: .LBB39_4: # %else2
; RV64ZVE32F-NEXT: andi a2, a1, 4
@@ -3022,9 +2951,8 @@ define <8 x i32> @mgather_baseidx_sext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
; RV64ZVE32F-NEXT: .LBB39_6: # %else5
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -3036,9 +2964,8 @@ define <8 x i32> @mgather_baseidx_sext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
; RV64ZVE32F-NEXT: .LBB39_8: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 16
@@ -3050,9 +2977,8 @@ define <8 x i32> @mgather_baseidx_sext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
; RV64ZVE32F-NEXT: .LBB39_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
@@ -3064,9 +2990,8 @@ define <8 x i32> @mgather_baseidx_sext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
; RV64ZVE32F-NEXT: .LBB39_12: # %else14
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -3078,9 +3003,8 @@ define <8 x i32> @mgather_baseidx_sext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 6
; RV64ZVE32F-NEXT: .LBB39_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
@@ -3092,9 +3016,8 @@ define <8 x i32> @mgather_baseidx_sext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: slli a1, a1, 2
; RV64ZVE32F-NEXT: add a0, a0, a1
; RV64ZVE32F-NEXT: lw a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
; RV64ZVE32F-NEXT: .LBB39_16: # %else20
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
@@ -3112,7 +3035,7 @@ define <8 x i32> @mgather_baseidx_zext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV32-NEXT: li a1, 4
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vwmulu.vx v12, v8, a1
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV32-NEXT: vluxei32.v v10, (a0), v12, v0.t
; RV32-NEXT: vmv.v.v v8, v10
; RV32-NEXT: ret
@@ -3122,7 +3045,7 @@ define <8 x i32> @mgather_baseidx_zext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64V-NEXT: li a1, 4
; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64V-NEXT: vwmulu.vx v12, v8, a1
-; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV64V-NEXT: vluxei32.v v10, (a0), v12, v0.t
; RV64V-NEXT: vmv.v.v v8, v10
; RV64V-NEXT: ret
@@ -3134,13 +3057,13 @@ define <8 x i32> @mgather_baseidx_zext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB40_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: .LBB40_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
@@ -3153,9 +3076,8 @@ define <8 x i32> @mgather_baseidx_zext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 1
; RV64ZVE32F-NEXT: .LBB40_4: # %else2
; RV64ZVE32F-NEXT: andi a2, a1, 4
@@ -3168,9 +3090,8 @@ define <8 x i32> @mgather_baseidx_zext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
; RV64ZVE32F-NEXT: .LBB40_6: # %else5
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -3183,9 +3104,8 @@ define <8 x i32> @mgather_baseidx_zext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
; RV64ZVE32F-NEXT: .LBB40_8: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 16
@@ -3198,9 +3118,8 @@ define <8 x i32> @mgather_baseidx_zext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
; RV64ZVE32F-NEXT: .LBB40_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
@@ -3213,9 +3132,8 @@ define <8 x i32> @mgather_baseidx_zext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
; RV64ZVE32F-NEXT: .LBB40_12: # %else14
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -3228,9 +3146,8 @@ define <8 x i32> @mgather_baseidx_zext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 6
; RV64ZVE32F-NEXT: .LBB40_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
@@ -3243,9 +3160,8 @@ define <8 x i32> @mgather_baseidx_zext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: srli a1, a1, 46
; RV64ZVE32F-NEXT: add a0, a0, a1
; RV64ZVE32F-NEXT: lw a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
; RV64ZVE32F-NEXT: .LBB40_16: # %else20
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
@@ -3282,7 +3198,7 @@ define <8 x i32> @mgather_baseidx_v8i32(ptr %base, <8 x i32> %idxs, <8 x i1> %m,
; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB41_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -3459,7 +3375,7 @@ define <2 x i64> @mgather_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i64> %passthr
; RV32ZVE32F-NEXT: andi a2, a4, 1
; RV32ZVE32F-NEXT: beqz a2, .LBB43_3
; RV32ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a3, v8
; RV32ZVE32F-NEXT: lw a2, 0(a3)
; RV32ZVE32F-NEXT: lw a3, 4(a3)
@@ -3532,7 +3448,7 @@ define <4 x i64> @mgather_v4i64(<4 x ptr> %ptrs, <4 x i1> %m, <4 x i64> %passthr
; RV32ZVE32F-NEXT: andi a2, a6, 1
; RV32ZVE32F-NEXT: beqz a2, .LBB44_5
; RV32ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a3, v8
; RV32ZVE32F-NEXT: lw a2, 0(a3)
; RV32ZVE32F-NEXT: lw a3, 4(a3)
@@ -3772,7 +3688,7 @@ define <8 x i64> @mgather_v8i64(<8 x ptr> %ptrs, <8 x i1> %m, <8 x i64> %passthr
; RV32ZVE32F-NEXT: andi a2, t0, 1
; RV32ZVE32F-NEXT: beqz a2, .LBB47_7
; RV32ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a3, v8
; RV32ZVE32F-NEXT: lw a2, 0(a3)
; RV32ZVE32F-NEXT: lw a3, 4(a3)
@@ -3997,7 +3913,7 @@ define <8 x i64> @mgather_baseidx_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32V-NEXT: vsext.vf4 v10, v8
; RV32V-NEXT: vsll.vi v8, v10, 3
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32V-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32V-NEXT: vmv.v.v v8, v12
; RV32V-NEXT: ret
@@ -4015,9 +3931,9 @@ define <8 x i64> @mgather_baseidx_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsext.vf4 v10, v8
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t0, v0
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: andi a3, t0, 1
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
@@ -4276,7 +4192,7 @@ define <8 x i64> @mgather_baseidx_sext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8
; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32V-NEXT: vsext.vf4 v10, v8
; RV32V-NEXT: vsll.vi v8, v10, 3
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32V-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32V-NEXT: vmv.v.v v8, v12
; RV32V-NEXT: ret
@@ -4294,9 +4210,9 @@ define <8 x i64> @mgather_baseidx_sext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsext.vf4 v10, v8
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t0, v0
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: andi a3, t0, 1
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
@@ -4556,7 +4472,7 @@ define <8 x i64> @mgather_baseidx_zext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8
; RV32V-NEXT: li a1, 8
; RV32V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32V-NEXT: vwmulu.vx v9, v8, a1
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32V-NEXT: vluxei16.v v12, (a0), v9, v0.t
; RV32V-NEXT: vmv.v.v v8, v12
; RV32V-NEXT: ret
@@ -4566,7 +4482,7 @@ define <8 x i64> @mgather_baseidx_zext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8
; RV64V-NEXT: li a1, 8
; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64V-NEXT: vwmulu.vx v9, v8, a1
-; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64V-NEXT: vluxei16.v v12, (a0), v9, v0.t
; RV64V-NEXT: vmv.v.v v8, v12
; RV64V-NEXT: ret
@@ -4575,9 +4491,9 @@ define <8 x i64> @mgather_baseidx_zext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vzext.vf4 v10, v8
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t0, v0
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: andi a3, t0, 1
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
@@ -4845,7 +4761,7 @@ define <8 x i64> @mgather_baseidx_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i
; RV32V-NEXT: li a1, 8
; RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32V-NEXT: vwmulsu.vx v10, v8, a1
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32V-NEXT: vluxei32.v v12, (a0), v10, v0.t
; RV32V-NEXT: vmv.v.v v8, v12
; RV32V-NEXT: ret
@@ -4864,14 +4780,14 @@ define <8 x i64> @mgather_baseidx_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.v.x v10, a1
; RV32ZVE32F-NEXT: li a1, 8
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t0, v0
; RV32ZVE32F-NEXT: andi a3, t0, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32ZVE32F-NEXT: vwmaccus.vx v10, a1, v8
; RV32ZVE32F-NEXT: beqz a3, .LBB51_7
; RV32ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a3, v10
; RV32ZVE32F-NEXT: lw a1, 0(a3)
; RV32ZVE32F-NEXT: lw a3, 4(a3)
@@ -5008,7 +4924,7 @@ define <8 x i64> @mgather_baseidx_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: andi a3, a5, 1
; RV64ZVE32F-NEXT: beqz a3, .LBB51_3
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
@@ -5126,7 +5042,7 @@ define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV32V-NEXT: li a1, 8
; RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32V-NEXT: vwmulsu.vx v10, v8, a1
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32V-NEXT: vluxei32.v v12, (a0), v10, v0.t
; RV32V-NEXT: vmv.v.v v8, v12
; RV32V-NEXT: ret
@@ -5145,14 +5061,14 @@ define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.v.x v10, a1
; RV32ZVE32F-NEXT: li a1, 8
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t0, v0
; RV32ZVE32F-NEXT: andi a3, t0, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32ZVE32F-NEXT: vwmaccus.vx v10, a1, v8
; RV32ZVE32F-NEXT: beqz a3, .LBB52_7
; RV32ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a3, v10
; RV32ZVE32F-NEXT: lw a1, 0(a3)
; RV32ZVE32F-NEXT: lw a3, 4(a3)
@@ -5289,7 +5205,7 @@ define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: andi a3, a5, 1
; RV64ZVE32F-NEXT: beqz a3, .LBB52_3
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
@@ -5408,7 +5324,7 @@ define <8 x i64> @mgather_baseidx_zext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV32V-NEXT: li a1, 8
; RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32V-NEXT: vwmulu.vx v10, v8, a1
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32V-NEXT: vluxei32.v v12, (a0), v10, v0.t
; RV32V-NEXT: vmv.v.v v8, v12
; RV32V-NEXT: ret
@@ -5418,7 +5334,7 @@ define <8 x i64> @mgather_baseidx_zext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64V-NEXT: li a1, 8
; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64V-NEXT: vwmulu.vx v10, v8, a1
-; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64V-NEXT: vluxei32.v v12, (a0), v10, v0.t
; RV64V-NEXT: vmv.v.v v8, v12
; RV64V-NEXT: ret
@@ -5428,14 +5344,14 @@ define <8 x i64> @mgather_baseidx_zext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.v.x v10, a1
; RV32ZVE32F-NEXT: li a1, 8
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t0, v0
; RV32ZVE32F-NEXT: andi a3, t0, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32ZVE32F-NEXT: vwmaccu.vx v10, a1, v8
; RV32ZVE32F-NEXT: beqz a3, .LBB53_7
; RV32ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a3, v10
; RV32ZVE32F-NEXT: lw a1, 0(a3)
; RV32ZVE32F-NEXT: lw a3, 4(a3)
@@ -5572,7 +5488,7 @@ define <8 x i64> @mgather_baseidx_zext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: andi a3, a5, 1
; RV64ZVE32F-NEXT: beqz a3, .LBB53_3
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 48
; RV64ZVE32F-NEXT: srli a3, a3, 45
@@ -5698,7 +5614,7 @@ define <8 x i64> @mgather_baseidx_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <8 x i
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32V-NEXT: vsll.vi v8, v8, 3
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32V-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32V-NEXT: vmv.v.v v8, v12
; RV32V-NEXT: ret
@@ -5708,7 +5624,7 @@ define <8 x i64> @mgather_baseidx_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <8 x i
; RV64V-NEXT: li a1, 8
; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64V-NEXT: vwmulsu.vx v16, v8, a1
-; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64V-NEXT: vluxei64.v v12, (a0), v16, v0.t
; RV64V-NEXT: vmv.v.v v8, v12
; RV64V-NEXT: ret
@@ -5717,10 +5633,10 @@ define <8 x i64> @mgather_baseidx_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <8 x i
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t0, v0
; RV32ZVE32F-NEXT: andi a3, t0, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
; RV32ZVE32F-NEXT: beqz a3, .LBB54_7
; RV32ZVE32F-NEXT: # %bb.1: # %cond.load
@@ -5860,7 +5776,7 @@ define <8 x i64> @mgather_baseidx_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <8 x i
; RV64ZVE32F-NEXT: andi a3, a5, 1
; RV64ZVE32F-NEXT: beqz a3, .LBB54_3
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
@@ -5979,7 +5895,7 @@ define <8 x i64> @mgather_baseidx_sext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32V-NEXT: vsll.vi v8, v8, 3
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32V-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32V-NEXT: vmv.v.v v8, v12
; RV32V-NEXT: ret
@@ -5989,7 +5905,7 @@ define <8 x i64> @mgather_baseidx_sext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64V-NEXT: li a1, 8
; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64V-NEXT: vwmulsu.vx v16, v8, a1
-; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64V-NEXT: vluxei64.v v12, (a0), v16, v0.t
; RV64V-NEXT: vmv.v.v v8, v12
; RV64V-NEXT: ret
@@ -5998,10 +5914,10 @@ define <8 x i64> @mgather_baseidx_sext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t0, v0
; RV32ZVE32F-NEXT: andi a3, t0, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
; RV32ZVE32F-NEXT: beqz a3, .LBB55_7
; RV32ZVE32F-NEXT: # %bb.1: # %cond.load
@@ -6141,7 +6057,7 @@ define <8 x i64> @mgather_baseidx_sext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: andi a3, a5, 1
; RV64ZVE32F-NEXT: beqz a3, .LBB55_3
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
@@ -6261,7 +6177,7 @@ define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32V-NEXT: vsll.vi v8, v8, 3
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32V-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32V-NEXT: vmv.v.v v8, v12
; RV32V-NEXT: ret
@@ -6271,7 +6187,7 @@ define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64V-NEXT: li a1, 8
; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64V-NEXT: vwmulu.vx v16, v8, a1
-; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64V-NEXT: vluxei64.v v12, (a0), v16, v0.t
; RV64V-NEXT: vmv.v.v v8, v12
; RV64V-NEXT: ret
@@ -6280,10 +6196,10 @@ define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t0, v0
; RV32ZVE32F-NEXT: andi a3, t0, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
; RV32ZVE32F-NEXT: beqz a3, .LBB56_7
; RV32ZVE32F-NEXT: # %bb.1: # %cond.load
@@ -6423,7 +6339,7 @@ define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: andi a3, a5, 1
; RV64ZVE32F-NEXT: beqz a3, .LBB56_3
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 32
; RV64ZVE32F-NEXT: srli a3, a3, 29
@@ -6552,7 +6468,7 @@ define <8 x i64> @mgather_baseidx_v8i64(ptr %base, <8 x i64> %idxs, <8 x i1> %m,
; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32V-NEXT: vnsrl.wi v16, v8, 0
; RV32V-NEXT: vsll.vi v8, v16, 3
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32V-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32V-NEXT: vmv.v.v v8, v12
; RV32V-NEXT: ret
@@ -6577,9 +6493,9 @@ define <8 x i64> @mgather_baseidx_v8i64(ptr %base, <8 x i64> %idxs, <8 x i1> %m,
; RV32ZVE32F-NEXT: lw a2, 24(a2)
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.v.x v8, t0
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t0, v0
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, t1
; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, t2
; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, a2
@@ -6902,15 +6818,14 @@ define <2 x bfloat> @mgather_v2bf16(<2 x ptr> %ptrs, <2 x i1> %m, <2 x bfloat> %
; RV64ZVE32F-NEXT: ret
; RV64ZVE32F-NEXT: .LBB59_3: # %cond.load
; RV64ZVE32F-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: andi a2, a2, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB59_2
; RV64ZVE32F-NEXT: .LBB59_4: # %cond.load1
; RV64ZVE32F-NEXT: lh a0, 0(a1)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: ret
%v = call <2 x bfloat> @llvm.masked.gather.v2bf16.v2p0(<2 x ptr> %ptrs, i32 2, <2 x i1> %m, <2 x bfloat> %passthru)
@@ -6954,16 +6869,15 @@ define <4 x bfloat> @mgather_v4bf16(<4 x ptr> %ptrs, <4 x i1> %m, <4 x bfloat> %
; RV64ZVE32F-NEXT: .LBB60_5: # %cond.load
; RV64ZVE32F-NEXT: ld a2, 0(a0)
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v8, a2
; RV64ZVE32F-NEXT: andi a2, a1, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB60_2
; RV64ZVE32F-NEXT: .LBB60_6: # %cond.load1
; RV64ZVE32F-NEXT: ld a2, 8(a0)
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: andi a2, a1, 4
; RV64ZVE32F-NEXT: beqz a2, .LBB60_3
@@ -7090,16 +7004,15 @@ define <8 x bfloat> @mgather_v8bf16(<8 x ptr> %ptrs, <8 x i1> %m, <8 x bfloat> %
; RV64ZVE32F-NEXT: .LBB63_9: # %cond.load
; RV64ZVE32F-NEXT: ld a2, 0(a0)
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v8, a2
; RV64ZVE32F-NEXT: andi a2, a1, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB63_2
; RV64ZVE32F-NEXT: .LBB63_10: # %cond.load1
; RV64ZVE32F-NEXT: ld a2, 8(a0)
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: andi a2, a1, 4
; RV64ZVE32F-NEXT: beqz a2, .LBB63_3
@@ -7160,7 +7073,7 @@ define <8 x bfloat> @mgather_baseidx_v8i8_v8bf16(ptr %base, <8 x i8> %idxs, <8 x
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vsext.vf4 v10, v8
; RV32-NEXT: vadd.vv v10, v10, v10
-; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t
; RV32-NEXT: vmv.v.v v8, v9
; RV32-NEXT: ret
@@ -7170,7 +7083,7 @@ define <8 x bfloat> @mgather_baseidx_v8i8_v8bf16(ptr %base, <8 x i8> %idxs, <8 x
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf8 v12, v8
; RV64V-NEXT: vadd.vv v12, v12, v12
-; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV64V-NEXT: vluxei64.v v9, (a0), v12, v0.t
; RV64V-NEXT: vmv.v.v v8, v9
; RV64V-NEXT: ret
@@ -7186,7 +7099,7 @@ define <8 x bfloat> @mgather_baseidx_v8i8_v8bf16(ptr %base, <8 x i8> %idxs, <8 x
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: .LBB64_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
@@ -7198,9 +7111,8 @@ define <8 x bfloat> @mgather_baseidx_v8i8_v8bf16(ptr %base, <8 x i8> %idxs, <8 x
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 1
; RV64ZVE32F-NEXT: .LBB64_4: # %else2
; RV64ZVE32F-NEXT: andi a2, a1, 4
@@ -7212,9 +7124,8 @@ define <8 x bfloat> @mgather_baseidx_v8i8_v8bf16(ptr %base, <8 x i8> %idxs, <8 x
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v11, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v11, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 2
; RV64ZVE32F-NEXT: .LBB64_6: # %else5
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -7226,9 +7137,8 @@ define <8 x bfloat> @mgather_baseidx_v8i8_v8bf16(ptr %base, <8 x i8> %idxs, <8 x
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
; RV64ZVE32F-NEXT: .LBB64_8: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 16
@@ -7240,9 +7150,8 @@ define <8 x bfloat> @mgather_baseidx_v8i8_v8bf16(ptr %base, <8 x i8> %idxs, <8 x
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 4
; RV64ZVE32F-NEXT: .LBB64_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
@@ -7254,9 +7163,8 @@ define <8 x bfloat> @mgather_baseidx_v8i8_v8bf16(ptr %base, <8 x i8> %idxs, <8 x
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 5
; RV64ZVE32F-NEXT: .LBB64_12: # %else14
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -7268,9 +7176,8 @@ define <8 x bfloat> @mgather_baseidx_v8i8_v8bf16(ptr %base, <8 x i8> %idxs, <8 x
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 6
; RV64ZVE32F-NEXT: .LBB64_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
@@ -7282,9 +7189,8 @@ define <8 x bfloat> @mgather_baseidx_v8i8_v8bf16(ptr %base, <8 x i8> %idxs, <8 x
; RV64ZVE32F-NEXT: slli a1, a1, 1
; RV64ZVE32F-NEXT: add a0, a0, a1
; RV64ZVE32F-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7
; RV64ZVE32F-NEXT: .LBB64_16: # %else20
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
@@ -7301,7 +7207,7 @@ define <8 x bfloat> @mgather_baseidx_sext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vsext.vf4 v10, v8
; RV32-NEXT: vadd.vv v10, v10, v10
-; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t
; RV32-NEXT: vmv.v.v v8, v9
; RV32-NEXT: ret
@@ -7311,7 +7217,7 @@ define <8 x bfloat> @mgather_baseidx_sext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf8 v12, v8
; RV64V-NEXT: vadd.vv v12, v12, v12
-; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV64V-NEXT: vluxei64.v v9, (a0), v12, v0.t
; RV64V-NEXT: vmv.v.v v8, v9
; RV64V-NEXT: ret
@@ -7327,7 +7233,7 @@ define <8 x bfloat> @mgather_baseidx_sext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: .LBB65_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
@@ -7339,9 +7245,8 @@ define <8 x bfloat> @mgather_baseidx_sext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 1
; RV64ZVE32F-NEXT: .LBB65_4: # %else2
; RV64ZVE32F-NEXT: andi a2, a1, 4
@@ -7353,9 +7258,8 @@ define <8 x bfloat> @mgather_baseidx_sext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v11, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v11, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 2
; RV64ZVE32F-NEXT: .LBB65_6: # %else5
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -7367,9 +7271,8 @@ define <8 x bfloat> @mgather_baseidx_sext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
; RV64ZVE32F-NEXT: .LBB65_8: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 16
@@ -7381,9 +7284,8 @@ define <8 x bfloat> @mgather_baseidx_sext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 4
; RV64ZVE32F-NEXT: .LBB65_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
@@ -7395,9 +7297,8 @@ define <8 x bfloat> @mgather_baseidx_sext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 5
; RV64ZVE32F-NEXT: .LBB65_12: # %else14
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -7409,9 +7310,8 @@ define <8 x bfloat> @mgather_baseidx_sext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 6
; RV64ZVE32F-NEXT: .LBB65_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
@@ -7423,9 +7323,8 @@ define <8 x bfloat> @mgather_baseidx_sext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: slli a1, a1, 1
; RV64ZVE32F-NEXT: add a0, a0, a1
; RV64ZVE32F-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7
; RV64ZVE32F-NEXT: .LBB65_16: # %else20
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
@@ -7442,7 +7341,7 @@ define <8 x bfloat> @mgather_baseidx_zext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vwaddu.vv v10, v8, v8
-; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV32-NEXT: vluxei16.v v9, (a0), v10, v0.t
; RV32-NEXT: vmv.v.v v8, v9
; RV32-NEXT: ret
@@ -7451,7 +7350,7 @@ define <8 x bfloat> @mgather_baseidx_zext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64V-NEXT: vwaddu.vv v10, v8, v8
-; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV64V-NEXT: vluxei16.v v9, (a0), v10, v0.t
; RV64V-NEXT: vmv.v.v v8, v9
; RV64V-NEXT: ret
@@ -7468,7 +7367,7 @@ define <8 x bfloat> @mgather_baseidx_zext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: .LBB66_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
@@ -7481,9 +7380,8 @@ define <8 x bfloat> @mgather_baseidx_zext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 1
; RV64ZVE32F-NEXT: .LBB66_4: # %else2
; RV64ZVE32F-NEXT: andi a2, a1, 4
@@ -7496,9 +7394,8 @@ define <8 x bfloat> @mgather_baseidx_zext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v11, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v11, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 2
; RV64ZVE32F-NEXT: .LBB66_6: # %else5
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -7511,9 +7408,8 @@ define <8 x bfloat> @mgather_baseidx_zext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
; RV64ZVE32F-NEXT: .LBB66_8: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 16
@@ -7526,9 +7422,8 @@ define <8 x bfloat> @mgather_baseidx_zext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 4
; RV64ZVE32F-NEXT: .LBB66_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
@@ -7541,9 +7436,8 @@ define <8 x bfloat> @mgather_baseidx_zext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 5
; RV64ZVE32F-NEXT: .LBB66_12: # %else14
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -7556,9 +7450,8 @@ define <8 x bfloat> @mgather_baseidx_zext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 6
; RV64ZVE32F-NEXT: .LBB66_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
@@ -7571,9 +7464,8 @@ define <8 x bfloat> @mgather_baseidx_zext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: slli a1, a1, 1
; RV64ZVE32F-NEXT: add a0, a0, a1
; RV64ZVE32F-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7
; RV64ZVE32F-NEXT: .LBB66_16: # %else20
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
@@ -7599,7 +7491,7 @@ define <8 x bfloat> @mgather_baseidx_v8bf16(ptr %base, <8 x i16> %idxs, <8 x i1>
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf4 v12, v8
; RV64V-NEXT: vadd.vv v12, v12, v12
-; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV64V-NEXT: vluxei64.v v9, (a0), v12, v0.t
; RV64V-NEXT: vmv.v.v v8, v9
; RV64V-NEXT: ret
@@ -7611,7 +7503,7 @@ define <8 x bfloat> @mgather_baseidx_v8bf16(ptr %base, <8 x i16> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB67_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -7792,15 +7684,14 @@ define <2 x half> @mgather_v2f16(<2 x ptr> %ptrs, <2 x i1> %m, <2 x half> %passt
; RV64ZVE32F-ZVFH-NEXT: ret
; RV64ZVE32F-ZVFH-NEXT: .LBB69_3: # %cond.load
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a0)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v8, fa5
; RV64ZVE32F-ZVFH-NEXT: andi a2, a2, 2
; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB69_2
; RV64ZVE32F-ZVFH-NEXT: .LBB69_4: # %cond.load1
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a1)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-ZVFH-NEXT: ret
;
@@ -7817,15 +7708,14 @@ define <2 x half> @mgather_v2f16(<2 x ptr> %ptrs, <2 x i1> %m, <2 x half> %passt
; RV64ZVE32F-ZVFHMIN-NEXT: ret
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB69_3: # %cond.load
; RV64ZVE32F-ZVFHMIN-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a2, 2
; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB69_2
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB69_4: # %cond.load1
; RV64ZVE32F-ZVFHMIN-NEXT: lh a0, 0(a1)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-ZVFHMIN-NEXT: ret
%v = call <2 x half> @llvm.masked.gather.v2f16.v2p0(<2 x ptr> %ptrs, i32 2, <2 x i1> %m, <2 x half> %passthru)
@@ -7869,16 +7759,15 @@ define <4 x half> @mgather_v4f16(<4 x ptr> %ptrs, <4 x i1> %m, <4 x half> %passt
; RV64ZVE32F-ZVFH-NEXT: .LBB70_5: # %cond.load
; RV64ZVE32F-ZVFH-NEXT: ld a2, 0(a0)
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v8, fa5
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 2
; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB70_2
; RV64ZVE32F-ZVFH-NEXT: .LBB70_6: # %cond.load1
; RV64ZVE32F-ZVFH-NEXT: ld a2, 8(a0)
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB70_3
@@ -7918,16 +7807,15 @@ define <4 x half> @mgather_v4f16(<4 x ptr> %ptrs, <4 x i1> %m, <4 x half> %passt
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_5: # %cond.load
; RV64ZVE32F-ZVFHMIN-NEXT: ld a2, 0(a0)
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v8, a2
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 2
; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB70_2
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_6: # %cond.load1
; RV64ZVE32F-ZVFHMIN-NEXT: ld a2, 8(a0)
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 4
; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB70_3
@@ -8071,16 +7959,15 @@ define <8 x half> @mgather_v8f16(<8 x ptr> %ptrs, <8 x i1> %m, <8 x half> %passt
; RV64ZVE32F-ZVFH-NEXT: .LBB73_9: # %cond.load
; RV64ZVE32F-ZVFH-NEXT: ld a2, 0(a0)
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v8, fa5
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 2
; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB73_2
; RV64ZVE32F-ZVFH-NEXT: .LBB73_10: # %cond.load1
; RV64ZVE32F-ZVFH-NEXT: ld a2, 8(a0)
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e16, m1, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB73_3
@@ -8164,16 +8051,15 @@ define <8 x half> @mgather_v8f16(<8 x ptr> %ptrs, <8 x i1> %m, <8 x half> %passt
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB73_9: # %cond.load
; RV64ZVE32F-ZVFHMIN-NEXT: ld a2, 0(a0)
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v8, a2
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 2
; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB73_2
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB73_10: # %cond.load1
; RV64ZVE32F-ZVFHMIN-NEXT: ld a2, 8(a0)
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e16, m1, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 4
; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB73_3
@@ -8234,7 +8120,7 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vsext.vf4 v10, v8
; RV32-NEXT: vadd.vv v10, v10, v10
-; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t
; RV32-NEXT: vmv.v.v v8, v9
; RV32-NEXT: ret
@@ -8244,7 +8130,7 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf8 v12, v8
; RV64V-NEXT: vadd.vv v12, v12, v12
-; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV64V-NEXT: vluxei64.v v9, (a0), v12, v0.t
; RV64V-NEXT: vmv.v.v v8, v9
; RV64V-NEXT: ret
@@ -8260,7 +8146,7 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-ZVFH-NEXT: .LBB74_2: # %else
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 2
@@ -8272,9 +8158,8 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e16, m1, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 1
; RV64ZVE32F-ZVFH-NEXT: .LBB74_4: # %else2
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
@@ -8286,9 +8171,8 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v11, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 3, e16, m1, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v11, fa5
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v11, 2
; RV64ZVE32F-ZVFH-NEXT: .LBB74_6: # %else5
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 8
@@ -8300,9 +8184,8 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 3
; RV64ZVE32F-ZVFH-NEXT: .LBB74_8: # %else8
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 16
@@ -8314,9 +8197,8 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 5, e16, m1, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 4
; RV64ZVE32F-ZVFH-NEXT: .LBB74_10: # %else11
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 32
@@ -8328,9 +8210,8 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 6, e16, m1, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 5
; RV64ZVE32F-ZVFH-NEXT: .LBB74_12: # %else14
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 64
@@ -8342,9 +8223,8 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 7, e16, m1, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 6
; RV64ZVE32F-ZVFH-NEXT: .LBB74_14: # %else17
; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -128
@@ -8356,9 +8236,8 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV64ZVE32F-ZVFH-NEXT: slli a1, a1, 1
; RV64ZVE32F-ZVFH-NEXT: add a0, a0, a1
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a0)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v8, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v8, fa5
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v8, 7
; RV64ZVE32F-ZVFH-NEXT: .LBB74_16: # %else20
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
@@ -8376,7 +8255,7 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_2: # %else
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 2
@@ -8388,9 +8267,8 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e16, m1, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 1
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_4: # %else2
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 4
@@ -8402,9 +8280,8 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v11, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 3, e16, m1, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v11, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v11, 2
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_6: # %else5
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 8
@@ -8416,9 +8293,8 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 3
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_8: # %else8
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 16
@@ -8430,9 +8306,8 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 5, e16, m1, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 4
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_10: # %else11
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 32
@@ -8444,9 +8319,8 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 5
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_12: # %else14
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 64
@@ -8458,9 +8332,8 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 7, e16, m1, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 6
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_14: # %else17
; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -128
@@ -8472,9 +8345,8 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV64ZVE32F-ZVFHMIN-NEXT: slli a1, a1, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a0, a0, a1
; RV64ZVE32F-ZVFHMIN-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v8, 7
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_16: # %else20
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma
@@ -8491,7 +8363,7 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vsext.vf4 v10, v8
; RV32-NEXT: vadd.vv v10, v10, v10
-; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t
; RV32-NEXT: vmv.v.v v8, v9
; RV32-NEXT: ret
@@ -8501,7 +8373,7 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf8 v12, v8
; RV64V-NEXT: vadd.vv v12, v12, v12
-; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV64V-NEXT: vluxei64.v v9, (a0), v12, v0.t
; RV64V-NEXT: vmv.v.v v8, v9
; RV64V-NEXT: ret
@@ -8517,7 +8389,7 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-ZVFH-NEXT: .LBB75_2: # %else
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 2
@@ -8529,9 +8401,8 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e16, m1, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 1
; RV64ZVE32F-ZVFH-NEXT: .LBB75_4: # %else2
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
@@ -8543,9 +8414,8 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v11, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 3, e16, m1, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v11, fa5
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v11, 2
; RV64ZVE32F-ZVFH-NEXT: .LBB75_6: # %else5
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 8
@@ -8557,9 +8427,8 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 3
; RV64ZVE32F-ZVFH-NEXT: .LBB75_8: # %else8
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 16
@@ -8571,9 +8440,8 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 5, e16, m1, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 4
; RV64ZVE32F-ZVFH-NEXT: .LBB75_10: # %else11
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 32
@@ -8585,9 +8453,8 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 6, e16, m1, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 5
; RV64ZVE32F-ZVFH-NEXT: .LBB75_12: # %else14
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 64
@@ -8599,9 +8466,8 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 7, e16, m1, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 6
; RV64ZVE32F-ZVFH-NEXT: .LBB75_14: # %else17
; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -128
@@ -8613,9 +8479,8 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: slli a1, a1, 1
; RV64ZVE32F-ZVFH-NEXT: add a0, a0, a1
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a0)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v8, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v8, fa5
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v8, 7
; RV64ZVE32F-ZVFH-NEXT: .LBB75_16: # %else20
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
@@ -8633,7 +8498,7 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_2: # %else
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 2
@@ -8645,9 +8510,8 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e16, m1, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 1
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_4: # %else2
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 4
@@ -8659,9 +8523,8 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v11, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 3, e16, m1, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v11, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v11, 2
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_6: # %else5
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 8
@@ -8673,9 +8536,8 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 3
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_8: # %else8
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 16
@@ -8687,9 +8549,8 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 5, e16, m1, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 4
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_10: # %else11
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 32
@@ -8701,9 +8562,8 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 5
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_12: # %else14
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 64
@@ -8715,9 +8575,8 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 7, e16, m1, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 6
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_14: # %else17
; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -128
@@ -8729,9 +8588,8 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFHMIN-NEXT: slli a1, a1, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a0, a0, a1
; RV64ZVE32F-ZVFHMIN-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v8, 7
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_16: # %else20
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma
@@ -8748,7 +8606,7 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vwaddu.vv v10, v8, v8
-; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV32-NEXT: vluxei16.v v9, (a0), v10, v0.t
; RV32-NEXT: vmv.v.v v8, v9
; RV32-NEXT: ret
@@ -8757,7 +8615,7 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64V-NEXT: vwaddu.vv v10, v8, v8
-; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV64V-NEXT: vluxei16.v v9, (a0), v10, v0.t
; RV64V-NEXT: vmv.v.v v8, v9
; RV64V-NEXT: ret
@@ -8774,7 +8632,7 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-ZVFH-NEXT: .LBB76_2: # %else
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 2
@@ -8787,9 +8645,8 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e16, m1, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 1
; RV64ZVE32F-ZVFH-NEXT: .LBB76_4: # %else2
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
@@ -8802,9 +8659,8 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v11, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 3, e16, m1, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v11, fa5
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v11, 2
; RV64ZVE32F-ZVFH-NEXT: .LBB76_6: # %else5
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 8
@@ -8817,9 +8673,8 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 3
; RV64ZVE32F-ZVFH-NEXT: .LBB76_8: # %else8
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 16
@@ -8832,9 +8687,8 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 5, e16, m1, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 4
; RV64ZVE32F-ZVFH-NEXT: .LBB76_10: # %else11
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 32
@@ -8847,9 +8701,8 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 6, e16, m1, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 5
; RV64ZVE32F-ZVFH-NEXT: .LBB76_12: # %else14
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 64
@@ -8862,9 +8715,8 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 7, e16, m1, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 6
; RV64ZVE32F-ZVFH-NEXT: .LBB76_14: # %else17
; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -128
@@ -8877,9 +8729,8 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: slli a1, a1, 1
; RV64ZVE32F-ZVFH-NEXT: add a0, a0, a1
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a0)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v8, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v8, fa5
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v8, 7
; RV64ZVE32F-ZVFH-NEXT: .LBB76_16: # %else20
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
@@ -8898,7 +8749,7 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_2: # %else
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 2
@@ -8911,9 +8762,8 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e16, m1, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 1
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_4: # %else2
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 4
@@ -8926,9 +8776,8 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v11, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 3, e16, m1, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v11, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v11, 2
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_6: # %else5
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 8
@@ -8941,9 +8790,8 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 3
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_8: # %else8
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 16
@@ -8956,9 +8804,8 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 5, e16, m1, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 4
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_10: # %else11
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 32
@@ -8971,9 +8818,8 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 5
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_12: # %else14
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 64
@@ -8986,9 +8832,8 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 7, e16, m1, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 6
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_14: # %else17
; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -128
@@ -9001,9 +8846,8 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFHMIN-NEXT: slli a1, a1, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a0, a0, a1
; RV64ZVE32F-ZVFHMIN-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v8, 7
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_16: # %else20
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma
@@ -9029,7 +8873,7 @@ define <8 x half> @mgather_baseidx_v8f16(ptr %base, <8 x i16> %idxs, <8 x i1> %m
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf4 v12, v8
; RV64V-NEXT: vadd.vv v12, v12, v12
-; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV64V-NEXT: vluxei64.v v9, (a0), v12, v0.t
; RV64V-NEXT: vmv.v.v v8, v9
; RV64V-NEXT: ret
@@ -9041,7 +8885,7 @@ define <8 x half> @mgather_baseidx_v8f16(ptr %base, <8 x i16> %idxs, <8 x i1> %m
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 1
; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB77_2
; RV64ZVE32F-ZVFH-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
@@ -9150,7 +8994,7 @@ define <8 x half> @mgather_baseidx_v8f16(ptr %base, <8 x i16> %idxs, <8 x i1> %m
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 1
; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB77_2
; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
@@ -9331,15 +9175,14 @@ define <2 x float> @mgather_v2f32(<2 x ptr> %ptrs, <2 x i1> %m, <2 x float> %pas
; RV64ZVE32F-NEXT: ret
; RV64ZVE32F-NEXT: .LBB79_3: # %cond.load
; RV64ZVE32F-NEXT: flw fa5, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
; RV64ZVE32F-NEXT: andi a2, a2, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB79_2
; RV64ZVE32F-NEXT: .LBB79_4: # %cond.load1
; RV64ZVE32F-NEXT: flw fa5, 0(a1)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: ret
%v = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %m, <2 x float> %passthru)
@@ -9383,16 +9226,15 @@ define <4 x float> @mgather_v4f32(<4 x ptr> %ptrs, <4 x i1> %m, <4 x float> %pas
; RV64ZVE32F-NEXT: .LBB80_5: # %cond.load
; RV64ZVE32F-NEXT: ld a2, 0(a0)
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
; RV64ZVE32F-NEXT: andi a2, a1, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB80_2
; RV64ZVE32F-NEXT: .LBB80_6: # %cond.load1
; RV64ZVE32F-NEXT: ld a2, 8(a0)
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: andi a2, a1, 4
; RV64ZVE32F-NEXT: beqz a2, .LBB80_3
@@ -9518,16 +9360,15 @@ define <8 x float> @mgather_v8f32(<8 x ptr> %ptrs, <8 x i1> %m, <8 x float> %pas
; RV64ZVE32F-NEXT: .LBB83_9: # %cond.load
; RV64ZVE32F-NEXT: ld a2, 0(a0)
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
; RV64ZVE32F-NEXT: andi a2, a1, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB83_2
; RV64ZVE32F-NEXT: .LBB83_10: # %cond.load1
; RV64ZVE32F-NEXT: ld a2, 8(a0)
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-NEXT: vslideup.vi v8, v10, 1
; RV64ZVE32F-NEXT: andi a2, a1, 4
; RV64ZVE32F-NEXT: beqz a2, .LBB83_3
@@ -9597,7 +9438,7 @@ define <8 x float> @mgather_baseidx_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <8 x i
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf8 v12, v8
; RV64V-NEXT: vsll.vi v12, v12, 2
-; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV64V-NEXT: vluxei64.v v10, (a0), v12, v0.t
; RV64V-NEXT: vmv.v.v v8, v10
; RV64V-NEXT: ret
@@ -9613,7 +9454,7 @@ define <8 x float> @mgather_baseidx_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-NEXT: .LBB84_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
@@ -9625,9 +9466,8 @@ define <8 x float> @mgather_baseidx_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 1
; RV64ZVE32F-NEXT: .LBB84_4: # %else2
; RV64ZVE32F-NEXT: andi a2, a1, 4
@@ -9639,9 +9479,8 @@ define <8 x float> @mgather_baseidx_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
; RV64ZVE32F-NEXT: .LBB84_6: # %else5
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -9653,9 +9492,8 @@ define <8 x float> @mgather_baseidx_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
; RV64ZVE32F-NEXT: .LBB84_8: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 16
@@ -9667,9 +9505,8 @@ define <8 x float> @mgather_baseidx_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
; RV64ZVE32F-NEXT: .LBB84_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
@@ -9681,9 +9518,8 @@ define <8 x float> @mgather_baseidx_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
; RV64ZVE32F-NEXT: .LBB84_12: # %else14
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -9695,9 +9531,8 @@ define <8 x float> @mgather_baseidx_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 6
; RV64ZVE32F-NEXT: .LBB84_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
@@ -9709,9 +9544,8 @@ define <8 x float> @mgather_baseidx_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli a1, a1, 2
; RV64ZVE32F-NEXT: add a0, a0, a1
; RV64ZVE32F-NEXT: flw fa5, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
; RV64ZVE32F-NEXT: .LBB84_16: # %else20
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
@@ -9737,7 +9571,7 @@ define <8 x float> @mgather_baseidx_sext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf8 v12, v8
; RV64V-NEXT: vsll.vi v12, v12, 2
-; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV64V-NEXT: vluxei64.v v10, (a0), v12, v0.t
; RV64V-NEXT: vmv.v.v v8, v10
; RV64V-NEXT: ret
@@ -9753,7 +9587,7 @@ define <8 x float> @mgather_baseidx_sext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-NEXT: .LBB85_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
@@ -9765,9 +9599,8 @@ define <8 x float> @mgather_baseidx_sext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 1
; RV64ZVE32F-NEXT: .LBB85_4: # %else2
; RV64ZVE32F-NEXT: andi a2, a1, 4
@@ -9779,9 +9612,8 @@ define <8 x float> @mgather_baseidx_sext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
; RV64ZVE32F-NEXT: .LBB85_6: # %else5
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -9793,9 +9625,8 @@ define <8 x float> @mgather_baseidx_sext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
; RV64ZVE32F-NEXT: .LBB85_8: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 16
@@ -9807,9 +9638,8 @@ define <8 x float> @mgather_baseidx_sext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
; RV64ZVE32F-NEXT: .LBB85_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
@@ -9821,9 +9651,8 @@ define <8 x float> @mgather_baseidx_sext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
; RV64ZVE32F-NEXT: .LBB85_12: # %else14
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -9835,9 +9664,8 @@ define <8 x float> @mgather_baseidx_sext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 6
; RV64ZVE32F-NEXT: .LBB85_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
@@ -9849,9 +9677,8 @@ define <8 x float> @mgather_baseidx_sext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: slli a1, a1, 2
; RV64ZVE32F-NEXT: add a0, a0, a1
; RV64ZVE32F-NEXT: flw fa5, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
; RV64ZVE32F-NEXT: .LBB85_16: # %else20
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
@@ -9869,7 +9696,7 @@ define <8 x float> @mgather_baseidx_zext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV32-NEXT: li a1, 4
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vwmulu.vx v9, v8, a1
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV32-NEXT: vluxei16.v v10, (a0), v9, v0.t
; RV32-NEXT: vmv.v.v v8, v10
; RV32-NEXT: ret
@@ -9879,7 +9706,7 @@ define <8 x float> @mgather_baseidx_zext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64V-NEXT: li a1, 4
; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64V-NEXT: vwmulu.vx v9, v8, a1
-; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV64V-NEXT: vluxei16.v v10, (a0), v9, v0.t
; RV64V-NEXT: vmv.v.v v8, v10
; RV64V-NEXT: ret
@@ -9896,7 +9723,7 @@ define <8 x float> @mgather_baseidx_zext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-NEXT: .LBB86_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
@@ -9909,9 +9736,8 @@ define <8 x float> @mgather_baseidx_zext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 1
; RV64ZVE32F-NEXT: .LBB86_4: # %else2
; RV64ZVE32F-NEXT: andi a2, a1, 4
@@ -9924,9 +9750,8 @@ define <8 x float> @mgather_baseidx_zext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
; RV64ZVE32F-NEXT: .LBB86_6: # %else5
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -9939,9 +9764,8 @@ define <8 x float> @mgather_baseidx_zext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
; RV64ZVE32F-NEXT: .LBB86_8: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 16
@@ -9954,9 +9778,8 @@ define <8 x float> @mgather_baseidx_zext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
; RV64ZVE32F-NEXT: .LBB86_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
@@ -9969,9 +9792,8 @@ define <8 x float> @mgather_baseidx_zext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
; RV64ZVE32F-NEXT: .LBB86_12: # %else14
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -9984,9 +9806,8 @@ define <8 x float> @mgather_baseidx_zext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 6
; RV64ZVE32F-NEXT: .LBB86_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
@@ -9999,9 +9820,8 @@ define <8 x float> @mgather_baseidx_zext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: slli a1, a1, 2
; RV64ZVE32F-NEXT: add a0, a0, a1
; RV64ZVE32F-NEXT: flw fa5, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
; RV64ZVE32F-NEXT: .LBB86_16: # %else20
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
@@ -10019,7 +9839,7 @@ define <8 x float> @mgather_baseidx_v8i16_v8f32(ptr %base, <8 x i16> %idxs, <8 x
; RV32-NEXT: li a1, 4
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vwmulsu.vx v12, v8, a1
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV32-NEXT: vluxei32.v v10, (a0), v12, v0.t
; RV32-NEXT: vmv.v.v v8, v10
; RV32-NEXT: ret
@@ -10029,7 +9849,7 @@ define <8 x float> @mgather_baseidx_v8i16_v8f32(ptr %base, <8 x i16> %idxs, <8 x
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf4 v12, v8
; RV64V-NEXT: vsll.vi v12, v12, 2
-; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV64V-NEXT: vluxei64.v v10, (a0), v12, v0.t
; RV64V-NEXT: vmv.v.v v8, v10
; RV64V-NEXT: ret
@@ -10041,12 +9861,12 @@ define <8 x float> @mgather_baseidx_v8i16_v8f32(ptr %base, <8 x i16> %idxs, <8 x
; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB87_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-NEXT: .LBB87_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
@@ -10058,9 +9878,8 @@ define <8 x float> @mgather_baseidx_v8i16_v8f32(ptr %base, <8 x i16> %idxs, <8 x
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 1
; RV64ZVE32F-NEXT: .LBB87_4: # %else2
; RV64ZVE32F-NEXT: andi a2, a1, 4
@@ -10072,9 +9891,8 @@ define <8 x float> @mgather_baseidx_v8i16_v8f32(ptr %base, <8 x i16> %idxs, <8 x
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
; RV64ZVE32F-NEXT: .LBB87_6: # %else5
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -10086,9 +9904,8 @@ define <8 x float> @mgather_baseidx_v8i16_v8f32(ptr %base, <8 x i16> %idxs, <8 x
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
; RV64ZVE32F-NEXT: .LBB87_8: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 16
@@ -10100,9 +9917,8 @@ define <8 x float> @mgather_baseidx_v8i16_v8f32(ptr %base, <8 x i16> %idxs, <8 x
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
; RV64ZVE32F-NEXT: .LBB87_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
@@ -10114,9 +9930,8 @@ define <8 x float> @mgather_baseidx_v8i16_v8f32(ptr %base, <8 x i16> %idxs, <8 x
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
; RV64ZVE32F-NEXT: .LBB87_12: # %else14
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -10128,9 +9943,8 @@ define <8 x float> @mgather_baseidx_v8i16_v8f32(ptr %base, <8 x i16> %idxs, <8 x
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 6
; RV64ZVE32F-NEXT: .LBB87_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
@@ -10142,9 +9956,8 @@ define <8 x float> @mgather_baseidx_v8i16_v8f32(ptr %base, <8 x i16> %idxs, <8 x
; RV64ZVE32F-NEXT: slli a1, a1, 2
; RV64ZVE32F-NEXT: add a0, a0, a1
; RV64ZVE32F-NEXT: flw fa5, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
; RV64ZVE32F-NEXT: .LBB87_16: # %else20
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
@@ -10161,7 +9974,7 @@ define <8 x float> @mgather_baseidx_sext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV32-NEXT: li a1, 4
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vwmulsu.vx v12, v8, a1
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV32-NEXT: vluxei32.v v10, (a0), v12, v0.t
; RV32-NEXT: vmv.v.v v8, v10
; RV32-NEXT: ret
@@ -10171,7 +9984,7 @@ define <8 x float> @mgather_baseidx_sext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf4 v12, v8
; RV64V-NEXT: vsll.vi v12, v12, 2
-; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV64V-NEXT: vluxei64.v v10, (a0), v12, v0.t
; RV64V-NEXT: vmv.v.v v8, v10
; RV64V-NEXT: ret
@@ -10183,12 +9996,12 @@ define <8 x float> @mgather_baseidx_sext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB88_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-NEXT: .LBB88_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
@@ -10200,9 +10013,8 @@ define <8 x float> @mgather_baseidx_sext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 1
; RV64ZVE32F-NEXT: .LBB88_4: # %else2
; RV64ZVE32F-NEXT: andi a2, a1, 4
@@ -10214,9 +10026,8 @@ define <8 x float> @mgather_baseidx_sext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
; RV64ZVE32F-NEXT: .LBB88_6: # %else5
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -10228,9 +10039,8 @@ define <8 x float> @mgather_baseidx_sext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
; RV64ZVE32F-NEXT: .LBB88_8: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 16
@@ -10242,9 +10052,8 @@ define <8 x float> @mgather_baseidx_sext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
; RV64ZVE32F-NEXT: .LBB88_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
@@ -10256,9 +10065,8 @@ define <8 x float> @mgather_baseidx_sext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
; RV64ZVE32F-NEXT: .LBB88_12: # %else14
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -10270,9 +10078,8 @@ define <8 x float> @mgather_baseidx_sext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 6
; RV64ZVE32F-NEXT: .LBB88_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
@@ -10284,9 +10091,8 @@ define <8 x float> @mgather_baseidx_sext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: slli a1, a1, 2
; RV64ZVE32F-NEXT: add a0, a0, a1
; RV64ZVE32F-NEXT: flw fa5, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
; RV64ZVE32F-NEXT: .LBB88_16: # %else20
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
@@ -10304,7 +10110,7 @@ define <8 x float> @mgather_baseidx_zext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV32-NEXT: li a1, 4
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vwmulu.vx v12, v8, a1
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV32-NEXT: vluxei32.v v10, (a0), v12, v0.t
; RV32-NEXT: vmv.v.v v8, v10
; RV32-NEXT: ret
@@ -10314,7 +10120,7 @@ define <8 x float> @mgather_baseidx_zext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64V-NEXT: li a1, 4
; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64V-NEXT: vwmulu.vx v12, v8, a1
-; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV64V-NEXT: vluxei32.v v10, (a0), v12, v0.t
; RV64V-NEXT: vmv.v.v v8, v10
; RV64V-NEXT: ret
@@ -10326,13 +10132,13 @@ define <8 x float> @mgather_baseidx_zext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB89_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-NEXT: .LBB89_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
@@ -10345,9 +10151,8 @@ define <8 x float> @mgather_baseidx_zext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 1
; RV64ZVE32F-NEXT: .LBB89_4: # %else2
; RV64ZVE32F-NEXT: andi a2, a1, 4
@@ -10360,9 +10165,8 @@ define <8 x float> @mgather_baseidx_zext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
; RV64ZVE32F-NEXT: .LBB89_6: # %else5
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -10375,9 +10179,8 @@ define <8 x float> @mgather_baseidx_zext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
; RV64ZVE32F-NEXT: .LBB89_8: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 16
@@ -10390,9 +10193,8 @@ define <8 x float> @mgather_baseidx_zext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
; RV64ZVE32F-NEXT: .LBB89_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
@@ -10405,9 +10207,8 @@ define <8 x float> @mgather_baseidx_zext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
; RV64ZVE32F-NEXT: .LBB89_12: # %else14
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -10420,9 +10221,8 @@ define <8 x float> @mgather_baseidx_zext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 6
; RV64ZVE32F-NEXT: .LBB89_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
@@ -10435,9 +10235,8 @@ define <8 x float> @mgather_baseidx_zext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: srli a1, a1, 46
; RV64ZVE32F-NEXT: add a0, a0, a1
; RV64ZVE32F-NEXT: flw fa5, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
; RV64ZVE32F-NEXT: .LBB89_16: # %else20
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
@@ -10474,7 +10273,7 @@ define <8 x float> @mgather_baseidx_v8f32(ptr %base, <8 x i32> %idxs, <8 x i1> %
; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB90_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -10654,7 +10453,7 @@ define <2 x double> @mgather_v2f64(<2 x ptr> %ptrs, <2 x i1> %m, <2 x double> %p
; RV32ZVE32F-NEXT: .LBB92_2: # %else2
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB92_3: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v8
; RV32ZVE32F-NEXT: fld fa0, 0(a1)
; RV32ZVE32F-NEXT: andi a0, a0, 2
@@ -10732,7 +10531,7 @@ define <4 x double> @mgather_v4f64(<4 x ptr> %ptrs, <4 x i1> %m, <4 x double> %p
; RV32ZVE32F-NEXT: fsd fa3, 24(a0)
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB93_6: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a2, v8
; RV32ZVE32F-NEXT: fld fa0, 0(a2)
; RV32ZVE32F-NEXT: andi a2, a1, 2
@@ -10942,7 +10741,7 @@ define <8 x double> @mgather_v8f64(<8 x ptr> %ptrs, <8 x i1> %m, <8 x double> %p
; RV32ZVE32F-NEXT: fsd fa7, 56(a0)
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB96_10: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a2, v8
; RV32ZVE32F-NEXT: fld fa0, 0(a2)
; RV32ZVE32F-NEXT: andi a2, a1, 2
@@ -11077,7 +10876,7 @@ define <8 x double> @mgather_baseidx_v8i8_v8f64(ptr %base, <8 x i8> %idxs, <8 x
; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32V-NEXT: vsext.vf4 v10, v8
; RV32V-NEXT: vsll.vi v8, v10, 3
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32V-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32V-NEXT: vmv.v.v v8, v12
; RV32V-NEXT: ret
@@ -11095,9 +10894,9 @@ define <8 x double> @mgather_baseidx_v8i8_v8f64(ptr %base, <8 x i8> %idxs, <8 x
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsext.vf4 v10, v8
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a2, v0
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: andi a3, a2, 1
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
@@ -11287,7 +11086,7 @@ define <8 x double> @mgather_baseidx_sext_v8i8_v8f64(ptr %base, <8 x i8> %idxs,
; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32V-NEXT: vsext.vf4 v10, v8
; RV32V-NEXT: vsll.vi v8, v10, 3
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32V-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32V-NEXT: vmv.v.v v8, v12
; RV32V-NEXT: ret
@@ -11305,9 +11104,9 @@ define <8 x double> @mgather_baseidx_sext_v8i8_v8f64(ptr %base, <8 x i8> %idxs,
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsext.vf4 v10, v8
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a2, v0
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: andi a3, a2, 1
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
@@ -11498,7 +11297,7 @@ define <8 x double> @mgather_baseidx_zext_v8i8_v8f64(ptr %base, <8 x i8> %idxs,
; RV32V-NEXT: li a1, 8
; RV32V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32V-NEXT: vwmulu.vx v9, v8, a1
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32V-NEXT: vluxei16.v v12, (a0), v9, v0.t
; RV32V-NEXT: vmv.v.v v8, v12
; RV32V-NEXT: ret
@@ -11508,7 +11307,7 @@ define <8 x double> @mgather_baseidx_zext_v8i8_v8f64(ptr %base, <8 x i8> %idxs,
; RV64V-NEXT: li a1, 8
; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64V-NEXT: vwmulu.vx v9, v8, a1
-; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64V-NEXT: vluxei16.v v12, (a0), v9, v0.t
; RV64V-NEXT: vmv.v.v v8, v12
; RV64V-NEXT: ret
@@ -11517,9 +11316,9 @@ define <8 x double> @mgather_baseidx_zext_v8i8_v8f64(ptr %base, <8 x i8> %idxs,
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vzext.vf4 v10, v8
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a2, v0
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: andi a3, a2, 1
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
@@ -11718,7 +11517,7 @@ define <8 x double> @mgather_baseidx_v8i16_v8f64(ptr %base, <8 x i16> %idxs, <8
; RV32V-NEXT: li a1, 8
; RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32V-NEXT: vwmulsu.vx v10, v8, a1
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32V-NEXT: vluxei32.v v12, (a0), v10, v0.t
; RV32V-NEXT: vmv.v.v v8, v12
; RV32V-NEXT: ret
@@ -11737,10 +11536,10 @@ define <8 x double> @mgather_baseidx_v8i16_v8f64(ptr %base, <8 x i16> %idxs, <8
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.v.x v10, a1
; RV32ZVE32F-NEXT: li a2, 8
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi a3, a1, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32ZVE32F-NEXT: vwmaccus.vx v10, a2, v8
; RV32ZVE32F-NEXT: bnez a3, .LBB100_10
; RV32ZVE32F-NEXT: # %bb.1: # %else
@@ -11780,7 +11579,7 @@ define <8 x double> @mgather_baseidx_v8i16_v8f64(ptr %base, <8 x i16> %idxs, <8
; RV32ZVE32F-NEXT: fsd fa7, 56(a0)
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB100_10: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a2, v10
; RV32ZVE32F-NEXT: fld fa0, 0(a2)
; RV32ZVE32F-NEXT: andi a2, a1, 2
@@ -11836,7 +11635,7 @@ define <8 x double> @mgather_baseidx_v8i16_v8f64(ptr %base, <8 x i16> %idxs, <8
; RV64ZVE32F-NEXT: andi a3, a2, 1
; RV64ZVE32F-NEXT: beqz a3, .LBB100_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
@@ -11930,7 +11729,7 @@ define <8 x double> @mgather_baseidx_sext_v8i16_v8f64(ptr %base, <8 x i16> %idxs
; RV32V-NEXT: li a1, 8
; RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32V-NEXT: vwmulsu.vx v10, v8, a1
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32V-NEXT: vluxei32.v v12, (a0), v10, v0.t
; RV32V-NEXT: vmv.v.v v8, v12
; RV32V-NEXT: ret
@@ -11949,10 +11748,10 @@ define <8 x double> @mgather_baseidx_sext_v8i16_v8f64(ptr %base, <8 x i16> %idxs
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.v.x v10, a1
; RV32ZVE32F-NEXT: li a2, 8
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi a3, a1, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32ZVE32F-NEXT: vwmaccus.vx v10, a2, v8
; RV32ZVE32F-NEXT: bnez a3, .LBB101_10
; RV32ZVE32F-NEXT: # %bb.1: # %else
@@ -11992,7 +11791,7 @@ define <8 x double> @mgather_baseidx_sext_v8i16_v8f64(ptr %base, <8 x i16> %idxs
; RV32ZVE32F-NEXT: fsd fa7, 56(a0)
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB101_10: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a2, v10
; RV32ZVE32F-NEXT: fld fa0, 0(a2)
; RV32ZVE32F-NEXT: andi a2, a1, 2
@@ -12048,7 +11847,7 @@ define <8 x double> @mgather_baseidx_sext_v8i16_v8f64(ptr %base, <8 x i16> %idxs
; RV64ZVE32F-NEXT: andi a3, a2, 1
; RV64ZVE32F-NEXT: beqz a3, .LBB101_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
@@ -12143,7 +11942,7 @@ define <8 x double> @mgather_baseidx_zext_v8i16_v8f64(ptr %base, <8 x i16> %idxs
; RV32V-NEXT: li a1, 8
; RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32V-NEXT: vwmulu.vx v10, v8, a1
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32V-NEXT: vluxei32.v v12, (a0), v10, v0.t
; RV32V-NEXT: vmv.v.v v8, v12
; RV32V-NEXT: ret
@@ -12153,7 +11952,7 @@ define <8 x double> @mgather_baseidx_zext_v8i16_v8f64(ptr %base, <8 x i16> %idxs
; RV64V-NEXT: li a1, 8
; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64V-NEXT: vwmulu.vx v10, v8, a1
-; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64V-NEXT: vluxei32.v v12, (a0), v10, v0.t
; RV64V-NEXT: vmv.v.v v8, v12
; RV64V-NEXT: ret
@@ -12163,10 +11962,10 @@ define <8 x double> @mgather_baseidx_zext_v8i16_v8f64(ptr %base, <8 x i16> %idxs
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.v.x v10, a1
; RV32ZVE32F-NEXT: li a2, 8
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi a3, a1, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32ZVE32F-NEXT: vwmaccu.vx v10, a2, v8
; RV32ZVE32F-NEXT: bnez a3, .LBB102_10
; RV32ZVE32F-NEXT: # %bb.1: # %else
@@ -12206,7 +12005,7 @@ define <8 x double> @mgather_baseidx_zext_v8i16_v8f64(ptr %base, <8 x i16> %idxs
; RV32ZVE32F-NEXT: fsd fa7, 56(a0)
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB102_10: # %cond.load
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a2, v10
; RV32ZVE32F-NEXT: fld fa0, 0(a2)
; RV32ZVE32F-NEXT: andi a2, a1, 2
@@ -12262,7 +12061,7 @@ define <8 x double> @mgather_baseidx_zext_v8i16_v8f64(ptr %base, <8 x i16> %idxs
; RV64ZVE32F-NEXT: andi a3, a2, 1
; RV64ZVE32F-NEXT: beqz a3, .LBB102_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 48
; RV64ZVE32F-NEXT: srli a3, a3, 45
@@ -12364,7 +12163,7 @@ define <8 x double> @mgather_baseidx_v8i32_v8f64(ptr %base, <8 x i32> %idxs, <8
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32V-NEXT: vsll.vi v8, v8, 3
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32V-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32V-NEXT: vmv.v.v v8, v12
; RV32V-NEXT: ret
@@ -12374,7 +12173,7 @@ define <8 x double> @mgather_baseidx_v8i32_v8f64(ptr %base, <8 x i32> %idxs, <8
; RV64V-NEXT: li a1, 8
; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64V-NEXT: vwmulsu.vx v16, v8, a1
-; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64V-NEXT: vluxei64.v v12, (a0), v16, v0.t
; RV64V-NEXT: vmv.v.v v8, v12
; RV64V-NEXT: ret
@@ -12383,10 +12182,10 @@ define <8 x double> @mgather_baseidx_v8i32_v8f64(ptr %base, <8 x i32> %idxs, <8
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a2, v0
; RV32ZVE32F-NEXT: andi a3, a2, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
; RV32ZVE32F-NEXT: bnez a3, .LBB103_10
; RV32ZVE32F-NEXT: # %bb.1: # %else
@@ -12481,7 +12280,7 @@ define <8 x double> @mgather_baseidx_v8i32_v8f64(ptr %base, <8 x i32> %idxs, <8
; RV64ZVE32F-NEXT: andi a3, a2, 1
; RV64ZVE32F-NEXT: beqz a3, .LBB103_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
@@ -12581,7 +12380,7 @@ define <8 x double> @mgather_baseidx_sext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32V-NEXT: vsll.vi v8, v8, 3
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32V-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32V-NEXT: vmv.v.v v8, v12
; RV32V-NEXT: ret
@@ -12591,7 +12390,7 @@ define <8 x double> @mgather_baseidx_sext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
; RV64V-NEXT: li a1, 8
; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64V-NEXT: vwmulsu.vx v16, v8, a1
-; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64V-NEXT: vluxei64.v v12, (a0), v16, v0.t
; RV64V-NEXT: vmv.v.v v8, v12
; RV64V-NEXT: ret
@@ -12600,10 +12399,10 @@ define <8 x double> @mgather_baseidx_sext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a2, v0
; RV32ZVE32F-NEXT: andi a3, a2, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
; RV32ZVE32F-NEXT: bnez a3, .LBB104_10
; RV32ZVE32F-NEXT: # %bb.1: # %else
@@ -12698,7 +12497,7 @@ define <8 x double> @mgather_baseidx_sext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
; RV64ZVE32F-NEXT: andi a3, a2, 1
; RV64ZVE32F-NEXT: beqz a3, .LBB104_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
@@ -12799,7 +12598,7 @@ define <8 x double> @mgather_baseidx_zext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32V-NEXT: vsll.vi v8, v8, 3
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32V-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32V-NEXT: vmv.v.v v8, v12
; RV32V-NEXT: ret
@@ -12809,7 +12608,7 @@ define <8 x double> @mgather_baseidx_zext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
; RV64V-NEXT: li a1, 8
; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64V-NEXT: vwmulu.vx v16, v8, a1
-; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64V-NEXT: vluxei64.v v12, (a0), v16, v0.t
; RV64V-NEXT: vmv.v.v v8, v12
; RV64V-NEXT: ret
@@ -12818,10 +12617,10 @@ define <8 x double> @mgather_baseidx_zext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a2, v0
; RV32ZVE32F-NEXT: andi a3, a2, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
; RV32ZVE32F-NEXT: bnez a3, .LBB105_10
; RV32ZVE32F-NEXT: # %bb.1: # %else
@@ -12916,7 +12715,7 @@ define <8 x double> @mgather_baseidx_zext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
; RV64ZVE32F-NEXT: andi a3, a2, 1
; RV64ZVE32F-NEXT: beqz a3, .LBB105_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 32
; RV64ZVE32F-NEXT: srli a3, a3, 29
@@ -13026,7 +12825,7 @@ define <8 x double> @mgather_baseidx_v8f64(ptr %base, <8 x i64> %idxs, <8 x i1>
; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32V-NEXT: vnsrl.wi v16, v8, 0
; RV32V-NEXT: vsll.vi v8, v16, 3
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32V-NEXT: vluxei32.v v12, (a0), v8, v0.t
; RV32V-NEXT: vmv.v.v v8, v12
; RV32V-NEXT: ret
@@ -13051,9 +12850,9 @@ define <8 x double> @mgather_baseidx_v8f64(ptr %base, <8 x i64> %idxs, <8 x i1>
; RV32ZVE32F-NEXT: lw t2, 24(a2)
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.v.x v8, a7
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a2, v0
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, t0
; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, t1
; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, t2
@@ -13254,7 +13053,7 @@ define <16 x i8> @mgather_baseidx_v16i8(ptr %base, <16 x i8> %idxs, <16 x i1> %m
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vsext.vf4 v12, v8
-; RV32-NEXT: vsetvli zero, zero, e8, m1, ta, mu
+; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV32-NEXT: vluxei32.v v9, (a0), v12, v0.t
; RV32-NEXT: vmv.v.v v8, v9
; RV32-NEXT: ret
@@ -13263,7 +13062,7 @@ define <16 x i8> @mgather_baseidx_v16i8(ptr %base, <16 x i8> %idxs, <16 x i1> %m
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64V-NEXT: vsext.vf8 v16, v8
-; RV64V-NEXT: vsetvli zero, zero, e8, m1, ta, mu
+; RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV64V-NEXT: vluxei64.v v9, (a0), v16, v0.t
; RV64V-NEXT: vmv.v.v v8, v9
; RV64V-NEXT: ret
@@ -13275,7 +13074,7 @@ define <16 x i8> @mgather_baseidx_v16i8(ptr %base, <16 x i8> %idxs, <16 x i1> %m
; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB107_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf2, tu, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
@@ -13496,7 +13295,7 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m
; RV64V-NEXT: vslidedown.vi v0, v0, 2
; RV64V-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64V-NEXT: vsext.vf8 v16, v8
-; RV64V-NEXT: vsetvli zero, zero, e8, m1, ta, mu
+; RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV64V-NEXT: vluxei64.v v12, (a0), v16, v0.t
; RV64V-NEXT: li a0, 32
; RV64V-NEXT: vsetvli zero, a0, e8, m2, ta, ma
@@ -13511,7 +13310,7 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m
; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB108_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, mf4, tu, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, tu, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
@@ -13520,7 +13319,7 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m
; RV64ZVE32F-NEXT: andi a2, a1, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB108_4
; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v12
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -14007,7 +13806,7 @@ define <4 x i32> @mgather_narrow_edge_case(ptr %base) {
; RV64V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64V-NEXT: vmv.v.x v8, a1
; RV64V-NEXT: vmerge.vim v10, v8, 0, v0
-; RV64V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64V-NEXT: vluxei64.v v8, (a0), v10
; RV64V-NEXT: ret
;
@@ -15273,7 +15072,7 @@ define <7 x i8> @mgather_baseidx_v7i8(ptr %base, <7 x i8> %idxs, <7 x i1> %m, <7
; RV32-NEXT: vmv.s.x v10, a1
; RV32-NEXT: vmand.mm v0, v0, v10
; RV32-NEXT: vsext.vf4 v10, v8
-; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
+; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vluxei32.v v9, (a0), v10, v0.t
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
@@ -15285,7 +15084,7 @@ define <7 x i8> @mgather_baseidx_v7i8(ptr %base, <7 x i8> %idxs, <7 x i1> %m, <7
; RV64V-NEXT: vmv.s.x v10, a1
; RV64V-NEXT: vmand.mm v0, v0, v10
; RV64V-NEXT: vsext.vf8 v12, v8
-; RV64V-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
+; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64V-NEXT: vluxei64.v v9, (a0), v12, v0.t
; RV64V-NEXT: vmv1r.v v8, v9
; RV64V-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
index e86fae6d501e5..16add56538260 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
@@ -152,7 +152,7 @@ define void @mscatter_v2i32_truncstore_v2i8(<2 x i32> %val, <2 x ptr> %ptrs, <2
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV32V-NEXT: vnsrl.wi v8, v8, 0
-; RV32V-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; RV32V-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; RV32V-NEXT: vnsrl.wi v8, v8, 0
; RV32V-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32V-NEXT: ret
@@ -161,7 +161,7 @@ define void @mscatter_v2i32_truncstore_v2i8(<2 x i32> %val, <2 x ptr> %ptrs, <2
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV64V-NEXT: vnsrl.wi v8, v8, 0
-; RV64V-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; RV64V-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; RV64V-NEXT: vnsrl.wi v8, v8, 0
; RV64V-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64V-NEXT: ret
@@ -170,7 +170,7 @@ define void @mscatter_v2i32_truncstore_v2i8(<2 x i32> %val, <2 x ptr> %ptrs, <2
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV32ZVE32F-NEXT: vnsrl.wi v8, v8, 0
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32ZVE32F-NEXT: vnsrl.wi v8, v8, 0
; RV32ZVE32F-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32ZVE32F-NEXT: ret
@@ -179,7 +179,7 @@ define void @mscatter_v2i32_truncstore_v2i8(<2 x i32> %val, <2 x ptr> %ptrs, <2
; RV64ZVE32F: # %bb.0:
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vnsrl.wi v8, v8, 0
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v0
; RV64ZVE32F-NEXT: andi a3, a2, 1
; RV64ZVE32F-NEXT: vnsrl.wi v8, v8, 0
@@ -209,9 +209,9 @@ define void @mscatter_v2i64_truncstore_v2i8(<2 x i64> %val, <2 x ptr> %ptrs, <2
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV32V-NEXT: vnsrl.wi v8, v8, 0
-; RV32V-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; RV32V-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV32V-NEXT: vnsrl.wi v8, v8, 0
-; RV32V-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; RV32V-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; RV32V-NEXT: vnsrl.wi v8, v8, 0
; RV32V-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32V-NEXT: ret
@@ -220,9 +220,9 @@ define void @mscatter_v2i64_truncstore_v2i8(<2 x i64> %val, <2 x ptr> %ptrs, <2
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64V-NEXT: vnsrl.wi v8, v8, 0
-; RV64V-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; RV64V-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV64V-NEXT: vnsrl.wi v8, v8, 0
-; RV64V-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; RV64V-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; RV64V-NEXT: vnsrl.wi v8, v8, 0
; RV64V-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64V-NEXT: ret
@@ -476,7 +476,7 @@ define void @mscatter_baseidx_v8i8(<8 x i8> %val, ptr %base, <8 x i8> %idxs, <8
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vsext.vf4 v10, v9
-; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
@@ -484,7 +484,7 @@ define void @mscatter_baseidx_v8i8(<8 x i8> %val, ptr %base, <8 x i8> %idxs, <8
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf8 v12, v9
-; RV64V-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64V-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64V-NEXT: ret
;
@@ -722,7 +722,7 @@ define void @mscatter_v2i64_truncstore_v2i16(<2 x i64> %val, <2 x ptr> %ptrs, <2
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV32V-NEXT: vnsrl.wi v8, v8, 0
-; RV32V-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; RV32V-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV32V-NEXT: vnsrl.wi v8, v8, 0
; RV32V-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32V-NEXT: ret
@@ -731,7 +731,7 @@ define void @mscatter_v2i64_truncstore_v2i16(<2 x i64> %val, <2 x ptr> %ptrs, <2
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64V-NEXT: vnsrl.wi v8, v8, 0
-; RV64V-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; RV64V-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV64V-NEXT: vnsrl.wi v8, v8, 0
; RV64V-NEXT: vsoxei64.v v8, (zero), v9, v0.t
; RV64V-NEXT: ret
@@ -752,7 +752,7 @@ define void @mscatter_v2i64_truncstore_v2i16(<2 x i64> %val, <2 x ptr> %ptrs, <2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.s.x v9, a1
; RV64ZVE32F-NEXT: vmv.s.x v8, a0
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a0, v0
; RV64ZVE32F-NEXT: andi a1, a0, 1
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
@@ -988,7 +988,7 @@ define void @mscatter_baseidx_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i8> %id
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vsext.vf4 v10, v9
; RV32-NEXT: vadd.vv v10, v10, v10
-; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
@@ -997,7 +997,7 @@ define void @mscatter_baseidx_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i8> %id
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf8 v12, v9
; RV64V-NEXT: vadd.vv v12, v12, v12
-; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64V-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64V-NEXT: ret
;
@@ -1058,9 +1058,8 @@ define void @mscatter_baseidx_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i8> %id
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: vse16.v v10, (a2)
; RV64ZVE32F-NEXT: .LBB18_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
@@ -1114,7 +1113,7 @@ define void @mscatter_baseidx_sext_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i8
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vsext.vf4 v10, v9
; RV32-NEXT: vadd.vv v10, v10, v10
-; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
@@ -1123,7 +1122,7 @@ define void @mscatter_baseidx_sext_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i8
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf8 v12, v9
; RV64V-NEXT: vadd.vv v12, v12, v12
-; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64V-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64V-NEXT: ret
;
@@ -1184,9 +1183,8 @@ define void @mscatter_baseidx_sext_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: vse16.v v10, (a2)
; RV64ZVE32F-NEXT: .LBB19_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
@@ -1240,7 +1238,7 @@ define void @mscatter_baseidx_zext_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i8
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vwaddu.vv v10, v9, v9
-; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vsoxei16.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
@@ -1248,7 +1246,7 @@ define void @mscatter_baseidx_zext_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i8
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64V-NEXT: vwaddu.vv v10, v9, v9
-; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64V-NEXT: vsoxei16.v v8, (a0), v10, v0.t
; RV64V-NEXT: ret
;
@@ -1314,9 +1312,8 @@ define void @mscatter_baseidx_zext_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: vse16.v v10, (a2)
; RV64ZVE32F-NEXT: .LBB20_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
@@ -1381,7 +1378,7 @@ define void @mscatter_baseidx_v8i16(<8 x i16> %val, ptr %base, <8 x i16> %idxs,
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf4 v12, v9
; RV64V-NEXT: vadd.vv v12, v12, v12
-; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64V-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64V-NEXT: ret
;
@@ -1601,10 +1598,10 @@ define void @mscatter_v2i64_truncstore_v2i32(<2 x i64> %val, <2 x ptr> %ptrs, <2
; RV64ZVE32F: # %bb.0:
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.v.x v8, a0
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a0, v0
; RV64ZVE32F-NEXT: andi a4, a0, 1
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a1
; RV64ZVE32F-NEXT: bnez a4, .LBB24_3
; RV64ZVE32F-NEXT: # %bb.1: # %else
@@ -1849,7 +1846,7 @@ define void @mscatter_baseidx_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8> %id
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf8 v12, v10
; RV64V-NEXT: vsll.vi v12, v12, 2
-; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64V-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64V-NEXT: ret
;
@@ -1874,7 +1871,7 @@ define void @mscatter_baseidx_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8> %id
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 1
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
; RV64ZVE32F-NEXT: .LBB29_4: # %else2
@@ -1886,9 +1883,8 @@ define void @mscatter_baseidx_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8> %id
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
; RV64ZVE32F-NEXT: .LBB29_6: # %else4
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -1899,7 +1895,7 @@ define void @mscatter_baseidx_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8> %id
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
; RV64ZVE32F-NEXT: .LBB29_8: # %else6
@@ -1911,7 +1907,7 @@ define void @mscatter_baseidx_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8> %id
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
@@ -1978,7 +1974,7 @@ define void @mscatter_baseidx_sext_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf8 v12, v10
; RV64V-NEXT: vsll.vi v12, v12, 2
-; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64V-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64V-NEXT: ret
;
@@ -2003,7 +1999,7 @@ define void @mscatter_baseidx_sext_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 1
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
; RV64ZVE32F-NEXT: .LBB30_4: # %else2
@@ -2015,9 +2011,8 @@ define void @mscatter_baseidx_sext_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
; RV64ZVE32F-NEXT: .LBB30_6: # %else4
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -2028,7 +2023,7 @@ define void @mscatter_baseidx_sext_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
; RV64ZVE32F-NEXT: .LBB30_8: # %else6
@@ -2040,7 +2035,7 @@ define void @mscatter_baseidx_sext_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
@@ -2100,7 +2095,7 @@ define void @mscatter_baseidx_zext_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8
; RV32-NEXT: li a1, 4
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vwmulu.vx v11, v10, a1
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vsoxei16.v v8, (a0), v11, v0.t
; RV32-NEXT: ret
;
@@ -2109,7 +2104,7 @@ define void @mscatter_baseidx_zext_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8
; RV64V-NEXT: li a1, 4
; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64V-NEXT: vwmulu.vx v11, v10, a1
-; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64V-NEXT: vsoxei16.v v8, (a0), v11, v0.t
; RV64V-NEXT: ret
;
@@ -2136,7 +2131,7 @@ define void @mscatter_baseidx_zext_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 1
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
; RV64ZVE32F-NEXT: .LBB31_4: # %else2
@@ -2149,9 +2144,8 @@ define void @mscatter_baseidx_zext_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
; RV64ZVE32F-NEXT: .LBB31_6: # %else4
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -2163,7 +2157,7 @@ define void @mscatter_baseidx_zext_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
; RV64ZVE32F-NEXT: .LBB31_8: # %else6
@@ -2176,7 +2170,7 @@ define void @mscatter_baseidx_zext_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
@@ -2239,7 +2233,7 @@ define void @mscatter_baseidx_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i16> %
; RV32-NEXT: li a1, 4
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vwmulsu.vx v12, v10, a1
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
@@ -2248,7 +2242,7 @@ define void @mscatter_baseidx_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i16> %
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf4 v12, v10
; RV64V-NEXT: vsll.vi v12, v12, 2
-; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64V-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64V-NEXT: ret
;
@@ -2259,7 +2253,7 @@ define void @mscatter_baseidx_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i16> %
; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB32_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -2274,7 +2268,7 @@ define void @mscatter_baseidx_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i16> %
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 1
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
; RV64ZVE32F-NEXT: .LBB32_4: # %else2
@@ -2286,9 +2280,8 @@ define void @mscatter_baseidx_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i16> %
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
; RV64ZVE32F-NEXT: .LBB32_6: # %else4
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -2299,7 +2292,7 @@ define void @mscatter_baseidx_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i16> %
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
; RV64ZVE32F-NEXT: .LBB32_8: # %else6
@@ -2311,7 +2304,7 @@ define void @mscatter_baseidx_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i16> %
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
@@ -2370,7 +2363,7 @@ define void @mscatter_baseidx_sext_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i
; RV32-NEXT: li a1, 4
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vwmulsu.vx v12, v10, a1
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
@@ -2379,7 +2372,7 @@ define void @mscatter_baseidx_sext_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf4 v12, v10
; RV64V-NEXT: vsll.vi v12, v12, 2
-; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64V-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64V-NEXT: ret
;
@@ -2390,7 +2383,7 @@ define void @mscatter_baseidx_sext_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB33_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -2405,7 +2398,7 @@ define void @mscatter_baseidx_sext_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 1
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
; RV64ZVE32F-NEXT: .LBB33_4: # %else2
@@ -2417,9 +2410,8 @@ define void @mscatter_baseidx_sext_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
; RV64ZVE32F-NEXT: .LBB33_6: # %else4
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -2430,7 +2422,7 @@ define void @mscatter_baseidx_sext_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
; RV64ZVE32F-NEXT: .LBB33_8: # %else6
@@ -2442,7 +2434,7 @@ define void @mscatter_baseidx_sext_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
@@ -2502,7 +2494,7 @@ define void @mscatter_baseidx_zext_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i
; RV32-NEXT: li a1, 4
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vwmulu.vx v12, v10, a1
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
@@ -2511,7 +2503,7 @@ define void @mscatter_baseidx_zext_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i
; RV64V-NEXT: li a1, 4
; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64V-NEXT: vwmulu.vx v12, v10, a1
-; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64V-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV64V-NEXT: ret
;
@@ -2522,7 +2514,7 @@ define void @mscatter_baseidx_zext_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB34_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 46
@@ -2539,7 +2531,7 @@ define void @mscatter_baseidx_zext_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 1
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
; RV64ZVE32F-NEXT: .LBB34_4: # %else2
@@ -2552,9 +2544,8 @@ define void @mscatter_baseidx_zext_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
; RV64ZVE32F-NEXT: .LBB34_6: # %else4
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -2566,7 +2557,7 @@ define void @mscatter_baseidx_zext_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
; RV64ZVE32F-NEXT: .LBB34_8: # %else6
@@ -2579,7 +2570,7 @@ define void @mscatter_baseidx_zext_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
@@ -2837,7 +2828,7 @@ define void @mscatter_v2i64(<2 x i64> %val, <2 x ptr> %ptrs, <2 x i1> %m) {
; RV32ZVE32F-NEXT: .LBB37_3: # %cond.store
; RV32ZVE32F-NEXT: lw a4, 0(a0)
; RV32ZVE32F-NEXT: lw a0, 4(a0)
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a5, v8
; RV32ZVE32F-NEXT: sw a4, 0(a5)
; RV32ZVE32F-NEXT: sw a0, 4(a5)
@@ -2914,7 +2905,7 @@ define void @mscatter_v4i64(<4 x i64> %val, <4 x ptr> %ptrs, <4 x i1> %m) {
; RV32ZVE32F-NEXT: .LBB38_5: # %cond.store
; RV32ZVE32F-NEXT: lw t0, 0(a0)
; RV32ZVE32F-NEXT: lw a0, 4(a0)
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t1, v8
; RV32ZVE32F-NEXT: sw t0, 0(t1)
; RV32ZVE32F-NEXT: sw a0, 4(t1)
@@ -3141,7 +3132,7 @@ define void @mscatter_v8i64(<8 x i64> %val, <8 x ptr> %ptrs, <8 x i1> %m) {
; RV32ZVE32F-NEXT: .cfi_restore_state
; RV32ZVE32F-NEXT: lw s1, 0(a0)
; RV32ZVE32F-NEXT: lw a0, 4(a0)
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s s2, v8
; RV32ZVE32F-NEXT: sw s1, 0(s2)
; RV32ZVE32F-NEXT: sw a0, 4(s2)
@@ -3301,7 +3292,7 @@ define void @mscatter_baseidx_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8> %id
; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32V-NEXT: vsext.vf4 v14, v12
; RV32V-NEXT: vsll.vi v12, v14, 3
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32V-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32V-NEXT: ret
;
@@ -3341,10 +3332,10 @@ define void @mscatter_baseidx_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8> %id
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsext.vf4 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t0, v0
; RV32ZVE32F-NEXT: andi s2, t0, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
; RV32ZVE32F-NEXT: bnez s2, .LBB42_10
; RV32ZVE32F-NEXT: # %bb.1: # %else
@@ -3546,7 +3537,7 @@ define void @mscatter_baseidx_sext_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8
; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32V-NEXT: vsext.vf4 v14, v12
; RV32V-NEXT: vsll.vi v12, v14, 3
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32V-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32V-NEXT: ret
;
@@ -3586,10 +3577,10 @@ define void @mscatter_baseidx_sext_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsext.vf4 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t0, v0
; RV32ZVE32F-NEXT: andi s2, t0, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
; RV32ZVE32F-NEXT: bnez s2, .LBB43_10
; RV32ZVE32F-NEXT: # %bb.1: # %else
@@ -3792,7 +3783,7 @@ define void @mscatter_baseidx_zext_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8
; RV32V-NEXT: li a1, 8
; RV32V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32V-NEXT: vwmulu.vx v13, v12, a1
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32V-NEXT: vsoxei16.v v8, (a0), v13, v0.t
; RV32V-NEXT: ret
;
@@ -3801,7 +3792,7 @@ define void @mscatter_baseidx_zext_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8
; RV64V-NEXT: li a1, 8
; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64V-NEXT: vwmulu.vx v13, v12, a1
-; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsoxei16.v v8, (a0), v13, v0.t
; RV64V-NEXT: ret
;
@@ -3833,10 +3824,10 @@ define void @mscatter_baseidx_zext_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vzext.vf4 v10, v8
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t0, v0
; RV32ZVE32F-NEXT: andi s2, t0, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
; RV32ZVE32F-NEXT: bnez s2, .LBB44_10
; RV32ZVE32F-NEXT: # %bb.1: # %else
@@ -4047,7 +4038,7 @@ define void @mscatter_baseidx_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i16> %
; RV32V-NEXT: li a1, 8
; RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32V-NEXT: vwmulsu.vx v14, v12, a1
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32V-NEXT: vsoxei32.v v8, (a0), v14, v0.t
; RV32V-NEXT: ret
;
@@ -4087,10 +4078,10 @@ define void @mscatter_baseidx_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i16> %
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.v.x v10, a1
; RV32ZVE32F-NEXT: li s1, 8
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi s2, a1, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32ZVE32F-NEXT: vwmaccus.vx v10, s1, v8
; RV32ZVE32F-NEXT: bnez s2, .LBB45_10
; RV32ZVE32F-NEXT: # %bb.1: # %else
@@ -4134,7 +4125,7 @@ define void @mscatter_baseidx_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i16> %
; RV32ZVE32F-NEXT: .cfi_restore_state
; RV32ZVE32F-NEXT: lw s1, 0(a0)
; RV32ZVE32F-NEXT: lw a0, 4(a0)
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s s2, v10
; RV32ZVE32F-NEXT: sw s1, 0(s2)
; RV32ZVE32F-NEXT: sw a0, 4(s2)
@@ -4205,7 +4196,7 @@ define void @mscatter_baseidx_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i16> %
; RV64ZVE32F-NEXT: beqz t2, .LBB45_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
; RV64ZVE32F-NEXT: ld a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s t2, v8
; RV64ZVE32F-NEXT: slli t2, t2, 3
; RV64ZVE32F-NEXT: add t2, a1, t2
@@ -4294,7 +4285,7 @@ define void @mscatter_baseidx_sext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV32V-NEXT: li a1, 8
; RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32V-NEXT: vwmulsu.vx v14, v12, a1
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32V-NEXT: vsoxei32.v v8, (a0), v14, v0.t
; RV32V-NEXT: ret
;
@@ -4334,10 +4325,10 @@ define void @mscatter_baseidx_sext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.v.x v10, a1
; RV32ZVE32F-NEXT: li s1, 8
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi s2, a1, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32ZVE32F-NEXT: vwmaccus.vx v10, s1, v8
; RV32ZVE32F-NEXT: bnez s2, .LBB46_10
; RV32ZVE32F-NEXT: # %bb.1: # %else
@@ -4381,7 +4372,7 @@ define void @mscatter_baseidx_sext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV32ZVE32F-NEXT: .cfi_restore_state
; RV32ZVE32F-NEXT: lw s1, 0(a0)
; RV32ZVE32F-NEXT: lw a0, 4(a0)
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s s2, v10
; RV32ZVE32F-NEXT: sw s1, 0(s2)
; RV32ZVE32F-NEXT: sw a0, 4(s2)
@@ -4452,7 +4443,7 @@ define void @mscatter_baseidx_sext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: beqz t2, .LBB46_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
; RV64ZVE32F-NEXT: ld a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s t2, v8
; RV64ZVE32F-NEXT: slli t2, t2, 3
; RV64ZVE32F-NEXT: add t2, a1, t2
@@ -4542,7 +4533,7 @@ define void @mscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV32V-NEXT: li a1, 8
; RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32V-NEXT: vwmulu.vx v14, v12, a1
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32V-NEXT: vsoxei32.v v8, (a0), v14, v0.t
; RV32V-NEXT: ret
;
@@ -4551,7 +4542,7 @@ define void @mscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV64V-NEXT: li a1, 8
; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64V-NEXT: vwmulu.vx v14, v12, a1
-; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsoxei32.v v8, (a0), v14, v0.t
; RV64V-NEXT: ret
;
@@ -4583,10 +4574,10 @@ define void @mscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.v.x v10, a1
; RV32ZVE32F-NEXT: li s1, 8
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi s2, a1, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32ZVE32F-NEXT: vwmaccu.vx v10, s1, v8
; RV32ZVE32F-NEXT: bnez s2, .LBB47_10
; RV32ZVE32F-NEXT: # %bb.1: # %else
@@ -4630,7 +4621,7 @@ define void @mscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV32ZVE32F-NEXT: .cfi_restore_state
; RV32ZVE32F-NEXT: lw s1, 0(a0)
; RV32ZVE32F-NEXT: lw a0, 4(a0)
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s s2, v10
; RV32ZVE32F-NEXT: sw s1, 0(s2)
; RV32ZVE32F-NEXT: sw a0, 4(s2)
@@ -4701,7 +4692,7 @@ define void @mscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: beqz t2, .LBB47_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
; RV64ZVE32F-NEXT: ld a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s t2, v8
; RV64ZVE32F-NEXT: slli t2, t2, 48
; RV64ZVE32F-NEXT: srli t2, t2, 45
@@ -4798,7 +4789,7 @@ define void @mscatter_baseidx_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i32> %
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32V-NEXT: vsll.vi v12, v12, 3
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32V-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32V-NEXT: ret
;
@@ -4807,7 +4798,7 @@ define void @mscatter_baseidx_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i32> %
; RV64V-NEXT: li a1, 8
; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64V-NEXT: vwmulsu.vx v16, v12, a1
-; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64V-NEXT: ret
;
@@ -4838,10 +4829,10 @@ define void @mscatter_baseidx_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i32> %
; RV32ZVE32F-NEXT: lw t6, 20(a0)
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t0, v0
; RV32ZVE32F-NEXT: andi s2, t0, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
; RV32ZVE32F-NEXT: bnez s2, .LBB48_10
; RV32ZVE32F-NEXT: # %bb.1: # %else
@@ -4955,7 +4946,7 @@ define void @mscatter_baseidx_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i32> %
; RV64ZVE32F-NEXT: beqz t2, .LBB48_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
; RV64ZVE32F-NEXT: ld a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s t2, v8
; RV64ZVE32F-NEXT: slli t2, t2, 3
; RV64ZVE32F-NEXT: add t2, a1, t2
@@ -5050,7 +5041,7 @@ define void @mscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32V-NEXT: vsll.vi v12, v12, 3
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32V-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32V-NEXT: ret
;
@@ -5059,7 +5050,7 @@ define void @mscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV64V-NEXT: li a1, 8
; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64V-NEXT: vwmulsu.vx v16, v12, a1
-; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64V-NEXT: ret
;
@@ -5090,10 +5081,10 @@ define void @mscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV32ZVE32F-NEXT: lw t6, 20(a0)
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t0, v0
; RV32ZVE32F-NEXT: andi s2, t0, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
; RV32ZVE32F-NEXT: bnez s2, .LBB49_10
; RV32ZVE32F-NEXT: # %bb.1: # %else
@@ -5207,7 +5198,7 @@ define void @mscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: beqz t2, .LBB49_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
; RV64ZVE32F-NEXT: ld a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s t2, v8
; RV64ZVE32F-NEXT: slli t2, t2, 3
; RV64ZVE32F-NEXT: add t2, a1, t2
@@ -5303,7 +5294,7 @@ define void @mscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32V-NEXT: vsll.vi v12, v12, 3
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32V-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32V-NEXT: ret
;
@@ -5312,7 +5303,7 @@ define void @mscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV64V-NEXT: li a1, 8
; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64V-NEXT: vwmulu.vx v16, v12, a1
-; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64V-NEXT: ret
;
@@ -5343,10 +5334,10 @@ define void @mscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV32ZVE32F-NEXT: lw t6, 20(a0)
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s t0, v0
; RV32ZVE32F-NEXT: andi s2, t0, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
; RV32ZVE32F-NEXT: bnez s2, .LBB50_10
; RV32ZVE32F-NEXT: # %bb.1: # %else
@@ -5460,7 +5451,7 @@ define void @mscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: beqz t2, .LBB50_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
; RV64ZVE32F-NEXT: ld a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s t2, v8
; RV64ZVE32F-NEXT: slli t2, t2, 32
; RV64ZVE32F-NEXT: srli t2, t2, 29
@@ -5565,7 +5556,7 @@ define void @mscatter_baseidx_v8i64(<8 x i64> %val, ptr %base, <8 x i64> %idxs,
; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32V-NEXT: vnsrl.wi v16, v12, 0
; RV32V-NEXT: vsll.vi v12, v16, 3
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32V-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32V-NEXT: ret
;
@@ -5625,9 +5616,9 @@ define void @mscatter_baseidx_v8i64(<8 x i64> %val, ptr %base, <8 x i64> %idxs,
; RV32ZVE32F-NEXT: lw s9, 24(a2)
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.v.x v8, s6
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a2, v0
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, s7
; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, s8
; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, s9
@@ -5938,7 +5929,7 @@ define void @mscatter_v2bf16(<2 x bfloat> %val, <2 x ptr> %ptrs, <2 x i1> %m) {
; RV64ZVE32F-NEXT: .LBB53_2: # %else2
; RV64ZVE32F-NEXT: ret
; RV64ZVE32F-NEXT: .LBB53_3: # %cond.store
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: fmv.h.x fa5, a3
; RV64ZVE32F-NEXT: fsh fa5, 0(a0)
@@ -5992,7 +5983,7 @@ define void @mscatter_v4bf16(<4 x bfloat> %val, <4 x ptr> %ptrs, <4 x i1> %m) {
; RV64ZVE32F-NEXT: ret
; RV64ZVE32F-NEXT: .LBB54_5: # %cond.store
; RV64ZVE32F-NEXT: ld a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a5, v8
; RV64ZVE32F-NEXT: fmv.h.x fa5, a5
; RV64ZVE32F-NEXT: fsh fa5, 0(a0)
@@ -6126,7 +6117,7 @@ define void @mscatter_v8bf16(<8 x bfloat> %val, <8 x ptr> %ptrs, <8 x i1> %m) {
; RV64ZVE32F-NEXT: ret
; RV64ZVE32F-NEXT: .LBB57_9: # %cond.store
; RV64ZVE32F-NEXT: ld a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s t1, v8
; RV64ZVE32F-NEXT: fmv.h.x fa5, t1
; RV64ZVE32F-NEXT: fsh fa5, 0(a0)
@@ -6197,7 +6188,7 @@ define void @mscatter_baseidx_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8 x i8>
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vsext.vf4 v10, v9
; RV32-NEXT: vadd.vv v10, v10, v10
-; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
@@ -6206,7 +6197,7 @@ define void @mscatter_baseidx_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8 x i8>
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf8 v12, v9
; RV64V-NEXT: vadd.vv v12, v12, v12
-; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64V-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64V-NEXT: ret
;
@@ -6218,7 +6209,7 @@ define void @mscatter_baseidx_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8 x i8>
; RV64ZVE32F-NEXT: beqz a2, .LBB58_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -6273,7 +6264,7 @@ define void @mscatter_baseidx_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8 x i8>
; RV64ZVE32F-NEXT: beqz a2, .LBB58_10
; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: vmv.x.s a3, v10
@@ -6320,11 +6311,11 @@ define void @mscatter_baseidx_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8 x i8>
; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v9
; RV64ZVE32F-NEXT: slli a1, a1, 1
; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: fmv.h.x fa5, a1
; RV64ZVE32F-NEXT: fsh fa5, 0(a0)
@@ -6340,7 +6331,7 @@ define void @mscatter_baseidx_sext_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vsext.vf4 v10, v9
; RV32-NEXT: vadd.vv v10, v10, v10
-; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
@@ -6349,7 +6340,7 @@ define void @mscatter_baseidx_sext_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf8 v12, v9
; RV64V-NEXT: vadd.vv v12, v12, v12
-; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64V-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64V-NEXT: ret
;
@@ -6361,7 +6352,7 @@ define void @mscatter_baseidx_sext_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8
; RV64ZVE32F-NEXT: beqz a2, .LBB59_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -6416,7 +6407,7 @@ define void @mscatter_baseidx_sext_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8
; RV64ZVE32F-NEXT: beqz a2, .LBB59_10
; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: vmv.x.s a3, v10
@@ -6463,11 +6454,11 @@ define void @mscatter_baseidx_sext_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8
; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v9
; RV64ZVE32F-NEXT: slli a1, a1, 1
; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: fmv.h.x fa5, a1
; RV64ZVE32F-NEXT: fsh fa5, 0(a0)
@@ -6483,7 +6474,7 @@ define void @mscatter_baseidx_zext_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vwaddu.vv v10, v9, v9
-; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vsoxei16.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
@@ -6491,7 +6482,7 @@ define void @mscatter_baseidx_zext_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64V-NEXT: vwaddu.vv v10, v9, v9
-; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64V-NEXT: vsoxei16.v v8, (a0), v10, v0.t
; RV64V-NEXT: ret
;
@@ -6503,7 +6494,7 @@ define void @mscatter_baseidx_zext_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8
; RV64ZVE32F-NEXT: beqz a2, .LBB60_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 1
@@ -6562,7 +6553,7 @@ define void @mscatter_baseidx_zext_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8
; RV64ZVE32F-NEXT: beqz a2, .LBB60_10
; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: vmv.x.s a3, v10
@@ -6612,12 +6603,12 @@ define void @mscatter_baseidx_zext_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8
; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v9
; RV64ZVE32F-NEXT: zext.b a1, a1
; RV64ZVE32F-NEXT: slli a1, a1, 1
; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: fmv.h.x fa5, a1
; RV64ZVE32F-NEXT: fsh fa5, 0(a0)
@@ -6641,7 +6632,7 @@ define void @mscatter_baseidx_v8bf16(<8 x bfloat> %val, ptr %base, <8 x i16> %id
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf4 v12, v9
; RV64V-NEXT: vadd.vv v12, v12, v12
-; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64V-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64V-NEXT: ret
;
@@ -6652,7 +6643,7 @@ define void @mscatter_baseidx_v8bf16(<8 x bfloat> %val, ptr %base, <8 x i16> %id
; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB61_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a2, a2, 1
@@ -6869,7 +6860,7 @@ define void @mscatter_v2f16(<2 x half> %val, <2 x ptr> %ptrs, <2 x i1> %m) {
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB63_2: # %else2
; RV64ZVE32F-ZVFHMIN-NEXT: ret
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB63_3: # %cond.store
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-ZVFHMIN-NEXT: fmv.h.x fa5, a3
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a0)
@@ -6967,7 +6958,7 @@ define void @mscatter_v4f16(<4 x half> %val, <4 x ptr> %ptrs, <4 x i1> %m) {
; RV64ZVE32F-ZVFHMIN-NEXT: ret
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB64_5: # %cond.store
; RV64ZVE32F-ZVFHMIN-NEXT: ld a0, 0(a0)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a5, v8
; RV64ZVE32F-ZVFHMIN-NEXT: fmv.h.x fa5, a5
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a0)
@@ -7201,7 +7192,7 @@ define void @mscatter_v8f16(<8 x half> %val, <8 x ptr> %ptrs, <8 x i1> %m) {
; RV64ZVE32F-ZVFHMIN-NEXT: ret
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB67_9: # %cond.store
; RV64ZVE32F-ZVFHMIN-NEXT: ld a0, 0(a0)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s t1, v8
; RV64ZVE32F-ZVFHMIN-NEXT: fmv.h.x fa5, t1
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a0)
@@ -7272,7 +7263,7 @@ define void @mscatter_baseidx_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i8> %i
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vsext.vf4 v10, v9
; RV32-NEXT: vadd.vv v10, v10, v10
-; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
@@ -7281,7 +7272,7 @@ define void @mscatter_baseidx_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i8> %i
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf8 v12, v9
; RV64V-NEXT: vadd.vv v12, v12, v12
-; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64V-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64V-NEXT: ret
;
@@ -7342,9 +7333,8 @@ define void @mscatter_baseidx_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i8> %i
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
; RV64ZVE32F-ZVFH-NEXT: .LBB68_10: # %else8
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 32
@@ -7396,7 +7386,7 @@ define void @mscatter_baseidx_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i8> %i
; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB68_2
; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %cond.store
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
@@ -7451,7 +7441,7 @@ define void @mscatter_baseidx_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i8> %i
; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB68_10
; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.9: # %cond.store7
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v10
@@ -7498,11 +7488,11 @@ define void @mscatter_baseidx_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i8> %i
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v9, v9, 1
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 7
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v9
; RV64ZVE32F-ZVFHMIN-NEXT: slli a1, a1, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a0, a0, a1
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-ZVFHMIN-NEXT: fmv.h.x fa5, a1
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a0)
@@ -7518,7 +7508,7 @@ define void @mscatter_baseidx_sext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vsext.vf4 v10, v9
; RV32-NEXT: vadd.vv v10, v10, v10
-; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
@@ -7527,7 +7517,7 @@ define void @mscatter_baseidx_sext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf8 v12, v9
; RV64V-NEXT: vadd.vv v12, v12, v12
-; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64V-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64V-NEXT: ret
;
@@ -7588,9 +7578,8 @@ define void @mscatter_baseidx_sext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
; RV64ZVE32F-ZVFH-NEXT: .LBB69_10: # %else8
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 32
@@ -7642,7 +7631,7 @@ define void @mscatter_baseidx_sext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB69_2
; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %cond.store
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
@@ -7697,7 +7686,7 @@ define void @mscatter_baseidx_sext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB69_10
; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.9: # %cond.store7
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v10
@@ -7744,11 +7733,11 @@ define void @mscatter_baseidx_sext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v9, v9, 1
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 7
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v9
; RV64ZVE32F-ZVFHMIN-NEXT: slli a1, a1, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a0, a0, a1
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-ZVFHMIN-NEXT: fmv.h.x fa5, a1
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a0)
@@ -7764,7 +7753,7 @@ define void @mscatter_baseidx_zext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vwaddu.vv v10, v9, v9
-; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vsoxei16.v v8, (a0), v10, v0.t
; RV32-NEXT: ret
;
@@ -7772,7 +7761,7 @@ define void @mscatter_baseidx_zext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64V-NEXT: vwaddu.vv v10, v9, v9
-; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64V-NEXT: vsoxei16.v v8, (a0), v10, v0.t
; RV64V-NEXT: ret
;
@@ -7838,9 +7827,8 @@ define void @mscatter_baseidx_zext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFH-NEXT: zext.b a2, a2
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
; RV64ZVE32F-ZVFH-NEXT: .LBB70_10: # %else8
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 32
@@ -7895,7 +7883,7 @@ define void @mscatter_baseidx_zext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB70_2
; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %cond.store
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-ZVFHMIN-NEXT: zext.b a2, a2
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
@@ -7954,7 +7942,7 @@ define void @mscatter_baseidx_zext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB70_10
; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.9: # %cond.store7
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-ZVFHMIN-NEXT: zext.b a2, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v10
@@ -8004,12 +7992,12 @@ define void @mscatter_baseidx_zext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v9, v9, 1
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 7
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v9
; RV64ZVE32F-ZVFHMIN-NEXT: zext.b a1, a1
; RV64ZVE32F-ZVFHMIN-NEXT: slli a1, a1, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a0, a0, a1
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-ZVFHMIN-NEXT: fmv.h.x fa5, a1
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a0)
@@ -8033,7 +8021,7 @@ define void @mscatter_baseidx_v8f16(<8 x half> %val, ptr %base, <8 x i16> %idxs,
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf4 v12, v9
; RV64V-NEXT: vadd.vv v12, v12, v12
-; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64V-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64V-NEXT: ret
;
@@ -8146,7 +8134,7 @@ define void @mscatter_baseidx_v8f16(<8 x half> %val, ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 1
; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB71_2
; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %cond.store
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
@@ -8563,7 +8551,7 @@ define void @mscatter_baseidx_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x i8> %
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf8 v12, v10
; RV64V-NEXT: vsll.vi v12, v12, 2
-; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64V-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64V-NEXT: ret
;
@@ -8588,7 +8576,7 @@ define void @mscatter_baseidx_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x i8> %
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 1
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
; RV64ZVE32F-NEXT: .LBB78_4: # %else2
@@ -8600,9 +8588,8 @@ define void @mscatter_baseidx_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x i8> %
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
; RV64ZVE32F-NEXT: .LBB78_6: # %else4
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -8613,7 +8600,7 @@ define void @mscatter_baseidx_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x i8> %
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
; RV64ZVE32F-NEXT: .LBB78_8: # %else6
@@ -8625,7 +8612,7 @@ define void @mscatter_baseidx_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x i8> %
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
@@ -8692,7 +8679,7 @@ define void @mscatter_baseidx_sext_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf8 v12, v10
; RV64V-NEXT: vsll.vi v12, v12, 2
-; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64V-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64V-NEXT: ret
;
@@ -8717,7 +8704,7 @@ define void @mscatter_baseidx_sext_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 1
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
; RV64ZVE32F-NEXT: .LBB79_4: # %else2
@@ -8729,9 +8716,8 @@ define void @mscatter_baseidx_sext_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
; RV64ZVE32F-NEXT: .LBB79_6: # %else4
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -8742,7 +8728,7 @@ define void @mscatter_baseidx_sext_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
; RV64ZVE32F-NEXT: .LBB79_8: # %else6
@@ -8754,7 +8740,7 @@ define void @mscatter_baseidx_sext_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
@@ -8814,7 +8800,7 @@ define void @mscatter_baseidx_zext_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x
; RV32-NEXT: li a1, 4
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vwmulu.vx v11, v10, a1
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vsoxei16.v v8, (a0), v11, v0.t
; RV32-NEXT: ret
;
@@ -8823,7 +8809,7 @@ define void @mscatter_baseidx_zext_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64V-NEXT: li a1, 4
; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64V-NEXT: vwmulu.vx v11, v10, a1
-; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64V-NEXT: vsoxei16.v v8, (a0), v11, v0.t
; RV64V-NEXT: ret
;
@@ -8850,7 +8836,7 @@ define void @mscatter_baseidx_zext_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 1
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
; RV64ZVE32F-NEXT: .LBB80_4: # %else2
@@ -8863,9 +8849,8 @@ define void @mscatter_baseidx_zext_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
; RV64ZVE32F-NEXT: .LBB80_6: # %else4
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -8877,7 +8862,7 @@ define void @mscatter_baseidx_zext_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
; RV64ZVE32F-NEXT: .LBB80_8: # %else6
@@ -8890,7 +8875,7 @@ define void @mscatter_baseidx_zext_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
@@ -8953,7 +8938,7 @@ define void @mscatter_baseidx_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x i16>
; RV32-NEXT: li a1, 4
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vwmulsu.vx v12, v10, a1
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
@@ -8962,7 +8947,7 @@ define void @mscatter_baseidx_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x i16>
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf4 v12, v10
; RV64V-NEXT: vsll.vi v12, v12, 2
-; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64V-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64V-NEXT: ret
;
@@ -8973,7 +8958,7 @@ define void @mscatter_baseidx_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x i16>
; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB81_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -8988,7 +8973,7 @@ define void @mscatter_baseidx_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x i16>
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 1
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
; RV64ZVE32F-NEXT: .LBB81_4: # %else2
@@ -9000,9 +8985,8 @@ define void @mscatter_baseidx_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x i16>
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
; RV64ZVE32F-NEXT: .LBB81_6: # %else4
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -9013,7 +8997,7 @@ define void @mscatter_baseidx_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x i16>
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
; RV64ZVE32F-NEXT: .LBB81_8: # %else6
@@ -9025,7 +9009,7 @@ define void @mscatter_baseidx_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x i16>
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
@@ -9084,7 +9068,7 @@ define void @mscatter_baseidx_sext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x
; RV32-NEXT: li a1, 4
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vwmulsu.vx v12, v10, a1
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
@@ -9093,7 +9077,7 @@ define void @mscatter_baseidx_sext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsext.vf4 v12, v10
; RV64V-NEXT: vsll.vi v12, v12, 2
-; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64V-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64V-NEXT: ret
;
@@ -9104,7 +9088,7 @@ define void @mscatter_baseidx_sext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB82_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -9119,7 +9103,7 @@ define void @mscatter_baseidx_sext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 1
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
; RV64ZVE32F-NEXT: .LBB82_4: # %else2
@@ -9131,9 +9115,8 @@ define void @mscatter_baseidx_sext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
; RV64ZVE32F-NEXT: .LBB82_6: # %else4
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -9144,7 +9127,7 @@ define void @mscatter_baseidx_sext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
; RV64ZVE32F-NEXT: .LBB82_8: # %else6
@@ -9156,7 +9139,7 @@ define void @mscatter_baseidx_sext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
@@ -9216,7 +9199,7 @@ define void @mscatter_baseidx_zext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x
; RV32-NEXT: li a1, 4
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vwmulu.vx v12, v10, a1
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
@@ -9225,7 +9208,7 @@ define void @mscatter_baseidx_zext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64V-NEXT: li a1, 4
; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64V-NEXT: vwmulu.vx v12, v10, a1
-; RV64V-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64V-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV64V-NEXT: ret
;
@@ -9236,7 +9219,7 @@ define void @mscatter_baseidx_zext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB83_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 46
@@ -9253,7 +9236,7 @@ define void @mscatter_baseidx_zext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 1
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
; RV64ZVE32F-NEXT: .LBB83_4: # %else2
@@ -9266,9 +9249,8 @@ define void @mscatter_baseidx_zext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
; RV64ZVE32F-NEXT: .LBB83_6: # %else4
; RV64ZVE32F-NEXT: andi a2, a1, 8
@@ -9280,7 +9262,7 @@ define void @mscatter_baseidx_zext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
; RV64ZVE32F-NEXT: .LBB83_8: # %else6
@@ -9293,7 +9275,7 @@ define void @mscatter_baseidx_zext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
@@ -9546,7 +9528,7 @@ define void @mscatter_v2f64(<2 x double> %val, <2 x ptr> %ptrs, <2 x i1> %m) {
; RV32ZVE32F-NEXT: .LBB86_2: # %else2
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB86_3: # %cond.store
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v8
; RV32ZVE32F-NEXT: fsd fa0, 0(a1)
; RV32ZVE32F-NEXT: andi a0, a0, 2
@@ -9613,7 +9595,7 @@ define void @mscatter_v4f64(<4 x double> %val, <4 x ptr> %ptrs, <4 x i1> %m) {
; RV32ZVE32F-NEXT: .LBB87_4: # %else6
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB87_5: # %cond.store
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v8
; RV32ZVE32F-NEXT: fsd fa0, 0(a1)
; RV32ZVE32F-NEXT: andi a1, a0, 2
@@ -9776,7 +9758,7 @@ define void @mscatter_v8f64(<8 x double> %val, <8 x ptr> %ptrs, <8 x i1> %m) {
; RV32ZVE32F-NEXT: .LBB90_8: # %else14
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB90_9: # %cond.store
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v8
; RV32ZVE32F-NEXT: fsd fa0, 0(a1)
; RV32ZVE32F-NEXT: andi a1, a0, 2
@@ -9908,7 +9890,7 @@ define void @mscatter_baseidx_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x i8>
; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32V-NEXT: vsext.vf4 v14, v12
; RV32V-NEXT: vsll.vi v12, v14, 3
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32V-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32V-NEXT: ret
;
@@ -9924,9 +9906,9 @@ define void @mscatter_baseidx_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x i8>
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsext.vf4 v10, v8
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: andi a2, a1, 1
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a0
@@ -10103,7 +10085,7 @@ define void @mscatter_baseidx_sext_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x
; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32V-NEXT: vsext.vf4 v14, v12
; RV32V-NEXT: vsll.vi v12, v14, 3
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32V-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32V-NEXT: ret
;
@@ -10119,9 +10101,9 @@ define void @mscatter_baseidx_sext_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsext.vf4 v10, v8
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: andi a2, a1, 1
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a0
@@ -10299,7 +10281,7 @@ define void @mscatter_baseidx_zext_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x
; RV32V-NEXT: li a1, 8
; RV32V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32V-NEXT: vwmulu.vx v13, v12, a1
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32V-NEXT: vsoxei16.v v8, (a0), v13, v0.t
; RV32V-NEXT: ret
;
@@ -10308,7 +10290,7 @@ define void @mscatter_baseidx_zext_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x
; RV64V-NEXT: li a1, 8
; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64V-NEXT: vwmulu.vx v13, v12, a1
-; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsoxei16.v v8, (a0), v13, v0.t
; RV64V-NEXT: ret
;
@@ -10316,9 +10298,9 @@ define void @mscatter_baseidx_zext_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vzext.vf4 v10, v8
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v10, 3
; RV32ZVE32F-NEXT: andi a2, a1, 1
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a0
@@ -10504,7 +10486,7 @@ define void @mscatter_baseidx_v8i16_v8f64(<8 x double> %val, ptr %base, <8 x i16
; RV32V-NEXT: li a1, 8
; RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32V-NEXT: vwmulsu.vx v14, v12, a1
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32V-NEXT: vsoxei32.v v8, (a0), v14, v0.t
; RV32V-NEXT: ret
;
@@ -10521,10 +10503,10 @@ define void @mscatter_baseidx_v8i16_v8f64(<8 x double> %val, ptr %base, <8 x i16
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.v.x v10, a0
; RV32ZVE32F-NEXT: li a1, 8
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a0, v0
; RV32ZVE32F-NEXT: andi a2, a0, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32ZVE32F-NEXT: vwmaccus.vx v10, a1, v8
; RV32ZVE32F-NEXT: bnez a2, .LBB94_9
; RV32ZVE32F-NEXT: # %bb.1: # %else
@@ -10551,7 +10533,7 @@ define void @mscatter_baseidx_v8i16_v8f64(<8 x double> %val, ptr %base, <8 x i16
; RV32ZVE32F-NEXT: .LBB94_8: # %else14
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB94_9: # %cond.store
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v10
; RV32ZVE32F-NEXT: fsd fa0, 0(a1)
; RV32ZVE32F-NEXT: andi a1, a0, 2
@@ -10612,7 +10594,7 @@ define void @mscatter_baseidx_v8i16_v8f64(<8 x double> %val, ptr %base, <8 x i16
; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB94_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -10701,7 +10683,7 @@ define void @mscatter_baseidx_sext_v8i16_v8f64(<8 x double> %val, ptr %base, <8
; RV32V-NEXT: li a1, 8
; RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32V-NEXT: vwmulsu.vx v14, v12, a1
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32V-NEXT: vsoxei32.v v8, (a0), v14, v0.t
; RV32V-NEXT: ret
;
@@ -10718,10 +10700,10 @@ define void @mscatter_baseidx_sext_v8i16_v8f64(<8 x double> %val, ptr %base, <8
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.v.x v10, a0
; RV32ZVE32F-NEXT: li a1, 8
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a0, v0
; RV32ZVE32F-NEXT: andi a2, a0, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32ZVE32F-NEXT: vwmaccus.vx v10, a1, v8
; RV32ZVE32F-NEXT: bnez a2, .LBB95_9
; RV32ZVE32F-NEXT: # %bb.1: # %else
@@ -10748,7 +10730,7 @@ define void @mscatter_baseidx_sext_v8i16_v8f64(<8 x double> %val, ptr %base, <8
; RV32ZVE32F-NEXT: .LBB95_8: # %else14
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB95_9: # %cond.store
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v10
; RV32ZVE32F-NEXT: fsd fa0, 0(a1)
; RV32ZVE32F-NEXT: andi a1, a0, 2
@@ -10809,7 +10791,7 @@ define void @mscatter_baseidx_sext_v8i16_v8f64(<8 x double> %val, ptr %base, <8
; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB95_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -10899,7 +10881,7 @@ define void @mscatter_baseidx_zext_v8i16_v8f64(<8 x double> %val, ptr %base, <8
; RV32V-NEXT: li a1, 8
; RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32V-NEXT: vwmulu.vx v14, v12, a1
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32V-NEXT: vsoxei32.v v8, (a0), v14, v0.t
; RV32V-NEXT: ret
;
@@ -10908,7 +10890,7 @@ define void @mscatter_baseidx_zext_v8i16_v8f64(<8 x double> %val, ptr %base, <8
; RV64V-NEXT: li a1, 8
; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64V-NEXT: vwmulu.vx v14, v12, a1
-; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsoxei32.v v8, (a0), v14, v0.t
; RV64V-NEXT: ret
;
@@ -10917,10 +10899,10 @@ define void @mscatter_baseidx_zext_v8i16_v8f64(<8 x double> %val, ptr %base, <8
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.v.x v10, a0
; RV32ZVE32F-NEXT: li a1, 8
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a0, v0
; RV32ZVE32F-NEXT: andi a2, a0, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32ZVE32F-NEXT: vwmaccu.vx v10, a1, v8
; RV32ZVE32F-NEXT: bnez a2, .LBB96_9
; RV32ZVE32F-NEXT: # %bb.1: # %else
@@ -10947,7 +10929,7 @@ define void @mscatter_baseidx_zext_v8i16_v8f64(<8 x double> %val, ptr %base, <8
; RV32ZVE32F-NEXT: .LBB96_8: # %else14
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB96_9: # %cond.store
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v10
; RV32ZVE32F-NEXT: fsd fa0, 0(a1)
; RV32ZVE32F-NEXT: andi a1, a0, 2
@@ -11008,7 +10990,7 @@ define void @mscatter_baseidx_zext_v8i16_v8f64(<8 x double> %val, ptr %base, <8
; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB96_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 45
@@ -11105,7 +11087,7 @@ define void @mscatter_baseidx_v8i32_v8f64(<8 x double> %val, ptr %base, <8 x i32
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32V-NEXT: vsll.vi v12, v12, 3
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32V-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32V-NEXT: ret
;
@@ -11114,7 +11096,7 @@ define void @mscatter_baseidx_v8i32_v8f64(<8 x double> %val, ptr %base, <8 x i32
; RV64V-NEXT: li a1, 8
; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64V-NEXT: vwmulsu.vx v16, v12, a1
-; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64V-NEXT: ret
;
@@ -11122,10 +11104,10 @@ define void @mscatter_baseidx_v8i32_v8f64(<8 x double> %val, ptr %base, <8 x i32
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi a2, a1, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a0
; RV32ZVE32F-NEXT: bnez a2, .LBB97_9
; RV32ZVE32F-NEXT: # %bb.1: # %else
@@ -11212,7 +11194,7 @@ define void @mscatter_baseidx_v8i32_v8f64(<8 x double> %val, ptr %base, <8 x i32
; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB97_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -11307,7 +11289,7 @@ define void @mscatter_baseidx_sext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32V-NEXT: vsll.vi v12, v12, 3
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32V-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32V-NEXT: ret
;
@@ -11316,7 +11298,7 @@ define void @mscatter_baseidx_sext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
; RV64V-NEXT: li a1, 8
; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64V-NEXT: vwmulsu.vx v16, v12, a1
-; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64V-NEXT: ret
;
@@ -11324,10 +11306,10 @@ define void @mscatter_baseidx_sext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi a2, a1, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a0
; RV32ZVE32F-NEXT: bnez a2, .LBB98_9
; RV32ZVE32F-NEXT: # %bb.1: # %else
@@ -11414,7 +11396,7 @@ define void @mscatter_baseidx_sext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB98_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -11510,7 +11492,7 @@ define void @mscatter_baseidx_zext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
; RV32V: # %bb.0:
; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32V-NEXT: vsll.vi v12, v12, 3
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32V-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32V-NEXT: ret
;
@@ -11519,7 +11501,7 @@ define void @mscatter_baseidx_zext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
; RV64V-NEXT: li a1, 8
; RV64V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64V-NEXT: vwmulu.vx v16, v12, a1
-; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64V-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64V-NEXT: ret
;
@@ -11527,10 +11509,10 @@ define void @mscatter_baseidx_zext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi a2, a1, 1
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a0
; RV32ZVE32F-NEXT: bnez a2, .LBB99_9
; RV32ZVE32F-NEXT: # %bb.1: # %else
@@ -11617,7 +11599,7 @@ define void @mscatter_baseidx_zext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB99_2
; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 32
; RV64ZVE32F-NEXT: srli a2, a2, 29
@@ -11722,7 +11704,7 @@ define void @mscatter_baseidx_v8f64(<8 x double> %val, ptr %base, <8 x i64> %idx
; RV32V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32V-NEXT: vnsrl.wi v16, v12, 0
; RV32V-NEXT: vsll.vi v12, v16, 3
-; RV32V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32V-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32V-NEXT: ret
;
@@ -11745,9 +11727,9 @@ define void @mscatter_baseidx_v8f64(<8 x double> %val, ptr %base, <8 x i64> %idx
; RV32ZVE32F-NEXT: lw t1, 24(a1)
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vmv.v.x v8, a6
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32ZVE32F-NEXT: vmv.x.s a1, v0
-; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, a7
; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, t0
; RV32ZVE32F-NEXT: vslide1down.vx v8, v8, t1
@@ -11932,7 +11914,7 @@ define void @mscatter_baseidx_v16i8(<16 x i8> %val, ptr %base, <16 x i8> %idxs,
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vsext.vf4 v12, v9
-; RV32-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
@@ -11940,7 +11922,7 @@ define void @mscatter_baseidx_v16i8(<16 x i8> %val, ptr %base, <16 x i8> %idxs,
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64V-NEXT: vsext.vf8 v16, v9
-; RV64V-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64V-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64V-NEXT: ret
;
@@ -12144,7 +12126,7 @@ define void @mscatter_baseidx_v32i8(<32 x i8> %val, ptr %base, <32 x i8> %idxs,
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64V-NEXT: vsext.vf8 v16, v10
-; RV64V-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64V-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64V-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; RV64V-NEXT: vslidedown.vi v16, v8, 16
@@ -12153,7 +12135,7 @@ define void @mscatter_baseidx_v32i8(<32 x i8> %val, ptr %base, <32 x i8> %idxs,
; RV64V-NEXT: vslidedown.vi v0, v0, 2
; RV64V-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64V-NEXT: vsext.vf8 v8, v18
-; RV64V-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64V-NEXT: vsoxei64.v v16, (a0), v8, v0.t
; RV64V-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
index 0f5cccd8cf2e2..0b17fc9451c39 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
@@ -129,7 +129,7 @@ define float @vpreduce_fadd_v64f32(float %s, <64 x float> %v, <64 x i1> %m, i32
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: .LBB8_2:
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
; CHECK-NEXT: vfmv.s.f v25, fa0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t
@@ -157,7 +157,7 @@ define float @vpreduce_ord_fadd_v64f32(float %s, <64 x float> %v, <64 x i1> %m,
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: .LBB9_2:
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
; CHECK-NEXT: vfmv.s.f v25, fa0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
index eec12212d0d37..b36bf60c5ae7e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
@@ -295,7 +295,7 @@ define float @vreduce_fwadd_v1f32(<1 x half> %v, float %s) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfmv.f.s fa5, v9
; CHECK-NEXT: fadd.s fa0, fa0, fa5
; CHECK-NEXT: ret
@@ -311,7 +311,7 @@ define float @vreduce_ord_fwadd_v1f32(<1 x half> %v, float %s) {
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%e = fpext <1 x half> %v to <1 x float>
@@ -355,9 +355,9 @@ define float @vreduce_fwadd_v2f32(ptr %x, float %s) {
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfwredusum.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <2 x half>, ptr %x
@@ -372,9 +372,9 @@ define float @vreduce_ord_fwadd_v2f32(ptr %x, float %s) {
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <2 x half>, ptr %x
@@ -419,9 +419,9 @@ define float @vreduce_fwadd_v4f32(ptr %x, float %s) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfwredusum.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x half>, ptr %x
@@ -436,9 +436,9 @@ define float @vreduce_ord_fwadd_v4f32(ptr %x, float %s) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x half>, ptr %x
@@ -558,9 +558,9 @@ define float @vreduce_fwadd_v8f32(ptr %x, float %s) {
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfwredusum.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <8 x half>, ptr %x
@@ -575,9 +575,9 @@ define float @vreduce_ord_fwadd_v8f32(ptr %x, float %s) {
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <8 x half>, ptr %x
@@ -622,9 +622,9 @@ define float @vreduce_fwadd_v16f32(ptr %x, float %s) {
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfmv.s.f v10, fa0
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vfwredusum.vs v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <16 x half>, ptr %x
@@ -639,9 +639,9 @@ define float @vreduce_ord_fwadd_v16f32(ptr %x, float %s) {
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfmv.s.f v10, fa0
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <16 x half>, ptr %x
@@ -831,7 +831,7 @@ define double @vreduce_fwadd_v1f64(<1 x float> %v, double %s) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-NEXT: vfmv.f.s fa5, v9
; CHECK-NEXT: fadd.d fa0, fa0, fa5
; CHECK-NEXT: ret
@@ -845,9 +845,9 @@ define double @vreduce_ord_fwadd_v1f64(<1 x float> %v, double %s) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%e = fpext <1 x float> %v to <1 x double>
@@ -891,9 +891,9 @@ define double @vreduce_fwadd_v2f64(ptr %x, double %s) {
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwredusum.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <2 x float>, ptr %x
@@ -908,9 +908,9 @@ define double @vreduce_ord_fwadd_v2f64(ptr %x, double %s) {
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <2 x float>, ptr %x
@@ -955,9 +955,9 @@ define double @vreduce_fwadd_v4f64(ptr %x, double %s) {
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfwredusum.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x float>, ptr %x
@@ -972,9 +972,9 @@ define double @vreduce_ord_fwadd_v4f64(ptr %x, double %s) {
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <4 x float>, ptr %x
@@ -1019,9 +1019,9 @@ define double @vreduce_fwadd_v8f64(ptr %x, double %s) {
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfmv.s.f v10, fa0
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfwredusum.vs v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <8 x float>, ptr %x
@@ -1036,9 +1036,9 @@ define double @vreduce_ord_fwadd_v8f64(ptr %x, double %s) {
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfmv.s.f v10, fa0
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <8 x float>, ptr %x
@@ -1083,9 +1083,9 @@ define double @vreduce_fwadd_v16f64(ptr %x, double %s) {
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfmv.s.f v12, fa0
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfwredusum.vs v8, v8, v12
-; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <16 x float>, ptr %x
@@ -1100,9 +1100,9 @@ define double @vreduce_ord_fwadd_v16f64(ptr %x, double %s) {
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfmv.s.f v12, fa0
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v12
-; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <16 x float>, ptr %x
@@ -1157,7 +1157,7 @@ define double @vreduce_fwadd_v32f64(ptr %x, double %s) {
; CHECK-NEXT: vslidedown.vi v16, v8, 16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfwadd.vv v24, v8, v16
-; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: vfredusum.vs v8, v24, v8
; CHECK-NEXT: vfmv.f.s fa0, v8
@@ -1181,7 +1181,7 @@ define double @vreduce_ord_fwadd_v32f64(ptr %x, double %s) {
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v24
; CHECK-NEXT: vfwredosum.vs v8, v16, v8
-; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
%v = load <32 x float>, ptr %x
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
index dfe8f358b7782..23cfb177c96c2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
@@ -752,7 +752,7 @@ define signext i32 @vpreduce_xor_v64i32(i32 signext %s, <64 x i32> %v, <64 x i1>
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: .LBB49_2:
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
; CHECK-NEXT: vmv.s.x v25, a0
; CHECK-NEXT: addi a0, a1, -32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
@@ -1344,7 +1344,7 @@ define i8 @vpreduce_mul_v1i8(i8 %s, <1 x i8> %v, <1 x i1> %m, i32 zeroext %evl)
; RV32-NEXT: vmsne.vi v9, v9, 0
; RV32-NEXT: vmand.mm v0, v9, v0
; RV32-NEXT: vmv.v.i v9, 1
-; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmerge.vvm v8, v9, v8, v0
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: mv a1, a2
@@ -1367,7 +1367,7 @@ define i8 @vpreduce_mul_v1i8(i8 %s, <1 x i8> %v, <1 x i1> %m, i32 zeroext %evl)
; RV64-NEXT: vmsne.vi v9, v9, 0
; RV64-NEXT: vmand.mm v0, v9, v0
; RV64-NEXT: vmv.v.i v9, 1
-; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV64-NEXT: vmerge.vvm v8, v9, v8, v0
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: mv a1, a2
@@ -1395,7 +1395,7 @@ define signext i8 @vpreduce_mul_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i3
; RV32-NEXT: vid.v v9
; RV32-NEXT: vmsltu.vx v9, v9, a1
; RV32-NEXT: vmand.mm v0, v9, v0
-; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.i v9, 1
; RV32-NEXT: vmerge.vvm v8, v9, v8, v0
; RV32-NEXT: vrgather.vi v9, v8, 1
@@ -1422,7 +1422,7 @@ define signext i8 @vpreduce_mul_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i3
; RV64-NEXT: vid.v v9
; RV64-NEXT: vmsltu.vx v9, v9, a1
; RV64-NEXT: vmand.mm v0, v9, v0
-; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; RV64-NEXT: vmv.v.i v9, 1
; RV64-NEXT: vmerge.vvm v8, v9, v8, v0
; RV64-NEXT: vrgather.vi v9, v8, 1
@@ -1455,7 +1455,7 @@ define signext i8 @vpreduce_mul_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i3
; RV32-NEXT: vid.v v9
; RV32-NEXT: vmsltu.vx v9, v9, a1
; RV32-NEXT: vmand.mm v0, v9, v0
-; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; RV32-NEXT: vmv.v.i v9, 1
; RV32-NEXT: vmerge.vvm v8, v9, v8, v0
; RV32-NEXT: vslidedown.vi v9, v8, 2
@@ -1484,7 +1484,7 @@ define signext i8 @vpreduce_mul_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i3
; RV64-NEXT: vid.v v9
; RV64-NEXT: vmsltu.vx v9, v9, a1
; RV64-NEXT: vmand.mm v0, v9, v0
-; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; RV64-NEXT: vmv.v.i v9, 1
; RV64-NEXT: vmerge.vvm v8, v9, v8, v0
; RV64-NEXT: vslidedown.vi v9, v8, 2
@@ -1519,7 +1519,7 @@ define signext i8 @vpreduce_mul_v8i8(i8 signext %s, <8 x i8> %v, <8 x i1> %m, i3
; RV32-NEXT: vid.v v10
; RV32-NEXT: vmsltu.vx v9, v10, a1
; RV32-NEXT: vmand.mm v0, v9, v0
-; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vmv.v.i v9, 1
; RV32-NEXT: vmerge.vvm v8, v9, v8, v0
; RV32-NEXT: vslidedown.vi v9, v8, 4
@@ -1550,7 +1550,7 @@ define signext i8 @vpreduce_mul_v8i8(i8 signext %s, <8 x i8> %v, <8 x i1> %m, i3
; RV64-NEXT: vid.v v10
; RV64-NEXT: vmsltu.vx v9, v10, a1
; RV64-NEXT: vmand.mm v0, v9, v0
-; RV64-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64-NEXT: vmv.v.i v9, 1
; RV64-NEXT: vmerge.vvm v8, v9, v8, v0
; RV64-NEXT: vslidedown.vi v9, v8, 4
@@ -1587,7 +1587,7 @@ define signext i8 @vpreduce_mul_v16i8(i8 signext %s, <16 x i8> %v, <16 x i1> %m,
; RV32-NEXT: vid.v v12
; RV32-NEXT: vmsltu.vx v9, v12, a1
; RV32-NEXT: vmand.mm v0, v9, v0
-; RV32-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmv.v.i v9, 1
; RV32-NEXT: vmerge.vvm v8, v9, v8, v0
; RV32-NEXT: vslidedown.vi v9, v8, 8
@@ -1620,7 +1620,7 @@ define signext i8 @vpreduce_mul_v16i8(i8 signext %s, <16 x i8> %v, <16 x i1> %m,
; RV64-NEXT: vid.v v12
; RV64-NEXT: vmsltu.vx v9, v12, a1
; RV64-NEXT: vmand.mm v0, v9, v0
-; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vmv.v.i v9, 1
; RV64-NEXT: vmerge.vvm v8, v9, v8, v0
; RV64-NEXT: vslidedown.vi v9, v8, 8
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
index d3a36525115c8..560882189a8ef 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
@@ -223,9 +223,9 @@ define i16 @vwreduce_add_v2i16(ptr %x) {
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmv.s.x v9, zero
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vwredsum.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i8>, ptr %x
@@ -240,9 +240,9 @@ define i16 @vwreduce_uadd_v2i16(ptr %x) {
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmv.s.x v9, zero
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vwredsumu.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i8>, ptr %x
@@ -273,9 +273,9 @@ define i16 @vwreduce_add_v4i16(ptr %x) {
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmv.s.x v9, zero
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vwredsum.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i8>, ptr %x
@@ -290,9 +290,9 @@ define i16 @vwreduce_uadd_v4i16(ptr %x) {
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmv.s.x v9, zero
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vwredsumu.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i8>, ptr %x
@@ -323,9 +323,9 @@ define i16 @vwreduce_add_v8i16(ptr %x) {
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmv.s.x v9, zero
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vwredsum.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i8>, ptr %x
@@ -340,9 +340,9 @@ define i16 @vwreduce_uadd_v8i16(ptr %x) {
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmv.s.x v9, zero
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vwredsumu.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i8>, ptr %x
@@ -373,9 +373,9 @@ define i16 @vwreduce_add_v16i16(ptr %x) {
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmv.s.x v9, zero
-; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vwredsum.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i8>, ptr %x
@@ -390,9 +390,9 @@ define i16 @vwreduce_uadd_v16i16(ptr %x) {
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmv.s.x v9, zero
-; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vwredsumu.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i8>, ptr %x
@@ -629,9 +629,9 @@ define i32 @vwreduce_add_v2i32(ptr %x) {
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmv.s.x v9, zero
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vwredsum.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i16>, ptr %x
@@ -646,9 +646,9 @@ define i32 @vwreduce_uadd_v2i32(ptr %x) {
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmv.s.x v9, zero
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vwredsumu.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <2 x i16>, ptr %x
@@ -679,9 +679,9 @@ define i32 @vwreduce_add_v4i32(ptr %x) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmv.s.x v9, zero
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vwredsum.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i16>, ptr %x
@@ -696,9 +696,9 @@ define i32 @vwreduce_uadd_v4i32(ptr %x) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmv.s.x v9, zero
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vwredsumu.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <4 x i16>, ptr %x
@@ -729,9 +729,9 @@ define i32 @vwreduce_add_v8i32(ptr %x) {
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmv.s.x v9, zero
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vwredsum.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i16>, ptr %x
@@ -746,9 +746,9 @@ define i32 @vwreduce_uadd_v8i32(ptr %x) {
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmv.s.x v9, zero
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vwredsumu.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <8 x i16>, ptr %x
@@ -779,9 +779,9 @@ define i32 @vwreduce_add_v16i32(ptr %x) {
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmv.s.x v10, zero
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vwredsum.vs v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i16>, ptr %x
@@ -796,9 +796,9 @@ define i32 @vwreduce_uadd_v16i32(ptr %x) {
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmv.s.x v10, zero
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vwredsumu.vs v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%v = load <16 x i16>, ptr %x
@@ -1025,7 +1025,7 @@ define i64 @vwreduce_add_v2i64(ptr %x) {
; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: vmv.s.x v9, zero
; RV32-NEXT: li a1, 32
-; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV32-NEXT: vwredsum.vs v8, v8, v9
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vmv.x.s a0, v8
@@ -1038,9 +1038,9 @@ define i64 @vwreduce_add_v2i64(ptr %x) {
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: vmv.s.x v9, zero
-; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64-NEXT: vwredsum.vs v8, v8, v9
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <2 x i32>, ptr %x
@@ -1056,7 +1056,7 @@ define i64 @vwreduce_uadd_v2i64(ptr %x) {
; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: vmv.s.x v9, zero
; RV32-NEXT: li a1, 32
-; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV32-NEXT: vwredsumu.vs v8, v8, v9
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vmv.x.s a0, v8
@@ -1069,9 +1069,9 @@ define i64 @vwreduce_uadd_v2i64(ptr %x) {
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: vmv.s.x v9, zero
-; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64-NEXT: vwredsumu.vs v8, v8, v9
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <2 x i32>, ptr %x
@@ -1116,7 +1116,7 @@ define i64 @vwreduce_add_v4i64(ptr %x) {
; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: vmv.s.x v9, zero
; RV32-NEXT: li a1, 32
-; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vwredsum.vs v8, v8, v9
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vmv.x.s a0, v8
@@ -1129,9 +1129,9 @@ define i64 @vwreduce_add_v4i64(ptr %x) {
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: vmv.s.x v9, zero
-; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vwredsum.vs v8, v8, v9
-; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <4 x i32>, ptr %x
@@ -1147,7 +1147,7 @@ define i64 @vwreduce_uadd_v4i64(ptr %x) {
; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: vmv.s.x v9, zero
; RV32-NEXT: li a1, 32
-; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vwredsumu.vs v8, v8, v9
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vmv.x.s a0, v8
@@ -1160,9 +1160,9 @@ define i64 @vwreduce_uadd_v4i64(ptr %x) {
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: vmv.s.x v9, zero
-; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vwredsumu.vs v8, v8, v9
-; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <4 x i32>, ptr %x
@@ -1207,7 +1207,7 @@ define i64 @vwreduce_add_v8i64(ptr %x) {
; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: vmv.s.x v10, zero
; RV32-NEXT: li a1, 32
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vwredsum.vs v8, v8, v10
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vmv.x.s a0, v8
@@ -1220,9 +1220,9 @@ define i64 @vwreduce_add_v8i64(ptr %x) {
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: vmv.s.x v10, zero
-; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64-NEXT: vwredsum.vs v8, v8, v10
-; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <8 x i32>, ptr %x
@@ -1238,7 +1238,7 @@ define i64 @vwreduce_uadd_v8i64(ptr %x) {
; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: vmv.s.x v10, zero
; RV32-NEXT: li a1, 32
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vwredsumu.vs v8, v8, v10
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vmv.x.s a0, v8
@@ -1251,9 +1251,9 @@ define i64 @vwreduce_uadd_v8i64(ptr %x) {
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: vmv.s.x v10, zero
-; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64-NEXT: vwredsumu.vs v8, v8, v10
-; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <8 x i32>, ptr %x
@@ -1298,7 +1298,7 @@ define i64 @vwreduce_add_v16i64(ptr %x) {
; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: vmv.s.x v12, zero
; RV32-NEXT: li a1, 32
-; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vwredsum.vs v8, v8, v12
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vmv.x.s a0, v8
@@ -1311,9 +1311,9 @@ define i64 @vwreduce_add_v16i64(ptr %x) {
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: vmv.s.x v12, zero
-; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV64-NEXT: vwredsum.vs v8, v8, v12
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <16 x i32>, ptr %x
@@ -1329,7 +1329,7 @@ define i64 @vwreduce_uadd_v16i64(ptr %x) {
; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: vmv.s.x v12, zero
; RV32-NEXT: li a1, 32
-; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vwredsumu.vs v8, v8, v12
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vmv.x.s a0, v8
@@ -1342,9 +1342,9 @@ define i64 @vwreduce_uadd_v16i64(ptr %x) {
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: vmv.s.x v12, zero
-; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV64-NEXT: vwredsumu.vs v8, v8, v12
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
%v = load <16 x i32>, ptr %x
@@ -1398,7 +1398,7 @@ define i64 @vwreduce_add_v32i64(ptr %x) {
; RV32-NEXT: vslidedown.vi v16, v8, 16
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vwadd.vv v24, v8, v16
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vmv.s.x v8, zero
; RV32-NEXT: vredsum.vs v8, v24, v8
; RV32-NEXT: vmv.x.s a0, v8
@@ -1416,7 +1416,7 @@ define i64 @vwreduce_add_v32i64(ptr %x) {
; RV64-NEXT: vslidedown.vi v16, v8, 16
; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV64-NEXT: vwadd.vv v24, v8, v16
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vmv.s.x v8, zero
; RV64-NEXT: vredsum.vs v8, v24, v8
; RV64-NEXT: vmv.x.s a0, v8
@@ -1437,7 +1437,7 @@ define i64 @vwreduce_uadd_v32i64(ptr %x) {
; RV32-NEXT: vslidedown.vi v16, v8, 16
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vwaddu.vv v24, v8, v16
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vmv.s.x v8, zero
; RV32-NEXT: vredsum.vs v8, v24, v8
; RV32-NEXT: vmv.x.s a0, v8
@@ -1455,7 +1455,7 @@ define i64 @vwreduce_uadd_v32i64(ptr %x) {
; RV64-NEXT: vslidedown.vi v16, v8, 16
; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV64-NEXT: vwaddu.vv v24, v8, v16
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vmv.s.x v8, zero
; RV64-NEXT: vredsum.vs v8, v24, v8
; RV64-NEXT: vmv.x.s a0, v8
@@ -1529,7 +1529,7 @@ define i64 @vwreduce_add_v64i64(ptr %x) {
; RV32-NEXT: vslidedown.vi v8, v16, 16
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vwadd.vv v16, v24, v8
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vadd.vv v8, v0, v16
; RV32-NEXT: vmv.s.x v16, zero
; RV32-NEXT: vredsum.vs v8, v8, v16
@@ -1561,7 +1561,7 @@ define i64 @vwreduce_add_v64i64(ptr %x) {
; RV64-NEXT: vwadd.vv v24, v8, v16
; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV64-NEXT: vwadd.vv v8, v16, v0
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vadd.vv v8, v24, v8
; RV64-NEXT: vmv.s.x v16, zero
; RV64-NEXT: vredsum.vs v8, v8, v16
@@ -1595,7 +1595,7 @@ define i64 @vwreduce_uadd_v64i64(ptr %x) {
; RV32-NEXT: vslidedown.vi v8, v16, 16
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vwaddu.vv v16, v24, v8
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vadd.vv v8, v0, v16
; RV32-NEXT: vmv.s.x v16, zero
; RV32-NEXT: vredsum.vs v8, v8, v16
@@ -1627,7 +1627,7 @@ define i64 @vwreduce_uadd_v64i64(ptr %x) {
; RV64-NEXT: vwaddu.vv v24, v8, v16
; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV64-NEXT: vwaddu.vv v8, v16, v0
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vadd.vv v8, v24, v8
; RV64-NEXT: vmv.s.x v16, zero
; RV64-NEXT: vredsum.vs v8, v8, v16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
index c0a213034c95b..39aa5a7dc03cf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
@@ -9,11 +9,11 @@ define signext i16 @sad_4x8_as_i16(<4 x i8> %a, <4 x i8> %b) {
; CHECK-NEXT: vminu.vv v10, v8, v9
; CHECK-NEXT: vmaxu.vv v8, v8, v9
; CHECK-NEXT: vsub.vv v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vmv.s.x v9, zero
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vwredsumu.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
entry:
@@ -32,7 +32,7 @@ define signext i32 @sad_4x8_as_i32(<4 x i8> %a, <4 x i8> %b) {
; CHECK-NEXT: vminu.vv v10, v8, v9
; CHECK-NEXT: vmaxu.vv v8, v8, v9
; CHECK-NEXT: vsub.vv v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vzext.vf4 v9, v8
; CHECK-NEXT: vmv.s.x v8, zero
; CHECK-NEXT: vredsum.vs v8, v9, v8
@@ -54,11 +54,11 @@ define signext i16 @sad_16x8_as_i16(<16 x i8> %a, <16 x i8> %b) {
; CHECK-NEXT: vminu.vv v10, v8, v9
; CHECK-NEXT: vmaxu.vv v8, v8, v9
; CHECK-NEXT: vsub.vv v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vmv.s.x v9, zero
-; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vwredsumu.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
entry:
@@ -77,7 +77,7 @@ define signext i32 @sad_16x8_as_i32(<16 x i8> %a, <16 x i8> %b) {
; CHECK-NEXT: vminu.vv v10, v8, v9
; CHECK-NEXT: vmaxu.vv v8, v8, v9
; CHECK-NEXT: vsub.vv v12, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vzext.vf4 v8, v12
; CHECK-NEXT: vmv.s.x v12, zero
; CHECK-NEXT: vredsum.vs v8, v8, v12
@@ -122,15 +122,15 @@ define signext i32 @sad_2block_16xi8_as_i32(ptr %a, ptr %b, i32 signext %stridea
; CHECK-NEXT: vsub.vv v8, v15, v14
; CHECK-NEXT: vminu.vv v10, v9, v11
; CHECK-NEXT: vmaxu.vv v9, v9, v11
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v14, v8
-; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vsub.vv v16, v9, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vwaddu.vv v8, v14, v12
; CHECK-NEXT: vzext.vf2 v12, v16
; CHECK-NEXT: vwaddu.wv v8, v8, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vmv.s.x v12, zero
; CHECK-NEXT: vredsum.vs v8, v8, v12
; CHECK-NEXT: vmv.x.s a0, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-bf16.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-bf16.ll
index 75ecd055a819d..c62ff7b95468b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-bf16.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-bf16.ll
@@ -10,7 +10,7 @@ define <2 x bfloat> @select_v2bf16(i1 zeroext %c, <2 x bfloat> %a, <2 x bfloat>
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <2 x bfloat> %a, <2 x bfloat> %b
@@ -26,7 +26,7 @@ define <2 x bfloat> @selectcc_v2bf16(bfloat %a, bfloat %b, <2 x bfloat> %c, <2 x
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%cmp = fcmp oeq bfloat %a, %b
@@ -40,7 +40,7 @@ define <4 x bfloat> @select_v4bf16(i1 zeroext %c, <4 x bfloat> %a, <4 x bfloat>
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <4 x bfloat> %a, <4 x bfloat> %b
@@ -56,7 +56,7 @@ define <4 x bfloat> @selectcc_v4bf16(bfloat %a, bfloat %b, <4 x bfloat> %c, <4 x
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%cmp = fcmp oeq bfloat %a, %b
@@ -70,7 +70,7 @@ define <8 x bfloat> @select_v8bf16(i1 zeroext %c, <8 x bfloat> %a, <8 x bfloat>
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <8 x bfloat> %a, <8 x bfloat> %b
@@ -86,7 +86,7 @@ define <8 x bfloat> @selectcc_v8bf16(bfloat %a, bfloat %b, <8 x bfloat> %c, <8 x
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%cmp = fcmp oeq bfloat %a, %b
@@ -100,7 +100,7 @@ define <16 x bfloat> @select_v16bf16(i1 zeroext %c, <16 x bfloat> %a, <16 x bflo
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vmsne.vi v0, v12, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <16 x bfloat> %a, <16 x bfloat> %b
@@ -116,7 +116,7 @@ define <16 x bfloat> @selectcc_v16bf16(bfloat %a, bfloat %b, <16 x bfloat> %c, <
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vmsne.vi v0, v12, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
%cmp = fcmp oeq bfloat %a, %b
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll
index d945cf5616981..ed25d3d5bfe05 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll
@@ -14,7 +14,7 @@ define <2 x half> @select_v2f16(i1 zeroext %c, <2 x half> %a, <2 x half> %b) {
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <2 x half> %a, <2 x half> %b
@@ -28,7 +28,7 @@ define <2 x half> @selectcc_v2f16(half %a, half %b, <2 x half> %c, <2 x half> %d
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%cmp = fcmp oeq half %a, %b
@@ -42,7 +42,7 @@ define <4 x half> @select_v4f16(i1 zeroext %c, <4 x half> %a, <4 x half> %b) {
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <4 x half> %a, <4 x half> %b
@@ -56,7 +56,7 @@ define <4 x half> @selectcc_v4f16(half %a, half %b, <4 x half> %c, <4 x half> %d
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%cmp = fcmp oeq half %a, %b
@@ -70,7 +70,7 @@ define <8 x half> @select_v8f16(i1 zeroext %c, <8 x half> %a, <8 x half> %b) {
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <8 x half> %a, <8 x half> %b
@@ -84,7 +84,7 @@ define <8 x half> @selectcc_v8f16(half %a, half %b, <8 x half> %c, <8 x half> %d
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%cmp = fcmp oeq half %a, %b
@@ -98,7 +98,7 @@ define <16 x half> @select_v16f16(i1 zeroext %c, <16 x half> %a, <16 x half> %b)
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vmsne.vi v0, v12, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <16 x half> %a, <16 x half> %b
@@ -112,7 +112,7 @@ define <16 x half> @selectcc_v16f16(half %a, half %b, <16 x half> %c, <16 x half
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vmsne.vi v0, v12, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
%cmp = fcmp oeq half %a, %b
@@ -126,7 +126,7 @@ define <2 x float> @select_v2f32(i1 zeroext %c, <2 x float> %a, <2 x float> %b)
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <2 x float> %a, <2 x float> %b
@@ -140,7 +140,7 @@ define <2 x float> @selectcc_v2f32(float %a, float %b, <2 x float> %c, <2 x floa
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%cmp = fcmp oeq float %a, %b
@@ -154,7 +154,7 @@ define <4 x float> @select_v4f32(i1 zeroext %c, <4 x float> %a, <4 x float> %b)
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <4 x float> %a, <4 x float> %b
@@ -168,7 +168,7 @@ define <4 x float> @selectcc_v4f32(float %a, float %b, <4 x float> %c, <4 x floa
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%cmp = fcmp oeq float %a, %b
@@ -182,7 +182,7 @@ define <8 x float> @select_v8f32(i1 zeroext %c, <8 x float> %a, <8 x float> %b)
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vmsne.vi v0, v12, 0
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <8 x float> %a, <8 x float> %b
@@ -196,7 +196,7 @@ define <8 x float> @selectcc_v8f32(float %a, float %b, <8 x float> %c, <8 x floa
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vmsne.vi v0, v12, 0
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
%cmp = fcmp oeq float %a, %b
@@ -210,7 +210,7 @@ define <16 x float> @select_v16f32(i1 zeroext %c, <16 x float> %a, <16 x float>
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vmsne.vi v0, v16, 0
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <16 x float> %a, <16 x float> %b
@@ -224,7 +224,7 @@ define <16 x float> @selectcc_v16f32(float %a, float %b, <16 x float> %c, <16 x
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vmsne.vi v0, v16, 0
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
%cmp = fcmp oeq float %a, %b
@@ -238,7 +238,7 @@ define <2 x double> @select_v2f64(i1 zeroext %c, <2 x double> %a, <2 x double> %
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <2 x double> %a, <2 x double> %b
@@ -252,7 +252,7 @@ define <2 x double> @selectcc_v2f64(double %a, double %b, <2 x double> %c, <2 x
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%cmp = fcmp oeq double %a, %b
@@ -266,7 +266,7 @@ define <4 x double> @select_v4f64(i1 zeroext %c, <4 x double> %a, <4 x double> %
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vmsne.vi v0, v12, 0
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <4 x double> %a, <4 x double> %b
@@ -280,7 +280,7 @@ define <4 x double> @selectcc_v4f64(double %a, double %b, <4 x double> %c, <4 x
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vmsne.vi v0, v12, 0
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
%cmp = fcmp oeq double %a, %b
@@ -294,7 +294,7 @@ define <8 x double> @select_v8f64(i1 zeroext %c, <8 x double> %a, <8 x double> %
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vmsne.vi v0, v16, 0
-; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <8 x double> %a, <8 x double> %b
@@ -308,7 +308,7 @@ define <8 x double> @selectcc_v8f64(double %a, double %b, <8 x double> %c, <8 x
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vmsne.vi v0, v16, 0
-; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
%cmp = fcmp oeq double %a, %b
@@ -322,7 +322,7 @@ define <16 x double> @select_v16f64(i1 zeroext %c, <16 x double> %a, <16 x doubl
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v24, a0
; CHECK-NEXT: vmsne.vi v0, v24, 0
-; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <16 x double> %a, <16 x double> %b
@@ -336,7 +336,7 @@ define <16 x double> @selectcc_v16f64(double %a, double %b, <16 x double> %c, <1
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v24, a0
; CHECK-NEXT: vmsne.vi v0, v24, 0
-; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: ret
%cmp = fcmp oeq double %a, %b
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll
index 69cc7c36b793b..3f53bc720eb63 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll
@@ -273,7 +273,7 @@ define <2 x i16> @select_v2i16(i1 zeroext %c, <2 x i16> %a, <2 x i16> %b) {
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <2 x i16> %a, <2 x i16> %b
@@ -288,7 +288,7 @@ define <2 x i16> @selectcc_v2i16(i16 signext %a, i16 signext %b, <2 x i16> %c, <
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%cmp = icmp ne i16 %a, %b
@@ -302,7 +302,7 @@ define <4 x i16> @select_v4i16(i1 zeroext %c, <4 x i16> %a, <4 x i16> %b) {
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <4 x i16> %a, <4 x i16> %b
@@ -317,7 +317,7 @@ define <4 x i16> @selectcc_v4i16(i16 signext %a, i16 signext %b, <4 x i16> %c, <
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%cmp = icmp ne i16 %a, %b
@@ -331,7 +331,7 @@ define <8 x i16> @select_v8i16(i1 zeroext %c, <8 x i16> %a, <8 x i16> %b) {
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <8 x i16> %a, <8 x i16> %b
@@ -346,7 +346,7 @@ define <8 x i16> @selectcc_v8i16(i16 signext %a, i16 signext %b, <8 x i16> %c, <
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%cmp = icmp ne i16 %a, %b
@@ -360,7 +360,7 @@ define <16 x i16> @select_v16i16(i1 zeroext %c, <16 x i16> %a, <16 x i16> %b) {
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vmsne.vi v0, v12, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <16 x i16> %a, <16 x i16> %b
@@ -375,7 +375,7 @@ define <16 x i16> @selectcc_v16i16(i16 signext %a, i16 signext %b, <16 x i16> %c
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vmsne.vi v0, v12, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
%cmp = icmp ne i16 %a, %b
@@ -389,7 +389,7 @@ define <2 x i32> @select_v2i32(i1 zeroext %c, <2 x i32> %a, <2 x i32> %b) {
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <2 x i32> %a, <2 x i32> %b
@@ -404,7 +404,7 @@ define <2 x i32> @selectcc_v2i32(i32 signext %a, i32 signext %b, <2 x i32> %c, <
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%cmp = icmp ne i32 %a, %b
@@ -418,7 +418,7 @@ define <4 x i32> @select_v4i32(i1 zeroext %c, <4 x i32> %a, <4 x i32> %b) {
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <4 x i32> %a, <4 x i32> %b
@@ -433,7 +433,7 @@ define <4 x i32> @selectcc_v4i32(i32 signext %a, i32 signext %b, <4 x i32> %c, <
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%cmp = icmp ne i32 %a, %b
@@ -447,7 +447,7 @@ define <8 x i32> @select_v8i32(i1 zeroext %c, <8 x i32> %a, <8 x i32> %b) {
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vmsne.vi v0, v12, 0
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <8 x i32> %a, <8 x i32> %b
@@ -462,7 +462,7 @@ define <8 x i32> @selectcc_v8i32(i32 signext %a, i32 signext %b, <8 x i32> %c, <
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vmsne.vi v0, v12, 0
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
%cmp = icmp ne i32 %a, %b
@@ -476,7 +476,7 @@ define <16 x i32> @select_v16i32(i1 zeroext %c, <16 x i32> %a, <16 x i32> %b) {
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vmsne.vi v0, v16, 0
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <16 x i32> %a, <16 x i32> %b
@@ -491,7 +491,7 @@ define <16 x i32> @selectcc_v16i32(i32 signext %a, i32 signext %b, <16 x i32> %c
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vmsne.vi v0, v16, 0
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
%cmp = icmp ne i32 %a, %b
@@ -505,7 +505,7 @@ define <2 x i64> @select_v2i64(i1 zeroext %c, <2 x i64> %a, <2 x i64> %b) {
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <2 x i64> %a, <2 x i64> %b
@@ -522,7 +522,7 @@ define <2 x i64> @selectcc_v2i64(i64 signext %a, i64 signext %b, <2 x i64> %c, <
; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.x v10, a0
; RV32-NEXT: vmsne.vi v0, v10, 0
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vmerge.vvm v8, v9, v8, v0
; RV32-NEXT: ret
;
@@ -533,7 +533,7 @@ define <2 x i64> @selectcc_v2i64(i64 signext %a, i64 signext %b, <2 x i64> %c, <
; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: vmsne.vi v0, v10, 0
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vmerge.vvm v8, v9, v8, v0
; RV64-NEXT: ret
%cmp = icmp ne i64 %a, %b
@@ -547,7 +547,7 @@ define <4 x i64> @select_v4i64(i1 zeroext %c, <4 x i64> %a, <4 x i64> %b) {
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vmsne.vi v0, v12, 0
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <4 x i64> %a, <4 x i64> %b
@@ -564,7 +564,7 @@ define <4 x i64> @selectcc_v4i64(i64 signext %a, i64 signext %b, <4 x i64> %c, <
; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; RV32-NEXT: vmv.v.x v12, a0
; RV32-NEXT: vmsne.vi v0, v12, 0
-; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32-NEXT: vmerge.vvm v8, v10, v8, v0
; RV32-NEXT: ret
;
@@ -575,7 +575,7 @@ define <4 x i64> @selectcc_v4i64(i64 signext %a, i64 signext %b, <4 x i64> %c, <
; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; RV64-NEXT: vmv.v.x v12, a0
; RV64-NEXT: vmsne.vi v0, v12, 0
-; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64-NEXT: vmerge.vvm v8, v10, v8, v0
; RV64-NEXT: ret
%cmp = icmp ne i64 %a, %b
@@ -589,7 +589,7 @@ define <8 x i64> @select_v8i64(i1 zeroext %c, <8 x i64> %a, <8 x i64> %b) {
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vmsne.vi v0, v16, 0
-; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <8 x i64> %a, <8 x i64> %b
@@ -606,7 +606,7 @@ define <8 x i64> @selectcc_v8i64(i64 signext %a, i64 signext %b, <8 x i64> %c, <
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vmv.v.x v16, a0
; RV32-NEXT: vmsne.vi v0, v16, 0
-; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: vmerge.vvm v8, v12, v8, v0
; RV32-NEXT: ret
;
@@ -617,7 +617,7 @@ define <8 x i64> @selectcc_v8i64(i64 signext %a, i64 signext %b, <8 x i64> %c, <
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64-NEXT: vmv.v.x v16, a0
; RV64-NEXT: vmsne.vi v0, v16, 0
-; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vmerge.vvm v8, v12, v8, v0
; RV64-NEXT: ret
%cmp = icmp ne i64 %a, %b
@@ -631,7 +631,7 @@ define <16 x i64> @select_v16i64(i1 zeroext %c, <16 x i64> %a, <16 x i64> %b) {
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v24, a0
; CHECK-NEXT: vmsne.vi v0, v24, 0
-; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: ret
%v = select i1 %c, <16 x i64> %a, <16 x i64> %b
@@ -648,7 +648,7 @@ define <16 x i64> @selectcc_v16i64(i64 signext %a, i64 signext %b, <16 x i64> %c
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmv.v.x v24, a0
; RV32-NEXT: vmsne.vi v0, v24, 0
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vmerge.vvm v8, v16, v8, v0
; RV32-NEXT: ret
;
@@ -659,7 +659,7 @@ define <16 x i64> @selectcc_v16i64(i64 signext %a, i64 signext %b, <16 x i64> %c
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vmv.v.x v24, a0
; RV64-NEXT: vmsne.vi v0, v24, 0
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vmerge.vvm v8, v16, v8, v0
; RV64-NEXT: ret
%cmp = icmp ne i64 %a, %b
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
index c05f306424519..949f075bd8566 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
@@ -236,24 +236,24 @@ define <16 x i32> @v16i32_v4i32(<4 x i32>) {
; CHECK-NEXT: lui a0, 2
; CHECK-NEXT: vmv.v.i v8, 3
; CHECK-NEXT: addi a1, a0, 265
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vmv.s.x v0, a1
; CHECK-NEXT: lui a1, 4
; CHECK-NEXT: addi a1, a1, 548
-; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmerge.vim v8, v8, 2, v0
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vmv.s.x v0, a1
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: addi a0, a0, -1856
-; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: srli a1, a1, 2
-; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vsext.vf2 v10, v8
; CHECK-NEXT: vslidedown.vx v14, v10, a1
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
index 63b96a96a284a..b21ab72956b31 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
@@ -63,7 +63,7 @@ define void @deinterleave4_0_i8(ptr %in, ptr %out) {
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vse8.v v8, (a1)
@@ -82,7 +82,7 @@ define void @deinterleave4_8_i8(ptr %in, ptr %out) {
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 8
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vse8.v v8, (a1)
@@ -234,9 +234,9 @@ define void @deinterleave8_0_i8(ptr %in, ptr %out) {
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vse8.v v8, (a1)
@@ -255,9 +255,9 @@ define void @deinterleave8_8_i8(ptr %in, ptr %out) {
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vse8.v v8, (a1)
@@ -303,7 +303,7 @@ define void @deinterleave4_0_i8_subvec(ptr %in, ptr %out) {
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
@@ -371,7 +371,7 @@ define void @deinterleave4_0_i8_two_source(ptr %in0, ptr %in1, ptr %out) {
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vnsrl.wi v9, v9, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vnsrl.wi v9, v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
@@ -396,7 +396,7 @@ define void @deinterleave4_8_i8_two_source(ptr %in0, ptr %in1, ptr %out) {
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 8
; CHECK-NEXT: vnsrl.wi v9, v9, 8
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vnsrl.wi v9, v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
@@ -419,7 +419,7 @@ define void @deinterleave8_0_i8_two_source(ptr %in0, ptr %in1, ptr %out) {
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, ma
; CHECK-NEXT: vle8.v v9, (a1)
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, tu, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vse8.v v8, (a2)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
index f80b7bd94490e..3d2e8ff2862d1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
@@ -1385,12 +1385,12 @@ define <16 x i64> @unzip2a_dual_v16i64(<16 x i64> %a, <16 x i64> %b) {
; V-NEXT: vmv.s.x v20, a0
; V-NEXT: li a0, -256
; V-NEXT: vadd.vv v21, v16, v16
-; V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; V-NEXT: vsetivli zero, 16, e64, m4, ta, ma
; V-NEXT: vcompress.vm v16, v8, v20
; V-NEXT: vmv.s.x v0, a0
-; V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; V-NEXT: vsetivli zero, 16, e16, m1, ta, ma
; V-NEXT: vadd.vi v8, v21, -16
-; V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; V-NEXT: vsetivli zero, 16, e64, m4, ta, mu
; V-NEXT: vrgatherei16.vv v16, v12, v8, v0.t
; V-NEXT: vmv.v.v v8, v16
; V-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
index 3250821a92534..b7e1533a2031a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
@@ -74,7 +74,7 @@ define <8 x i32> @m2_pair_swap_vl8(<8 x i32> %v1) vscale_range(2,2) {
; RV32-NEXT: li a0, 32
; RV32-NEXT: li a1, 63
; RV32-NEXT: vwsubu.vx v10, v12, a0
-; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32-NEXT: vmv.v.x v12, a0
; RV32-NEXT: vand.vx v10, v10, a1
; RV32-NEXT: vand.vx v12, v12, a1
@@ -310,7 +310,7 @@ define <16 x i32> @m4_square_num_of_shuffles_in_chunks(<16 x i32> %0) vscale_ran
; CHECK-NEXT: vl1r.v v12, (a0)
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vsext.vf2 v16, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vrgatherei16.vv v12, v8, v16
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
@@ -342,7 +342,7 @@ define i64 @multi_chunks_shuffle(<32 x i32> %0) vscale_range(8,8) {
; RV32-NEXT: li a0, 32
; RV32-NEXT: li a1, 63
; RV32-NEXT: vwsubu.vx v10, v12, a0
-; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e64, m2, ta, ma
; RV32-NEXT: vmv.v.x v12, a0
; RV32-NEXT: lui a0, 61681
; RV32-NEXT: addi a0, a0, -241
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp-interleave.ll
index bc8cdf8832d41..4bb9f12d341cc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp-interleave.ll
@@ -344,9 +344,9 @@ define <4 x double> @unary_interleave_v4f64(<4 x double> %x) {
; V128-NEXT: addi a0, a0, 512
; V128-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; V128-NEXT: vmv.s.x v10, a0
-; V128-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; V128-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; V128-NEXT: vsext.vf2 v12, v10
-; V128-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; V128-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; V128-NEXT: vrgatherei16.vv v10, v8, v12
; V128-NEXT: vmv.v.v v8, v10
; V128-NEXT: ret
@@ -359,7 +359,7 @@ define <4 x double> @unary_interleave_v4f64(<4 x double> %x) {
; RV32-V512-NEXT: vmv.s.x v9, a0
; RV32-V512-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
; RV32-V512-NEXT: vsext.vf2 v10, v9
-; RV32-V512-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-V512-NEXT: vsetivli zero, 4, e64, m1, ta, ma
; RV32-V512-NEXT: vrgatherei16.vv v9, v8, v10
; RV32-V512-NEXT: vmv.v.v v8, v9
; RV32-V512-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp.ll
index 965d0b0fe0f9b..e5604d538f08d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp.ll
@@ -501,9 +501,9 @@ define <16 x float> @shuffle_disjoint_lanes(<16 x float> %v, <16 x float> %w) {
; CHECK-NEXT: addi a0, a0, -1366
; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vmerge.vvm v12, v12, v8, v0
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vsext.vf2 v16, v18
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vrgatherei16.vv v8, v12, v16
; CHECK-NEXT: ret
%out = shufflevector <16 x float> %v, <16 x float> %w, <16 x i32> <i32 11, i32 15, i32 7, i32 3, i32 26, i32 30, i32 22, i32 18, i32 9, i32 13, i32 5, i32 1, i32 24, i32 28, i32 20, i32 16>
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
index 9bbfad4f32ffa..877041d5b574f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
@@ -723,7 +723,7 @@ define <4 x i8> @unary_interleave_v4i8_invalid(<4 x i8> %x) {
; V128-NEXT: addi a0, a0, 768
; V128-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; V128-NEXT: vmv.s.x v10, a0
-; V128-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; V128-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; V128-NEXT: vrgather.vv v9, v8, v10
; V128-NEXT: vmv1r.v v8, v9
; V128-NEXT: ret
@@ -745,7 +745,7 @@ define <4 x i8> @unary_interleave_v4i8_invalid(<4 x i8> %x) {
; ZIP-NEXT: addi a0, a0, 768
; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZIP-NEXT: vmv.s.x v10, a0
-; ZIP-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; ZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; ZIP-NEXT: vrgather.vv v9, v8, v10
; ZIP-NEXT: vmv1r.v v8, v9
; ZIP-NEXT: ret
@@ -829,9 +829,9 @@ define <4 x i64> @unary_interleave_v4i64(<4 x i64> %x) {
; V128-NEXT: addi a0, a0, 512
; V128-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; V128-NEXT: vmv.s.x v10, a0
-; V128-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; V128-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; V128-NEXT: vsext.vf2 v12, v10
-; V128-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; V128-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; V128-NEXT: vrgatherei16.vv v10, v8, v12
; V128-NEXT: vmv.v.v v8, v10
; V128-NEXT: ret
@@ -844,7 +844,7 @@ define <4 x i64> @unary_interleave_v4i64(<4 x i64> %x) {
; RV32-V512-NEXT: vmv.s.x v9, a0
; RV32-V512-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
; RV32-V512-NEXT: vsext.vf2 v10, v9
-; RV32-V512-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-V512-NEXT: vsetivli zero, 4, e64, m1, ta, ma
; RV32-V512-NEXT: vrgatherei16.vv v9, v8, v10
; RV32-V512-NEXT: vmv.v.v v8, v9
; RV32-V512-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll
index 5683476852683..cb555e1357e98 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll
@@ -151,13 +151,13 @@ define <8 x i64> @vrgather_shuffle_vv_v8i64(<8 x i64> %x, <8 x i64> %y) {
; RV32-NEXT: vle16.v v20, (a0)
; RV32-NEXT: vmv.v.i v21, 2
; RV32-NEXT: li a0, 164
-; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: vrgatherei16.vv v16, v8, v20
; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: li a0, 5
-; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vslide1down.vx v8, v21, a0
-; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vrgatherei16.vv v16, v12, v8, v0.t
; RV32-NEXT: vmv.v.v v8, v16
; RV32-NEXT: ret
@@ -325,9 +325,9 @@ define <8 x i8> @splat_ve4_ins_i0ve2(<8 x i8> %v) {
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v10, 4
; CHECK-NEXT: li a0, 2
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, tu, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, tu, ma
; CHECK-NEXT: vmv.s.x v10, a0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
@@ -372,11 +372,11 @@ define <8 x i8> @splat_ve2_we0_ins_i0ve4(<8 x i8> %v, <8 x i8> %w) {
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v11, 2
; CHECK-NEXT: li a0, 4
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, tu, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, tu, ma
; CHECK-NEXT: vmv.s.x v11, a0
; CHECK-NEXT: li a0, 66
; CHECK-NEXT: vmv.s.x v0, a0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vv v10, v8, v11
; CHECK-NEXT: vrgather.vi v10, v9, 0, v0.t
; CHECK-NEXT: vmv1r.v v8, v10
@@ -705,9 +705,9 @@ define <8 x i8> @shuffle_v64i8_v8i8(<64 x i8> %wide.vec) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v12, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%s = shufflevector <64 x i8> %wide.vec, <64 x i8> poison, <8 x i32> <i32 0, i32 8, i32 16, i32 24, i32 32, i32 40, i32 48, i32 56>
@@ -1013,9 +1013,9 @@ define <16 x i32> @shuffle_disjoint_lanes(<16 x i32> %v, <16 x i32> %w) {
; CHECK-NEXT: addi a0, a0, -1366
; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vmerge.vvm v12, v12, v8, v0
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vsext.vf2 v16, v18
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vrgatherei16.vv v8, v12, v16
; CHECK-NEXT: ret
%out = shufflevector <16 x i32> %v, <16 x i32> %w, <16 x i32> <i32 11, i32 15, i32 7, i32 3, i32 26, i32 30, i32 22, i32 18, i32 9, i32 13, i32 5, i32 1, i32 24, i32 28, i32 20, i32 16>
@@ -1200,7 +1200,7 @@ define void @shuffle_i256_ldst(ptr %p) {
; CHECK-NEXT: vle8.v v16, (a1)
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsext.vf2 v24, v16
-; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vrgatherei16.vv v16, v8, v24
; CHECK-NEXT: vse64.v v16, (a0)
; CHECK-NEXT: ret
@@ -1264,7 +1264,7 @@ define void @shuffle_i256_splat(ptr %p) nounwind {
; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV32-NEXT: vsext.vf2 v24, v16
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vrgatherei16.vv v16, v8, v24
; RV32-NEXT: vse64.v v16, (a0)
; RV32-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
index 06521a8739bac..00afcf4c16a2a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
@@ -776,7 +776,7 @@ define <3 x i64> @reverse_v3i64(<3 x i64> %a) {
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vid.v v10
; CHECK-NEXT: vrsub.vi v12, v10, 2
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
@@ -790,7 +790,7 @@ define <6 x i64> @reverse_v6i64(<6 x i64> %a) {
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vid.v v12
; CHECK-NEXT: vrsub.vi v16, v12, 5
-; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vrgatherei16.vv v12, v8, v16
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
@@ -804,7 +804,7 @@ define <12 x i64> @reverse_v12i64(<12 x i64> %a) {
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vid.v v16
; CHECK-NEXT: vrsub.vi v24, v16, 11
-; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vrgatherei16.vv v16, v8, v24
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
index 5c17283cacd1b..b4c1eaf083826 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
@@ -484,7 +484,7 @@ define <8 x i16> @shuffle_v8i16_as_i64_16(<8 x i16> %v) {
; RV32-NEXT: li a0, 48
; RV32-NEXT: li a1, 63
; RV32-NEXT: vwsubu.vx v10, v9, a0
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vand.vx v10, v10, a1
; RV32-NEXT: vand.vx v9, v9, a1
@@ -529,7 +529,7 @@ define <8 x i16> @shuffle_v8i16_as_i64_32(<8 x i16> %v) {
; RV32-NEXT: li a0, 32
; RV32-NEXT: li a1, 63
; RV32-NEXT: vwsubu.vx v10, v9, a0
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vand.vx v10, v10, a1
; RV32-NEXT: vand.vx v9, v9, a1
@@ -574,7 +574,7 @@ define <8 x i16> @shuffle_v8i16_as_i64_48(<8 x i16> %v) {
; RV32-NEXT: li a0, 16
; RV32-NEXT: li a1, 63
; RV32-NEXT: vwsubu.vx v10, v9, a0
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vand.vx v10, v10, a1
; RV32-NEXT: vand.vx v9, v9, a1
@@ -619,7 +619,7 @@ define <8 x i32> @shuffle_v8i32_as_i64(<8 x i32> %v) {
; RV32-NEXT: li a0, 32
; RV32-NEXT: li a1, 63
; RV32-NEXT: vwsubu.vx v10, v12, a0
-; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32-NEXT: vmv.v.x v12, a0
; RV32-NEXT: vand.vx v10, v10, a1
; RV32-NEXT: vand.vx v12, v12, a1
@@ -688,7 +688,7 @@ define <8 x half> @shuffle_v8f16_as_i64_16(<8 x half> %v) {
; RV32-NEXT: li a0, 48
; RV32-NEXT: li a1, 63
; RV32-NEXT: vwsubu.vx v10, v9, a0
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vand.vx v10, v10, a1
; RV32-NEXT: vand.vx v9, v9, a1
@@ -733,7 +733,7 @@ define <8 x half> @shuffle_v8f16_as_i64_32(<8 x half> %v) {
; RV32-NEXT: li a0, 32
; RV32-NEXT: li a1, 63
; RV32-NEXT: vwsubu.vx v10, v9, a0
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vand.vx v10, v10, a1
; RV32-NEXT: vand.vx v9, v9, a1
@@ -778,7 +778,7 @@ define <8 x half> @shuffle_v8f16_as_i64_48(<8 x half> %v) {
; RV32-NEXT: li a0, 16
; RV32-NEXT: li a1, 63
; RV32-NEXT: vwsubu.vx v10, v9, a0
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vmv.v.x v9, a0
; RV32-NEXT: vand.vx v10, v10, a1
; RV32-NEXT: vand.vx v9, v9, a1
@@ -823,7 +823,7 @@ define <8 x float> @shuffle_v8f32_as_i64(<8 x float> %v) {
; RV32-NEXT: li a0, 32
; RV32-NEXT: li a1, 63
; RV32-NEXT: vwsubu.vx v10, v12, a0
-; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32-NEXT: vmv.v.x v12, a0
; RV32-NEXT: vand.vx v10, v10, a1
; RV32-NEXT: vand.vx v12, v12, a1
@@ -868,7 +868,7 @@ define <8 x float> @shuffle_v8f32_as_i64_exact(<8 x float> %v) vscale_range(2,2)
; RV32-NEXT: li a0, 32
; RV32-NEXT: li a1, 63
; RV32-NEXT: vwsubu.vx v10, v12, a0
-; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32-NEXT: vmv.v.x v12, a0
; RV32-NEXT: vand.vx v10, v10, a1
; RV32-NEXT: vand.vx v12, v12, a1
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll
index 348c221c9dcea..102f92e7a50cc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll
@@ -277,7 +277,7 @@ define <2 x double> @vslide1up_v2f64_inverted(<2 x double> %v, double %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vrgather.vi v9, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, tu, ma
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
@@ -291,7 +291,7 @@ define <4 x i8> @vslide1up_4xi8_inverted(<4 x i8> %v, i8 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v9, v8, 1
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, tu, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, tu, ma
; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
index d18e1246ea54f..3ca3563413519 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
@@ -160,7 +160,7 @@ define void @store_constant_v4i16(ptr %p) {
; CHECK-NEXT: addi a1, a1, 1539
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.s.x v8, a1
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vsext.vf2 v9, v8
; CHECK-NEXT: vse16.v v9, (a0)
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-sat-clip.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-sat-clip.ll
index 3b1dc298c12ce..1b774a3e28848 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-sat-clip.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-sat-clip.ll
@@ -53,7 +53,7 @@ define void @trunc_sat_i8i16_notopt(ptr %x, ptr %y) {
; CHECK-NEXT: vmax.vx v8, v8, a0
; CHECK-NEXT: li a0, 128
; CHECK-NEXT: vmin.vx v8, v8, a0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
@@ -87,7 +87,7 @@ define void @trunc_sat_u8u16_notopt(ptr %x, ptr %y) {
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vminu.vx v8, v8, a0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
@@ -104,7 +104,7 @@ define void @trunc_sat_u8u16_maxmin(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmax.vx v8, v8, zero
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
@@ -122,7 +122,7 @@ define void @trunc_sat_u8u16_minmax(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmax.vx v8, v8, zero
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
@@ -145,7 +145,7 @@ define void @trunc_sat_i16i32_notopt(ptr %x, ptr %y) {
; CHECK-NEXT: vmax.vx v8, v8, a0
; CHECK-NEXT: lui a0, 8
; CHECK-NEXT: vmin.vx v8, v8, a0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
@@ -197,7 +197,7 @@ define void @trunc_sat_u16u32_notopt(ptr %x, ptr %y) {
; CHECK-NEXT: lui a0, 8
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vminu.vx v8, v8, a0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
@@ -230,7 +230,7 @@ define void @trunc_sat_u16u32_maxmin(ptr %x, ptr %y) {
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: li a0, 1
; CHECK-NEXT: vmax.vx v8, v8, a0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v8, 0
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
@@ -249,7 +249,7 @@ define void @trunc_sat_u16u32_minmax(ptr %x, ptr %y) {
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: li a0, 50
; CHECK-NEXT: vmax.vx v8, v8, a0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v8, 0
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
@@ -273,7 +273,7 @@ define void @trunc_sat_i32i64_notopt(ptr %x, ptr %y) {
; CHECK-NEXT: li a0, 1
; CHECK-NEXT: slli a0, a0, 31
; CHECK-NEXT: vmin.vx v8, v8, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vse32.v v10, (a1)
; CHECK-NEXT: ret
@@ -326,7 +326,7 @@ define void @trunc_sat_u32u64_notopt(ptr %x, ptr %y) {
; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: addiw a0, a0, -1
; CHECK-NEXT: vminu.vx v8, v8, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vse32.v v10, (a1)
; CHECK-NEXT: ret
@@ -359,7 +359,7 @@ define void @trunc_sat_u32u64_maxmin(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmax.vx v8, v8, zero
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vnclipu.wi v10, v8, 0
; CHECK-NEXT: vse32.v v10, (a1)
; CHECK-NEXT: ret
@@ -377,7 +377,7 @@ define void @trunc_sat_u32u64_minmax(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmax.vx v8, v8, zero
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vnclipu.wi v10, v8, 0
; CHECK-NEXT: vse32.v v10, (a1)
; CHECK-NEXT: ret
@@ -395,7 +395,7 @@ define void @trunc_sat_i8i32_maxmin(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vnclip.wi v8, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnclip.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
@@ -413,7 +413,7 @@ define void @trunc_sat_i8i32_minmax(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vnclip.wi v8, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnclip.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
@@ -431,7 +431,7 @@ define void @trunc_sat_u8u32_min(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vnclipu.wi v8, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
@@ -448,9 +448,9 @@ define void @trunc_sat_u8u32_maxmin(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmax.vx v8, v8, zero
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
@@ -468,9 +468,9 @@ define void @trunc_sat_u8u32_minmax(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmax.vx v8, v8, zero
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
@@ -488,9 +488,9 @@ define void @trunc_sat_i8i64_maxmin(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vnclip.wi v10, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnclip.wi v8, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnclip.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
@@ -508,9 +508,9 @@ define void @trunc_sat_i8i64_minmax(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vnclip.wi v10, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnclip.wi v8, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnclip.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
@@ -528,9 +528,9 @@ define void @trunc_sat_u8u64_min(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vnclipu.wi v10, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
@@ -547,11 +547,11 @@ define void @trunc_sat_u8u64_maxmin(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmax.vx v8, v8, zero
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vnclipu.wi v10, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
@@ -569,11 +569,11 @@ define void @trunc_sat_u8u64_minmax(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmax.vx v8, v8, zero
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vnclipu.wi v10, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
@@ -591,7 +591,7 @@ define void @trunc_sat_i16i64_maxmin(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vnclip.wi v10, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnclip.wi v8, v10, 0
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
@@ -609,7 +609,7 @@ define void @trunc_sat_i16i64_minmax(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vnclip.wi v10, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnclip.wi v8, v10, 0
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
@@ -629,9 +629,9 @@ define void @trunc_sat_u16u64_notopt(ptr %x, ptr %y) {
; CHECK-NEXT: lui a0, 8
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vminu.vx v8, v8, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
@@ -648,7 +648,7 @@ define void @trunc_sat_u16u64_min(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vnclipu.wi v10, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v10, 0
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
@@ -666,9 +666,9 @@ define void @trunc_sat_u16u64_maxmin(ptr %x, ptr %y) {
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: li a0, 1
; CHECK-NEXT: vmax.vx v8, v8, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vnclipu.wi v10, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v10, 0
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
@@ -687,9 +687,9 @@ define void @trunc_sat_u16u64_minmax(ptr %x, ptr %y) {
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: li a0, 50
; CHECK-NEXT: vmax.vx v8, v8, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vnclipu.wi v10, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v10, 0
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
index fa39b06b4d779..3943c408624ac 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
@@ -82,13 +82,13 @@ define <2 x i16> @mgather_v2i16_align1(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i16> %
; RV32-SLOW-NEXT: andi a1, a0, 1
; RV32-SLOW-NEXT: beqz a1, .LBB4_2
; RV32-SLOW-NEXT: # %bb.1: # %cond.load
-; RV32-SLOW-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32-SLOW-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV32-SLOW-NEXT: vmv.x.s a1, v8
; RV32-SLOW-NEXT: lbu a2, 1(a1)
; RV32-SLOW-NEXT: lbu a1, 0(a1)
; RV32-SLOW-NEXT: slli a2, a2, 8
; RV32-SLOW-NEXT: or a1, a2, a1
-; RV32-SLOW-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV32-SLOW-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV32-SLOW-NEXT: vmv.s.x v9, a1
; RV32-SLOW-NEXT: .LBB4_2: # %else
; RV32-SLOW-NEXT: andi a0, a0, 2
@@ -116,13 +116,13 @@ define <2 x i16> @mgather_v2i16_align1(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i16> %
; RV64-SLOW-NEXT: andi a1, a0, 1
; RV64-SLOW-NEXT: beqz a1, .LBB4_2
; RV64-SLOW-NEXT: # %bb.1: # %cond.load
-; RV64-SLOW-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64-SLOW-NEXT: vsetivli zero, 1, e64, m8, ta, ma
; RV64-SLOW-NEXT: vmv.x.s a1, v8
; RV64-SLOW-NEXT: lbu a2, 1(a1)
; RV64-SLOW-NEXT: lbu a1, 0(a1)
; RV64-SLOW-NEXT: slli a2, a2, 8
; RV64-SLOW-NEXT: or a1, a2, a1
-; RV64-SLOW-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64-SLOW-NEXT: vsetivli zero, 1, e16, m2, tu, ma
; RV64-SLOW-NEXT: vmv.s.x v9, a1
; RV64-SLOW-NEXT: .LBB4_2: # %else
; RV64-SLOW-NEXT: andi a0, a0, 2
@@ -202,7 +202,7 @@ define <2 x i64> @mgather_v2i64_align4(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i64> %
; RV64-SLOW-NEXT: andi a1, a0, 1
; RV64-SLOW-NEXT: beqz a1, .LBB5_2
; RV64-SLOW-NEXT: # %bb.1: # %cond.load
-; RV64-SLOW-NEXT: vsetvli zero, zero, e64, m8, tu, ma
+; RV64-SLOW-NEXT: vsetivli zero, 1, e64, m8, tu, ma
; RV64-SLOW-NEXT: vmv.x.s a1, v8
; RV64-SLOW-NEXT: lw a2, 4(a1)
; RV64-SLOW-NEXT: lwu a1, 0(a1)
@@ -265,9 +265,9 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x ptr> %ptrs, <4 x i1> %m)
; RV32-SLOW-NEXT: .LBB6_4: # %else6
; RV32-SLOW-NEXT: ret
; RV32-SLOW-NEXT: .LBB6_5: # %cond.store
-; RV32-SLOW-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32-SLOW-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV32-SLOW-NEXT: vmv.x.s a1, v8
-; RV32-SLOW-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32-SLOW-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV32-SLOW-NEXT: vmv.x.s a2, v9
; RV32-SLOW-NEXT: srli a3, a1, 8
; RV32-SLOW-NEXT: sb a1, 0(a2)
@@ -278,7 +278,7 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x ptr> %ptrs, <4 x i1> %m)
; RV32-SLOW-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV32-SLOW-NEXT: vslidedown.vi v10, v8, 1
; RV32-SLOW-NEXT: vmv.x.s a1, v10
-; RV32-SLOW-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32-SLOW-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32-SLOW-NEXT: vslidedown.vi v10, v9, 1
; RV32-SLOW-NEXT: vmv.x.s a2, v10
; RV32-SLOW-NEXT: srli a3, a1, 8
@@ -290,7 +290,7 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x ptr> %ptrs, <4 x i1> %m)
; RV32-SLOW-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV32-SLOW-NEXT: vslidedown.vi v10, v8, 2
; RV32-SLOW-NEXT: vmv.x.s a1, v10
-; RV32-SLOW-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32-SLOW-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32-SLOW-NEXT: vslidedown.vi v10, v9, 2
; RV32-SLOW-NEXT: vmv.x.s a2, v10
; RV32-SLOW-NEXT: srli a3, a1, 8
@@ -301,11 +301,11 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x ptr> %ptrs, <4 x i1> %m)
; RV32-SLOW-NEXT: .LBB6_8: # %cond.store5
; RV32-SLOW-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV32-SLOW-NEXT: vslidedown.vi v8, v8, 3
-; RV32-SLOW-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32-SLOW-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32-SLOW-NEXT: vslidedown.vi v9, v9, 3
-; RV32-SLOW-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV32-SLOW-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV32-SLOW-NEXT: vmv.x.s a0, v8
-; RV32-SLOW-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32-SLOW-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32-SLOW-NEXT: vmv.x.s a1, v9
; RV32-SLOW-NEXT: srli a2, a0, 8
; RV32-SLOW-NEXT: sb a0, 0(a1)
@@ -330,9 +330,9 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x ptr> %ptrs, <4 x i1> %m)
; RV64-SLOW-NEXT: .LBB6_4: # %else6
; RV64-SLOW-NEXT: ret
; RV64-SLOW-NEXT: .LBB6_5: # %cond.store
-; RV64-SLOW-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64-SLOW-NEXT: vsetivli zero, 1, e16, m2, ta, ma
; RV64-SLOW-NEXT: vmv.x.s a1, v8
-; RV64-SLOW-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64-SLOW-NEXT: vsetivli zero, 1, e64, m8, ta, ma
; RV64-SLOW-NEXT: vmv.x.s a2, v10
; RV64-SLOW-NEXT: srli a3, a1, 8
; RV64-SLOW-NEXT: sb a1, 0(a2)
@@ -355,7 +355,7 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x ptr> %ptrs, <4 x i1> %m)
; RV64-SLOW-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64-SLOW-NEXT: vslidedown.vi v9, v8, 2
; RV64-SLOW-NEXT: vmv.x.s a1, v9
-; RV64-SLOW-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV64-SLOW-NEXT: vsetivli zero, 1, e64, m2, ta, ma
; RV64-SLOW-NEXT: vslidedown.vi v12, v10, 2
; RV64-SLOW-NEXT: vmv.x.s a2, v12
; RV64-SLOW-NEXT: srli a3, a1, 8
@@ -366,11 +366,11 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x ptr> %ptrs, <4 x i1> %m)
; RV64-SLOW-NEXT: .LBB6_8: # %cond.store5
; RV64-SLOW-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64-SLOW-NEXT: vslidedown.vi v12, v8, 3
-; RV64-SLOW-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV64-SLOW-NEXT: vsetivli zero, 1, e64, m2, ta, ma
; RV64-SLOW-NEXT: vslidedown.vi v8, v10, 3
-; RV64-SLOW-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64-SLOW-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64-SLOW-NEXT: vmv.x.s a0, v12
-; RV64-SLOW-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV64-SLOW-NEXT: vsetivli zero, 1, e64, m2, ta, ma
; RV64-SLOW-NEXT: vmv.x.s a1, v8
; RV64-SLOW-NEXT: srli a2, a0, 8
; RV64-SLOW-NEXT: sb a0, 0(a1)
@@ -407,7 +407,7 @@ define void @mscatter_v2i32_align2(<2 x i32> %val, <2 x ptr> %ptrs, <2 x i1> %m)
; RV32-SLOW-NEXT: .LBB7_2: # %else2
; RV32-SLOW-NEXT: ret
; RV32-SLOW-NEXT: .LBB7_3: # %cond.store
-; RV32-SLOW-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32-SLOW-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV32-SLOW-NEXT: vmv.x.s a1, v8
; RV32-SLOW-NEXT: vmv.x.s a2, v9
; RV32-SLOW-NEXT: srli a3, a1, 16
@@ -438,9 +438,9 @@ define void @mscatter_v2i32_align2(<2 x i32> %val, <2 x ptr> %ptrs, <2 x i1> %m)
; RV64-SLOW-NEXT: .LBB7_2: # %else2
; RV64-SLOW-NEXT: ret
; RV64-SLOW-NEXT: .LBB7_3: # %cond.store
-; RV64-SLOW-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64-SLOW-NEXT: vsetivli zero, 1, e32, m4, ta, ma
; RV64-SLOW-NEXT: vmv.x.s a1, v8
-; RV64-SLOW-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64-SLOW-NEXT: vsetivli zero, 1, e64, m8, ta, ma
; RV64-SLOW-NEXT: vmv.x.s a2, v9
; RV64-SLOW-NEXT: srli a3, a1, 16
; RV64-SLOW-NEXT: sh a1, 0(a2)
@@ -450,11 +450,11 @@ define void @mscatter_v2i32_align2(<2 x i32> %val, <2 x ptr> %ptrs, <2 x i1> %m)
; RV64-SLOW-NEXT: .LBB7_4: # %cond.store1
; RV64-SLOW-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV64-SLOW-NEXT: vslidedown.vi v8, v8, 1
-; RV64-SLOW-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64-SLOW-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-SLOW-NEXT: vslidedown.vi v9, v9, 1
-; RV64-SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-SLOW-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV64-SLOW-NEXT: vmv.x.s a0, v8
-; RV64-SLOW-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64-SLOW-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-SLOW-NEXT: vmv.x.s a1, v9
; RV64-SLOW-NEXT: srli a2, a0, 16
; RV64-SLOW-NEXT: sh a0, 0(a1)
@@ -483,7 +483,7 @@ define void @masked_load_v2i32_align1(ptr %a, <2 x i32> %m, ptr %res_ptr) nounwi
; RV32-SLOW: # %bb.0:
; RV32-SLOW-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV32-SLOW-NEXT: vmseq.vi v8, v8, 0
-; RV32-SLOW-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; RV32-SLOW-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; RV32-SLOW-NEXT: vmv.x.s a2, v8
; RV32-SLOW-NEXT: andi a3, a2, 1
; RV32-SLOW-NEXT: # implicit-def: $v8
@@ -499,7 +499,7 @@ define void @masked_load_v2i32_align1(ptr %a, <2 x i32> %m, ptr %res_ptr) nounwi
; RV32-SLOW-NEXT: slli a6, a6, 24
; RV32-SLOW-NEXT: or a4, a6, a5
; RV32-SLOW-NEXT: or a3, a4, a3
-; RV32-SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32-SLOW-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV32-SLOW-NEXT: vmv.s.x v8, a3
; RV32-SLOW-NEXT: .LBB8_2: # %else
; RV32-SLOW-NEXT: andi a2, a2, 2
@@ -515,11 +515,11 @@ define void @masked_load_v2i32_align1(ptr %a, <2 x i32> %m, ptr %res_ptr) nounwi
; RV32-SLOW-NEXT: slli a0, a0, 24
; RV32-SLOW-NEXT: or a0, a0, a4
; RV32-SLOW-NEXT: or a0, a0, a2
-; RV32-SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32-SLOW-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV32-SLOW-NEXT: vmv.s.x v9, a0
; RV32-SLOW-NEXT: vslideup.vi v8, v9, 1
; RV32-SLOW-NEXT: .LBB8_4: # %else2
-; RV32-SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32-SLOW-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV32-SLOW-NEXT: vse32.v v8, (a1)
; RV32-SLOW-NEXT: ret
;
@@ -527,7 +527,7 @@ define void @masked_load_v2i32_align1(ptr %a, <2 x i32> %m, ptr %res_ptr) nounwi
; RV64-SLOW: # %bb.0:
; RV64-SLOW-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64-SLOW-NEXT: vmseq.vi v8, v8, 0
-; RV64-SLOW-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; RV64-SLOW-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; RV64-SLOW-NEXT: vmv.x.s a2, v8
; RV64-SLOW-NEXT: andi a3, a2, 1
; RV64-SLOW-NEXT: # implicit-def: $v8
@@ -543,7 +543,7 @@ define void @masked_load_v2i32_align1(ptr %a, <2 x i32> %m, ptr %res_ptr) nounwi
; RV64-SLOW-NEXT: slli a6, a6, 24
; RV64-SLOW-NEXT: or a4, a6, a5
; RV64-SLOW-NEXT: or a3, a4, a3
-; RV64-SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-SLOW-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64-SLOW-NEXT: vmv.s.x v8, a3
; RV64-SLOW-NEXT: .LBB8_2: # %else
; RV64-SLOW-NEXT: andi a2, a2, 2
@@ -559,11 +559,11 @@ define void @masked_load_v2i32_align1(ptr %a, <2 x i32> %m, ptr %res_ptr) nounwi
; RV64-SLOW-NEXT: slli a0, a0, 24
; RV64-SLOW-NEXT: or a0, a0, a4
; RV64-SLOW-NEXT: or a0, a0, a2
-; RV64-SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-SLOW-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64-SLOW-NEXT: vmv.s.x v9, a0
; RV64-SLOW-NEXT: vslideup.vi v8, v9, 1
; RV64-SLOW-NEXT: .LBB8_4: # %else2
-; RV64-SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-SLOW-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64-SLOW-NEXT: vse32.v v8, (a1)
; RV64-SLOW-NEXT: ret
;
@@ -587,7 +587,7 @@ define void @masked_store_v2i32_align2(<2 x i32> %val, ptr %a, <2 x i32> %m) nou
; SLOW: # %bb.0:
; SLOW-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; SLOW-NEXT: vmseq.vi v9, v9, 0
-; SLOW-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; SLOW-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; SLOW-NEXT: vmv.x.s a1, v9
; SLOW-NEXT: andi a2, a1, 1
; SLOW-NEXT: bnez a2, .LBB9_3
@@ -597,7 +597,7 @@ define void @masked_store_v2i32_align2(<2 x i32> %val, ptr %a, <2 x i32> %m) nou
; SLOW-NEXT: .LBB9_2: # %else2
; SLOW-NEXT: ret
; SLOW-NEXT: .LBB9_3: # %cond.store
-; SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; SLOW-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; SLOW-NEXT: vmv.x.s a2, v8
; SLOW-NEXT: srli a3, a2, 16
; SLOW-NEXT: sh a2, 0(a0)
@@ -605,7 +605,7 @@ define void @masked_store_v2i32_align2(<2 x i32> %val, ptr %a, <2 x i32> %m) nou
; SLOW-NEXT: andi a1, a1, 2
; SLOW-NEXT: beqz a1, .LBB9_2
; SLOW-NEXT: .LBB9_4: # %cond.store1
-; SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; SLOW-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; SLOW-NEXT: vslidedown.vi v8, v8, 1
; SLOW-NEXT: vmv.x.s a1, v8
; SLOW-NEXT: srli a2, a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll
index dc432efbd5c47..c048a4bece54c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll
@@ -283,9 +283,9 @@ define <8 x i8> @vaaddu_vv_v8i8_ceil_lshr2(<8 x i8> %x, <8 x i8> %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vwaddu.vv v10, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vadd.vi v8, v10, 2
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 2
; CHECK-NEXT: ret
%xzv = zext <8 x i8> %x to <8 x i16>
@@ -304,9 +304,9 @@ define <8 x i8> @vaaddu_vv_v8i8_ceil_add2(<8 x i8> %x, <8 x i8> %y) {
; CHECK-NEXT: vwaddu.vv v10, v8, v9
; CHECK-NEXT: li a0, 2
; CHECK-NEXT: csrwi vxrm, 2
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vaaddu.vx v8, v10, a0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%xzv = zext <8 x i8> %x to <8 x i16>
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
index c37df892de442..f68b8e3b539d1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
@@ -22,9 +22,9 @@ define <2 x half> @vfmax_v2f16_vv(<2 x half> %a, <2 x half> %b) {
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfmax.vv v9, v9, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%v = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %b)
@@ -45,9 +45,9 @@ define <2 x half> @vfmax_v2f16_vf(<2 x half> %a, half %b) {
; ZVFHMIN-NEXT: vmv.v.x v9, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfmax.vv v9, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%head = insertelement <2 x half> poison, half %b, i32 0
@@ -70,9 +70,9 @@ define <2 x half> @vfmax_v2f16_fv(<2 x half> %a, half %b) {
; ZVFHMIN-NEXT: vmv.v.x v9, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfmax.vv v9, v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%head = insertelement <2 x half> poison, half %b, i32 0
@@ -95,9 +95,9 @@ define <4 x half> @vfmax_v4f16_vv(<4 x half> %a, <4 x half> %b) {
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfmax.vv v9, v9, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%v = call <4 x half> @llvm.maxnum.v4f16(<4 x half> %a, <4 x half> %b)
@@ -118,9 +118,9 @@ define <4 x half> @vfmax_v4f16_vf(<4 x half> %a, half %b) {
; ZVFHMIN-NEXT: vmv.v.x v9, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfmax.vv v9, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%head = insertelement <4 x half> poison, half %b, i32 0
@@ -143,9 +143,9 @@ define <4 x half> @vfmax_v4f16_fv(<4 x half> %a, half %b) {
; ZVFHMIN-NEXT: vmv.v.x v9, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfmax.vv v9, v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%head = insertelement <4 x half> poison, half %b, i32 0
@@ -168,9 +168,9 @@ define <8 x half> @vfmax_v8f16_vv(<8 x half> %a, <8 x half> %b) {
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmax.vv v10, v12, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
; ZVFHMIN-NEXT: ret
%v = call <8 x half> @llvm.maxnum.v8f16(<8 x half> %a, <8 x half> %b)
@@ -191,9 +191,9 @@ define <8 x half> @vfmax_v8f16_vf(<8 x half> %a, half %b) {
; ZVFHMIN-NEXT: vmv.v.x v12, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmax.vv v10, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
; ZVFHMIN-NEXT: ret
%head = insertelement <8 x half> poison, half %b, i32 0
@@ -216,9 +216,9 @@ define <8 x half> @vfmax_v8f16_fv(<8 x half> %a, half %b) {
; ZVFHMIN-NEXT: vmv.v.x v12, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmax.vv v10, v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
; ZVFHMIN-NEXT: ret
%head = insertelement <8 x half> poison, half %b, i32 0
@@ -241,9 +241,9 @@ define <16 x half> @vfmax_v16f16_vv(<16 x half> %a, <16 x half> %b) {
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfmax.vv v12, v16, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: ret
%v = call <16 x half> @llvm.maxnum.v16f16(<16 x half> %a, <16 x half> %b)
@@ -264,9 +264,9 @@ define <16 x half> @vfmax_v16f16_vf(<16 x half> %a, half %b) {
; ZVFHMIN-NEXT: vmv.v.x v16, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfmax.vv v12, v12, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: ret
%head = insertelement <16 x half> poison, half %b, i32 0
@@ -289,9 +289,9 @@ define <16 x half> @vfmax_v16f16_fv(<16 x half> %a, half %b) {
; ZVFHMIN-NEXT: vmv.v.x v16, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfmax.vv v12, v8, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: ret
%head = insertelement <16 x half> poison, half %b, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
index 90afe36a36c0f..9b61801f4123a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
@@ -22,9 +22,9 @@ define <2 x half> @vfmin_v2f16_vv(<2 x half> %a, <2 x half> %b) {
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfmin.vv v9, v9, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%v = call <2 x half> @llvm.minnum.v2f16(<2 x half> %a, <2 x half> %b)
@@ -45,9 +45,9 @@ define <2 x half> @vfmin_v2f16_vf(<2 x half> %a, half %b) {
; ZVFHMIN-NEXT: vmv.v.x v9, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfmin.vv v9, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%head = insertelement <2 x half> poison, half %b, i32 0
@@ -70,9 +70,9 @@ define <2 x half> @vfmin_v2f16_fv(<2 x half> %a, half %b) {
; ZVFHMIN-NEXT: vmv.v.x v9, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfmin.vv v9, v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%head = insertelement <2 x half> poison, half %b, i32 0
@@ -95,9 +95,9 @@ define <4 x half> @vfmin_v4f16_vv(<4 x half> %a, <4 x half> %b) {
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfmin.vv v9, v9, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%v = call <4 x half> @llvm.minnum.v4f16(<4 x half> %a, <4 x half> %b)
@@ -118,9 +118,9 @@ define <4 x half> @vfmin_v4f16_vf(<4 x half> %a, half %b) {
; ZVFHMIN-NEXT: vmv.v.x v9, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfmin.vv v9, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%head = insertelement <4 x half> poison, half %b, i32 0
@@ -143,9 +143,9 @@ define <4 x half> @vfmin_v4f16_fv(<4 x half> %a, half %b) {
; ZVFHMIN-NEXT: vmv.v.x v9, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfmin.vv v9, v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
%head = insertelement <4 x half> poison, half %b, i32 0
@@ -168,9 +168,9 @@ define <8 x half> @vfmin_v8f16_vv(<8 x half> %a, <8 x half> %b) {
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmin.vv v10, v12, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
; ZVFHMIN-NEXT: ret
%v = call <8 x half> @llvm.minnum.v8f16(<8 x half> %a, <8 x half> %b)
@@ -191,9 +191,9 @@ define <8 x half> @vfmin_v8f16_vf(<8 x half> %a, half %b) {
; ZVFHMIN-NEXT: vmv.v.x v12, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmin.vv v10, v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
; ZVFHMIN-NEXT: ret
%head = insertelement <8 x half> poison, half %b, i32 0
@@ -216,9 +216,9 @@ define <8 x half> @vfmin_v8f16_fv(<8 x half> %a, half %b) {
; ZVFHMIN-NEXT: vmv.v.x v12, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmin.vv v10, v8, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
; ZVFHMIN-NEXT: ret
%head = insertelement <8 x half> poison, half %b, i32 0
@@ -241,9 +241,9 @@ define <16 x half> @vfmin_v16f16_vv(<16 x half> %a, <16 x half> %b) {
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfmin.vv v12, v16, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: ret
%v = call <16 x half> @llvm.minnum.v16f16(<16 x half> %a, <16 x half> %b)
@@ -264,9 +264,9 @@ define <16 x half> @vfmin_v16f16_vf(<16 x half> %a, half %b) {
; ZVFHMIN-NEXT: vmv.v.x v16, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfmin.vv v12, v12, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: ret
%head = insertelement <16 x half> poison, half %b, i32 0
@@ -289,9 +289,9 @@ define <16 x half> @vfmin_v16f16_fv(<16 x half> %a, half %b) {
; ZVFHMIN-NEXT: vmv.v.x v16, a0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfmin.vv v12, v8, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
; ZVFHMIN-NEXT: ret
%head = insertelement <16 x half> poison, half %b, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfpext-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfpext-constrained-sdnode.ll
index b8a6be40b3f32..ee08c76e906be 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfpext-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfpext-constrained-sdnode.ll
@@ -22,7 +22,7 @@ define <2 x double> @vfpext_v2f16_v2f64(<2 x half> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v8, v9
; CHECK-NEXT: ret
%evec = call <2 x double> @llvm.experimental.constrained.fpext.v2f64.v2f16(<2 x half> %va, metadata !"fpexcept.strict")
@@ -47,7 +47,7 @@ define <4 x double> @vfpext_v4f16_v4f64(<4 x half> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v8, v10
; CHECK-NEXT: ret
%evec = call <4 x double> @llvm.experimental.constrained.fpext.v4f64.v4f16(<4 x half> %va, metadata !"fpexcept.strict")
@@ -72,7 +72,7 @@ define <8 x double> @vfpext_v8f16_v8f64(<8 x half> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v8, v12
; CHECK-NEXT: ret
%evec = call <8 x double> @llvm.experimental.constrained.fpext.v8f64.v8f16(<8 x half> %va, metadata !"fpexcept.strict")
@@ -133,7 +133,7 @@ define <2 x double> @vfpext_v2bf16_v2f64(<2 x bfloat> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v8, v9
; CHECK-NEXT: ret
%evec = call <2 x double> @llvm.experimental.constrained.fpext.v2f64.v2bf16(<2 x bfloat> %va, metadata !"fpexcept.strict")
@@ -158,7 +158,7 @@ define <4 x double> @vfpext_v4bf16_v4f64(<4 x bfloat> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v8, v10
; CHECK-NEXT: ret
%evec = call <4 x double> @llvm.experimental.constrained.fpext.v4f64.v4bf16(<4 x bfloat> %va, metadata !"fpexcept.strict")
@@ -183,7 +183,7 @@ define <8 x double> @vfpext_v8bf16_v8f64(<8 x bfloat> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v8, v12
; CHECK-NEXT: ret
%evec = call <8 x double> @llvm.experimental.constrained.fpext.v8f64.v8bf16(<8 x bfloat> %va, metadata !"fpexcept.strict")
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
index ac58a597a0812..bf6ab55e2e463 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
@@ -144,7 +144,7 @@ define <1 x i64> @vfptosi_v1f16_v1i64(<1 x half> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v9
; CHECK-NEXT: ret
%evec = call <1 x i64> @llvm.experimental.constrained.fptosi.v1i64.v1f16(<1 x half> %va, metadata !"fpexcept.strict")
@@ -157,7 +157,7 @@ define <1 x i64> @vfptoui_v1f16_v1i64(<1 x half> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v9
; CHECK-NEXT: ret
%evec = call <1 x i64> @llvm.experimental.constrained.fptoui.v1i64.v1f16(<1 x half> %va, metadata !"fpexcept.strict")
@@ -266,7 +266,7 @@ define <2 x i64> @vfptosi_v2f16_v2i64(<2 x half> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v9
; CHECK-NEXT: ret
%evec = call <2 x i64> @llvm.experimental.constrained.fptosi.v2i64.v2f16(<2 x half> %va, metadata !"fpexcept.strict")
@@ -279,7 +279,7 @@ define <2 x i64> @vfptoui_v2f16_v2i64(<2 x half> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v9
; CHECK-NEXT: ret
%evec = call <2 x i64> @llvm.experimental.constrained.fptoui.v2i64.v2f16(<2 x half> %va, metadata !"fpexcept.strict")
@@ -388,7 +388,7 @@ define <4 x i64> @vfptosi_v4f16_v4i64(<4 x half> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v10
; CHECK-NEXT: ret
%evec = call <4 x i64> @llvm.experimental.constrained.fptosi.v4i64.v4f16(<4 x half> %va, metadata !"fpexcept.strict")
@@ -401,7 +401,7 @@ define <4 x i64> @vfptoui_v4f16_v4i64(<4 x half> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v10
; CHECK-NEXT: ret
%evec = call <4 x i64> @llvm.experimental.constrained.fptoui.v4i64.v4f16(<4 x half> %va, metadata !"fpexcept.strict")
@@ -510,7 +510,7 @@ define <8 x i64> @vfptosi_v8f16_v8i64(<8 x half> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v12
; CHECK-NEXT: ret
%evec = call <8 x i64> @llvm.experimental.constrained.fptosi.v8i64.v8f16(<8 x half> %va, metadata !"fpexcept.strict")
@@ -523,7 +523,7 @@ define <8 x i64> @vfptoui_v8f16_v8i64(<8 x half> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v12
; CHECK-NEXT: ret
%evec = call <8 x i64> @llvm.experimental.constrained.fptoui.v8i64.v8f16(<8 x half> %va, metadata !"fpexcept.strict")
@@ -736,7 +736,7 @@ define <1 x i8> @vfptosi_v1f32_v1i8(<1 x float> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v9, 0
; CHECK-NEXT: ret
%evec = call <1 x i8> @llvm.experimental.constrained.fptosi.v1i8.v1f32(<1 x float> %va, metadata !"fpexcept.strict")
@@ -749,7 +749,7 @@ define <1 x i8> @vfptoui_v1f32_v1i8(<1 x float> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v9, 0
; CHECK-NEXT: ret
%evec = call <1 x i8> @llvm.experimental.constrained.fptoui.v1i8.v1f32(<1 x float> %va, metadata !"fpexcept.strict")
@@ -858,7 +858,7 @@ define <2 x i8> @vfptosi_v2f32_v2i8(<2 x float> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v9, 0
; CHECK-NEXT: ret
%evec = call <2 x i8> @llvm.experimental.constrained.fptosi.v2i8.v2f32(<2 x float> %va, metadata !"fpexcept.strict")
@@ -871,7 +871,7 @@ define <2 x i8> @vfptoui_v2f32_v2i8(<2 x float> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v9, 0
; CHECK-NEXT: ret
%evec = call <2 x i8> @llvm.experimental.constrained.fptoui.v2i8.v2f32(<2 x float> %va, metadata !"fpexcept.strict")
@@ -980,7 +980,7 @@ define <4 x i8> @vfptosi_v4f32_v4i8(<4 x float> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v9, 0
; CHECK-NEXT: ret
%evec = call <4 x i8> @llvm.experimental.constrained.fptosi.v4i8.v4f32(<4 x float> %va, metadata !"fpexcept.strict")
@@ -993,7 +993,7 @@ define <4 x i8> @vfptoui_v4f32_v4i8(<4 x float> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v9, 0
; CHECK-NEXT: ret
%evec = call <4 x i8> @llvm.experimental.constrained.fptoui.v4i8.v4f32(<4 x float> %va, metadata !"fpexcept.strict")
@@ -1102,7 +1102,7 @@ define <8 x i8> @vfptosi_v8f32_v8i8(<8 x float> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%evec = call <8 x i8> @llvm.experimental.constrained.fptosi.v8i8.v8f32(<8 x float> %va, metadata !"fpexcept.strict")
@@ -1115,7 +1115,7 @@ define <8 x i8> @vfptoui_v8f32_v8i8(<8 x float> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%evec = call <8 x i8> @llvm.experimental.constrained.fptoui.v8i8.v8f32(<8 x float> %va, metadata !"fpexcept.strict")
@@ -1224,7 +1224,7 @@ define <16 x i8> @vfptosi_v16f32_v16i8(<16 x float> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: ret
%evec = call <16 x i8> @llvm.experimental.constrained.fptosi.v16i8.v16f32(<16 x float> %va, metadata !"fpexcept.strict")
@@ -1237,7 +1237,7 @@ define <16 x i8> @vfptoui_v16f32_v16i8(<16 x float> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: ret
%evec = call <16 x i8> @llvm.experimental.constrained.fptoui.v16i8.v16f32(<16 x float> %va, metadata !"fpexcept.strict")
@@ -1322,9 +1322,9 @@ define <1 x i8> @vfptosi_v1f64_v1i8(<1 x double> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v9, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%evec = call <1 x i8> @llvm.experimental.constrained.fptosi.v1i8.v1f64(<1 x double> %va, metadata !"fpexcept.strict")
@@ -1337,9 +1337,9 @@ define <1 x i8> @vfptoui_v1f64_v1i8(<1 x double> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v9, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%evec = call <1 x i8> @llvm.experimental.constrained.fptoui.v1i8.v1f64(<1 x double> %va, metadata !"fpexcept.strict")
@@ -1352,7 +1352,7 @@ define <1 x i16> @vfptosi_v1f64_v1i16(<1 x double> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v9, 0
; CHECK-NEXT: ret
%evec = call <1 x i16> @llvm.experimental.constrained.fptosi.v1i16.v1f64(<1 x double> %va, metadata !"fpexcept.strict")
@@ -1365,7 +1365,7 @@ define <1 x i16> @vfptoui_v1f64_v1i16(<1 x double> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v9, 0
; CHECK-NEXT: ret
%evec = call <1 x i16> @llvm.experimental.constrained.fptoui.v1i16.v1f64(<1 x double> %va, metadata !"fpexcept.strict")
@@ -1450,9 +1450,9 @@ define <2 x i8> @vfptosi_v2f64_v2i8(<2 x double> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v9, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%evec = call <2 x i8> @llvm.experimental.constrained.fptosi.v2i8.v2f64(<2 x double> %va, metadata !"fpexcept.strict")
@@ -1465,9 +1465,9 @@ define <2 x i8> @vfptoui_v2f64_v2i8(<2 x double> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v9, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%evec = call <2 x i8> @llvm.experimental.constrained.fptoui.v2i8.v2f64(<2 x double> %va, metadata !"fpexcept.strict")
@@ -1480,7 +1480,7 @@ define <2 x i16> @vfptosi_v2f64_v2i16(<2 x double> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v9, 0
; CHECK-NEXT: ret
%evec = call <2 x i16> @llvm.experimental.constrained.fptosi.v2i16.v2f64(<2 x double> %va, metadata !"fpexcept.strict")
@@ -1493,7 +1493,7 @@ define <2 x i16> @vfptoui_v2f64_v2i16(<2 x double> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v9, 0
; CHECK-NEXT: ret
%evec = call <2 x i16> @llvm.experimental.constrained.fptoui.v2i16.v2f64(<2 x double> %va, metadata !"fpexcept.strict")
@@ -1578,9 +1578,9 @@ define <4 x i8> @vfptosi_v4f64_v4i8(<4 x double> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%evec = call <4 x i8> @llvm.experimental.constrained.fptosi.v4i8.v4f64(<4 x double> %va, metadata !"fpexcept.strict")
@@ -1593,9 +1593,9 @@ define <4 x i8> @vfptoui_v4f64_v4i8(<4 x double> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%evec = call <4 x i8> @llvm.experimental.constrained.fptoui.v4i8.v4f64(<4 x double> %va, metadata !"fpexcept.strict")
@@ -1608,7 +1608,7 @@ define <4 x i16> @vfptosi_v4f64_v4i16(<4 x double> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%evec = call <4 x i16> @llvm.experimental.constrained.fptosi.v4i16.v4f64(<4 x double> %va, metadata !"fpexcept.strict")
@@ -1621,7 +1621,7 @@ define <4 x i16> @vfptoui_v4f64_v4i16(<4 x double> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%evec = call <4 x i16> @llvm.experimental.constrained.fptoui.v4i16.v4f64(<4 x double> %va, metadata !"fpexcept.strict")
@@ -1706,9 +1706,9 @@ define <8 x i8> @vfptosi_v8f64_v8i8(<8 x double> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%evec = call <8 x i8> @llvm.experimental.constrained.fptosi.v8i8.v8f64(<8 x double> %va, metadata !"fpexcept.strict")
@@ -1721,9 +1721,9 @@ define <8 x i8> @vfptoui_v8f64_v8i8(<8 x double> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%evec = call <8 x i8> @llvm.experimental.constrained.fptoui.v8i8.v8f64(<8 x double> %va, metadata !"fpexcept.strict")
@@ -1736,7 +1736,7 @@ define <8 x i16> @vfptosi_v8f64_v8i16(<8 x double> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: ret
%evec = call <8 x i16> @llvm.experimental.constrained.fptosi.v8i16.v8f64(<8 x double> %va, metadata !"fpexcept.strict")
@@ -1749,7 +1749,7 @@ define <8 x i16> @vfptoui_v8f64_v8i16(<8 x double> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: ret
%evec = call <8 x i16> @llvm.experimental.constrained.fptoui.v8i16.v8f64(<8 x double> %va, metadata !"fpexcept.strict")
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptrunc-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptrunc-constrained-sdnode.ll
index 1f74691437ad2..d1edfd54517dd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptrunc-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptrunc-constrained-sdnode.ll
@@ -26,7 +26,7 @@ define <2 x half> @vfptrunc_v2f64_v2f16(<2 x double> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfncvt.rod.f.f.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfncvt.f.f.w v8, v9
; CHECK-NEXT: ret
%evec = call <2 x half> @llvm.experimental.constrained.fptrunc.v2f16.v2f64(<2 x double> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -63,7 +63,7 @@ define <4 x half> @vfptrunc_v4f64_v4f16(<4 x double> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfncvt.rod.f.f.w v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfncvt.f.f.w v8, v10
; CHECK-NEXT: ret
%evec = call <4 x half> @llvm.experimental.constrained.fptrunc.v4f16.v4f64(<4 x double> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -100,7 +100,7 @@ define <8 x half> @vfptrunc_v8f64_v8f16(<8 x double> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfncvt.rod.f.f.w v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvt.f.f.w v8, v12
; CHECK-NEXT: ret
%evec = call <8 x half> @llvm.experimental.constrained.fptrunc.v8f16.v8f64(<8 x double> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -125,7 +125,7 @@ define <2 x bfloat> @vfptrunc_v2f64_v2bf16(<2 x double> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfncvt.rod.f.f.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
; CHECK-NEXT: ret
%evec = call <2 x bfloat> @llvm.experimental.constrained.fptrunc.v2bf16.v2f64(<2 x double> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -150,7 +150,7 @@ define <4 x bfloat> @vfptrunc_v4f64_v4bf16(<4 x double> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfncvt.rod.f.f.w v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
; CHECK-NEXT: ret
%evec = call <4 x bfloat> @llvm.experimental.constrained.fptrunc.v4bf16.v4f64(<4 x double> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -175,7 +175,7 @@ define <8 x bfloat> @vfptrunc_v8f64_v8bf16(<8 x double> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfncvt.rod.f.f.w v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
; CHECK-NEXT: ret
%evec = call <8 x bfloat> @llvm.experimental.constrained.fptrunc.v8bf16.v8f64(<8 x double> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfw-web-simplification.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfw-web-simplification.ll
index 0561ee9addc7b..b5a2b52265e2c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfw-web-simplification.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfw-web-simplification.ll
@@ -14,7 +14,7 @@ define void @vfwmul_v2f116_multiple_users(ptr %x, ptr %y, ptr %z, <2 x half> %a,
; NO_FOLDING1-NEXT: vfwcvt.f.f.v v11, v8
; NO_FOLDING1-NEXT: vfwcvt.f.f.v v8, v9
; NO_FOLDING1-NEXT: vfwcvt.f.f.v v9, v10
-; NO_FOLDING1-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; NO_FOLDING1-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; NO_FOLDING1-NEXT: vfmul.vv v10, v11, v8
; NO_FOLDING1-NEXT: vfadd.vv v11, v11, v9
; NO_FOLDING1-NEXT: vfsub.vv v8, v8, v9
@@ -28,9 +28,9 @@ define void @vfwmul_v2f116_multiple_users(ptr %x, ptr %y, ptr %z, <2 x half> %a,
; NO_FOLDING2-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; NO_FOLDING2-NEXT: vfwcvt.f.f.v v11, v8
; NO_FOLDING2-NEXT: vfwcvt.f.f.v v8, v9
-; NO_FOLDING2-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; NO_FOLDING2-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; NO_FOLDING2-NEXT: vfmul.vv v9, v11, v8
-; NO_FOLDING2-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; NO_FOLDING2-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; NO_FOLDING2-NEXT: vfwadd.wv v11, v11, v10
; NO_FOLDING2-NEXT: vfwsub.wv v8, v8, v10
; NO_FOLDING2-NEXT: vse32.v v9, (a0)
@@ -55,7 +55,7 @@ define void @vfwmul_v2f116_multiple_users(ptr %x, ptr %y, ptr %z, <2 x half> %a,
; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfmul.vv v10, v11, v8
; ZVFHMIN-NEXT: vfadd.vv v11, v11, v9
; ZVFHMIN-NEXT: vfsub.vv v8, v8, v9
@@ -82,7 +82,7 @@ define void @vfwmul_v2f32_multiple_users(ptr %x, ptr %y, ptr %z, <2 x float> %a,
; NO_FOLDING1-NEXT: vfwcvt.f.f.v v11, v8
; NO_FOLDING1-NEXT: vfwcvt.f.f.v v8, v9
; NO_FOLDING1-NEXT: vfwcvt.f.f.v v9, v10
-; NO_FOLDING1-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; NO_FOLDING1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; NO_FOLDING1-NEXT: vfmul.vv v10, v11, v8
; NO_FOLDING1-NEXT: vfadd.vv v11, v11, v9
; NO_FOLDING1-NEXT: vfsub.vv v8, v8, v9
@@ -96,9 +96,9 @@ define void @vfwmul_v2f32_multiple_users(ptr %x, ptr %y, ptr %z, <2 x float> %a,
; NO_FOLDING2-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; NO_FOLDING2-NEXT: vfwcvt.f.f.v v11, v8
; NO_FOLDING2-NEXT: vfwcvt.f.f.v v8, v9
-; NO_FOLDING2-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; NO_FOLDING2-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; NO_FOLDING2-NEXT: vfmul.vv v9, v11, v8
-; NO_FOLDING2-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; NO_FOLDING2-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; NO_FOLDING2-NEXT: vfwadd.wv v11, v11, v10
; NO_FOLDING2-NEXT: vfwsub.wv v8, v8, v10
; NO_FOLDING2-NEXT: vse64.v v9, (a0)
@@ -135,7 +135,7 @@ define void @vfwmacc_v2f32_multiple_users(ptr %x, ptr %y, ptr %z, <2 x float> %a
; NO_FOLDING-NEXT: vfwcvt.f.f.v v12, v8
; NO_FOLDING-NEXT: vfwcvt.f.f.v v8, v9
; NO_FOLDING-NEXT: vfwcvt.f.f.v v9, v10
-; NO_FOLDING-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; NO_FOLDING-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; NO_FOLDING-NEXT: vfmul.vv v10, v12, v8
; NO_FOLDING-NEXT: vfmadd.vv v12, v9, v11
; NO_FOLDING-NEXT: vfsub.vv v8, v8, v9
@@ -174,7 +174,7 @@ define void @vfwmacc_v2f32_multiple_users_addend_user(ptr %x, ptr %y, ptr %z, <2
; NO_FOLDING-NEXT: vfwcvt.f.f.v v11, v8
; NO_FOLDING-NEXT: vfwcvt.f.f.v v8, v9
; NO_FOLDING-NEXT: vfwcvt.f.f.v v9, v10
-; NO_FOLDING-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; NO_FOLDING-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; NO_FOLDING-NEXT: vfmul.vv v10, v11, v8
; NO_FOLDING-NEXT: vfmadd.vv v11, v9, v8
; NO_FOLDING-NEXT: vfsub.vv v8, v8, v9
@@ -189,7 +189,7 @@ define void @vfwmacc_v2f32_multiple_users_addend_user(ptr %x, ptr %y, ptr %z, <2
; FOLDING-NEXT: vfwcvt.f.f.v v11, v8
; FOLDING-NEXT: vfwcvt.f.f.v v8, v9
; FOLDING-NEXT: vfwcvt.f.f.v v9, v10
-; FOLDING-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; FOLDING-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; FOLDING-NEXT: vfmul.vv v10, v11, v8
; FOLDING-NEXT: vfmadd.vv v11, v9, v8
; FOLDING-NEXT: vfsub.vv v8, v8, v9
@@ -216,7 +216,7 @@ define void @vfwmacc_v2f32_addend_user(ptr %x, <2 x float> %a, <2 x float> %b) {
; NO_FOLDING-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; NO_FOLDING-NEXT: vfwcvt.f.f.v v10, v8
; NO_FOLDING-NEXT: vfwcvt.f.f.v v8, v9
-; NO_FOLDING-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; NO_FOLDING-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; NO_FOLDING-NEXT: vfmadd.vv v8, v10, v8
; NO_FOLDING-NEXT: vse64.v v8, (a0)
; NO_FOLDING-NEXT: ret
@@ -226,7 +226,7 @@ define void @vfwmacc_v2f32_addend_user(ptr %x, <2 x float> %a, <2 x float> %b) {
; FOLDING-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; FOLDING-NEXT: vfwcvt.f.f.v v10, v8
; FOLDING-NEXT: vfwcvt.f.f.v v8, v9
-; FOLDING-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; FOLDING-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; FOLDING-NEXT: vfmadd.vv v8, v10, v8
; FOLDING-NEXT: vse64.v v8, (a0)
; FOLDING-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
index a9e9b757f372e..7929e7e24c6a0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
@@ -1317,7 +1317,7 @@ define <1 x double> @vfwmacc_vv_v1f64_v1f16(<1 x double> %va, <1 x half> %vb, <1
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v11, v9
; CHECK-NEXT: vfwcvt.f.f.v v9, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfwmacc.vv v8, v11, v9
; CHECK-NEXT: ret
%vd = fpext <1 x half> %vb to <1 x double>
@@ -1333,7 +1333,7 @@ define <1 x double> @vfwmacc_vf_v1f64_v1f16(<1 x double> %va, <1 x half> %vb, ha
; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vfwcvt.f.f.v v11, v9
; CHECK-NEXT: vfwcvt.f.f.v v9, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfwmacc.vv v8, v11, v9
; CHECK-NEXT: ret
%head = insertelement <1 x half> poison, half %c, i32 0
@@ -1350,7 +1350,7 @@ define <1 x double> @vfwnmacc_vv_v1f64_v1f16(<1 x double> %va, <1 x half> %vb, <
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v11, v9
; CHECK-NEXT: vfwcvt.f.f.v v9, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfwnmacc.vv v8, v11, v9
; CHECK-NEXT: ret
%vd = fpext <1 x half> %vb to <1 x double>
@@ -1368,7 +1368,7 @@ define <1 x double> @vfwnmacc_vf_v1f64_v1f16(<1 x double> %va, <1 x half> %vb, h
; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vfwcvt.f.f.v v11, v9
; CHECK-NEXT: vfwcvt.f.f.v v9, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfwnmacc.vv v8, v11, v9
; CHECK-NEXT: ret
%head = insertelement <1 x half> poison, half %c, i32 0
@@ -1388,7 +1388,7 @@ define <1 x double> @vfwnmacc_fv_v1f64_v1f16(<1 x double> %va, <1 x half> %vb, h
; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vfwcvt.f.f.v v11, v9
; CHECK-NEXT: vfwcvt.f.f.v v9, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfwnmacc.vv v8, v11, v9
; CHECK-NEXT: ret
%head = insertelement <1 x half> poison, half %c, i32 0
@@ -1407,7 +1407,7 @@ define <1 x double> @vfwmsac_vv_v1f64_v1f16(<1 x double> %va, <1 x half> %vb, <1
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v11, v9
; CHECK-NEXT: vfwcvt.f.f.v v9, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfwmsac.vv v8, v11, v9
; CHECK-NEXT: ret
%vd = fpext <1 x half> %vb to <1 x double>
@@ -1424,7 +1424,7 @@ define <1 x double> @vfwmsac_vf_v1f64_v1f16(<1 x double> %va, <1 x half> %vb, ha
; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vfwcvt.f.f.v v11, v9
; CHECK-NEXT: vfwcvt.f.f.v v9, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfwmsac.vv v8, v11, v9
; CHECK-NEXT: ret
%head = insertelement <1 x half> poison, half %c, i32 0
@@ -1442,7 +1442,7 @@ define <1 x double> @vfwnmsac_vv_v1f64_v1f16(<1 x double> %va, <1 x half> %vb, <
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v11, v9
; CHECK-NEXT: vfwcvt.f.f.v v9, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfwnmsac.vv v8, v11, v9
; CHECK-NEXT: ret
%vd = fpext <1 x half> %vb to <1 x double>
@@ -1459,7 +1459,7 @@ define <1 x double> @vfwnmsac_vf_v1f64_v1f16(<1 x double> %va, <1 x half> %vb, h
; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vfwcvt.f.f.v v11, v9
; CHECK-NEXT: vfwcvt.f.f.v v9, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfwnmsac.vv v8, v11, v9
; CHECK-NEXT: ret
%head = insertelement <1 x half> poison, half %c, i32 0
@@ -1478,7 +1478,7 @@ define <1 x double> @vfwnmsac_fv_v1f64_v1f16(<1 x double> %va, <1 x half> %vb, h
; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vfwcvt.f.f.v v11, v9
; CHECK-NEXT: vfwcvt.f.f.v v9, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfwnmsac.vv v8, v11, v9
; CHECK-NEXT: ret
%head = insertelement <1 x half> poison, half %c, i32 0
@@ -1496,7 +1496,7 @@ define <2 x double> @vfwmacc_vv_v2f64_v2f16(<2 x double> %va, <2 x half> %vb, <2
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v11, v9
; CHECK-NEXT: vfwcvt.f.f.v v9, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwmacc.vv v8, v11, v9
; CHECK-NEXT: ret
%vd = fpext <2 x half> %vb to <2 x double>
@@ -1512,7 +1512,7 @@ define <2 x double> @vfwmacc_vf_v2f64_v2f16(<2 x double> %va, <2 x half> %vb, ha
; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vfwcvt.f.f.v v11, v9
; CHECK-NEXT: vfwcvt.f.f.v v9, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwmacc.vv v8, v11, v9
; CHECK-NEXT: ret
%head = insertelement <2 x half> poison, half %c, i32 0
@@ -1529,7 +1529,7 @@ define <2 x double> @vfwnmacc_vv_v2f64_v2f16(<2 x double> %va, <2 x half> %vb, <
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v11, v9
; CHECK-NEXT: vfwcvt.f.f.v v9, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwnmacc.vv v8, v11, v9
; CHECK-NEXT: ret
%vd = fpext <2 x half> %vb to <2 x double>
@@ -1547,7 +1547,7 @@ define <2 x double> @vfwnmacc_vf_v2f64_v2f16(<2 x double> %va, <2 x half> %vb, h
; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vfwcvt.f.f.v v11, v9
; CHECK-NEXT: vfwcvt.f.f.v v9, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwnmacc.vv v8, v11, v9
; CHECK-NEXT: ret
%head = insertelement <2 x half> poison, half %c, i32 0
@@ -1567,7 +1567,7 @@ define <2 x double> @vfwnmacc_fv_v2f64_v2f16(<2 x double> %va, <2 x half> %vb, h
; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vfwcvt.f.f.v v11, v9
; CHECK-NEXT: vfwcvt.f.f.v v9, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwnmacc.vv v8, v11, v9
; CHECK-NEXT: ret
%head = insertelement <2 x half> poison, half %c, i32 0
@@ -1586,7 +1586,7 @@ define <2 x double> @vfwmsac_vv_v2f64_v2f16(<2 x double> %va, <2 x half> %vb, <2
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v11, v9
; CHECK-NEXT: vfwcvt.f.f.v v9, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwmsac.vv v8, v11, v9
; CHECK-NEXT: ret
%vd = fpext <2 x half> %vb to <2 x double>
@@ -1603,7 +1603,7 @@ define <2 x double> @vfwmsac_vf_v2f64_v2f16(<2 x double> %va, <2 x half> %vb, ha
; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vfwcvt.f.f.v v11, v9
; CHECK-NEXT: vfwcvt.f.f.v v9, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwmsac.vv v8, v11, v9
; CHECK-NEXT: ret
%head = insertelement <2 x half> poison, half %c, i32 0
@@ -1621,7 +1621,7 @@ define <2 x double> @vfwnmsac_vv_v2f64_v2f16(<2 x double> %va, <2 x half> %vb, <
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v11, v9
; CHECK-NEXT: vfwcvt.f.f.v v9, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwnmsac.vv v8, v11, v9
; CHECK-NEXT: ret
%vd = fpext <2 x half> %vb to <2 x double>
@@ -1638,7 +1638,7 @@ define <2 x double> @vfwnmsac_vf_v2f64_v2f16(<2 x double> %va, <2 x half> %vb, h
; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vfwcvt.f.f.v v11, v9
; CHECK-NEXT: vfwcvt.f.f.v v9, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwnmsac.vv v8, v11, v9
; CHECK-NEXT: ret
%head = insertelement <2 x half> poison, half %c, i32 0
@@ -1657,7 +1657,7 @@ define <2 x double> @vfwnmsac_fv_v2f64_v2f16(<2 x double> %va, <2 x half> %vb, h
; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vfwcvt.f.f.v v11, v9
; CHECK-NEXT: vfwcvt.f.f.v v9, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwnmsac.vv v8, v11, v9
; CHECK-NEXT: ret
%head = insertelement <2 x half> poison, half %c, i32 0
@@ -1676,7 +1676,7 @@ define <4 x double> @vfwmacc_vv_v4f64_v4f16(<4 x double> %va, <4 x half> %vb, <4
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v12, v10
; CHECK-NEXT: vfwcvt.f.f.v v10, v11
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfwmacc.vv v8, v12, v10
; CHECK-NEXT: ret
%vd = fpext <4 x half> %vb to <4 x double>
@@ -1692,7 +1692,7 @@ define <4 x double> @vfwmacc_vf_v4f64_v4f16(<4 x double> %va, <4 x half> %vb, ha
; CHECK-NEXT: vfmv.v.f v11, fa0
; CHECK-NEXT: vfwcvt.f.f.v v12, v10
; CHECK-NEXT: vfwcvt.f.f.v v10, v11
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfwmacc.vv v8, v12, v10
; CHECK-NEXT: ret
%head = insertelement <4 x half> poison, half %c, i32 0
@@ -1709,7 +1709,7 @@ define <4 x double> @vfwnmacc_vv_v4f64_v4f16(<4 x double> %va, <4 x half> %vb, <
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v12, v10
; CHECK-NEXT: vfwcvt.f.f.v v10, v11
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfwnmacc.vv v8, v12, v10
; CHECK-NEXT: ret
%vd = fpext <4 x half> %vb to <4 x double>
@@ -1727,7 +1727,7 @@ define <4 x double> @vfwnmacc_vf_v4f64_v4f16(<4 x double> %va, <4 x half> %vb, h
; CHECK-NEXT: vfmv.v.f v11, fa0
; CHECK-NEXT: vfwcvt.f.f.v v12, v10
; CHECK-NEXT: vfwcvt.f.f.v v10, v11
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfwnmacc.vv v8, v12, v10
; CHECK-NEXT: ret
%head = insertelement <4 x half> poison, half %c, i32 0
@@ -1747,7 +1747,7 @@ define <4 x double> @vfwnmacc_fv_v4f64_v4f16(<4 x double> %va, <4 x half> %vb, h
; CHECK-NEXT: vfmv.v.f v11, fa0
; CHECK-NEXT: vfwcvt.f.f.v v12, v10
; CHECK-NEXT: vfwcvt.f.f.v v10, v11
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfwnmacc.vv v8, v12, v10
; CHECK-NEXT: ret
%head = insertelement <4 x half> poison, half %c, i32 0
@@ -1766,7 +1766,7 @@ define <4 x double> @vfwmsac_vv_v4f64_v4f16(<4 x double> %va, <4 x half> %vb, <4
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v12, v10
; CHECK-NEXT: vfwcvt.f.f.v v10, v11
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfwmsac.vv v8, v12, v10
; CHECK-NEXT: ret
%vd = fpext <4 x half> %vb to <4 x double>
@@ -1783,7 +1783,7 @@ define <4 x double> @vfwmsac_vf_v4f64_v4f16(<4 x double> %va, <4 x half> %vb, ha
; CHECK-NEXT: vfmv.v.f v11, fa0
; CHECK-NEXT: vfwcvt.f.f.v v12, v10
; CHECK-NEXT: vfwcvt.f.f.v v10, v11
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfwmsac.vv v8, v12, v10
; CHECK-NEXT: ret
%head = insertelement <4 x half> poison, half %c, i32 0
@@ -1801,7 +1801,7 @@ define <4 x double> @vfwnmsac_vv_v4f64_v4f16(<4 x double> %va, <4 x half> %vb, <
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v12, v10
; CHECK-NEXT: vfwcvt.f.f.v v10, v11
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfwnmsac.vv v8, v12, v10
; CHECK-NEXT: ret
%vd = fpext <4 x half> %vb to <4 x double>
@@ -1818,7 +1818,7 @@ define <4 x double> @vfwnmsac_vf_v4f64_v4f16(<4 x double> %va, <4 x half> %vb, h
; CHECK-NEXT: vfmv.v.f v11, fa0
; CHECK-NEXT: vfwcvt.f.f.v v12, v10
; CHECK-NEXT: vfwcvt.f.f.v v10, v11
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfwnmsac.vv v8, v12, v10
; CHECK-NEXT: ret
%head = insertelement <4 x half> poison, half %c, i32 0
@@ -1837,7 +1837,7 @@ define <4 x double> @vfwnmsac_fv_v4f64_v4f16(<4 x double> %va, <4 x half> %vb, h
; CHECK-NEXT: vfmv.v.f v11, fa0
; CHECK-NEXT: vfwcvt.f.f.v v12, v10
; CHECK-NEXT: vfwcvt.f.f.v v10, v11
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfwnmsac.vv v8, v12, v10
; CHECK-NEXT: ret
%head = insertelement <4 x half> poison, half %c, i32 0
@@ -1855,7 +1855,7 @@ define <8 x double> @vfwmacc_vv_v8f64_v8f16(<8 x double> %va, <8 x half> %vb, <8
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v14, v12
; CHECK-NEXT: vfwcvt.f.f.v v16, v13
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfwmacc.vv v8, v14, v16
; CHECK-NEXT: ret
%vd = fpext <8 x half> %vb to <8 x double>
@@ -1871,7 +1871,7 @@ define <8 x double> @vfwmacc_vf_v8f64_v8f16(<8 x double> %va, <8 x half> %vb, ha
; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vfwcvt.f.f.v v14, v12
; CHECK-NEXT: vfwcvt.f.f.v v12, v16
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfwmacc.vv v8, v14, v12
; CHECK-NEXT: ret
%head = insertelement <8 x half> poison, half %c, i32 0
@@ -1888,7 +1888,7 @@ define <8 x double> @vfwnmacc_vv_v8f64_v8f16(<8 x double> %va, <8 x half> %vb, <
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v14, v12
; CHECK-NEXT: vfwcvt.f.f.v v16, v13
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfwnmacc.vv v8, v14, v16
; CHECK-NEXT: ret
%vd = fpext <8 x half> %vb to <8 x double>
@@ -1906,7 +1906,7 @@ define <8 x double> @vfwnmacc_vf_v8f64_v8f16(<8 x double> %va, <8 x half> %vb, h
; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vfwcvt.f.f.v v14, v12
; CHECK-NEXT: vfwcvt.f.f.v v12, v16
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfwnmacc.vv v8, v14, v12
; CHECK-NEXT: ret
%head = insertelement <8 x half> poison, half %c, i32 0
@@ -1926,7 +1926,7 @@ define <8 x double> @vfwnmacc_fv_v8f64_v8f16(<8 x double> %va, <8 x half> %vb, h
; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vfwcvt.f.f.v v14, v12
; CHECK-NEXT: vfwcvt.f.f.v v12, v16
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfwnmacc.vv v8, v14, v12
; CHECK-NEXT: ret
%head = insertelement <8 x half> poison, half %c, i32 0
@@ -1945,7 +1945,7 @@ define <8 x double> @vfwmsac_vv_v8f64_v8f16(<8 x double> %va, <8 x half> %vb, <8
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v14, v12
; CHECK-NEXT: vfwcvt.f.f.v v16, v13
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfwmsac.vv v8, v14, v16
; CHECK-NEXT: ret
%vd = fpext <8 x half> %vb to <8 x double>
@@ -1962,7 +1962,7 @@ define <8 x double> @vfwmsac_vf_v8f64_v8f16(<8 x double> %va, <8 x half> %vb, ha
; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vfwcvt.f.f.v v14, v12
; CHECK-NEXT: vfwcvt.f.f.v v12, v16
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfwmsac.vv v8, v14, v12
; CHECK-NEXT: ret
%head = insertelement <8 x half> poison, half %c, i32 0
@@ -1980,7 +1980,7 @@ define <8 x double> @vfwnmsac_vv_v8f64_v8f16(<8 x double> %va, <8 x half> %vb, <
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v14, v12
; CHECK-NEXT: vfwcvt.f.f.v v16, v13
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfwnmsac.vv v8, v14, v16
; CHECK-NEXT: ret
%vd = fpext <8 x half> %vb to <8 x double>
@@ -1997,7 +1997,7 @@ define <8 x double> @vfwnmsac_vf_v8f64_v8f16(<8 x double> %va, <8 x half> %vb, h
; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vfwcvt.f.f.v v14, v12
; CHECK-NEXT: vfwcvt.f.f.v v12, v16
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfwnmsac.vv v8, v14, v12
; CHECK-NEXT: ret
%head = insertelement <8 x half> poison, half %c, i32 0
@@ -2016,7 +2016,7 @@ define <8 x double> @vfwnmsac_fv_v8f64_v8f16(<8 x double> %va, <8 x half> %vb, h
; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vfwcvt.f.f.v v14, v12
; CHECK-NEXT: vfwcvt.f.f.v v12, v16
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfwnmsac.vv v8, v14, v12
; CHECK-NEXT: ret
%head = insertelement <8 x half> poison, half %c, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmaccbf16.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmaccbf16.ll
index aec970adff51e..ab237cac55783 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmaccbf16.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmaccbf16.ll
@@ -16,7 +16,7 @@ define <1 x float> @vfwmaccbf16_vv_v1f32(<1 x float> %a, <1 x bfloat> %b, <1 x b
; ZVFBFMIN-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v11, v9
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v10
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFBFMIN-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; ZVFBFMIN-NEXT: vfmacc.vv v8, v11, v9
; ZVFBFMIN-NEXT: ret
%b.ext = fpext <1 x bfloat> %b to <1 x float>
@@ -41,7 +41,7 @@ define <1 x float> @vfwmaccbf16_vf_v1f32(<1 x float> %a, bfloat %b, <1 x bfloat>
; ZVFBFMIN-NEXT: vmv.s.x v10, a0
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v11, v10
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v9
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFBFMIN-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; ZVFBFMIN-NEXT: vfmacc.vv v8, v11, v10
; ZVFBFMIN-NEXT: ret
%b.head = insertelement <1 x bfloat> poison, bfloat %b, i32 0
@@ -64,7 +64,7 @@ define <2 x float> @vfwmaccbf16_vv_v2f32(<2 x float> %a, <2 x bfloat> %b, <2 x b
; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v11, v9
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v10
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFBFMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFBFMIN-NEXT: vfmacc.vv v8, v11, v9
; ZVFBFMIN-NEXT: ret
%b.ext = fpext <2 x bfloat> %b to <2 x float>
@@ -89,7 +89,7 @@ define <2 x float> @vfwmaccbf16_vf_v2f32(<2 x float> %a, bfloat %b, <2 x bfloat>
; ZVFBFMIN-NEXT: vmv.v.x v10, a0
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v11, v10
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v9
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFBFMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFBFMIN-NEXT: vfmacc.vv v8, v11, v10
; ZVFBFMIN-NEXT: ret
%b.head = insertelement <2 x bfloat> poison, bfloat %b, i32 0
@@ -112,7 +112,7 @@ define <4 x float> @vfwmaccbf16_vv_v4f32(<4 x float> %a, <4 x bfloat> %b, <4 x b
; ZVFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v11, v9
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v10
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFBFMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFBFMIN-NEXT: vfmacc.vv v8, v11, v9
; ZVFBFMIN-NEXT: ret
%b.ext = fpext <4 x bfloat> %b to <4 x float>
@@ -137,7 +137,7 @@ define <4 x float> @vfwmaccbf16_vf_v4f32(<4 x float> %a, bfloat %b, <4 x bfloat>
; ZVFBFMIN-NEXT: vmv.v.x v10, a0
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v11, v10
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v9
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFBFMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFBFMIN-NEXT: vfmacc.vv v8, v11, v10
; ZVFBFMIN-NEXT: ret
%b.head = insertelement <4 x bfloat> poison, bfloat %b, i32 0
@@ -160,7 +160,7 @@ define <8 x float> @vfwmaccbf16_vv_v8f32(<8 x float> %a, <8 x bfloat> %b, <8 x b
; ZVFBFMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v10
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v14, v11
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFBFMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFBFMIN-NEXT: vfmacc.vv v8, v12, v14
; ZVFBFMIN-NEXT: ret
%b.ext = fpext <8 x bfloat> %b to <8 x float>
@@ -185,7 +185,7 @@ define <8 x float> @vfwmaccbf16_vf_v8f32(<8 x float> %a, bfloat %b, <8 x bfloat>
; ZVFBFMIN-NEXT: vmv.v.x v11, a0
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v11
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v14, v10
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFBFMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVFBFMIN-NEXT: vfmacc.vv v8, v12, v14
; ZVFBFMIN-NEXT: ret
%b.head = insertelement <8 x bfloat> poison, bfloat %b, i32 0
@@ -208,7 +208,7 @@ define <16 x float> @vfwmaccbf16_vv_v16f32(<16 x float> %a, <16 x bfloat> %b, <1
; ZVFBFMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v12
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v20, v14
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFBFMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFBFMIN-NEXT: vfmacc.vv v8, v16, v20
; ZVFBFMIN-NEXT: ret
%b.ext = fpext <16 x bfloat> %b to <16 x float>
@@ -233,7 +233,7 @@ define <16 x float> @vfwmaccbf16_vf_v16f32(<16 x float> %a, bfloat %b, <16 x bfl
; ZVFBFMIN-NEXT: vmv.v.x v14, a0
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v14
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v20, v12
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFBFMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVFBFMIN-NEXT: vfmacc.vv v8, v16, v20
; ZVFBFMIN-NEXT: ret
%b.head = insertelement <16 x bfloat> poison, bfloat %b, i32 0
@@ -310,7 +310,7 @@ define <4 x float> @vfwmaccbf16_vf_v4f32_scalar_extend(<4 x float> %rd, bfloat %
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v9
; ZVFBFMIN-NEXT: slli a0, a0, 16
; ZVFBFMIN-NEXT: fmv.w.x fa5, a0
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFBFMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFBFMIN-NEXT: vfmacc.vf v8, fa5, v10
; ZVFBFMIN-NEXT: ret
%b_ext = fpext <4 x bfloat> %b to <4 x float>
@@ -328,7 +328,7 @@ define <4 x float> @mix(<4 x float> %rd, <4 x half> %a, <4 x bfloat> %b) {
; ZVFBFWMA-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFBFWMA-NEXT: vfwcvt.f.f.v v11, v9
; ZVFBFWMA-NEXT: vfwcvtbf16.f.f.v v9, v10
-; ZVFBFWMA-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFBFWMA-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFBFWMA-NEXT: vfmacc.vv v8, v11, v9
; ZVFBFWMA-NEXT: ret
;
@@ -337,7 +337,7 @@ define <4 x float> @mix(<4 x float> %rd, <4 x half> %a, <4 x bfloat> %b) {
; ZVFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFBFMIN-NEXT: vfwcvt.f.f.v v11, v9
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v10
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFBFMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFBFMIN-NEXT: vfmacc.vv v8, v11, v9
; ZVFBFMIN-NEXT: ret
%a_ext = fpext <4 x half> %a to <4 x float>
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
index 47ac1c1a88df4..660235f0a6d44 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
@@ -423,7 +423,7 @@ define <2 x double> @vfwmul_squared_v2f16_v2f64(ptr %x) {
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfwcvt.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfwmul.vv v8, v9, v9
; CHECK-NEXT: ret
%a = load <2 x half>, ptr %x
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll
index ce5483e3ae8cc..baa9ecd5b794a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll
@@ -1478,7 +1478,7 @@ define <1 x half> @vsitofp_v1i64_v1f16(<1 x i64> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfncvt.f.x.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vfncvt.f.f.w v8, v9
; CHECK-NEXT: ret
%evec = call <1 x half> @llvm.experimental.constrained.sitofp.v1f16.v1i64(<1 x i64> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -1491,7 +1491,7 @@ define <1 x half> @vuitofp_v1i64_v1f16(<1 x i64> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vfncvt.f.xu.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vfncvt.f.f.w v8, v9
; CHECK-NEXT: ret
%evec = call <1 x half> @llvm.experimental.constrained.uitofp.v1f16.v1i64(<1 x i64> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -1551,7 +1551,7 @@ define <2 x half> @vsitofp_v2i64_v2f16(<2 x i64> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfncvt.f.x.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfncvt.f.f.w v8, v9
; CHECK-NEXT: ret
%evec = call <2 x half> @llvm.experimental.constrained.sitofp.v2f16.v2i64(<2 x i64> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -1564,7 +1564,7 @@ define <2 x half> @vuitofp_v2i64_v2f16(<2 x i64> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vfncvt.f.xu.w v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfncvt.f.f.w v8, v9
; CHECK-NEXT: ret
%evec = call <2 x half> @llvm.experimental.constrained.uitofp.v2f16.v2i64(<2 x i64> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -1623,7 +1623,7 @@ define <4 x half> @vsitofp_v4i64_v4f16(<4 x i64> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfncvt.f.x.w v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfncvt.f.f.w v8, v10
; CHECK-NEXT: ret
%evec = call <4 x half> @llvm.experimental.constrained.sitofp.v4f16.v4i64(<4 x i64> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -1636,7 +1636,7 @@ define <4 x half> @vuitofp_v4i64_v4f16(<4 x i64> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfncvt.f.xu.w v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfncvt.f.f.w v8, v10
; CHECK-NEXT: ret
%evec = call <4 x half> @llvm.experimental.constrained.uitofp.v4f16.v4i64(<4 x i64> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -1695,7 +1695,7 @@ define <8 x half> @vsitofp_v8i64_v8f16(<8 x i64> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfncvt.f.x.w v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvt.f.f.w v8, v12
; CHECK-NEXT: ret
%evec = call <8 x half> @llvm.experimental.constrained.sitofp.v8f16.v8i64(<8 x i64> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
@@ -1708,7 +1708,7 @@ define <8 x half> @vuitofp_v8i64_v8f16(<8 x i64> %va) strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfncvt.f.xu.w v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfncvt.f.f.w v8, v12
; CHECK-NEXT: ret
%evec = call <8 x half> @llvm.experimental.constrained.uitofp.v8f16.v8i64(<8 x i64> %va, metadata !"round.dynamic", metadata !"fpexcept.strict")
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
index c361ccce14e4a..1aa9da1bf577a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
@@ -52,7 +52,7 @@ define void @vpscatter_v2i32_truncstore_v2i8(<2 x i32> %val, <2 x ptr> %ptrs, <2
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV32-NEXT: vnsrl.wi v8, v8, 0
-; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
@@ -62,7 +62,7 @@ define void @vpscatter_v2i32_truncstore_v2i8(<2 x i32> %val, <2 x ptr> %ptrs, <2
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV64-NEXT: vnsrl.wi v8, v8, 0
-; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
@@ -77,9 +77,9 @@ define void @vpscatter_v2i64_truncstore_v2i8(<2 x i64> %val, <2 x ptr> %ptrs, <2
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV32-NEXT: vnsrl.wi v8, v8, 0
-; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV32-NEXT: vnsrl.wi v8, v8, 0
-; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
@@ -89,9 +89,9 @@ define void @vpscatter_v2i64_truncstore_v2i8(<2 x i64> %val, <2 x ptr> %ptrs, <2
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64-NEXT: vnsrl.wi v8, v8, 0
-; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV64-NEXT: vnsrl.wi v8, v8, 0
-; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
@@ -218,7 +218,7 @@ define void @vpscatter_v2i64_truncstore_v2i16(<2 x i64> %val, <2 x ptr> %ptrs, <
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV32-NEXT: vnsrl.wi v8, v8, 0
-; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
@@ -228,7 +228,7 @@ define void @vpscatter_v2i64_truncstore_v2i16(<2 x i64> %val, <2 x ptr> %ptrs, <
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64-NEXT: vnsrl.wi v8, v8, 0
-; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; RV64-NEXT: vsoxei64.v v8, (zero), v9, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-fp-vp-bf16.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-fp-vp-bf16.ll
index 2c9f1d2c5c1e0..886b8cbfa6834 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-fp-vp-bf16.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-fp-vp-bf16.ll
@@ -10,7 +10,7 @@ define bfloat @vpreduce_fmin_nxv4bf16(bfloat %start, <4 x bfloat> %val, <4 x i1>
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v8, fa5
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: vfredmin.vs v8, v9, v8, v0.t
@@ -27,7 +27,7 @@ define bfloat @vpreduce_fmax_nxv4bf16(bfloat %start, <4 x bfloat> %val, <4 x i1>
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v8, fa5
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: vfredmax.vs v8, v9, v8, v0.t
@@ -44,7 +44,7 @@ define bfloat @vpreduce_fmin_nnan_nxv4bf16(bfloat %start, <4 x bfloat> %val, <4
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v8, fa5
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: vfredmin.vs v8, v9, v8, v0.t
@@ -61,7 +61,7 @@ define bfloat @vpreduce_fmax_nnan_nxv4bf16(bfloat %start, <4 x bfloat> %val, <4
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v8, fa5
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: vfredmax.vs v8, v9, v8, v0.t
@@ -138,7 +138,7 @@ define bfloat @vpreduce_fminimum_nnan_nxv4bf16(bfloat %start, <4 x bfloat> %val,
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v8, fa5
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: vfredmin.vs v8, v9, v8, v0.t
@@ -155,7 +155,7 @@ define bfloat @vpreduce_fmaximum_nnan_nxv4bf16(bfloat %start, <4 x bfloat> %val,
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v8, fa5
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: vfredmax.vs v8, v9, v8, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
index 32ae81926bbee..a9e0d65a68a90 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
@@ -950,11 +950,11 @@ define <2 x i64> @vrol_vx_v2i64(<2 x i64> %a, i64 %b) {
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vmv.v.x v9, a0
-; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: vwsub.vx v11, v10, a0
; RV32-NEXT: li a0, 63
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vand.vx v9, v9, a0
; RV32-NEXT: vand.vx v10, v11, a0
; RV32-NEXT: vsrl.vv v10, v8, v10
@@ -1015,11 +1015,11 @@ define <4 x i64> @vrol_vx_v4i64(<4 x i64> %a, i64 %b) {
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32-NEXT: vmv.v.x v10, a0
-; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.i v14, 0
; RV32-NEXT: vwsub.vx v12, v14, a0
; RV32-NEXT: li a0, 63
-; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32-NEXT: vand.vx v10, v10, a0
; RV32-NEXT: vand.vx v12, v12, a0
; RV32-NEXT: vsrl.vv v12, v8, v12
@@ -1080,11 +1080,11 @@ define <8 x i64> @vrol_vx_v8i64(<8 x i64> %a, i64 %b) {
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: vmv.v.x v12, a0
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.i v20, 0
; RV32-NEXT: vwsub.vx v16, v20, a0
; RV32-NEXT: li a0, 63
-; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: vand.vx v12, v12, a0
; RV32-NEXT: vand.vx v16, v16, a0
; RV32-NEXT: vsrl.vv v16, v8, v16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
index ec22d2be1eaad..7142bb6c369cd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
@@ -1696,11 +1696,11 @@ define <2 x i64> @vror_vx_v2i64(<2 x i64> %a, i64 %b) {
; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-RV32-NEXT: vmv.v.x v9, a0
-; CHECK-RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-RV32-NEXT: vmv.v.i v10, 0
; CHECK-RV32-NEXT: vwsub.vx v11, v10, a0
; CHECK-RV32-NEXT: li a0, 63
-; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-RV32-NEXT: vand.vx v9, v9, a0
; CHECK-RV32-NEXT: vand.vx v10, v11, a0
; CHECK-RV32-NEXT: vsll.vv v10, v8, v10
@@ -1740,7 +1740,7 @@ define <2 x i64> @vror_vi_v2i64(<2 x i64> %a) {
; CHECK-RV32-NEXT: li a0, 1
; CHECK-RV32-NEXT: vwsubu.vx v10, v9, a0
; CHECK-RV32-NEXT: li a0, 63
-; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-RV32-NEXT: vmv.v.x v9, a0
; CHECK-RV32-NEXT: vand.vx v10, v10, a0
; CHECK-RV32-NEXT: vand.vi v9, v9, 1
@@ -1775,7 +1775,7 @@ define <2 x i64> @vror_vi_rotl_v2i64(<2 x i64> %a) {
; CHECK-RV32-NEXT: li a0, 1
; CHECK-RV32-NEXT: vwsubu.vx v10, v9, a0
; CHECK-RV32-NEXT: li a0, 63
-; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-RV32-NEXT: vmv.v.x v9, a0
; CHECK-RV32-NEXT: vand.vx v10, v10, a0
; CHECK-RV32-NEXT: vand.vi v9, v9, 1
@@ -1832,11 +1832,11 @@ define <4 x i64> @vror_vx_v4i64(<4 x i64> %a, i64 %b) {
; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-RV32-NEXT: vmv.v.x v10, a0
-; CHECK-RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-RV32-NEXT: vmv.v.i v14, 0
; CHECK-RV32-NEXT: vwsub.vx v12, v14, a0
; CHECK-RV32-NEXT: li a0, 63
-; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-RV32-NEXT: vand.vx v10, v10, a0
; CHECK-RV32-NEXT: vand.vx v12, v12, a0
; CHECK-RV32-NEXT: vsll.vv v12, v8, v12
@@ -1876,7 +1876,7 @@ define <4 x i64> @vror_vi_v4i64(<4 x i64> %a) {
; CHECK-RV32-NEXT: li a0, 1
; CHECK-RV32-NEXT: vwsubu.vx v10, v12, a0
; CHECK-RV32-NEXT: li a0, 63
-; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-RV32-NEXT: vmv.v.x v12, a0
; CHECK-RV32-NEXT: vand.vx v10, v10, a0
; CHECK-RV32-NEXT: vand.vi v12, v12, 1
@@ -1911,7 +1911,7 @@ define <4 x i64> @vror_vi_rotl_v4i64(<4 x i64> %a) {
; CHECK-RV32-NEXT: li a0, 1
; CHECK-RV32-NEXT: vwsubu.vx v10, v12, a0
; CHECK-RV32-NEXT: li a0, 63
-; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-RV32-NEXT: vmv.v.x v12, a0
; CHECK-RV32-NEXT: vand.vx v10, v10, a0
; CHECK-RV32-NEXT: vand.vi v12, v12, 1
@@ -1968,11 +1968,11 @@ define <8 x i64> @vror_vx_v8i64(<8 x i64> %a, i64 %b) {
; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-RV32-NEXT: vmv.v.x v12, a0
-; CHECK-RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-RV32-NEXT: vmv.v.i v20, 0
; CHECK-RV32-NEXT: vwsub.vx v16, v20, a0
; CHECK-RV32-NEXT: li a0, 63
-; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; CHECK-RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-RV32-NEXT: vand.vx v12, v12, a0
; CHECK-RV32-NEXT: vand.vx v16, v16, a0
; CHECK-RV32-NEXT: vsll.vv v16, v8, v16
@@ -2012,7 +2012,7 @@ define <8 x i64> @vror_vi_v8i64(<8 x i64> %a) {
; CHECK-RV32-NEXT: li a0, 1
; CHECK-RV32-NEXT: vwsubu.vx v12, v16, a0
; CHECK-RV32-NEXT: li a0, 63
-; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; CHECK-RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-RV32-NEXT: vmv.v.x v16, a0
; CHECK-RV32-NEXT: vand.vx v12, v12, a0
; CHECK-RV32-NEXT: vand.vi v16, v16, 1
@@ -2047,7 +2047,7 @@ define <8 x i64> @vror_vi_rotl_v8i64(<8 x i64> %a) {
; CHECK-RV32-NEXT: li a0, 1
; CHECK-RV32-NEXT: vwsubu.vx v12, v16, a0
; CHECK-RV32-NEXT: li a0, 63
-; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; CHECK-RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-RV32-NEXT: vmv.v.x v16, a0
; CHECK-RV32-NEXT: vand.vx v12, v12, a0
; CHECK-RV32-NEXT: vand.vi v16, v16, 1
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
index b97fa1d3a51ec..768e38ed1964c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
@@ -29,7 +29,7 @@ define void @vselect_vv_v6i32(ptr %a, ptr %b, ptr %cc, ptr %z) {
; RV32-NEXT: vslidedown.vi v10, v10, 2
; RV32-NEXT: vand.vi v10, v10, 1
; RV32-NEXT: vmsne.vi v0, v10, 0
-; RV32-NEXT: vsetvli zero, zero, e32, m2, tu, mu
+; RV32-NEXT: vsetivli zero, 6, e32, m2, tu, mu
; RV32-NEXT: vle32.v v8, (a0), v0.t
; RV32-NEXT: vse32.v v8, (a3)
; RV32-NEXT: ret
@@ -60,7 +60,7 @@ define void @vselect_vv_v6i32(ptr %a, ptr %b, ptr %cc, ptr %z) {
; RV64-NEXT: vslidedown.vi v10, v10, 2
; RV64-NEXT: vand.vi v10, v10, 1
; RV64-NEXT: vmsne.vi v0, v10, 0
-; RV64-NEXT: vsetvli zero, zero, e32, m2, tu, mu
+; RV64-NEXT: vsetivli zero, 6, e32, m2, tu, mu
; RV64-NEXT: vle32.v v8, (a0), v0.t
; RV64-NEXT: vse32.v v8, (a3)
; RV64-NEXT: ret
@@ -99,7 +99,7 @@ define void @vselect_vx_v6i32(i32 %a, ptr %b, ptr %cc, ptr %z) {
; RV32-NEXT: vslidedown.vi v10, v10, 2
; RV32-NEXT: vand.vi v10, v10, 1
; RV32-NEXT: vmsne.vi v0, v10, 0
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; RV32-NEXT: vmerge.vxm v8, v8, a0, v0
; RV32-NEXT: vse32.v v8, (a3)
; RV32-NEXT: ret
@@ -130,7 +130,7 @@ define void @vselect_vx_v6i32(i32 %a, ptr %b, ptr %cc, ptr %z) {
; RV64-NEXT: vslidedown.vi v10, v10, 2
; RV64-NEXT: vand.vi v10, v10, 1
; RV64-NEXT: vmsne.vi v0, v10, 0
-; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; RV64-NEXT: vmerge.vxm v8, v8, a0, v0
; RV64-NEXT: vse32.v v8, (a3)
; RV64-NEXT: ret
@@ -170,7 +170,7 @@ define void @vselect_vi_v6i32(ptr %b, ptr %cc, ptr %z) {
; RV32-NEXT: vslidedown.vi v10, v10, 2
; RV32-NEXT: vand.vi v10, v10, 1
; RV32-NEXT: vmsne.vi v0, v10, 0
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; RV32-NEXT: vmerge.vim v8, v8, -1, v0
; RV32-NEXT: vse32.v v8, (a2)
; RV32-NEXT: ret
@@ -201,7 +201,7 @@ define void @vselect_vi_v6i32(ptr %b, ptr %cc, ptr %z) {
; RV64-NEXT: vslidedown.vi v10, v10, 2
; RV64-NEXT: vand.vi v10, v10, 1
; RV64-NEXT: vmsne.vi v0, v10, 0
-; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; RV64-NEXT: vmerge.vim v8, v8, -1, v0
; RV64-NEXT: vse32.v v8, (a2)
; RV64-NEXT: ret
@@ -240,7 +240,7 @@ define void @vselect_vv_v6f32(ptr %a, ptr %b, ptr %cc, ptr %z) {
; RV32-NEXT: vslidedown.vi v10, v10, 2
; RV32-NEXT: vand.vi v10, v10, 1
; RV32-NEXT: vmsne.vi v0, v10, 0
-; RV32-NEXT: vsetvli zero, zero, e32, m2, tu, mu
+; RV32-NEXT: vsetivli zero, 6, e32, m2, tu, mu
; RV32-NEXT: vle32.v v8, (a0), v0.t
; RV32-NEXT: vse32.v v8, (a3)
; RV32-NEXT: ret
@@ -271,7 +271,7 @@ define void @vselect_vv_v6f32(ptr %a, ptr %b, ptr %cc, ptr %z) {
; RV64-NEXT: vslidedown.vi v10, v10, 2
; RV64-NEXT: vand.vi v10, v10, 1
; RV64-NEXT: vmsne.vi v0, v10, 0
-; RV64-NEXT: vsetvli zero, zero, e32, m2, tu, mu
+; RV64-NEXT: vsetivli zero, 6, e32, m2, tu, mu
; RV64-NEXT: vle32.v v8, (a0), v0.t
; RV64-NEXT: vse32.v v8, (a3)
; RV64-NEXT: ret
@@ -310,7 +310,7 @@ define void @vselect_vx_v6f32(float %a, ptr %b, ptr %cc, ptr %z) {
; RV32-NEXT: vslidedown.vi v10, v10, 2
; RV32-NEXT: vand.vi v10, v10, 1
; RV32-NEXT: vmsne.vi v0, v10, 0
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; RV32-NEXT: vfmerge.vfm v8, v8, fa0, v0
; RV32-NEXT: vse32.v v8, (a2)
; RV32-NEXT: ret
@@ -341,7 +341,7 @@ define void @vselect_vx_v6f32(float %a, ptr %b, ptr %cc, ptr %z) {
; RV64-NEXT: vslidedown.vi v10, v10, 2
; RV64-NEXT: vand.vi v10, v10, 1
; RV64-NEXT: vmsne.vi v0, v10, 0
-; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; RV64-NEXT: vfmerge.vfm v8, v8, fa0, v0
; RV64-NEXT: vse32.v v8, (a2)
; RV64-NEXT: ret
@@ -381,7 +381,7 @@ define void @vselect_vfpzero_v6f32(ptr %b, ptr %cc, ptr %z) {
; RV32-NEXT: vslidedown.vi v10, v10, 2
; RV32-NEXT: vand.vi v10, v10, 1
; RV32-NEXT: vmsne.vi v0, v10, 0
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; RV32-NEXT: vmerge.vim v8, v8, 0, v0
; RV32-NEXT: vse32.v v8, (a2)
; RV32-NEXT: ret
@@ -412,7 +412,7 @@ define void @vselect_vfpzero_v6f32(ptr %b, ptr %cc, ptr %z) {
; RV64-NEXT: vslidedown.vi v10, v10, 2
; RV64-NEXT: vand.vi v10, v10, 1
; RV64-NEXT: vmsne.vi v0, v10, 0
-; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; RV64-NEXT: vmerge.vim v8, v8, 0, v0
; RV64-NEXT: vse32.v v8, (a2)
; RV64-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vw-web-simplification.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vw-web-simplification.ll
index b9466e9f7cc15..b67d8b1165a37 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vw-web-simplification.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vw-web-simplification.ll
@@ -41,10 +41,10 @@ define <2 x i16> @vwmul_v2i16_multiple_users(ptr %x, ptr %y, ptr %z) {
; NO_FOLDING2-NEXT: vsext.vf2 v11, v8
; NO_FOLDING2-NEXT: vsext.vf2 v8, v9
; NO_FOLDING2-NEXT: vmul.vv v8, v11, v8
-; NO_FOLDING2-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; NO_FOLDING2-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; NO_FOLDING2-NEXT: vwadd.wv v9, v11, v10
; NO_FOLDING2-NEXT: vwsub.wv v11, v11, v10
-; NO_FOLDING2-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; NO_FOLDING2-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; NO_FOLDING2-NEXT: vor.vv v8, v8, v9
; NO_FOLDING2-NEXT: vor.vv v8, v8, v11
; NO_FOLDING2-NEXT: ret
@@ -58,7 +58,7 @@ define <2 x i16> @vwmul_v2i16_multiple_users(ptr %x, ptr %y, ptr %z) {
; FOLDING-NEXT: vwmul.vv v11, v8, v9
; FOLDING-NEXT: vwadd.vv v9, v8, v10
; FOLDING-NEXT: vwsub.vv v12, v8, v10
-; FOLDING-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; FOLDING-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; FOLDING-NEXT: vor.vv v8, v11, v9
; FOLDING-NEXT: vor.vv v8, v8, v12
; FOLDING-NEXT: ret
@@ -86,6 +86,22 @@ define <4 x i32> @pr159152(<4 x i8> %x) {
; NO_FOLDING-NEXT: vwaddu.vx v8, v9, a0
; NO_FOLDING-NEXT: ret
;
+; NO_FOLDING1-LABEL: pr159152:
+; NO_FOLDING1: # %bb.0:
+; NO_FOLDING1-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; NO_FOLDING1-NEXT: vsext.vf2 v9, v8
+; NO_FOLDING1-NEXT: li a0, 9
+; NO_FOLDING1-NEXT: vwaddu.vx v8, v9, a0
+; NO_FOLDING1-NEXT: ret
+;
+; NO_FOLDING2-LABEL: pr159152:
+; NO_FOLDING2: # %bb.0:
+; NO_FOLDING2-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; NO_FOLDING2-NEXT: vsext.vf2 v9, v8
+; NO_FOLDING2-NEXT: li a0, 9
+; NO_FOLDING2-NEXT: vwaddu.vx v8, v9, a0
+; NO_FOLDING2-NEXT: ret
+;
; FOLDING-LABEL: pr159152:
; FOLDING: # %bb.0:
; FOLDING-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd-mask.ll
index 7bac239cfffea..bacf59228f45e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd-mask.ll
@@ -10,7 +10,7 @@ define <8 x i64> @vwadd_wv_mask_v8i32(<8 x i32> %x, <8 x i64> %y) {
; CHECK-NEXT: li a0, 42
; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: vmv4r.v v8, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, tu, mu
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, tu, mu
; CHECK-NEXT: vwadd.wv v8, v8, v16, v0.t
; CHECK-NEXT: ret
%mask = icmp slt <8 x i32> %x, <i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42>
@@ -28,7 +28,7 @@ define <8 x i64> @vwaddu_wv_mask_v8i32(<8 x i32> %x, <8 x i64> %y) {
; CHECK-NEXT: li a0, 42
; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: vmv4r.v v8, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, tu, mu
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, tu, mu
; CHECK-NEXT: vwaddu.wv v8, v8, v16, v0.t
; CHECK-NEXT: ret
%mask = icmp slt <8 x i32> %x, <i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42>
@@ -65,7 +65,7 @@ define <8 x i64> @vwadd_wv_mask_v8i32_commutative(<8 x i32> %x, <8 x i64> %y) {
; CHECK-NEXT: li a0, 42
; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: vmv4r.v v8, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, tu, mu
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, tu, mu
; CHECK-NEXT: vwadd.wv v8, v8, v16, v0.t
; CHECK-NEXT: ret
%mask = icmp slt <8 x i32> %x, <i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42>
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
index b39fff64b1090..40b57fe43a04a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
@@ -668,7 +668,7 @@ define <8 x i16> @vwadd_vx_v8i16_i16(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vmv.v.x v8, a1
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vwadd.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <8 x i8>, ptr %x
@@ -723,7 +723,7 @@ define <4 x i32> @vwadd_vx_v4i32_i32(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vmv.v.x v8, a1
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vwadd.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <4 x i16>, ptr %x
@@ -811,7 +811,7 @@ define <2 x i64> @vwadd_vx_v2i64_i64(ptr %x, ptr %y) nounwind {
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vle32.v v9, (a0)
; RV64-NEXT: vmv.v.x v8, a1
-; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64-NEXT: vwadd.wv v8, v8, v9
; RV64-NEXT: ret
%a = load <2 x i32>, ptr %x
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll
index e89bac54a7b66..00fc280b09b17 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll
@@ -355,7 +355,7 @@ define <2 x i32> @vwaddu_v2i32_v2i8(ptr %x, ptr %y) {
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vle8.v v9, (a1)
; CHECK-NEXT: vwaddu.vv v10, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vzext.vf2 v8, v10
; CHECK-NEXT: ret
%a = load <2 x i8>, ptr %x
@@ -668,7 +668,7 @@ define <8 x i16> @vwaddu_vx_v8i16_i16(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vmv.v.x v8, a1
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vwaddu.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <8 x i8>, ptr %x
@@ -723,7 +723,7 @@ define <4 x i32> @vwaddu_vx_v4i32_i32(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vmv.v.x v8, a1
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vwaddu.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <4 x i16>, ptr %x
@@ -853,7 +853,7 @@ define <2 x i64> @vwaddu_vx_v2i64_i64(ptr %x, ptr %y) nounwind {
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vle32.v v9, (a0)
; RV64-NEXT: vmv.v.x v8, a1
-; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64-NEXT: vwaddu.wv v8, v8, v9
; RV64-NEXT: ret
%a = load <2 x i32>, ptr %x
@@ -872,7 +872,7 @@ define <4 x i64> @crash(<4 x i16> %x, <4 x i16> %y) {
; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v11, v8
; CHECK-NEXT: vsext.vf4 v8, v11
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vzext.vf2 v11, v10
; CHECK-NEXT: vwaddu.wv v8, v8, v11
; CHECK-NEXT: ret
@@ -889,7 +889,7 @@ define <2 x i32> @vwaddu_v2i32_of_v2i8(ptr %x, ptr %y) {
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vle8.v v9, (a1)
; CHECK-NEXT: vwaddu.vv v10, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vzext.vf2 v8, v10
; CHECK-NEXT: ret
%a = load <2 x i8>, ptr %x
@@ -907,7 +907,7 @@ define <2 x i64> @vwaddu_v2i64_of_v2i8(ptr %x, ptr %y) {
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vle8.v v9, (a1)
; CHECK-NEXT: vwaddu.vv v10, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vzext.vf4 v8, v10
; CHECK-NEXT: ret
%a = load <2 x i8>, ptr %x
@@ -925,7 +925,7 @@ define <2 x i64> @vwaddu_v2i64_of_v2i16(ptr %x, ptr %y) {
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vle16.v v9, (a1)
; CHECK-NEXT: vwaddu.vv v10, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vzext.vf2 v8, v10
; CHECK-NEXT: ret
%a = load <2 x i16>, ptr %x
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
index 94c3138fd330b..dba2787b19dba 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
@@ -27,7 +27,7 @@ define <2 x i16> @vwmul_v2i16_multiple_users(ptr %x, ptr %y, ptr %z) {
; CHECK-NEXT: vle8.v v10, (a2)
; CHECK-NEXT: vwmul.vv v11, v8, v9
; CHECK-NEXT: vwmul.vv v9, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vor.vv v8, v11, v9
; CHECK-NEXT: ret
%a = load <2 x i8>, ptr %x
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
index eeb232ec1555c..e29c6c885c268 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
@@ -367,7 +367,7 @@ define <2 x i32> @vwmulu_v2i32_v2i8(ptr %x, ptr %y) {
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vle8.v v9, (a1)
; CHECK-NEXT: vwmulu.vv v10, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vzext.vf2 v8, v10
; CHECK-NEXT: ret
%a = load <2 x i8>, ptr %x
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll
index 2c9aed6274dd8..67d15ef3868b2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll
@@ -78,7 +78,7 @@ define <4 x i64> @vwsll_vx_i32_v4i64_sext(<4 x i32> %a, i32 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v8
; CHECK-NEXT: vsext.vf2 v8, v12
; CHECK-NEXT: vsll.vv v8, v10, v8
@@ -104,7 +104,7 @@ define <4 x i64> @vwsll_vx_i32_v4i64_zext(<4 x i32> %a, i32 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v8
; CHECK-NEXT: vzext.vf2 v8, v12
; CHECK-NEXT: vsll.vv v8, v10, v8
@@ -129,7 +129,7 @@ define <4 x i64> @vwsll_vx_i16_v4i64_sext(<4 x i32> %a, i16 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v8
; CHECK-NEXT: vsext.vf4 v8, v12
; CHECK-NEXT: vsll.vv v8, v10, v8
@@ -154,7 +154,7 @@ define <4 x i64> @vwsll_vx_i16_v4i64_zext(<4 x i32> %a, i16 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v8
; CHECK-NEXT: vzext.vf4 v8, v12
; CHECK-NEXT: vsll.vv v8, v10, v8
@@ -179,7 +179,7 @@ define <4 x i64> @vwsll_vx_i8_v4i64_sext(<4 x i32> %a, i8 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v8
; CHECK-NEXT: vsext.vf8 v8, v12
; CHECK-NEXT: vsll.vv v8, v10, v8
@@ -204,7 +204,7 @@ define <4 x i64> @vwsll_vx_i8_v4i64_zext(<4 x i32> %a, i8 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v8
; CHECK-NEXT: vzext.vf8 v8, v12
; CHECK-NEXT: vsll.vv v8, v10, v8
@@ -340,7 +340,7 @@ define <8 x i32> @vwsll_vx_i16_v8i32_sext(<8 x i16> %a, i16 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v8
; CHECK-NEXT: vsext.vf2 v8, v12
; CHECK-NEXT: vsll.vv v8, v10, v8
@@ -366,7 +366,7 @@ define <8 x i32> @vwsll_vx_i16_v8i32_zext(<8 x i16> %a, i16 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v8
; CHECK-NEXT: vzext.vf2 v8, v12
; CHECK-NEXT: vsll.vv v8, v10, v8
@@ -391,7 +391,7 @@ define <8 x i32> @vwsll_vx_i8_v8i32_sext(<8 x i16> %a, i8 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v8
; CHECK-NEXT: vsext.vf4 v8, v12
; CHECK-NEXT: vsll.vv v8, v10, v8
@@ -416,7 +416,7 @@ define <8 x i32> @vwsll_vx_i8_v8i32_zext(<8 x i16> %a, i8 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v8
; CHECK-NEXT: vzext.vf4 v8, v12
; CHECK-NEXT: vsll.vv v8, v10, v8
@@ -511,11 +511,11 @@ define <16 x i16> @vwsll_vx_i64_v16i16(<16 x i8> %a, i64 %b) {
; RV32-NEXT: vmv.v.x v16, a0
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vrgather.vi v24, v16, 0
-; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV32-NEXT: vzext.vf2 v12, v8
-; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vnsrl.wi v8, v24, 0
-; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV32-NEXT: vnsrl.wi v14, v8, 0
; RV32-NEXT: vsll.vv v8, v12, v14
; RV32-NEXT: ret
@@ -524,11 +524,11 @@ define <16 x i16> @vwsll_vx_i64_v16i16(<16 x i8> %a, i64 %b) {
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vmv.v.x v16, a0
-; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV64-NEXT: vzext.vf2 v12, v8
-; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV64-NEXT: vnsrl.wi v8, v16, 0
-; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV64-NEXT: vnsrl.wi v14, v8, 0
; RV64-NEXT: vsll.vv v8, v12, v14
; RV64-NEXT: ret
@@ -539,11 +539,11 @@ define <16 x i16> @vwsll_vx_i64_v16i16(<16 x i8> %a, i64 %b) {
; CHECK-ZVBB-RV32-NEXT: vmv.v.x v16, a0
; CHECK-ZVBB-RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-ZVBB-RV32-NEXT: vrgather.vi v24, v16, 0
-; CHECK-ZVBB-RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-ZVBB-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-ZVBB-RV32-NEXT: vzext.vf2 v12, v8
-; CHECK-ZVBB-RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-ZVBB-RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-ZVBB-RV32-NEXT: vnsrl.wi v8, v24, 0
-; CHECK-ZVBB-RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-ZVBB-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-ZVBB-RV32-NEXT: vnsrl.wi v14, v8, 0
; CHECK-ZVBB-RV32-NEXT: vsll.vv v8, v12, v14
; CHECK-ZVBB-RV32-NEXT: ret
@@ -567,7 +567,7 @@ define <16 x i16> @vwsll_vx_i32_v16i16(<16 x i8> %a, i32 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v8
; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: vsll.vv v8, v10, v8
@@ -613,7 +613,7 @@ define <16 x i16> @vwsll_vx_i8_v16i16_sext(<16 x i8> %a, i8 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v8
; CHECK-NEXT: vsext.vf2 v8, v12
; CHECK-NEXT: vsll.vv v8, v10, v8
@@ -639,7 +639,7 @@ define <16 x i16> @vwsll_vx_i8_v16i16_zext(<16 x i8> %a, i8 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v8
; CHECK-NEXT: vzext.vf2 v8, v12
; CHECK-NEXT: vsll.vv v8, v10, v8
@@ -753,7 +753,7 @@ define <4 x i64> @vwsll_vx_i32_v4i64_v4i8_sext(<4 x i8> %a, i32 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vzext.vf8 v10, v8
; CHECK-NEXT: vsext.vf2 v8, v12
; CHECK-NEXT: vsll.vv v8, v10, v8
@@ -763,7 +763,7 @@ define <4 x i64> @vwsll_vx_i32_v4i64_v4i8_sext(<4 x i8> %a, i32 %b) {
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-ZVBB-NEXT: vmv.v.x v12, a0
-; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
; CHECK-ZVBB-NEXT: vsext.vf2 v8, v12
; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v8
@@ -781,7 +781,7 @@ define <4 x i64> @vwsll_vx_i32_v4i64_v4i8_zext(<4 x i8> %a, i32 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vzext.vf8 v10, v8
; CHECK-NEXT: vzext.vf2 v8, v12
; CHECK-NEXT: vsll.vv v8, v10, v8
@@ -806,7 +806,7 @@ define <4 x i64> @vwsll_vx_i16_v4i64_v4i8_sext(<4 x i8> %a, i16 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vzext.vf8 v10, v8
; CHECK-NEXT: vsext.vf4 v8, v12
; CHECK-NEXT: vsll.vv v8, v10, v8
@@ -816,7 +816,7 @@ define <4 x i64> @vwsll_vx_i16_v4i64_v4i8_sext(<4 x i8> %a, i16 %b) {
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-ZVBB-NEXT: vmv.v.x v12, a0
-; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
; CHECK-ZVBB-NEXT: vsext.vf4 v8, v12
; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v8
@@ -834,7 +834,7 @@ define <4 x i64> @vwsll_vx_i16_v4i64_v4i8_zext(<4 x i8> %a, i16 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vzext.vf8 v10, v8
; CHECK-NEXT: vzext.vf4 v8, v12
; CHECK-NEXT: vsll.vv v8, v10, v8
@@ -859,7 +859,7 @@ define <4 x i64> @vwsll_vx_i8_v4i64_v4i8_sext(<4 x i8> %a, i8 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vzext.vf8 v10, v8
; CHECK-NEXT: vsext.vf8 v8, v12
; CHECK-NEXT: vsll.vv v8, v10, v8
@@ -869,7 +869,7 @@ define <4 x i64> @vwsll_vx_i8_v4i64_v4i8_sext(<4 x i8> %a, i8 %b) {
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vmv.v.x v12, a0
-; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
; CHECK-ZVBB-NEXT: vsext.vf8 v8, v12
; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v8
@@ -887,7 +887,7 @@ define <4 x i64> @vwsll_vx_i8_v4i64_v4i8_zext(<4 x i8> %a, i8 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vzext.vf8 v10, v8
; CHECK-NEXT: vzext.vf8 v8, v12
; CHECK-NEXT: vsll.vv v8, v10, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub-mask.ll
index eafea7292a54b..88b426eabf148 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub-mask.ll
@@ -10,7 +10,7 @@ define <8 x i64> @vwsub_wv_mask_v8i32(<8 x i32> %x, <8 x i64> %y) {
; CHECK-NEXT: li a0, 42
; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: vmv4r.v v8, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, tu, mu
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, tu, mu
; CHECK-NEXT: vwsub.wv v8, v8, v16, v0.t
; CHECK-NEXT: ret
%mask = icmp slt <8 x i32> %x, <i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42>
@@ -28,7 +28,7 @@ define <8 x i64> @vwsubu_wv_mask_v8i32(<8 x i32> %x, <8 x i64> %y) {
; CHECK-NEXT: li a0, 42
; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: vmv4r.v v8, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, tu, mu
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, tu, mu
; CHECK-NEXT: vwsubu.wv v8, v8, v16, v0.t
; CHECK-NEXT: ret
%mask = icmp slt <8 x i32> %x, <i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42>
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll
index 783de24100613..4a520b55423f6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll
@@ -669,7 +669,7 @@ define <8 x i16> @vwsub_vx_v8i16_i16(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vmv.v.x v8, a1
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vwsub.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <8 x i8>, ptr %x
@@ -726,7 +726,7 @@ define <4 x i32> @vwsub_vx_v4i32_i32(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vmv.v.x v8, a1
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vwsub.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <4 x i16>, ptr %x
@@ -817,7 +817,7 @@ define <2 x i64> @vwsub_vx_v2i64_i64(ptr %x, ptr %y) nounwind {
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vle32.v v9, (a0)
; RV64-NEXT: vmv.v.x v8, a1
-; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64-NEXT: vwsub.wv v8, v8, v9
; RV64-NEXT: ret
%a = load <2 x i32>, ptr %x
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll
index 86ac038eed221..838f04f548a6e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll
@@ -355,7 +355,7 @@ define <2 x i32> @vwsubu_v2i32_v2i8(ptr %x, ptr %y) {
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vle8.v v9, (a1)
; CHECK-NEXT: vwsubu.vv v10, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vsext.vf2 v8, v10
; CHECK-NEXT: ret
%a = load <2 x i8>, ptr %x
@@ -669,7 +669,7 @@ define <8 x i16> @vwsubu_vx_v8i16_i16(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vmv.v.x v8, a1
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vwsubu.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <8 x i8>, ptr %x
@@ -726,7 +726,7 @@ define <4 x i32> @vwsubu_vx_v4i32_i32(ptr %x, ptr %y) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vmv.v.x v8, a1
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vwsubu.wv v8, v8, v9
; CHECK-NEXT: ret
%a = load <4 x i16>, ptr %x
@@ -859,7 +859,7 @@ define <2 x i64> @vwsubu_vx_v2i64_i64(ptr %x, ptr %y) nounwind {
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vle32.v v9, (a0)
; RV64-NEXT: vmv.v.x v8, a1
-; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64-NEXT: vwsubu.wv v8, v8, v9
; RV64-NEXT: ret
%a = load <2 x i32>, ptr %x
@@ -878,7 +878,7 @@ define <2 x i32> @vwsubu_v2i32_of_v2i8(ptr %x, ptr %y) {
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vle8.v v9, (a1)
; CHECK-NEXT: vwsubu.vv v10, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vsext.vf2 v8, v10
; CHECK-NEXT: ret
%a = load <2 x i8>, ptr %x
@@ -896,7 +896,7 @@ define <2 x i64> @vwsubu_v2i64_of_v2i8(ptr %x, ptr %y) {
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vle8.v v9, (a1)
; CHECK-NEXT: vwsubu.vv v10, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vsext.vf4 v8, v10
; CHECK-NEXT: ret
%a = load <2 x i8>, ptr %x
@@ -914,7 +914,7 @@ define <2 x i64> @vwsubu_v2i64_of_v2i16(ptr %x, ptr %y) {
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vle16.v v9, (a1)
; CHECK-NEXT: vwsubu.vv v10, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vsext.vf2 v8, v10
; CHECK-NEXT: ret
%a = load <2 x i16>, ptr %x
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvqdotq.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvqdotq.ll
index e6ca6875e1412..87c32aa8348b2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvqdotq.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvqdotq.ll
@@ -11,7 +11,7 @@ define i32 @vqdot_vv(<16 x i8> %a, <16 x i8> %b) {
; NODOT-NEXT: vsext.vf2 v12, v8
; NODOT-NEXT: vsext.vf2 v14, v9
; NODOT-NEXT: vwmul.vv v8, v12, v14
-; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; NODOT-NEXT: vmv.s.x v12, zero
; NODOT-NEXT: vredsum.vs v8, v8, v12
; NODOT-NEXT: vmv.x.s a0, v8
@@ -41,7 +41,7 @@ define i32 @vqdot_vx_constant(<16 x i8> %a) {
; CHECK-NEXT: vsext.vf2 v12, v8
; CHECK-NEXT: li a0, 23
; CHECK-NEXT: vwmul.vx v8, v12, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vmv.s.x v12, zero
; CHECK-NEXT: vredsum.vs v8, v8, v12
; CHECK-NEXT: vmv.x.s a0, v8
@@ -60,7 +60,7 @@ define i32 @vqdot_vx_constant_swapped(<16 x i8> %a) {
; CHECK-NEXT: vsext.vf2 v12, v8
; CHECK-NEXT: li a0, 23
; CHECK-NEXT: vwmul.vx v8, v12, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vmv.s.x v12, zero
; CHECK-NEXT: vredsum.vs v8, v8, v12
; CHECK-NEXT: vmv.x.s a0, v8
@@ -77,11 +77,11 @@ define i32 @vqdotu_vv(<16 x i8> %a, <16 x i8> %b) {
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; NODOT-NEXT: vwmulu.vv v10, v8, v9
-; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; NODOT-NEXT: vmv.s.x v8, zero
-; NODOT-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vwredsumu.vs v8, v10, v8
-; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
@@ -109,7 +109,7 @@ define i32 @vqdotu_vx_constant(<16 x i8> %a) {
; CHECK-NEXT: vzext.vf2 v12, v8
; CHECK-NEXT: li a0, 123
; CHECK-NEXT: vwmulu.vx v8, v12, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vmv.s.x v12, zero
; CHECK-NEXT: vredsum.vs v8, v8, v12
; CHECK-NEXT: vmv.x.s a0, v8
@@ -128,7 +128,7 @@ define i32 @vqdotsu_vv(<16 x i8> %a, <16 x i8> %b) {
; NODOT-NEXT: vsext.vf2 v12, v8
; NODOT-NEXT: vzext.vf2 v14, v9
; NODOT-NEXT: vwmulsu.vv v8, v12, v14
-; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; NODOT-NEXT: vmv.s.x v12, zero
; NODOT-NEXT: vredsum.vs v8, v8, v12
; NODOT-NEXT: vmv.x.s a0, v8
@@ -158,7 +158,7 @@ define i32 @vqdotsu_vv_swapped(<16 x i8> %a, <16 x i8> %b) {
; NODOT-NEXT: vsext.vf2 v12, v8
; NODOT-NEXT: vzext.vf2 v14, v9
; NODOT-NEXT: vwmulsu.vv v8, v12, v14
-; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; NODOT-NEXT: vmv.s.x v12, zero
; NODOT-NEXT: vredsum.vs v8, v8, v12
; NODOT-NEXT: vmv.x.s a0, v8
@@ -188,7 +188,7 @@ define i32 @vdotqsu_vx_constant(<16 x i8> %a) {
; CHECK-NEXT: vsext.vf2 v12, v8
; CHECK-NEXT: li a0, 123
; CHECK-NEXT: vwmul.vx v8, v12, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vmv.s.x v12, zero
; CHECK-NEXT: vredsum.vs v8, v8, v12
; CHECK-NEXT: vmv.x.s a0, v8
@@ -208,7 +208,7 @@ define i32 @vdotqus_vx_constant(<16 x i8> %a) {
; CHECK-NEXT: li a0, -23
; CHECK-NEXT: vmv.v.x v14, a0
; CHECK-NEXT: vwmulsu.vv v8, v14, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vmv.s.x v12, zero
; CHECK-NEXT: vredsum.vs v8, v8, v12
; CHECK-NEXT: vmv.x.s a0, v8
@@ -281,7 +281,7 @@ define i32 @vqdot_vv_accum(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
; NODOT-NEXT: vsext.vf2 v10, v8
; NODOT-NEXT: vsext.vf2 v16, v9
; NODOT-NEXT: vwmacc.vv v12, v10, v16
-; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; NODOT-NEXT: vmv.s.x v8, zero
; NODOT-NEXT: vredsum.vs v8, v12, v8
; NODOT-NEXT: vmv.x.s a0, v8
@@ -313,9 +313,9 @@ define i32 @vqdotu_vv_accum(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; NODOT-NEXT: vwmulu.vv v10, v8, v9
-; NODOT-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vwaddu.wv v12, v12, v10
-; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; NODOT-NEXT: vmv.s.x v8, zero
; NODOT-NEXT: vredsum.vs v8, v12, v8
; NODOT-NEXT: vmv.x.s a0, v8
@@ -349,7 +349,7 @@ define i32 @vqdotsu_vv_accum(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
; NODOT-NEXT: vsext.vf2 v10, v8
; NODOT-NEXT: vzext.vf2 v16, v9
; NODOT-NEXT: vwmaccsu.vv v12, v10, v16
-; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; NODOT-NEXT: vmv.s.x v8, zero
; NODOT-NEXT: vredsum.vs v8, v12, v8
; NODOT-NEXT: vmv.x.s a0, v8
@@ -383,7 +383,7 @@ define i32 @vqdot_vv_scalar_add(<16 x i8> %a, <16 x i8> %b, i32 %x) {
; NODOT-NEXT: vsext.vf2 v12, v8
; NODOT-NEXT: vsext.vf2 v14, v9
; NODOT-NEXT: vwmul.vv v8, v12, v14
-; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; NODOT-NEXT: vmv.s.x v12, a0
; NODOT-NEXT: vredsum.vs v8, v8, v12
; NODOT-NEXT: vmv.x.s a0, v8
@@ -412,11 +412,11 @@ define i32 @vqdotu_vv_scalar_add(<16 x i8> %a, <16 x i8> %b, i32 %x) {
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; NODOT-NEXT: vwmulu.vv v10, v8, v9
-; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; NODOT-NEXT: vmv.s.x v8, a0
-; NODOT-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vwredsumu.vs v8, v10, v8
-; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
@@ -445,7 +445,7 @@ define i32 @vqdotsu_vv_scalar_add(<16 x i8> %a, <16 x i8> %b, i32 %x) {
; NODOT-NEXT: vsext.vf2 v12, v8
; NODOT-NEXT: vzext.vf2 v14, v9
; NODOT-NEXT: vwmulsu.vv v8, v12, v14
-; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; NODOT-NEXT: vmv.s.x v12, a0
; NODOT-NEXT: vredsum.vs v8, v8, v12
; NODOT-NEXT: vmv.x.s a0, v8
@@ -479,7 +479,7 @@ define i32 @vqdot_vv_split(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %
; NODOT-NEXT: vsext.vf2 v18, v11
; NODOT-NEXT: vwmul.vv v8, v12, v14
; NODOT-NEXT: vwmacc.vv v8, v16, v18
-; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; NODOT-NEXT: vmv.s.x v12, zero
; NODOT-NEXT: vredsum.vs v8, v8, v12
; NODOT-NEXT: vmv.x.s a0, v8
@@ -514,7 +514,7 @@ define <1 x i32> @vqdot_vv_partial_reduce_v1i32_v4i8(<4 x i8> %a, <4 x i8> %b) {
; NODOT-NEXT: vsext.vf2 v10, v8
; NODOT-NEXT: vsext.vf2 v8, v9
; NODOT-NEXT: vwmul.vv v9, v10, v8
-; NODOT-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; NODOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; NODOT-NEXT: vslidedown.vi v8, v9, 3
; NODOT-NEXT: vslidedown.vi v10, v9, 2
; NODOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
@@ -546,7 +546,7 @@ define <1 x i32> @vqdotu_vv_partial_reduce_v1i32_v4i8(<4 x i8> %a, <4 x i8> %b)
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; NODOT-NEXT: vwmulu.vv v10, v8, v9
-; NODOT-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; NODOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; NODOT-NEXT: vzext.vf2 v8, v10
; NODOT-NEXT: vslidedown.vi v9, v8, 3
; NODOT-NEXT: vslidedown.vi v10, v8, 2
@@ -652,7 +652,7 @@ define <1 x i32> @vqdotsu_vv_partial_reduce_v1i32_v4i8(<4 x i8> %a, <4 x i8> %b)
; NODOT-NEXT: vsext.vf2 v10, v8
; NODOT-NEXT: vzext.vf2 v8, v9
; NODOT-NEXT: vwmulsu.vv v9, v10, v8
-; NODOT-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; NODOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; NODOT-NEXT: vslidedown.vi v8, v9, 3
; NODOT-NEXT: vslidedown.vi v10, v9, 2
; NODOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
@@ -686,7 +686,7 @@ define <1 x i32> @vqdotsu_vv_partial_reduce_swapped(<4 x i8> %a, <4 x i8> %b) {
; NODOT-NEXT: vsext.vf2 v10, v8
; NODOT-NEXT: vzext.vf2 v8, v9
; NODOT-NEXT: vwmulsu.vv v9, v10, v8
-; NODOT-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; NODOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; NODOT-NEXT: vslidedown.vi v8, v9, 3
; NODOT-NEXT: vslidedown.vi v10, v9, 2
; NODOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
@@ -1381,10 +1381,10 @@ define <4 x i31> @vqdotsu_vv_partial_v4i31_v16i7(<16 x i7> %a, <16 x i7> %b) {
; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; NODOT-NEXT: vzext.vf4 v12, v8
; NODOT-NEXT: li a0, 127
-; NODOT-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; NODOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; NODOT-NEXT: vand.vx v16, v9, a0
; NODOT-NEXT: lui a0, 524288
-; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; NODOT-NEXT: vsll.vi v8, v12, 25
; NODOT-NEXT: addi a0, a0, -1
; NODOT-NEXT: vsra.vi v8, v8, 25
@@ -1432,9 +1432,8 @@ define <1 x i32> @vqdotsu_vv_partial_v1i32_v2i8(<2 x i8> %a, <2 x i8> %b) {
; CHECK-NEXT: vsext.vf2 v10, v8
; CHECK-NEXT: vzext.vf2 v8, v9
; CHECK-NEXT: vwmulsu.vv v9, v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vi v8, v9, 1
; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
entry:
@@ -1455,7 +1454,7 @@ define <1 x i32> @vqdotsu_vv_partial_v1i32_v8i8(<8 x i8> %a, <8 x i8> %b) {
; CHECK-NEXT: vsext.vf2 v10, v8
; CHECK-NEXT: vzext.vf2 v11, v9
; CHECK-NEXT: vwmulsu.vv v8, v10, v11
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 6
; CHECK-NEXT: vslidedown.vi v12, v8, 5
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
@@ -1560,7 +1559,7 @@ define i32 @vqdot_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x
; NODOT-NEXT: vsext.vf2 v16, v8
; NODOT-NEXT: vsext.vf2 v18, v9
; NODOT-NEXT: vwmul.vv v8, v16, v18
-; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; NODOT-NEXT: vor.vv v8, v8, v12
; NODOT-NEXT: vmv.s.x v12, zero
; NODOT-NEXT: vredsum.vs v8, v8, v12
@@ -1595,7 +1594,7 @@ define i32 @vqdot_vv_accum_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
; CHECK-NEXT: vsext.vf2 v16, v8
; CHECK-NEXT: vsext.vf2 v18, v9
; CHECK-NEXT: vwmul.vv v8, v16, v18
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vor.vv v8, v8, v12
; CHECK-NEXT: vmv.s.x v12, zero
; CHECK-NEXT: vredsum.vs v8, v8, v12
@@ -1615,9 +1614,9 @@ define i32 @vqdotu_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; NODOT-NEXT: vwmulu.vv v10, v8, v9
-; NODOT-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vwaddu.wv v12, v12, v10
-; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; NODOT-NEXT: vmv.s.x v8, zero
; NODOT-NEXT: vredsum.vs v8, v12, v8
; NODOT-NEXT: vmv.x.s a0, v8
@@ -1651,7 +1650,7 @@ define i32 @vqdotsu_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32>
; NODOT-NEXT: vsext.vf2 v16, v8
; NODOT-NEXT: vzext.vf2 v18, v9
; NODOT-NEXT: vwmulsu.vv v8, v16, v18
-; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; NODOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; NODOT-NEXT: vor.vv v8, v8, v12
; NODOT-NEXT: vmv.s.x v12, zero
; NODOT-NEXT: vredsum.vs v8, v8, v12
diff --git a/llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll b/llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
index 143545ccfd4f6..ce22e7d40594b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
@@ -408,7 +408,7 @@ define i64 @two_reduce_scalar_bypass_zext(<4 x i64> %v, <4 x i32> %v2) {
; CHECK-NEXT: vmv.x.s a0, v10
; CHECK-NEXT: slli a0, a0, 32
; CHECK-NEXT: srli a0, a0, 32
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vredsum.vs v8, v8, v10
; CHECK-NEXT: vmv.x.s a0, v8
@@ -428,7 +428,7 @@ define i64 @two_reduce_scalar_bypass_sext(<4 x i64> %v, <4 x i32> %v2) {
; CHECK-NEXT: vmv.s.x v11, zero
; CHECK-NEXT: vredsum.vs v10, v10, v11
; CHECK-NEXT: vmv.x.s a0, v10
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vredsum.vs v8, v8, v10
; CHECK-NEXT: vmv.x.s a0, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll b/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
index f597762521006..326352c1ed3fa 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
@@ -39,7 +39,7 @@ define <2 x i32> @stest_f64i32(<2 x double> %x) {
; CHECK-V: # %bb.0: # %entry
; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-V-NEXT: vfcvt.rtz.x.f.v v8, v8
-; CHECK-V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-V-NEXT: vnclip.wi v8, v8, 0
; CHECK-V-NEXT: ret
entry:
@@ -75,7 +75,7 @@ define <2 x i32> @utest_f64i32(<2 x double> %x) {
; CHECK-V: # %bb.0: # %entry
; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-V-NEXT: vfcvt.rtz.xu.f.v v8, v8
-; CHECK-V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-V-NEXT: vnclipu.wi v8, v8, 0
; CHECK-V-NEXT: ret
entry:
@@ -114,7 +114,7 @@ define <2 x i32> @ustest_f64i32(<2 x double> %x) {
; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-V-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-V-NEXT: vmax.vx v8, v8, zero
-; CHECK-V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-V-NEXT: vnclipu.wi v8, v8, 0
; CHECK-V-NEXT: ret
entry:
@@ -304,9 +304,9 @@ define <4 x i32> @ustest_f32i32(<4 x float> %x) {
; CHECK-V: # %bb.0: # %entry
; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-V-NEXT: vfwcvt.rtz.x.f.v v10, v8
-; CHECK-V-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-V-NEXT: vmax.vx v10, v10, zero
-; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-V-NEXT: vnclipu.wi v8, v10, 0
; CHECK-V-NEXT: ret
entry:
@@ -491,7 +491,7 @@ define <4 x i32> @stest_f16i32(<4 x half> %x) {
; CHECK-V-NEXT: vl2r.v v8, (a0) # vscale x 16-byte Folded Reload
; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-V-NEXT: vslideup.vi v10, v8, 2
-; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-V-NEXT: vnclip.wi v8, v10, 0
; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a1, a0, 1
@@ -671,7 +671,7 @@ define <4 x i32> @utest_f16i32(<4 x half> %x) {
; CHECK-V-NEXT: vl2r.v v8, (a0) # vscale x 16-byte Folded Reload
; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-V-NEXT: vslideup.vi v10, v8, 2
-; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-V-NEXT: vnclipu.wi v8, v10, 0
; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a1, a0, 1
@@ -862,7 +862,7 @@ define <4 x i32> @ustest_f16i32(<4 x half> %x) {
; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-V-NEXT: vslideup.vi v8, v10, 2
; CHECK-V-NEXT: vmax.vx v10, v8, zero
-; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-V-NEXT: vnclipu.wi v8, v10, 0
; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a1, a0, 1
@@ -927,7 +927,7 @@ define <2 x i16> @stest_f64i16(<2 x double> %x) {
; CHECK-V: # %bb.0: # %entry
; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-V-NEXT: vfncvt.rtz.x.f.w v9, v8
-; CHECK-V-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-V-NEXT: vnclip.wi v8, v9, 0
; CHECK-V-NEXT: ret
entry:
@@ -963,7 +963,7 @@ define <2 x i16> @utest_f64i16(<2 x double> %x) {
; CHECK-V: # %bb.0: # %entry
; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-V-NEXT: vfncvt.rtz.xu.f.w v9, v8
-; CHECK-V-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-V-NEXT: vnclipu.wi v8, v9, 0
; CHECK-V-NEXT: ret
entry:
@@ -1002,7 +1002,7 @@ define <2 x i16> @ustest_f64i16(<2 x double> %x) {
; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-V-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-V-NEXT: vmax.vx v8, v9, zero
-; CHECK-V-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-V-NEXT: vnclipu.wi v8, v8, 0
; CHECK-V-NEXT: ret
entry:
@@ -1078,7 +1078,7 @@ define <4 x i16> @stest_f32i16(<4 x float> %x) {
; CHECK-V: # %bb.0: # %entry
; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-V-NEXT: vfcvt.rtz.x.f.v v8, v8
-; CHECK-V-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-V-NEXT: vnclip.wi v8, v8, 0
; CHECK-V-NEXT: ret
entry:
@@ -1132,7 +1132,7 @@ define <4 x i16> @utest_f32i16(<4 x float> %x) {
; CHECK-V: # %bb.0: # %entry
; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-V-NEXT: vfcvt.rtz.xu.f.v v8, v8
-; CHECK-V-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-V-NEXT: vnclipu.wi v8, v8, 0
; CHECK-V-NEXT: ret
entry:
@@ -1197,7 +1197,7 @@ define <4 x i16> @ustest_f32i16(<4 x float> %x) {
; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-V-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-V-NEXT: vmax.vx v8, v8, zero
-; CHECK-V-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-V-NEXT: vnclipu.wi v8, v8, 0
; CHECK-V-NEXT: ret
entry:
@@ -1559,7 +1559,7 @@ define <8 x i16> @stest_f16i16(<8 x half> %x) {
; CHECK-V-NEXT: vl2r.v v8, (a0) # vscale x 16-byte Folded Reload
; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-V-NEXT: vslideup.vi v10, v8, 4
-; CHECK-V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-V-NEXT: vnclip.wi v8, v10, 0
; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 2
@@ -1901,7 +1901,7 @@ define <8 x i16> @utest_f16i16(<8 x half> %x) {
; CHECK-V-NEXT: vl2r.v v8, (a0) # vscale x 16-byte Folded Reload
; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-V-NEXT: vslideup.vi v10, v8, 4
-; CHECK-V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-V-NEXT: vnclipu.wi v8, v10, 0
; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 2
@@ -2266,7 +2266,7 @@ define <8 x i16> @ustest_f16i16(<8 x half> %x) {
; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-V-NEXT: vslideup.vi v8, v10, 4
; CHECK-V-NEXT: vmax.vx v10, v8, zero
-; CHECK-V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-V-NEXT: vnclipu.wi v8, v10, 0
; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 2
@@ -3606,7 +3606,7 @@ define <2 x i32> @stest_f64i32_mm(<2 x double> %x) {
; CHECK-V: # %bb.0: # %entry
; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-V-NEXT: vfcvt.rtz.x.f.v v8, v8
-; CHECK-V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-V-NEXT: vnclip.wi v8, v8, 0
; CHECK-V-NEXT: ret
entry:
@@ -3640,7 +3640,7 @@ define <2 x i32> @utest_f64i32_mm(<2 x double> %x) {
; CHECK-V: # %bb.0: # %entry
; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-V-NEXT: vfcvt.rtz.xu.f.v v8, v8
-; CHECK-V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-V-NEXT: vnclipu.wi v8, v8, 0
; CHECK-V-NEXT: ret
entry:
@@ -3678,7 +3678,7 @@ define <2 x i32> @ustest_f64i32_mm(<2 x double> %x) {
; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-V-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-V-NEXT: vmax.vx v8, v8, zero
-; CHECK-V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-V-NEXT: vnclipu.wi v8, v8, 0
; CHECK-V-NEXT: ret
entry:
@@ -3863,9 +3863,9 @@ define <4 x i32> @ustest_f32i32_mm(<4 x float> %x) {
; CHECK-V: # %bb.0: # %entry
; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-V-NEXT: vfwcvt.rtz.x.f.v v10, v8
-; CHECK-V-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-V-NEXT: vmax.vx v10, v10, zero
-; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-V-NEXT: vnclipu.wi v8, v10, 0
; CHECK-V-NEXT: ret
entry:
@@ -4048,7 +4048,7 @@ define <4 x i32> @stest_f16i32_mm(<4 x half> %x) {
; CHECK-V-NEXT: vl2r.v v8, (a0) # vscale x 16-byte Folded Reload
; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-V-NEXT: vslideup.vi v10, v8, 2
-; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-V-NEXT: vnclip.wi v8, v10, 0
; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a1, a0, 1
@@ -4226,7 +4226,7 @@ define <4 x i32> @utest_f16i32_mm(<4 x half> %x) {
; CHECK-V-NEXT: vl2r.v v8, (a0) # vscale x 16-byte Folded Reload
; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-V-NEXT: vslideup.vi v10, v8, 2
-; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-V-NEXT: vnclipu.wi v8, v10, 0
; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a1, a0, 1
@@ -4416,7 +4416,7 @@ define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) {
; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-V-NEXT: vslideup.vi v8, v10, 2
; CHECK-V-NEXT: vmax.vx v10, v8, zero
-; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-V-NEXT: vnclipu.wi v8, v10, 0
; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a1, a0, 1
@@ -4479,7 +4479,7 @@ define <2 x i16> @stest_f64i16_mm(<2 x double> %x) {
; CHECK-V: # %bb.0: # %entry
; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-V-NEXT: vfncvt.rtz.x.f.w v9, v8
-; CHECK-V-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-V-NEXT: vnclip.wi v8, v9, 0
; CHECK-V-NEXT: ret
entry:
@@ -4513,7 +4513,7 @@ define <2 x i16> @utest_f64i16_mm(<2 x double> %x) {
; CHECK-V: # %bb.0: # %entry
; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-V-NEXT: vfncvt.rtz.xu.f.w v9, v8
-; CHECK-V-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-V-NEXT: vnclipu.wi v8, v9, 0
; CHECK-V-NEXT: ret
entry:
@@ -4551,7 +4551,7 @@ define <2 x i16> @ustest_f64i16_mm(<2 x double> %x) {
; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-V-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-V-NEXT: vmax.vx v8, v9, zero
-; CHECK-V-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-V-NEXT: vnclipu.wi v8, v8, 0
; CHECK-V-NEXT: ret
entry:
@@ -4625,7 +4625,7 @@ define <4 x i16> @stest_f32i16_mm(<4 x float> %x) {
; CHECK-V: # %bb.0: # %entry
; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-V-NEXT: vfcvt.rtz.x.f.v v8, v8
-; CHECK-V-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-V-NEXT: vnclip.wi v8, v8, 0
; CHECK-V-NEXT: ret
entry:
@@ -4677,7 +4677,7 @@ define <4 x i16> @utest_f32i16_mm(<4 x float> %x) {
; CHECK-V: # %bb.0: # %entry
; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-V-NEXT: vfcvt.rtz.xu.f.v v8, v8
-; CHECK-V-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-V-NEXT: vnclipu.wi v8, v8, 0
; CHECK-V-NEXT: ret
entry:
@@ -4741,7 +4741,7 @@ define <4 x i16> @ustest_f32i16_mm(<4 x float> %x) {
; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-V-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-V-NEXT: vmax.vx v8, v8, zero
-; CHECK-V-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-V-NEXT: vnclipu.wi v8, v8, 0
; CHECK-V-NEXT: ret
entry:
@@ -5101,7 +5101,7 @@ define <8 x i16> @stest_f16i16_mm(<8 x half> %x) {
; CHECK-V-NEXT: vl2r.v v8, (a0) # vscale x 16-byte Folded Reload
; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-V-NEXT: vslideup.vi v10, v8, 4
-; CHECK-V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-V-NEXT: vnclip.wi v8, v10, 0
; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 2
@@ -5441,7 +5441,7 @@ define <8 x i16> @utest_f16i16_mm(<8 x half> %x) {
; CHECK-V-NEXT: vl2r.v v8, (a0) # vscale x 16-byte Folded Reload
; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-V-NEXT: vslideup.vi v10, v8, 4
-; CHECK-V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-V-NEXT: vnclipu.wi v8, v10, 0
; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 2
@@ -5805,7 +5805,7 @@ define <8 x i16> @ustest_f16i16_mm(<8 x half> %x) {
; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-V-NEXT: vslideup.vi v8, v10, 4
; CHECK-V-NEXT: vmax.vx v10, v8, zero
-; CHECK-V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-V-NEXT: vnclipu.wi v8, v10, 0
; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 2
diff --git a/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
index 65ac424c2359a..e6478761953ee 100644
--- a/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
@@ -2415,7 +2415,7 @@ define <4 x i32> @scalar_prefix_with_splat(ptr %base, i32 %index, <4 x i32> %vec
; RV64-NEXT: li a2, 1024
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64-NEXT: vmv.v.x v10, a0
-; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vmv.v.x v9, a2
; RV64-NEXT: vwmaccsu.vx v10, a1, v9
; RV64-NEXT: li a0, 4
@@ -2471,7 +2471,7 @@ define <4 x i32> @reassociate(ptr %base, i32 %index, <4 x i32> %vecidx) {
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: li a0, 1024
-; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vwmaccus.vx v10, a0, v8
; RV64-NEXT: vmv.v.i v8, 4
; RV64-NEXT: vwmaccsu.vx v10, a1, v8
@@ -2499,7 +2499,7 @@ define <4 x i32> @reassociate_with_splat(ptr %base, i32 %index, <4 x i32> %vecid
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: li a0, 1024
-; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vwmaccus.vx v10, a0, v8
; RV64-NEXT: vmv.v.i v8, 4
; RV64-NEXT: vwmaccsu.vx v10, a1, v8
@@ -2554,7 +2554,7 @@ define <4 x i32> @diagonal(ptr %base, <4 x i64> %vecidx) {
; RV64-NEXT: vadd.vx v10, v10, a0
; RV64-NEXT: vsll.vi v8, v8, 2
; RV64-NEXT: vadd.vv v10, v10, v8
-; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vluxei64.v v8, (zero), v10
; RV64-NEXT: ret
%gep = getelementptr inbounds nuw [256 x [256 x float]], ptr %base, i64 0, <4 x i64> %vecidx, <4 x i64> %vecidx
@@ -2581,7 +2581,7 @@ define <4 x i32> @diagonal_i32(ptr %base, <4 x i32> %vecidx) {
; RV64-NEXT: vadd.vx v8, v8, a0
; RV64-NEXT: vsll.vi v10, v10, 2
; RV64-NEXT: vadd.vv v10, v8, v10
-; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vluxei64.v v8, (zero), v10
; RV64-NEXT: ret
%gep = getelementptr inbounds nuw [256 x [256 x float]], ptr %base, i64 0, <4 x i32> %vecidx, <4 x i32> %vecidx
diff --git a/llvm/test/CodeGen/RISCV/rvv/pr141907.ll b/llvm/test/CodeGen/RISCV/rvv/pr141907.ll
index 1f485ea348396..8019a0a61af72 100644
--- a/llvm/test/CodeGen/RISCV/rvv/pr141907.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/pr141907.ll
@@ -12,7 +12,7 @@ define void @pr141907(ptr %0) nounwind {
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: li a1, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 0, e16, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: addi a3, sp, 20
diff --git a/llvm/test/CodeGen/RISCV/rvv/pr165232.ll b/llvm/test/CodeGen/RISCV/rvv/pr165232.ll
index bef53c6a5ae62..50c62c54358bb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/pr165232.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/pr165232.ll
@@ -125,7 +125,7 @@ define i1 @main(ptr %var_117, ptr %arrayinit.element3045, ptr %arrayinit.element
; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.i v19, 0
; CHECK-NEXT: vmclr.m v10
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 0, e64, m2, ta, ma
; CHECK-NEXT: vmv.v.i v6, 0
; CHECK-NEXT: .LBB0_1: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -143,7 +143,7 @@ define i1 @main(ptr %var_117, ptr %arrayinit.element3045, ptr %arrayinit.element
; CHECK-NEXT: vmv2r.v v8, v6
; CHECK-NEXT: vmv1r.v v18, v19
; CHECK-NEXT: vmv1r.v v21, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma
+; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, ma
; CHECK-NEXT: vle32.v v20, (t4)
; CHECK-NEXT: vle32.v v3, (t1)
; CHECK-NEXT: vle32.v v30, (a7)
@@ -152,10 +152,10 @@ define i1 @main(ptr %var_117, ptr %arrayinit.element3045, ptr %arrayinit.element
; CHECK-NEXT: vle32.v v2, (t3)
; CHECK-NEXT: vle32.v v31, (a6)
; CHECK-NEXT: vmv1r.v v24, v30
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
+; CHECK-NEXT: vsetivli zero, 0, e64, m2, ta, mu
; CHECK-NEXT: vmflt.vv v21, v8, v6, v0.t
; CHECK-NEXT: vmv1r.v v8, v19
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, mu
+; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
; CHECK-NEXT: vle32.v v18, (a2)
; CHECK-NEXT: vle32.v v8, (a3)
; CHECK-NEXT: vle32.v v4, (a5)
@@ -194,7 +194,7 @@ define i1 @main(ptr %var_117, ptr %arrayinit.element3045, ptr %arrayinit.element
; CHECK-NEXT: vl4r.v v24, (t5) # vscale x 32-byte Folded Reload
; CHECK-NEXT: vsetivli zero, 0, e64, m2, ta, ma
; CHECK-NEXT: vsseg4e64.v v20, (zero), v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, ma
; CHECK-NEXT: vsseg8e32.v v8, (a0)
; CHECK-NEXT: csrr t5, vlenb
; CHECK-NEXT: slli t5, t5, 4
@@ -205,7 +205,7 @@ define i1 @main(ptr %var_117, ptr %arrayinit.element3045, ptr %arrayinit.element
; CHECK-NEXT: slli t6, t6, 2
; CHECK-NEXT: add t5, t5, t6
; CHECK-NEXT: vl4r.v v24, (t5) # vscale x 32-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 0, e64, m2, ta, ma
; CHECK-NEXT: vsseg4e64.v v20, (zero)
; CHECK-NEXT: j .LBB0_1
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/pr63459.ll b/llvm/test/CodeGen/RISCV/rvv/pr63459.ll
index 08a2e588330b5..3a7591efb2867 100644
--- a/llvm/test/CodeGen/RISCV/rvv/pr63459.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/pr63459.ll
@@ -7,7 +7,7 @@ define void @snork(ptr %arg, <vscale x 2 x i64> %arg1) {
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vmul.vx v8, v8, a1
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.i v10, 1
; CHECK-NEXT: vsoxei64.v v10, (a0), v8
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/regcoal-liveinterval-pruning-crash.ll b/llvm/test/CodeGen/RISCV/rvv/regcoal-liveinterval-pruning-crash.ll
index c19e93d1f6c21..cbaabd9702f30 100644
--- a/llvm/test/CodeGen/RISCV/rvv/regcoal-liveinterval-pruning-crash.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/regcoal-liveinterval-pruning-crash.ll
@@ -8,7 +8,7 @@ define i32 @pr134424(i64 %input_value, i32 %base_value, i1 %cond_flag1, i1 %cond
; CHECK-NEXT: andi a5, a2, 1
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vmv.v.x v8, a0
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, ma
; CHECK-NEXT: vmv.s.x v8, zero
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v0, 14
@@ -32,7 +32,7 @@ define i32 @pr134424(i64 %input_value, i32 %base_value, i1 %cond_flag1, i1 %cond
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: .LBB0_6: # %for.body.us.preheader.i
; CHECK-NEXT: sext.w a0, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
index 364831f530747..4d30f260937f5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
@@ -896,13 +896,13 @@ define void @test_dag_loop() {
; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, m4, tu, mu
+; CHECK-NEXT: vsetivli zero, 0, e8, m4, tu, mu
; CHECK-NEXT: vssubu.vx v12, v8, zero, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, ma
+; CHECK-NEXT: vsetivli zero, 0, e8, m4, ta, ma
; CHECK-NEXT: vmseq.vv v0, v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma
+; CHECK-NEXT: vsetivli zero, 0, e16, m8, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, m8, tu, mu
+; CHECK-NEXT: vsetivli zero, 0, e16, m8, tu, mu
; CHECK-NEXT: vle16.v v8, (zero), v0.t
; CHECK-NEXT: vse16.v v8, (zero)
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-vmerge-to-vmv.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-vmerge-to-vmv.ll
index 9ffc84a8a0e4a..840346e61b8ae 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rvv-vmerge-to-vmv.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-vmerge-to-vmv.ll
@@ -92,7 +92,7 @@ define <vscale x 2 x i32> @preserve_false_avl_known_le(ptr %p, <vscale x 2 x i32
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v9, (a0), v0.t
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma
+; CHECK-NEXT: vsetivli zero, 1, e32, m1, tu, ma
; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
%true = call <vscale x 2 x i32> @llvm.riscv.vle.mask(<vscale x 2 x i32> %false, ptr %p, <vscale x 2 x i1> %mask, i64 2, i64 3)
diff --git a/llvm/test/CodeGen/RISCV/rvv/trunc-select-to-max-usat.ll b/llvm/test/CodeGen/RISCV/rvv/trunc-select-to-max-usat.ll
index d2f73826e4e9e..e4d0774ec28af 100644
--- a/llvm/test/CodeGen/RISCV/rvv/trunc-select-to-max-usat.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/trunc-select-to-max-usat.ll
@@ -7,7 +7,7 @@ define <4 x i8> @test_v4i16_v4i8(<4 x i16> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vmax.vx v8, v8, zero
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v8, 0
; CHECK-NEXT: ret
%a = icmp sgt <4 x i16> %x, zeroinitializer
@@ -23,9 +23,9 @@ define <4 x i8> @test_v4i32_v4i8(<4 x i32> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmax.vx v8, v8, zero
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v8, 0
; CHECK-NEXT: ret
%a = icmp sgt <4 x i32> %x, zeroinitializer
@@ -41,11 +41,11 @@ define <4 x i8> @test_v4i64_v4i8(<4 x i64> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vmax.vx v8, v8, zero
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vnclipu.wi v10, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v10, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v8, 0
; CHECK-NEXT: ret
%a = icmp sgt <4 x i64> %x, zeroinitializer
@@ -61,7 +61,7 @@ define <4 x i16> @test_v4i32_v4i16(<4 x i32> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmax.vx v8, v8, zero
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v8, 0
; CHECK-NEXT: ret
%a = icmp sgt <4 x i32> %x, zeroinitializer
@@ -77,9 +77,9 @@ define <4 x i16> @test_v4i64_v4i16(<4 x i64> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vmax.vx v8, v8, zero
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vnclipu.wi v10, v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v10, 0
; CHECK-NEXT: ret
%a = icmp sgt <4 x i64> %x, zeroinitializer
@@ -95,7 +95,7 @@ define <4 x i32> @test_v4i64_v4i32(<4 x i64> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vmax.vx v10, v8, zero
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vnclipu.wi v8, v10, 0
; CHECK-NEXT: ret
%a = icmp sgt <4 x i64> %x, zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
index 5c04a09c9953b..817812ff0db66 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
@@ -153,11 +153,11 @@ define {<8 x i64>, <8 x i64>} @vector_deinterleave_v8i64_v16i64(<16 x i64> %vec)
; V-NEXT: vadd.vv v13, v16, v16
; V-NEXT: vmv.s.x v20, a0
; V-NEXT: vadd.vi v21, v13, -8
-; V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; V-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; V-NEXT: vcompress.vm v16, v8, v12
-; V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; V-NEXT: vadd.vi v22, v13, -7
-; V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; V-NEXT: vcompress.vm v12, v8, v20
; V-NEXT: vrgatherei16.vv v16, v24, v21, v0.t
; V-NEXT: vrgatherei16.vv v12, v24, v22, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll b/llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll
index 1df4076aa2069..9ca66fbff4fdf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll
@@ -11,7 +11,7 @@ define i8 @extract_last_i8(<16 x i8> %data, <16 x i8> %mask, i8 %passthru) {
; CHECK-NEXT: beqz a1, .LBB0_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; CHECK-NEXT: vid.v v9, v0.t
; CHECK-NEXT: vredmaxu.vs v9, v9, v9
; CHECK-NEXT: vmv.x.s a0, v9
@@ -33,13 +33,13 @@ define i16 @extract_last_i16(<8 x i16> %data, <8 x i16> %mask, i16 %passthru) {
; CHECK-NEXT: vcpop.m a1, v0
; CHECK-NEXT: beqz a1, .LBB1_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vid.v v9, v0.t
; CHECK-NEXT: vredmaxu.vs v9, v9, v9
; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: zext.b a0, a0
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: .LBB1_2:
@@ -57,13 +57,13 @@ define i32 @extract_last_i32(<4 x i32> %data, <4 x i32> %mask, i32 %passthru) {
; CHECK-NEXT: vcpop.m a1, v0
; CHECK-NEXT: beqz a1, .LBB2_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vid.v v9, v0.t
; CHECK-NEXT: vredmaxu.vs v9, v9, v9
; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: zext.b a0, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: .LBB2_2:
@@ -81,17 +81,16 @@ define i64 @extract_last_i64(<2 x i64> %data, <2 x i64> %mask, i64 %passthru) {
; RV32-NEXT: vcpop.m a2, v0
; RV32-NEXT: beqz a2, .LBB3_2
; RV32-NEXT: # %bb.1:
-; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
+; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: li a1, 32
; RV32-NEXT: vid.v v9, v0.t
; RV32-NEXT: vredmaxu.vs v9, v9, v9
; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: zext.b a0, a0
-; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vslidedown.vx v8, v8, a0
; RV32-NEXT: vmv.x.s a0, v8
-; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: .LBB3_2:
@@ -104,13 +103,13 @@ define i64 @extract_last_i64(<2 x i64> %data, <2 x i64> %mask, i64 %passthru) {
; RV64-NEXT: vcpop.m a1, v0
; RV64-NEXT: beqz a1, .LBB3_2
; RV64-NEXT: # %bb.1:
-; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
+; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV64-NEXT: vmv.v.i v9, 0
; RV64-NEXT: vid.v v9, v0.t
; RV64-NEXT: vredmaxu.vs v9, v9, v9
; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: zext.b a0, a0
-; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vslidedown.vx v8, v8, a0
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: .LBB3_2:
@@ -128,13 +127,13 @@ define float @extract_last_float(<4 x float> %data, <4 x i32> %mask, float %pass
; CHECK-NEXT: vcpop.m a0, v0
; CHECK-NEXT: beqz a0, .LBB4_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vid.v v9, v0.t
; CHECK-NEXT: vredmaxu.vs v9, v9, v9
; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: zext.b a0, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: .LBB4_2:
@@ -152,13 +151,13 @@ define double @extract_last_double(<2 x double> %data, <2 x i64> %mask, double %
; CHECK-NEXT: vcpop.m a0, v0
; CHECK-NEXT: beqz a0, .LBB5_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vid.v v9, v0.t
; CHECK-NEXT: vredmaxu.vs v9, v9, v9
; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: zext.b a0, a0
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: .LBB5_2:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
index 38d38f78c6054..284e4e6d212a9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
@@ -134,9 +134,9 @@ define <4 x i64> @vector_interleave_v4i64_v2i64(<2 x i64> %a, <2 x i64> %b) {
; CHECK-NEXT: addi a0, a0, 512
; CHECK-NEXT: vslideup.vi v8, v10, 2
; CHECK-NEXT: vmv.s.x v10, a0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vsext.vf2 v12, v10
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
@@ -149,9 +149,9 @@ define <4 x i64> @vector_interleave_v4i64_v2i64(<2 x i64> %a, <2 x i64> %b) {
; ZVBB-NEXT: addi a0, a0, 512
; ZVBB-NEXT: vslideup.vi v8, v10, 2
; ZVBB-NEXT: vmv.s.x v10, a0
-; ZVBB-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVBB-NEXT: vsext.vf2 v12, v10
-; ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; ZVBB-NEXT: vrgatherei16.vv v10, v8, v12
; ZVBB-NEXT: vmv.v.v v8, v10
; ZVBB-NEXT: ret
@@ -959,9 +959,9 @@ define <4 x double> @vector_interleave_v4f64_v2f64(<2 x double> %a, <2 x double>
; CHECK-NEXT: addi a0, a0, 512
; CHECK-NEXT: vslideup.vi v8, v10, 2
; CHECK-NEXT: vmv.s.x v10, a0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vsext.vf2 v12, v10
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
@@ -974,9 +974,9 @@ define <4 x double> @vector_interleave_v4f64_v2f64(<2 x double> %a, <2 x double>
; ZVBB-NEXT: addi a0, a0, 512
; ZVBB-NEXT: vslideup.vi v8, v10, 2
; ZVBB-NEXT: vmv.s.x v10, a0
-; ZVBB-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVBB-NEXT: vsext.vf2 v12, v10
-; ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; ZVBB-NEXT: vrgatherei16.vv v10, v8, v12
; ZVBB-NEXT: vmv.v.v v8, v10
; ZVBB-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt.ll b/llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
index 359601150cb98..58f67431252ac 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
@@ -339,7 +339,7 @@ define <vscale x 2 x i64> @dead_vsmul() {
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetivli zero, 0, e64, m2, tu, ma
; CHECK-NEXT: vmv.v.v v8, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, tu, ma
+; CHECK-NEXT: vsetivli zero, 0, e16, mf2, tu, ma
; CHECK-NEXT: vsmul.vx v10, v10, zero
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
index 05b76ec7733bb..137a36edef7b1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
@@ -850,9 +850,10 @@ for.end: ; preds = %for.body
define <vscale x 4 x i32> @cross_block_mutate(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b,
; CHECK-LABEL: cross_block_mutate:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetivli a0, 6, e32, m2, tu, ma
+; CHECK-NEXT: vsetivli a0, 6, e16, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, tu, ma
; CHECK-NEXT: vmv.s.x v8, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
<vscale x 4 x i1> %mask) {
@@ -936,7 +937,7 @@ define <vscale x 2 x i32> @test_ratio_only_vmv_s_x(ptr %x, ptr %y, i1 %cond) nou
; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: .LBB21_3: # %if.end
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; CHECK-NEXT: vmv.s.x v8, zero
; CHECK-NEXT: ret
entry:
@@ -968,7 +969,7 @@ define <vscale x 2 x i32> @test_ratio_only_vmv_s_x2(ptr %x, ptr %y, i1 %cond) no
; CHECK-NEXT: vle16.v v9, (a1)
; CHECK-NEXT: vwcvt.x.x.v v8, v9
; CHECK-NEXT: .LBB22_3: # %if.end
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; CHECK-NEXT: vmv.s.x v8, zero
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
index 2293a1e6979f4..652fbd71e9841 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
@@ -352,7 +352,7 @@ define <vscale x 1 x double> @test18(<vscale x 1 x double> %a, double %b) nounwi
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 6, e64, m1, ta, ma
; CHECK-NEXT: vfadd.vv v9, v8, v8
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, ma
+; CHECK-NEXT: vsetivli zero, 6, e64, m1, tu, ma
; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
@@ -903,7 +903,7 @@ define void @coalesce_vl_clobber(ptr %p) {
; CHECK-NEXT: srli a1, a1, 32
; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
; CHECK-NEXT: vslideup.vx v10, v9, a1, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 0, e8, mf2, ta, ma
; CHECK-NEXT: vmsne.vi v0, v10, 0, v0.t
; CHECK-NEXT: vsetvli zero, a3, e32, m2, ta, ma
; CHECK-NEXT: vmv.v.i v10, 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
index 396ca517e4017..c59d6ccb790f2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
@@ -451,7 +451,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 4, 217 /* e64, m2, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: dead [[PseudoVID_V_M2_:%[0-9]+]]:vrm2 = PseudoVID_V_M2 undef $noreg, 4, 6 /* e64 */, 3 /* ta, ma */, implicit $vl, implicit $vtype
- ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 198 /* e8, mf4, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
+ ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 4, 198 /* e8, mf4, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: dead [[PseudoVMV_V_I_MF4_:%[0-9]+]]:vr = PseudoVMV_V_I_MF4 undef $noreg, 0, 4, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: PseudoRET
%0:vrm2 = PseudoVID_V_M2 undef $noreg, 4, 6, 3
@@ -477,7 +477,7 @@ body: |
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
+ ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: dead [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 undef $noreg, 1, 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
diff --git a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
index 06bbe5209df35..6265b25955c17 100644
--- a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
@@ -749,7 +749,7 @@ define void @test_srem_vec(ptr %X) nounwind {
; RV32MV-NEXT: vmsne.vv v0, v8, v10
; RV32MV-NEXT: vmv.v.i v8, 0
; RV32MV-NEXT: vmerge.vim v8, v8, -1, v0
-; RV32MV-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32MV-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32MV-NEXT: vslidedown.vi v12, v8, 1
; RV32MV-NEXT: vslidedown.vi v13, v8, 2
; RV32MV-NEXT: vsetivli zero, 1, e32, m2, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll b/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
index ba9c926c57152..4a7f6e5cbccb6 100644
--- a/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
@@ -584,10 +584,10 @@ define void @test_urem_vec(ptr %X) nounwind {
; RV32MV-NEXT: srli a1, a1, 21
; RV32MV-NEXT: vslide1down.vx v10, v10, a1
; RV32MV-NEXT: li a1, 2047
-; RV32MV-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32MV-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32MV-NEXT: vmv.v.i v11, 1
; RV32MV-NEXT: andi a2, a2, 2047
-; RV32MV-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV32MV-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV32MV-NEXT: vslide1down.vx v10, v10, a2
; RV32MV-NEXT: lui a2, %hi(.LCPI4_1)
; RV32MV-NEXT: addi a2, a2, %lo(.LCPI4_1)
@@ -595,9 +595,9 @@ define void @test_urem_vec(ptr %X) nounwind {
; RV32MV-NEXT: vsext.vf2 v12, v11
; RV32MV-NEXT: vslidedown.vi v10, v10, 1
; RV32MV-NEXT: vsub.vv v8, v10, v8
-; RV32MV-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32MV-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32MV-NEXT: vmv.s.x v10, a3
-; RV32MV-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV32MV-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV32MV-NEXT: vsext.vf2 v11, v10
; RV32MV-NEXT: vmul.vv v8, v8, v9
; RV32MV-NEXT: vadd.vv v9, v8, v8
@@ -645,10 +645,10 @@ define void @test_urem_vec(ptr %X) nounwind {
; RV64MV-NEXT: srli a2, a2, 53
; RV64MV-NEXT: vslide1down.vx v10, v10, a2
; RV64MV-NEXT: li a2, 2047
-; RV64MV-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64MV-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64MV-NEXT: vmv.v.i v11, 1
; RV64MV-NEXT: srli a1, a1, 22
-; RV64MV-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64MV-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV64MV-NEXT: vslide1down.vx v10, v10, a1
; RV64MV-NEXT: lui a1, %hi(.LCPI4_1)
; RV64MV-NEXT: addi a1, a1, %lo(.LCPI4_1)
@@ -656,9 +656,9 @@ define void @test_urem_vec(ptr %X) nounwind {
; RV64MV-NEXT: vsext.vf2 v12, v11
; RV64MV-NEXT: vslidedown.vi v10, v10, 1
; RV64MV-NEXT: vsub.vv v8, v10, v8
-; RV64MV-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64MV-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64MV-NEXT: vmv.s.x v10, a3
-; RV64MV-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64MV-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV64MV-NEXT: vsext.vf2 v11, v10
; RV64MV-NEXT: vmul.vv v8, v8, v9
; RV64MV-NEXT: vadd.vv v9, v8, v8
>From 612f55cedc3121ce7d7f5af5dffee8409449459c Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: Mon, 24 Nov 2025 20:15:29 +0800
Subject: [PATCH 2/5] Refactor code and fix regression in @cross_block_mutate
---
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 76 +++++++++----------
.../RISCV/rvv/vsetvli-insert-crossbb.ll | 3 +-
2 files changed, 39 insertions(+), 40 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index ead5eb9033285..88836b68af193 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -32,6 +32,7 @@
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LiveStacks.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
#include <queue>
using namespace llvm;
@@ -951,6 +952,7 @@ class RISCVInsertVSETVLI : public MachineFunctionPass {
void doPRE(MachineBasicBlock &MBB);
void insertReadVL(MachineBasicBlock &MBB);
+ bool isVLPreserving(const MachineInstr &PrevMI, const MachineInstr &MI) const;
bool canMutatePriorConfig(const MachineInstr &PrevMI, const MachineInstr &MI,
const DemandedFields &Used) const;
void coalesceVSETVLIs(MachineBasicBlock &MBB) const;
@@ -1736,6 +1738,14 @@ void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
AvailableInfo, OldExit);
}
+bool RISCVInsertVSETVLI::isVLPreserving(const MachineInstr &PrevMI,
+ const MachineInstr &MI) const {
+ return MI.getOpcode() == RISCV::PseudoVSETIVLI &&
+ PrevMI.getOpcode() == RISCV::PseudoVSETIVLI &&
+ getInfoForVSETVLI(PrevMI).getAVLImm() ==
+ getInfoForVSETVLI(MI).getAVLImm();
+}
+
// Return true if we can mutate PrevMI to match MI without changing any the
// fields which would be observed.
bool RISCVInsertVSETVLI::canMutatePriorConfig(
@@ -1744,48 +1754,37 @@ bool RISCVInsertVSETVLI::canMutatePriorConfig(
// If the VL values aren't equal, return false if either a) the former is
// demanded, or b) we can't rewrite the former to be the later for
// implementation reasons.
- if (!RISCVInstrInfo::isVLPreservingConfig(MI)) {
- bool Skip = false;
- if (MI.getOpcode() == RISCV::PseudoVSETIVLI &&
- PrevMI.getOpcode() == RISCV::PseudoVSETIVLI &&
- PrevMI.getOperand(0).isDead()) {
- VSETVLIInfo PrevInfo = getInfoForVSETVLI(PrevMI);
- VSETVLIInfo Info = getInfoForVSETVLI(MI);
- if (PrevInfo.hasAVLImm() && Info.hasAVLImm() &&
- PrevInfo.getAVLImm() == Info.getAVLImm())
- Skip = true;
- }
- if (!Skip) {
- if (Used.VLAny)
- return false;
-
- if (Used.VLZeroness) {
- if (RISCVInstrInfo::isVLPreservingConfig(PrevMI))
- return false;
- if (!getInfoForVSETVLI(PrevMI).hasEquallyZeroAVL(getInfoForVSETVLI(MI),
- LIS))
- return false;
- }
+ if (!RISCVInstrInfo::isVLPreservingConfig(MI) &&
+ !isVLPreserving(PrevMI, MI)) {
+ if (Used.VLAny)
+ return false;
- auto &AVL = MI.getOperand(1);
+ if (Used.VLZeroness) {
+ if (RISCVInstrInfo::isVLPreservingConfig(PrevMI))
+ return false;
+ if (!getInfoForVSETVLI(PrevMI).hasEquallyZeroAVL(getInfoForVSETVLI(MI),
+ LIS))
+ return false;
+ }
- // If the AVL is a register, we need to make sure its definition is the
- // same at PrevMI as it was at MI.
- if (AVL.isReg() && AVL.getReg() != RISCV::X0) {
- VNInfo *VNI = getVNInfoFromReg(AVL.getReg(), MI, LIS);
- VNInfo *PrevVNI = getVNInfoFromReg(AVL.getReg(), PrevMI, LIS);
- if (!VNI || !PrevVNI || VNI != PrevVNI)
- return false;
- }
+ auto &AVL = MI.getOperand(1);
- // If we define VL and need to move the definition up, check we can extend
- // the live interval upwards from MI to PrevMI.
- Register VL = MI.getOperand(0).getReg();
- if (VL.isVirtual() && LIS &&
- LIS->getInterval(VL).overlaps(LIS->getInstructionIndex(PrevMI),
- LIS->getInstructionIndex(MI)))
+ // If the AVL is a register, we need to make sure its definition is the
+ // same at PrevMI as it was at MI.
+ if (AVL.isReg() && AVL.getReg() != RISCV::X0) {
+ VNInfo *VNI = getVNInfoFromReg(AVL.getReg(), MI, LIS);
+ VNInfo *PrevVNI = getVNInfoFromReg(AVL.getReg(), PrevMI, LIS);
+ if (!VNI || !PrevVNI || VNI != PrevVNI)
return false;
}
+
+ // If we define VL and need to move the definition up, check we can extend
+ // the live interval upwards from MI to PrevMI.
+ Register VL = MI.getOperand(0).getReg();
+ if (VL.isVirtual() && LIS &&
+ LIS->getInterval(VL).overlaps(LIS->getInstructionIndex(PrevMI),
+ LIS->getInstructionIndex(MI)))
+ return false;
}
assert(PrevMI.getOperand(2).isImm() && MI.getOperand(2).isImm());
@@ -1850,7 +1849,8 @@ void RISCVInsertVSETVLI::coalesceVSETVLIs(MachineBasicBlock &MBB) const {
}
if (canMutatePriorConfig(MI, *NextMI, Used)) {
- if (!RISCVInstrInfo::isVLPreservingConfig(*NextMI)) {
+ if (!RISCVInstrInfo::isVLPreservingConfig(*NextMI) &&
+ !isVLPreserving(MI, *NextMI)) {
Register DefReg = NextMI->getOperand(0).getReg();
MI.getOperand(0).setReg(DefReg);
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
index 137a36edef7b1..4d7dbdfc842e8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
@@ -850,8 +850,7 @@ for.end: ; preds = %for.body
define <vscale x 4 x i32> @cross_block_mutate(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b,
; CHECK-LABEL: cross_block_mutate:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetivli a0, 6, e16, m1, ta, ma
-; CHECK-NEXT: vsetivli zero, 6, e32, m2, tu, ma
+; CHECK-NEXT: vsetivli a0, 6, e32, m2, tu, ma
; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t
>From d5b3005f355d0ef22a67f0b838ea474fd1266318 Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: Mon, 24 Nov 2025 20:19:44 +0800
Subject: [PATCH 3/5] cleanup
---
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 88836b68af193..d91654a72a786 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -32,7 +32,6 @@
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LiveStacks.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineInstr.h"
#include <queue>
using namespace llvm;
@@ -1769,8 +1768,8 @@ bool RISCVInsertVSETVLI::canMutatePriorConfig(
auto &AVL = MI.getOperand(1);
- // If the AVL is a register, we need to make sure its definition is the
- // same at PrevMI as it was at MI.
+ // If the AVL is a register, we need to make sure its definition is the same
+ // at PrevMI as it was at MI.
if (AVL.isReg() && AVL.getReg() != RISCV::X0) {
VNInfo *VNI = getVNInfoFromReg(AVL.getReg(), MI, LIS);
VNInfo *PrevVNI = getVNInfoFromReg(AVL.getReg(), PrevMI, LIS);
>From 0f50f394cc7b6a9b0da0c8ced89c3a8e7c9dddf5 Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: Tue, 25 Nov 2025 19:58:56 +0800
Subject: [PATCH 4/5] Address comments
---
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 20 +++++++++-----------
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index d91654a72a786..3d1bb4bb7e981 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -951,7 +951,6 @@ class RISCVInsertVSETVLI : public MachineFunctionPass {
void doPRE(MachineBasicBlock &MBB);
void insertReadVL(MachineBasicBlock &MBB);
- bool isVLPreserving(const MachineInstr &PrevMI, const MachineInstr &MI) const;
bool canMutatePriorConfig(const MachineInstr &PrevMI, const MachineInstr &MI,
const DemandedFields &Used) const;
void coalesceVSETVLIs(MachineBasicBlock &MBB) const;
@@ -1737,12 +1736,13 @@ void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
AvailableInfo, OldExit);
}
-bool RISCVInsertVSETVLI::isVLPreserving(const MachineInstr &PrevMI,
- const MachineInstr &MI) const {
- return MI.getOpcode() == RISCV::PseudoVSETIVLI &&
- PrevMI.getOpcode() == RISCV::PseudoVSETIVLI &&
- getInfoForVSETVLI(PrevMI).getAVLImm() ==
- getInfoForVSETVLI(MI).getAVLImm();
+// If the VL is preserved between PrevMI and NextMI.
+static bool isVLPreserved(const MachineInstr &PrevMI,
+ const MachineInstr &NextMI) {
+ return RISCVInstrInfo::isVLPreservingConfig(NextMI) ||
+ (PrevMI.getOpcode() == RISCV::PseudoVSETIVLI &&
+ NextMI.getOpcode() == RISCV::PseudoVSETIVLI &&
+ PrevMI.getOperand(1).getImm() == NextMI.getOperand(1).getImm());
}
// Return true if we can mutate PrevMI to match MI without changing any the
@@ -1753,8 +1753,7 @@ bool RISCVInsertVSETVLI::canMutatePriorConfig(
// If the VL values aren't equal, return false if either a) the former is
// demanded, or b) we can't rewrite the former to be the later for
// implementation reasons.
- if (!RISCVInstrInfo::isVLPreservingConfig(MI) &&
- !isVLPreserving(PrevMI, MI)) {
+ if (!isVLPreserved(PrevMI, MI)) {
if (Used.VLAny)
return false;
@@ -1848,8 +1847,7 @@ void RISCVInsertVSETVLI::coalesceVSETVLIs(MachineBasicBlock &MBB) const {
}
if (canMutatePriorConfig(MI, *NextMI, Used)) {
- if (!RISCVInstrInfo::isVLPreservingConfig(*NextMI) &&
- !isVLPreserving(MI, *NextMI)) {
+ if (!isVLPreserved(MI, *NextMI)) {
Register DefReg = NextMI->getOperand(0).getReg();
MI.getOperand(0).setReg(DefReg);
>From c22e35b0b6486219dc3e28a72a5b2cc827080e5f Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: Wed, 26 Nov 2025 14:50:46 +0800
Subject: [PATCH 5/5] Remove UseVsetivliForImmAVL
---
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 3d1bb4bb7e981..b23348afb8173 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -47,11 +47,6 @@ static cl::opt<bool> EnsureWholeVectorRegisterMoveValidVTYPE(
"vill is cleared"),
cl::init(true));
-static cl::opt<bool> UseVsetivliForImmAVL(
- DEBUG_TYPE "-use-vsetivli-for-imm-avl", cl::Hidden,
- cl::desc("Use vsetivli to replace x0,x0 form when AVL is an immediate."),
- cl::init(true));
-
namespace {
/// Given a virtual register \p Reg, return the corresponding VNInfo for it.
@@ -1173,7 +1168,7 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
// VLMAX.
if (Info.hasSameAVL(PrevInfo) && Info.hasSameVLMAX(PrevInfo)) {
auto MI =
- UseVsetivliForImmAVL && Info.hasAVLImm()
+ Info.hasAVLImm()
? BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETIVLI))
.addReg(RISCV::X0, RegState::Define | RegState::Dead)
.addImm(PrevInfo.getAVLImm())
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