[llvm] [RISCV] Only convert volatile i64 load/store to Zilsd in SelectionDAG. (PR #169529)

[Brandon Wu via llvm-commits]

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@@ -44,10 +45,10 @@ define i64 @load_align4(ptr %a) nounwind {
 define void @store(ptr %a, i64 %b) nounwind {
 ; CHECK-LABEL: store:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    mv a3, a2
-; CHECK-NEXT:    mv a2, a1
-; CHECK-NEXT:    sd a2, 0(a0)
-; CHECK-NEXT:    sd a2, 88(a0)
+; CHECK-NEXT:    sw a1, 0(a0)
+; CHECK-NEXT:    sw a2, 4(a0)
+; CHECK-NEXT:    sw a1, 88(a0)
+; CHECK-NEXT:    sw a2, 92(a0)
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4vtomat wrote:

Curious that does this also considered a regression in terms of latency since it turns 2 loads to 4 loads?
Or it doesn't matter since latency of sd is 2 * sw

https://github.com/llvm/llvm-project/pull/169529