[llvm] Redesign Straight-Line Strength Reduction (SLSR) (PR #162930)

[Fei Peng via llvm-commits]

fiigii wrote:

@akuegel Thank you for reporting and analyzing the issue. I did not know SCEV 's equivalent check is so optimistic. Let me investigate how to prevent it. 

Btw, the original SLSR also has this problem, but my change triggered this issue with more cases. I believe the example below is still miscompiled even if reverting my change.
```
; RUN: opt < %s -passes=slsr -S | FileCheck %s
target datalayout = "e-p6:32:32-i64:64-i128:128-i256:256-v16:16-v32:32-n16:32:64"
target triple = "nvptx64-nvidia-cuda"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite)
define ptx_kernel void @loop_subtract_fusion(i64 %0, ptr  writeonly align 256 captures(none) dereferenceable(15) %1, i32 %row, i32 %column) {
  %3 = icmp samesign ult i32 %column, 4
  %4 = shl nuw nsw i32 %row, 2
  %5 = or disjoint i32 %4, %column
  %6 = zext nneg i32 %5 to i64
  %7 = add i64 %0, %6
  br i1 %3, label %8, label %10

8:                                                ; preds = %2
  %9 = call i64 @foo(i64 %7)
  br label %10

10:                                               ; preds = %8, %2
  %11 = phi i64 [ %9, %8 ], [ 1, %2 ]
  %.not = icmp eq i32 %column, 0
  %12 = shl nuw nsw i32 %row, 2
  %13 = add nuw nsw i32 %12, %column
  %14 = zext nneg i32 %13 to i64
  %15 = mul i64 %0, 4
  %16 = add i64 %15, %14
  %17 = add i64 %16, -1
  br i1 %.not, label %20, label %18

18:                                               ; preds = %10
  %19 = call i64 @bar(i64 %17)
  br label %20

20:                                               ; preds = %17, %10
  ret void
}

declare i64 @foo(i64)
declare i64 @bar(i64)
```

https://github.com/llvm/llvm-project/pull/162930