[llvm] [RISCV] Lower flag check pattern to use a bitmask-shift (PR #169557)

[Ryan Buchner via llvm-commits]

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@@ -16736,6 +16736,52 @@ static SDValue combineOrAndToBitfieldInsert(SDNode *N, SelectionDAG &DAG,
   return DAG.getNode(RISCVISD::QC_INSB, DL, MVT::i32, Ops);
 }
 
+// or (icmp eq x, imm0), (icmp eq x, imm1) -> czero.eqz (sltui x, 64), (bext x,
+// 1 << imm0 | 1 << imm1) If [imm0, imm1] < 64
+static SDValue combineOrOfImmCmpToBitExtract(SDNode *N, SelectionDAG &DAG,
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bababuck wrote:

In InstCombine must lower to a `select` rather than an `and`: https://alive2.llvm.org/ce/z/dqXbEC.

The concern about XLEN is still valid I think.

https://github.com/llvm/llvm-project/pull/169557