[llvm] Passes for widening vector operations and shuffle opt (PR #169559)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/lib/Target/Hexagon/HexagonGenWideningVecFloatInstr.cpp llvm/lib/Target/Hexagon/HexagonGenWideningVecInstr.cpp llvm/lib/Target/Hexagon/HexagonOptShuffleVector.cpp llvm/lib/Target/Hexagon/Hexagon.h llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp llvm/lib/Target/Hexagon/HexagonISelLowering.h llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index 612198069..981521c9b 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -219,7 +219,6 @@ HexagonTargetLowering::initializeHVXLowering() {
       setOperationAction(ISD::FP_EXTEND, MVT::v64f32, Legal);
       setOperationAction(ISD::FP_ROUND,  MVT::v64f16, Legal);
     }
-
   }
 
   for (MVT T : LegalV) {
@@ -3405,10 +3404,10 @@ HexagonTargetLowering::WidenHvxSetCC(SDValue Op, SelectionDAG &DAG) const {
                      {SetCC, getZero(dl, MVT::i32, DAG)});
 }
 
-SDValue
-HexagonTargetLowering::WidenHvxIntrinsic(SDValue Op, SelectionDAG &DAG) const {
+SDValue HexagonTargetLowering::WidenHvxIntrinsic(SDValue Op,
+                                                 SelectionDAG &DAG) const {
   const SDLoc &dl(Op);
-  unsigned HwWidth = 8*Subtarget.getVectorLength();
+  unsigned HwWidth = 8 * Subtarget.getVectorLength();
   bool IsResInterleaved = false;
 
   SDValue WideRes = SDValue();
@@ -3449,8 +3448,8 @@ HexagonTargetLowering::WidenHvxIntrinsic(SDValue Op, SelectionDAG &DAG) const {
   case Intrinsic::hexagon_vasrsat_uu:
   case Intrinsic::hexagon_vasrsat_ss:
     WideRes = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, WideResTy,
-                          DAG.getConstant(IID, dl, MVT::i32), WideOp1,
-                          WideOp2, Op.getOperand(3));
+                          DAG.getConstant(IID, dl, MVT::i32), WideOp1, WideOp2,
+                          Op.getOperand(3));
     break;
   case Intrinsic::hexagon_vadd_su:
   case Intrinsic::hexagon_vadd_uu:
@@ -3481,15 +3480,15 @@ HexagonTargetLowering::WidenHvxIntrinsic(SDValue Op, SelectionDAG &DAG) const {
     break;
   }
   unsigned OrigLen = ResTy.getVectorNumElements();
-  assert(OrigLen%2 == 0);
-  unsigned HalfOrigLen = OrigLen/2;
-  unsigned SplitLen = WideLen/2;
+  assert(OrigLen % 2 == 0);
+  unsigned HalfOrigLen = OrigLen / 2;
+  unsigned SplitLen = WideLen / 2;
   if (IsResInterleaved) {
     // Get the valid odd and even elements from the widened vector-pair while
     // maintaining their deinterleaved order. The following shuffle_vector will
     // produce a vector-pair with all the valid elements (even followed by odd)
     // accumulated together followed by undefs.
-    SmallVector<int,128> ShuffV;
+    SmallVector<int, 128> ShuffV;
     for (unsigned j = 0; j < WidenFactor; j++) {
       for (unsigned i = 0; i < HalfOrigLen; i++)
         ShuffV.push_back(j * HalfOrigLen + i);
@@ -3769,7 +3768,7 @@ HexagonTargetLowering::LowerHvxOperationWrapper(SDNode *N,
         Results.push_back(S);
       }
       break;
-      case ISD::INTRINSIC_WO_CHAIN:
+    case ISD::INTRINSIC_WO_CHAIN:
       if (shouldWidenToHvx(ty(Op.getOperand(1)), DAG)) {
         if (SDValue T = WidenHvxIntrinsic(Op, DAG))
           Results.push_back(T);
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp
index 9d72d704e..10c350e0e 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp
@@ -68,9 +68,10 @@ void HexagonMCELFStreamer::emitInstruction(const MCInst &MCB,
   assert(HexagonMCInstrInfo::bundleSize(MCB) <= HEXAGON_PACKET_SIZE);
   assert(HexagonMCInstrInfo::bundleSize(MCB) > 0);
   const MCRegisterInfo *RI = getContext().getRegisterInfo();
-  HexagonMCChecker Check(getContext(), *MCII, STI, const_cast<MCInst &>(MCB), *RI);
+  HexagonMCChecker Check(getContext(), *MCII, STI, const_cast<MCInst &>(MCB),
+                         *RI);
   [[maybe_unused]] bool CheckOk = Check.check(false);
-  assert (CheckOk);
+  assert(CheckOk);
 
   // At this point, MCB is a bundle
   // Iterate through the bundle and assign addends for the instructions

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https://github.com/llvm/llvm-project/pull/169559