[llvm] [X86] Remove redundant TEST after shifts when count is non-zero (PR #169069)

[via llvm-commits]

================
@@ -23625,6 +23625,60 @@ static SDValue EmitTest(SDValue Op, X86::CondCode X86CC, const SDLoc &dl,
     return DAG.getNode(X86ISD::SUB, dl, VTs, Op->getOperand(0),
                        Op->getOperand(1)).getValue(1);
   }
+  case ISD::SHL:
+  case ISD::SRL:
+  case ISD::SRA: {
+    SDValue Amt = ArithOp.getOperand(1);
+
+    // Skip Constants
+    if (isa<ConstantSDNode>(Amt))
+      break;
+
+    // If optimising for size and can guarantee the shift amt is never zero
+    // the test.
+    bool OptForSize = DAG.getMachineFunction().getFunction().hasOptSize();
+
+    if (!OptForSize)
----------------
GrumpyPigSkin wrote:

Update:

7800X3D (Zen 4):
```
Run on (16 X 4200 MHz CPU s)
CPU Caches:
  L1 Data 32K (x8)
  L1 Instruction 32K (x8)
  L2 Unified 1048K (x8)
  L3 Unified 100663K (x1)
-----------------------------------------------------
Benchmark           Time             CPU   Iterations
-----------------------------------------------------
BM_TEST          1.02 ns         1.03 ns    746666667
BM_NO_TEST       1.01 ns         1.00 ns    640000000
```
5900X (Zen3):
```
Run on (24 X 3700 MHz CPU s)
CPU Caches:
  L1 Data 32K (x12)
  L1 Instruction 32K (x12)
  L2 Unified 524K (x12)
  L3 Unified 33554K (x2)
-----------------------------------------------------
Benchmark           Time             CPU   Iterations
-----------------------------------------------------
BM_TEST          1.07 ns         1.05 ns    640000000
BM_NO_TEST       1.07 ns         1.07 ns    640000000
```


https://github.com/llvm/llvm-project/pull/169069