[llvm] [RISCV] Propagate SDNode flags when combining `(fmul (fneg X), ...)` (PR #169460)

[Min-Yih Hsu via llvm-commits]

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@@ -20822,7 +20822,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
     // Undo this and sink the fneg so we match more fmsub/fnmadd patterns.
     if (sd_match(N, m_FMul(m_Value(X), m_OneUse(m_FNeg(m_Value(Y))))))
       return DAG.getNode(ISD::FNEG, DL, VT,
-                         DAG.getNode(ISD::FMUL, DL, VT, X, Y));
+                         DAG.getNode(ISD::FMUL, DL, VT, X, Y, N->getFlags()));
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mshockwave wrote:

It's done now. But I got nerd-sniped by one question: in this InstCombine code, should we _merge_ the flags from fneg and fmul instead? Some of other InstCombine code does that (i.e. merging) using `FastMathFlags::unionValue/intersectRewrite` when doing similar transformations.

https://github.com/llvm/llvm-project/pull/169460