[llvm] [RISCV] Propagate SDNode flags when combining `(fmul (fneg X), ...)` (PR #169460)

[Min-Yih Hsu via llvm-commits]

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@@ -0,0 +1,52 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=riscv64 -mattr='+d,+m' < %s | FileCheck %s
+
+define double @fnmadd_non_trivial(ptr %p0, ptr %p1, ptr %dst, double %mul425) {
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mshockwave wrote:

Done

https://github.com/llvm/llvm-project/pull/169460