[llvm] AMDGPU: Add baseline test for gws handling with AGPR inputs (PR #169372)

[Shilei Tian via llvm-commits]

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@@ -0,0 +1,395 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=CHECK,SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=CHECK,GISEL %s
+
+define void @gws_init_offset0() #0 {
+; SDAG-LABEL: gws_init_offset0:
+; SDAG:       ; %bb.0:
+; SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-NEXT:    ;;#ASMSTART
+; SDAG-NEXT:    ; def a0
+; SDAG-NEXT:    ;;#ASMEND
+; SDAG-NEXT:    s_mov_b32 m0, 0
+; SDAG-NEXT:    s_nop 0
+; SDAG-NEXT:    ds_gws_init a0 gds
+; SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GISEL-LABEL: gws_init_offset0:
+; GISEL:       ; %bb.0:
+; GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-NEXT:    ;;#ASMSTART
+; GISEL-NEXT:    ; def a0
+; GISEL-NEXT:    ;;#ASMEND
+; GISEL-NEXT:    v_accvgpr_read_b32 v0, a0
+; GISEL-NEXT:    s_mov_b32 m0, 0
+; GISEL-NEXT:    s_nop 0
+; GISEL-NEXT:    ds_gws_init v0 gds
+; GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-NEXT:    s_setpc_b64 s[30:31]
+  %val = call i32 asm "; def $0", "=a"()
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shiltian wrote:

Is this the canonical way to do an implicit define at IR level?

https://github.com/llvm/llvm-project/pull/169372