[llvm] [AArch64] Combine vector FNEG+FMA into `FNML[A|S]` (PR #167900)

[Damian Heaton via llvm-commits]

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@@ -20692,6 +20694,47 @@ static SDValue performFADDCombine(SDNode *N,
   return SDValue();
 }
 
+static SDValue performFMACombine(SDNode *N,
+                                 TargetLowering::DAGCombinerInfo &DCI,
+                                 const AArch64Subtarget *Subtarget) {
+  SelectionDAG &DAG = DCI.DAG;
+  SDValue OpA = N->getOperand(0);
+  SDValue OpB = N->getOperand(1);
+  SDValue OpC = N->getOperand(2);
+  EVT VT = N->getValueType(0);
+  SDLoc DL(N);
+
+  // Convert FMA/FNEG nodes to SVE to enable the following patterns:
+  // fma(a, b, neg(c)) -> fnmls(a, b, c)
+  // fma(neg(a), b, neg(c)) -> fnmla(a, b, c)
+  // fma(a, neg(b), neg(c)) -> fnmla(a, b, c)
+  if (!VT.isFixedLengthVector() ||
+      !DAG.getTargetLoweringInfo().isTypeLegal(VT) ||
+      !Subtarget->isSVEorStreamingSVEAvailable() ||
+      OpC.getOpcode() != ISD::FNEG) {
+    return SDValue();
+  }
+
+  SDValue Pg = getPredicateForVector(DAG, DL, VT);
+  EVT ContainerVT = getContainerForFixedLengthVector(DAG, VT);
+  OpC =
+      DAG.getNode(AArch64ISD::FNEG_MERGE_PASSTHRU, DL, ContainerVT, Pg,
+                  convertToScalableVector(DAG, ContainerVT, OpC.getOperand(0)),
+                  DAG.getUNDEF(ContainerVT));
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dheaton-arm wrote:

`LowerToPredicatedOp` is a private method for `TargetLowering`, so without changing the visibility we can't use it in a DAG combiner.

https://github.com/llvm/llvm-project/pull/167900