[llvm] d748c81 - [AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 25 03:55:38 PST 2025
Author: Jay Foad
Date: 2025-11-25T11:55:26Z
New Revision: d748c81218bee39dafb9cc0c00ed7831a3ed44c3
URL: https://github.com/llvm/llvm-project/commit/d748c81218bee39dafb9cc0c00ed7831a3ed44c3
DIFF: https://github.com/llvm/llvm-project/commit/d748c81218bee39dafb9cc0c00ed7831a3ed44c3.diff
LOG: [AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (#169378)
The 16-bit immediate operand of s_waitcnt_depctr / s_wait_alu has some
unused bits. Previously codegen would set these bits to 1, but setting
them to 0 matches the SP3 assembler behaviour better, which in turn
means that we can print them using the human readable SP3 syntax:
s_wait_alu 0xfffd ; unused bits set to 1
s_wait_alu 0xff9d ; unused bits set to 0
s_wait_alu depctr_va_vcc(0) ; unused bits set to 0, human readable
Note that the set of unused bits changed between GFX10.1 and GFX10.3.
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform-in-vgpr.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
llvm/test/CodeGen/AMDGPU/add_i1.ll
llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll
llvm/test/CodeGen/AMDGPU/amdgcn-cs-chain-intrinsic-dyn-vgpr-w32.ll
llvm/test/CodeGen/AMDGPU/amdgpu-branch-weight-metadata.ll
llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll
llvm/test/CodeGen/AMDGPU/atomic-optimizer-strict-wqm.ll
llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
llvm/test/CodeGen/AMDGPU/bf16.ll
llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
llvm/test/CodeGen/AMDGPU/carryout-selection.ll
llvm/test/CodeGen/AMDGPU/cc-entry.ll
llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
llvm/test/CodeGen/AMDGPU/cse-convergent.ll
llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
llvm/test/CodeGen/AMDGPU/fdiv.ll
llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-wwm.ll
llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
llvm/test/CodeGen/AMDGPU/flat-scratch.ll
llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
llvm/test/CodeGen/AMDGPU/fma.f16.ll
llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
llvm/test/CodeGen/AMDGPU/fmaximum.ll
llvm/test/CodeGen/AMDGPU/fmaximum3.ll
llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
llvm/test/CodeGen/AMDGPU/fminimum.ll
llvm/test/CodeGen/AMDGPU/fminimum3.ll
llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
llvm/test/CodeGen/AMDGPU/fpow.ll
llvm/test/CodeGen/AMDGPU/fract-match.ll
llvm/test/CodeGen/AMDGPU/freeze-binary.ll
llvm/test/CodeGen/AMDGPU/frem.ll
llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll
llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
llvm/test/CodeGen/AMDGPU/hazards-gfx1250.mir
llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
llvm/test/CodeGen/AMDGPU/idiv-licm.ll
llvm/test/CodeGen/AMDGPU/idot2.ll
llvm/test/CodeGen/AMDGPU/idot4s.ll
llvm/test/CodeGen/AMDGPU/idot4u.ll
llvm/test/CodeGen/AMDGPU/idot8s.ll
llvm/test/CodeGen/AMDGPU/idot8u.ll
llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx11.mir
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ptr.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
llvm/test/CodeGen/AMDGPU/llvm.log.ll
llvm/test/CodeGen/AMDGPU/llvm.log10.ll
llvm/test/CodeGen/AMDGPU/llvm.log2.ll
llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
llvm/test/CodeGen/AMDGPU/llvm.powi.ll
llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
llvm/test/CodeGen/AMDGPU/mad_64_32.ll
llvm/test/CodeGen/AMDGPU/madak.ll
llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
llvm/test/CodeGen/AMDGPU/merge-consecutive-wait-alus.mir
llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll
llvm/test/CodeGen/AMDGPU/nor-divergent-lanemask.ll
llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
llvm/test/CodeGen/AMDGPU/offset-split-global.ll
llvm/test/CodeGen/AMDGPU/partial-forwarding-hazards.mir
llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll
llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
llvm/test/CodeGen/AMDGPU/s-barrier.ll
llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
llvm/test/CodeGen/AMDGPU/should-not-hoist-set-inactive.ll
llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll
llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
llvm/test/CodeGen/AMDGPU/sub.ll
llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
llvm/test/CodeGen/AMDGPU/sub_i1.ll
llvm/test/CodeGen/AMDGPU/trans-forwarding-hazards.mir
llvm/test/CodeGen/AMDGPU/v_cndmask.ll
llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard-true16.mir
llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard-attrs.mir
llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard.mir
llvm/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir
llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
llvm/test/CodeGen/AMDGPU/wave32.ll
llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
llvm/test/CodeGen/AMDGPU/workitem-intrinsic-opts.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp b/llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
index ded2f5ae1f8af..8d8386c3a8a7c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
@@ -44,6 +44,7 @@ namespace {
class AMDGPUWaitSGPRHazards {
public:
+ const GCNSubtarget *ST;
const SIInstrInfo *TII;
const SIRegisterInfo *TRI;
const MachineRegisterInfo *MRI;
@@ -165,7 +166,7 @@ class AMDGPUWaitSGPRHazards {
}
unsigned mergeMasks(unsigned Mask1, unsigned Mask2) {
- unsigned Mask = 0xffff;
+ unsigned Mask = AMDGPU::DepCtr::getDefaultDepCtrEncoding(*ST);
Mask = AMDGPU::DepCtr::encodeFieldSaSdst(
Mask, std::min(AMDGPU::DepCtr::decodeFieldSaSdst(Mask1),
AMDGPU::DepCtr::decodeFieldSaSdst(Mask2)));
@@ -387,7 +388,7 @@ class AMDGPUWaitSGPRHazards {
// Apply wait
if (Wait) {
- unsigned Mask = 0xffff;
+ unsigned Mask = AMDGPU::DepCtr::getDefaultDepCtrEncoding(*ST);
if (Wait & WA_VCC) {
State.VCCHazard &= ~HazardState::VALU;
Mask = AMDGPU::DepCtr::encodeFieldVaVcc(Mask, 0);
@@ -438,8 +439,8 @@ class AMDGPUWaitSGPRHazards {
}
bool run(MachineFunction &MF) {
- const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
- if (!ST.hasVALUReadSGPRHazard())
+ ST = &MF.getSubtarget<GCNSubtarget>();
+ if (!ST->hasVALUReadSGPRHazard())
return false;
// Parse settings
@@ -467,10 +468,10 @@ class AMDGPUWaitSGPRHazards {
if (!EnableSGPRHazardWaits)
return false;
- TII = ST.getInstrInfo();
- TRI = ST.getRegisterInfo();
+ TII = ST->getInstrInfo();
+ TRI = ST->getRegisterInfo();
MRI = &MF.getRegInfo();
- DsNopCount = ST.isWave64() ? WAVE64_NOPS : WAVE32_NOPS;
+ DsNopCount = ST->isWave64() ? WAVE64_NOPS : WAVE32_NOPS;
auto CallingConv = MF.getFunction().getCallingConv();
if (!AMDGPU::isEntryFunctionCC(CallingConv) &&
diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index 29d22f27a2d8e..7fbf520c670ae 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -1354,7 +1354,7 @@ bool GCNHazardRecognizer::fixVMEMtoScalarWriteHazards(MachineInstr *MI) {
const SIInstrInfo *TII = ST.getInstrInfo();
BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
TII->get(AMDGPU::S_WAITCNT_DEPCTR))
- .addImm(AMDGPU::DepCtr::encodeFieldVmVsrc(0));
+ .addImm(AMDGPU::DepCtr::encodeFieldVmVsrc(0, ST));
return true;
}
@@ -1487,7 +1487,7 @@ bool GCNHazardRecognizer::fixVcmpxExecWARHazard(MachineInstr *MI) {
BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
TII->get(AMDGPU::S_WAITCNT_DEPCTR))
- .addImm(AMDGPU::DepCtr::encodeFieldSaSdst(0));
+ .addImm(AMDGPU::DepCtr::encodeFieldSaSdst(0, ST));
return true;
}
@@ -1651,7 +1651,7 @@ bool GCNHazardRecognizer::fixLdsDirectVMEMHazard(MachineInstr *MI) {
} else {
BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
TII.get(AMDGPU::S_WAITCNT_DEPCTR))
- .addImm(AMDGPU::DepCtr::encodeFieldVmVsrc(0));
+ .addImm(AMDGPU::DepCtr::encodeFieldVmVsrc(0, ST));
}
return true;
@@ -1809,7 +1809,7 @@ bool GCNHazardRecognizer::fixVALUPartialForwardingHazard(MachineInstr *MI) {
BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
TII.get(AMDGPU::S_WAITCNT_DEPCTR))
- .addImm(AMDGPU::DepCtr::encodeFieldVaVdst(0));
+ .addImm(AMDGPU::DepCtr::encodeFieldVaVdst(0, ST));
return true;
}
@@ -1895,7 +1895,7 @@ bool GCNHazardRecognizer::fixVALUTransUseHazard(MachineInstr *MI) {
// avoided.
BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
TII.get(AMDGPU::S_WAITCNT_DEPCTR))
- .addImm(AMDGPU::DepCtr::encodeFieldVaVdst(0));
+ .addImm(AMDGPU::DepCtr::encodeFieldVaVdst(0, ST));
return true;
}
@@ -3404,7 +3404,8 @@ bool GCNHazardRecognizer::fixVALUMaskWriteHazard(MachineInstr *MI) {
};
const unsigned ConstantMaskBits = AMDGPU::DepCtr::encodeFieldSaSdst(
- AMDGPU::DepCtr::encodeFieldVaSdst(AMDGPU::DepCtr::encodeFieldVaVcc(0), 0),
+ AMDGPU::DepCtr::encodeFieldVaSdst(AMDGPU::DepCtr::encodeFieldVaVcc(0, ST),
+ 0),
0);
auto UpdateStateFn = [&](StateType &State, const MachineInstr &I) {
switch (I.getOpcode()) {
@@ -3456,9 +3457,9 @@ bool GCNHazardRecognizer::fixVALUMaskWriteHazard(MachineInstr *MI) {
// Compute counter mask
unsigned DepCtr =
- IsVALU ? (IsVCC(HazardReg) ? AMDGPU::DepCtr::encodeFieldVaVcc(0)
- : AMDGPU::DepCtr::encodeFieldVaSdst(0))
- : AMDGPU::DepCtr::encodeFieldSaSdst(0);
+ IsVALU ? (IsVCC(HazardReg) ? AMDGPU::DepCtr::encodeFieldVaVcc(0, ST)
+ : AMDGPU::DepCtr::encodeFieldVaSdst(0, ST))
+ : AMDGPU::DepCtr::encodeFieldSaSdst(0, ST);
// Try to merge previous waits into this one for regions with no SGPR reads.
if (!WaitInstrs.empty()) {
@@ -3723,7 +3724,7 @@ bool GCNHazardRecognizer::fixScratchBaseForwardingHazard(MachineInstr *MI) {
BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
TII->get(AMDGPU::S_WAITCNT_DEPCTR))
.addImm(AMDGPU::DepCtr::encodeFieldVaSdst(
- AMDGPU::DepCtr::encodeFieldSaSdst(0), 0));
+ AMDGPU::DepCtr::encodeFieldSaSdst(0, ST), 0));
return true;
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 7504452dc777f..fa28a969439d9 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -2934,7 +2934,7 @@ void SIInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
auto ApplyHazardWorkarounds = [this, &MBB, &I, &DL, FlushSGPRWrites]() {
if (FlushSGPRWrites)
BuildMI(MBB, I, DL, get(AMDGPU::S_WAITCNT_DEPCTR))
- .addImm(AMDGPU::DepCtr::encodeFieldSaSdst(0));
+ .addImm(AMDGPU::DepCtr::encodeFieldSaSdst(0, ST));
};
// We need to compute the offset relative to the instruction immediately after
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 998a2b5b36a87..90f0b49ab9a78 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -2052,56 +2052,63 @@ unsigned encodeFieldVmVsrc(unsigned Encoded, unsigned VmVsrc) {
return packBits(VmVsrc, Encoded, getVmVsrcBitShift(), getVmVsrcBitWidth());
}
-unsigned encodeFieldVmVsrc(unsigned VmVsrc) {
- return encodeFieldVmVsrc(0xffff, VmVsrc);
+unsigned encodeFieldVmVsrc(unsigned VmVsrc, const MCSubtargetInfo &STI) {
+ unsigned Encoded = getDefaultDepCtrEncoding(STI);
+ return encodeFieldVmVsrc(Encoded, VmVsrc);
}
unsigned encodeFieldVaVdst(unsigned Encoded, unsigned VaVdst) {
return packBits(VaVdst, Encoded, getVaVdstBitShift(), getVaVdstBitWidth());
}
-unsigned encodeFieldVaVdst(unsigned VaVdst) {
- return encodeFieldVaVdst(0xffff, VaVdst);
+unsigned encodeFieldVaVdst(unsigned VaVdst, const MCSubtargetInfo &STI) {
+ unsigned Encoded = getDefaultDepCtrEncoding(STI);
+ return encodeFieldVaVdst(Encoded, VaVdst);
}
unsigned encodeFieldSaSdst(unsigned Encoded, unsigned SaSdst) {
return packBits(SaSdst, Encoded, getSaSdstBitShift(), getSaSdstBitWidth());
}
-unsigned encodeFieldSaSdst(unsigned SaSdst) {
- return encodeFieldSaSdst(0xffff, SaSdst);
+unsigned encodeFieldSaSdst(unsigned SaSdst, const MCSubtargetInfo &STI) {
+ unsigned Encoded = getDefaultDepCtrEncoding(STI);
+ return encodeFieldSaSdst(Encoded, SaSdst);
}
unsigned encodeFieldVaSdst(unsigned Encoded, unsigned VaSdst) {
return packBits(VaSdst, Encoded, getVaSdstBitShift(), getVaSdstBitWidth());
}
-unsigned encodeFieldVaSdst(unsigned VaSdst) {
- return encodeFieldVaSdst(0xffff, VaSdst);
+unsigned encodeFieldVaSdst(unsigned VaSdst, const MCSubtargetInfo &STI) {
+ unsigned Encoded = getDefaultDepCtrEncoding(STI);
+ return encodeFieldVaSdst(Encoded, VaSdst);
}
unsigned encodeFieldVaVcc(unsigned Encoded, unsigned VaVcc) {
return packBits(VaVcc, Encoded, getVaVccBitShift(), getVaVccBitWidth());
}
-unsigned encodeFieldVaVcc(unsigned VaVcc) {
- return encodeFieldVaVcc(0xffff, VaVcc);
+unsigned encodeFieldVaVcc(unsigned VaVcc, const MCSubtargetInfo &STI) {
+ unsigned Encoded = getDefaultDepCtrEncoding(STI);
+ return encodeFieldVaVcc(Encoded, VaVcc);
}
unsigned encodeFieldVaSsrc(unsigned Encoded, unsigned VaSsrc) {
return packBits(VaSsrc, Encoded, getVaSsrcBitShift(), getVaSsrcBitWidth());
}
-unsigned encodeFieldVaSsrc(unsigned VaSsrc) {
- return encodeFieldVaSsrc(0xffff, VaSsrc);
+unsigned encodeFieldVaSsrc(unsigned VaSsrc, const MCSubtargetInfo &STI) {
+ unsigned Encoded = getDefaultDepCtrEncoding(STI);
+ return encodeFieldVaSsrc(Encoded, VaSsrc);
}
unsigned encodeFieldHoldCnt(unsigned Encoded, unsigned HoldCnt) {
return packBits(HoldCnt, Encoded, getHoldCntBitShift(), getHoldCntWidth());
}
-unsigned encodeFieldHoldCnt(unsigned HoldCnt) {
- return encodeFieldHoldCnt(0xffff, HoldCnt);
+unsigned encodeFieldHoldCnt(unsigned HoldCnt, const MCSubtargetInfo &STI) {
+ unsigned Encoded = getDefaultDepCtrEncoding(STI);
+ return encodeFieldHoldCnt(Encoded, HoldCnt);
}
} // namespace DepCtr
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index 9f65f9326a73e..4ca328eb06303 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -1301,43 +1301,43 @@ unsigned decodeFieldVaSsrc(unsigned Encoded);
unsigned decodeFieldHoldCnt(unsigned Encoded);
/// \returns \p VmVsrc as an encoded Depctr immediate.
-unsigned encodeFieldVmVsrc(unsigned VmVsrc);
+unsigned encodeFieldVmVsrc(unsigned VmVsrc, const MCSubtargetInfo &STI);
/// \returns \p Encoded combined with encoded \p VmVsrc.
unsigned encodeFieldVmVsrc(unsigned Encoded, unsigned VmVsrc);
/// \returns \p VaVdst as an encoded Depctr immediate.
-unsigned encodeFieldVaVdst(unsigned VaVdst);
+unsigned encodeFieldVaVdst(unsigned VaVdst, const MCSubtargetInfo &STI);
/// \returns \p Encoded combined with encoded \p VaVdst.
unsigned encodeFieldVaVdst(unsigned Encoded, unsigned VaVdst);
/// \returns \p SaSdst as an encoded Depctr immediate.
-unsigned encodeFieldSaSdst(unsigned SaSdst);
+unsigned encodeFieldSaSdst(unsigned SaSdst, const MCSubtargetInfo &STI);
/// \returns \p Encoded combined with encoded \p SaSdst.
unsigned encodeFieldSaSdst(unsigned Encoded, unsigned SaSdst);
/// \returns \p VaSdst as an encoded Depctr immediate.
-unsigned encodeFieldVaSdst(unsigned VaSdst);
+unsigned encodeFieldVaSdst(unsigned VaSdst, const MCSubtargetInfo &STI);
/// \returns \p Encoded combined with encoded \p VaSdst.
unsigned encodeFieldVaSdst(unsigned Encoded, unsigned VaSdst);
/// \returns \p VaVcc as an encoded Depctr immediate.
-unsigned encodeFieldVaVcc(unsigned VaVcc);
+unsigned encodeFieldVaVcc(unsigned VaVcc, const MCSubtargetInfo &STI);
/// \returns \p Encoded combined with encoded \p VaVcc.
unsigned encodeFieldVaVcc(unsigned Encoded, unsigned VaVcc);
/// \returns \p HoldCnt as an encoded Depctr immediate.
-unsigned encodeFieldHoldCnt(unsigned HoldCnt);
+unsigned encodeFieldHoldCnt(unsigned HoldCnt, const MCSubtargetInfo &STI);
/// \returns \p Encoded combined with encoded \p HoldCnt.
-unsigned encodeFieldHoldCnt(unsigned HoldCnt, unsigned Encoded);
+unsigned encodeFieldHoldCnt(unsigned Encoded, unsigned HoldCnt);
/// \returns \p VaSsrc as an encoded Depctr immediate.
-unsigned encodeFieldVaSsrc(unsigned VaSsrc);
+unsigned encodeFieldVaSsrc(unsigned VaSsrc, const MCSubtargetInfo &STI);
/// \returns \p Encoded combined with encoded \p VaSsrc.
unsigned encodeFieldVaSsrc(unsigned Encoded, unsigned VaSsrc);
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
index e11720011af10..d6f1b142b36e0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
@@ -50,7 +50,7 @@ define i16 @s_add_i16(i16 inreg %a, i16 inreg %b) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_add_co_i32 s0, s0, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
%c = add i16 %a, %b
@@ -145,7 +145,7 @@ define i32 @s_add_i32(i32 inreg %a, i32 inreg %b) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_add_co_i32 s0, s0, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
%c = add i32 %a, %b
@@ -263,11 +263,11 @@ define <2 x i16> @s_add_v2i16(<2 x i16> inreg %a, <2 x i16> inreg %b) {
; GFX12-NEXT: s_lshr_b32 s2, s0, 16
; GFX12-NEXT: s_lshr_b32 s3, s1, 16
; GFX12-NEXT: s_add_co_i32 s0, s0, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_i32 s2, s2, s3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_pack_ll_b32_b16 s0, s0, s2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
%c = add <2 x i16> %a, %b
@@ -374,7 +374,7 @@ define i64 @s_add_i64(i64 inreg %a, i64 inreg %b) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-NEXT: s_setpc_b64 s[30:31]
%c = add i64 %a, %b
@@ -425,7 +425,7 @@ define i64 @v_add_i64(i64 %a, i64 %b) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
%c = add i64 %a, %b
@@ -513,7 +513,7 @@ define void @s_uaddo_uadde(i64 inreg %a, i64 inreg %b, ptr addrspace(1) %res, pt
; GFX12-NEXT: s_add_co_u32 s0, s0, s2
; GFX12-NEXT: s_add_co_ci_u32 s1, s1, s3
; GFX12-NEXT: s_cselect_b32 s2, 1, 0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v5, s1 :: v_dual_mov_b32 v4, s0
; GFX12-NEXT: v_mov_b32_e32 v6, s2
; GFX12-NEXT: global_store_b64 v[0:1], v[4:5], off
@@ -593,9 +593,9 @@ define void @v_uaddo_uadde(i64 %a, i64 %b, ptr addrspace(1) %res, ptr addrspace(
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX12-NEXT: global_store_b64 v[4:5], v[0:1], off
; GFX12-NEXT: global_store_b32 v[6:7], v2, off
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
index ff618c05e2b80..8063b29c29985 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
@@ -622,9 +622,9 @@ define double @global_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB6_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -779,9 +779,9 @@ define void @global_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB7_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1212,9 +1212,9 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB10_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1367,9 +1367,9 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB11_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1833,7 +1833,7 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; GFX12-NEXT: s_cbranch_execnz .LBB14_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2000,7 +2000,7 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
; GFX12-NEXT: v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; GFX12-NEXT: s_cbranch_execnz .LBB15_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
index 007417c83e324..5b0b602bd99ba 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
@@ -622,9 +622,9 @@ define double @global_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB6_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -779,9 +779,9 @@ define void @global_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB7_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1212,9 +1212,9 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB10_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1367,9 +1367,9 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB11_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1833,7 +1833,7 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; GFX12-NEXT: s_cbranch_execnz .LBB14_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2000,7 +2000,7 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
; GFX12-NEXT: v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; GFX12-NEXT: s_cbranch_execnz .LBB15_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
index 77d212afa0594..7f3e24f97b6e2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
@@ -3069,7 +3069,7 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset_addr64(ptr %out, ptr %
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-NEXT: flat_store_b32 v[0:1], v3
@@ -4161,7 +4161,7 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset_addr64(ptr %out, ptr %
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX12-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX12-NEXT: flat_store_b64 v[2:3], v[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
index 8372d22b72afc..121dd309fddf9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
@@ -303,7 +303,7 @@ define void @divergent_i1_xor_used_outside_loop_larger_loop_body(i32 %num.elts,
; GFX10-NEXT: v_mov_b32_e32 v0, 5
; GFX10-NEXT: flat_store_dword v[3:4], v0
; GFX10-NEXT: .LBB4_8: ; %exit
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -377,7 +377,7 @@ define void @divergent_i1_icmp_used_outside_loop(i32 %v0, i32 %v1, ptr addrspace
; GFX10-NEXT: global_store_dword v[8:9], v5, off
; GFX10-NEXT: .LBB5_4: ; %loop.break.block
; GFX10-NEXT: ; in Loop: Header=BB5_2 Depth=1
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s8
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, s4, v1
; GFX10-NEXT: s_mov_b32 s5, exec_lo
@@ -397,7 +397,7 @@ define void @divergent_i1_icmp_used_outside_loop(i32 %v0, i32 %v1, ptr addrspace
; GFX10-NEXT: ; %bb.7: ; %if.block.1
; GFX10-NEXT: global_store_dword v[6:7], v4, off
; GFX10-NEXT: .LBB5_8: ; %exit
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -542,7 +542,7 @@ define amdgpu_cs void @loop_with_1break(ptr addrspace(1) %x, ptr addrspace(1) %a
; GFX10-NEXT: s_branch .LBB7_2
; GFX10-NEXT: .LBB7_1: ; %Flow
; GFX10-NEXT: ; in Loop: Header=BB7_2 Depth=1
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX10-NEXT: s_and_b32 s1, exec_lo, s6
; GFX10-NEXT: s_or_b32 s4, s1, s4
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
index 484536bd27f4e..5c57d355959ef 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
@@ -112,7 +112,7 @@ define amdgpu_cs void @loop_with_1break(ptr addrspace(1) %x, ptr addrspace(1) %a
; GFX10-NEXT: s_branch .LBB2_2
; GFX10-NEXT: .LBB2_1: ; %Flow
; GFX10-NEXT: ; in Loop: Header=BB2_2 Depth=1
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX10-NEXT: s_and_b32 s1, exec_lo, s5
; GFX10-NEXT: s_or_b32 s4, s1, s4
@@ -186,7 +186,7 @@ define amdgpu_cs void @loop_with_2breaks(ptr addrspace(1) %x, ptr addrspace(1) %
; GFX10-NEXT: s_branch .LBB3_3
; GFX10-NEXT: .LBB3_1: ; %Flow3
; GFX10-NEXT: ; in Loop: Header=BB3_3 Depth=1
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s7
; GFX10-NEXT: s_andn2_b32 s2, s5, exec_lo
; GFX10-NEXT: s_and_b32 s3, exec_lo, s6
@@ -284,7 +284,7 @@ define amdgpu_cs void @loop_with_3breaks(ptr addrspace(1) %x, ptr addrspace(1) %
; GFX10-NEXT: s_branch .LBB4_4
; GFX10-NEXT: .LBB4_1: ; %Flow5
; GFX10-NEXT: ; in Loop: Header=BB4_4 Depth=1
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s9
; GFX10-NEXT: s_andn2_b32 s2, s6, exec_lo
; GFX10-NEXT: s_and_b32 s3, exec_lo, s8
@@ -412,7 +412,7 @@ define amdgpu_cs void @loop_with_div_break_with_body(ptr addrspace(1) %x, ptr ad
; GFX10-NEXT: s_branch .LBB5_2
; GFX10-NEXT: .LBB5_1: ; %Flow
; GFX10-NEXT: ; in Loop: Header=BB5_2 Depth=1
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX10-NEXT: s_and_b32 s1, exec_lo, s6
; GFX10-NEXT: s_or_b32 s4, s1, s4
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
index 69baf613fdfe5..a8b27ecd7e9fc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
@@ -131,7 +131,7 @@ define amdgpu_cs void @loop_with_1break(ptr addrspace(1) %x, i32 %x.size, ptr ad
; GFX10-NEXT: s_andn2_b32 s6, s9, exec_lo
; GFX10-NEXT: s_and_b32 s5, exec_lo, s5
; GFX10-NEXT: s_or_b32 s9, s6, s5
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s8
; GFX10-NEXT: s_cbranch_execz .LBB2_5
; GFX10-NEXT: .LBB2_3: ; %A
@@ -241,7 +241,7 @@ define void @nested_loops_temporal_divergence_inner(float %pre.cond.val, i32 %n.
; GFX10-NEXT: v_add_co_ci_u32_e64 v7, s4, v5, v7, s4
; GFX10-NEXT: s_or_b32 s8, vcc_lo, s8
; GFX10-NEXT: flat_store_byte v[6:7], v0
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s8
; GFX10-NEXT: s_cbranch_execnz .LBB3_1
; GFX10-NEXT: ; %bb.4: ; %exit
@@ -332,7 +332,7 @@ define void @nested_loops_temporal_divergence_outer(float %pre.cond.val, i32 %n.
; GFX10-NEXT: v_add_co_ci_u32_e64 v7, s4, v5, v7, s4
; GFX10-NEXT: s_or_b32 s8, vcc_lo, s8
; GFX10-NEXT: flat_store_byte v[6:7], v0
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s8
; GFX10-NEXT: s_cbranch_execnz .LBB4_1
; GFX10-NEXT: ; %bb.4: ; %exit
@@ -423,7 +423,7 @@ define void @nested_loops_temporal_divergence_both(float %pre.cond.val, i32 %n.i
; GFX10-NEXT: v_add_co_ci_u32_e64 v9, s4, v5, v9, s4
; GFX10-NEXT: s_or_b32 s8, vcc_lo, s8
; GFX10-NEXT: flat_store_byte v[8:9], v0
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s8
; GFX10-NEXT: s_cbranch_execnz .LBB5_1
; GFX10-NEXT: ; %bb.4: ; %exit
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
index 990e4f67e420d..a28827a8c4683 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
@@ -28,7 +28,7 @@ define i32 @v_extract_v64i32_varidx(ptr addrspace(1) %ptr, i32 %idx) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_lshlrev_b32_e32 v2, 2, v2
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-NEXT: global_load_b32 v0, v[0:1], off
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -61,7 +61,7 @@ define i16 @v_extract_v128i16_varidx(ptr addrspace(1) %ptr, i32 %idx) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_lshlrev_b32_e32 v2, 1, v2
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-NEXT: global_load_u16 v0, v[0:1], off
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -94,7 +94,7 @@ define i64 @v_extract_v32i64_varidx(ptr addrspace(1) %ptr, i32 %idx) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_lshlrev_b32_e32 v2, 3, v2
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX12-NEXT: s_wait_loadcnt 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
index 96cf528056cb1..39a793ce67bb9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
@@ -161,7 +161,7 @@ define amdgpu_ps void @s_fabs_f64_salu_use(double inreg %in, i32 inreg %val, ptr
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT: v_readfirstlane_b32 s1, v3
; GFX12-NEXT: s_cselect_b64 s[0:1], s[0:1], 0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX12-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
index 1b879a604d715..62b264a537457 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
@@ -174,7 +174,7 @@ define half @v_fdiv_f16(half %a, half %b) {
; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v1
; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v0
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v3, v3, v2
; GFX11-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v2
@@ -218,7 +218,7 @@ define half @v_fdiv_f16_afn(half %a, half %b) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_rcp_f16_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv afn half %a, %b
@@ -384,7 +384,7 @@ define half @v_fdiv_f16_ulp25(half %a, half %b) {
; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v1
; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v0
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v3, v3, v2
; GFX11-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]
; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v2
@@ -672,7 +672,7 @@ define half @v_fdiv_f16_afn_ulp25(half %a, half %b) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_rcp_f16_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv afn half %a, %b
@@ -739,7 +739,7 @@ define half @v_fdiv_f16_arcp_ulp25(half %a, half %b) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_rcp_f16_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv arcp half %a, %b
@@ -1041,7 +1041,7 @@ define <2 x half> @v_fdiv_v2f16(<2 x half> %a, <2 x half> %b) {
; GFX11-NEXT: v_rcp_f32_e32 v3, v3
; GFX11-NEXT: v_cvt_f32_f16_e32 v7, v5
; GFX11-NEXT: v_rcp_f32_e32 v4, v4
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_dual_mul_f32 v6, v6, v3 :: v_dual_mul_f32 v7, v7, v4
; GFX11-NEXT: v_fma_mix_f32 v8, -v1, v6, v0 op_sel_hi:[1,0,1]
; GFX11-NEXT: v_fma_mix_f32 v9, -v1, v7, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]
@@ -1115,7 +1115,7 @@ define <2 x half> @v_fdiv_v2f16_afn(<2 x half> %a, <2 x half> %b) {
; GFX11-NEXT: v_rcp_f16_e32 v1, v1
; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX11-NEXT: v_rcp_f16_e32 v2, v2
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1
; GFX11-NEXT: v_mul_f16_e32 v1, v3, v2
; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1
@@ -1419,7 +1419,7 @@ define <2 x half> @v_fdiv_v2f16_ulp25(<2 x half> %a, <2 x half> %b) {
; GFX11-NEXT: v_rcp_f32_e32 v3, v3
; GFX11-NEXT: v_cvt_f32_f16_e32 v7, v5
; GFX11-NEXT: v_rcp_f32_e32 v4, v4
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_dual_mul_f32 v6, v6, v3 :: v_dual_mul_f32 v7, v7, v4
; GFX11-NEXT: v_fma_mix_f32 v8, -v1, v6, v0 op_sel_hi:[1,0,1]
; GFX11-NEXT: v_fma_mix_f32 v9, -v1, v7, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]
@@ -1700,7 +1700,7 @@ define <2 x half> @v_rcp_v2f16(<2 x half> %x) {
; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v1
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_rcp_f32_e32 v3, v3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_mix_f32 v5, -v0, v2, v4 op_sel_hi:[1,0,0]
; GFX11-NEXT: v_fma_mix_f32 v6, -v0, v3, v4 op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX11-NEXT: v_fma_f32 v5, v5, v2, v2
@@ -1981,7 +1981,7 @@ define <2 x half> @v_neg_rcp_v2f16(<2 x half> %x) {
; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v1
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_rcp_f32_e32 v3, v3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_mix_f32 v5, v0, v2, v4 op_sel_hi:[1,0,0]
; GFX11-NEXT: v_fma_mix_f32 v6, v0, v3, v4 op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX11-NEXT: v_fma_f32 v5, v5, v2, -v2
@@ -2277,7 +2277,7 @@ define <2 x half> @v_rcp_v2f16_fabs(<2 x half> %x) {
; GFX11-NEXT: v_cvt_f32_f16_e32 v4, v2
; GFX11-NEXT: v_rcp_f32_e32 v4, v4
; GFX11-NEXT: v_mov_b32_e32 v5, 1.0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_mix_f32 v7, -|v0|, v4, v5 op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX11-NEXT: v_fma_f32 v7, v7, v4, v4
; GFX11-NEXT: v_fma_mix_f32 v0, -|v0|, v7, v5 op_sel:[1,0,0] op_sel_hi:[1,0,0]
@@ -2288,7 +2288,7 @@ define <2 x half> @v_rcp_v2f16_fabs(<2 x half> %x) {
; GFX11-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX11-NEXT: v_rcp_f32_e32 v3, v3
; GFX11-NEXT: v_div_fixup_f16 v0, v0, v2, 1.0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_mix_f32 v6, -v1, v3, v5 op_sel_hi:[1,0,0]
; GFX11-NEXT: v_fma_f32 v6, v6, v3, v3
; GFX11-NEXT: v_fma_mix_f32 v8, -v1, v6, v5 op_sel_hi:[1,0,0]
@@ -2579,7 +2579,7 @@ define <2 x half> @v_neg_rcp_v2f16_fabs(<2 x half> %x) {
; GFX11-NEXT: v_cvt_f32_f16_e32 v4, v2
; GFX11-NEXT: v_rcp_f32_e32 v4, v4
; GFX11-NEXT: v_mov_b32_e32 v5, -1.0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_mix_f32 v7, |v0|, v4, v5 op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX11-NEXT: v_fma_f32 v7, v7, v4, -v4
; GFX11-NEXT: v_fma_mix_f32 v0, -|v0|, v7, v5 op_sel:[1,0,0] op_sel_hi:[1,0,0]
@@ -2590,7 +2590,7 @@ define <2 x half> @v_neg_rcp_v2f16_fabs(<2 x half> %x) {
; GFX11-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX11-NEXT: v_rcp_f32_e32 v3, v3
; GFX11-NEXT: v_div_fixup_f16 v0, v0, v2, -1.0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_mix_f32 v6, v1, v3, v5 op_sel_hi:[1,0,0]
; GFX11-NEXT: v_fma_f32 v6, v6, v3, -v3
; GFX11-NEXT: v_fma_mix_f32 v8, -v1, v6, v5 op_sel_hi:[1,0,0]
@@ -2704,7 +2704,7 @@ define <2 x half> @v_rcp_v2f16_arcp(<2 x half> %x) {
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX11-NEXT: v_rcp_f16_e32 v0, v0
; GFX11-NEXT: v_rcp_f16_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv arcp <2 x half> <half 1.0, half 1.0>, %x
@@ -2753,7 +2753,7 @@ define <2 x half> @v_rcp_v2f16_arcp_afn(<2 x half> %x) {
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX11-NEXT: v_rcp_f16_e32 v0, v0
; GFX11-NEXT: v_rcp_f16_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv arcp afn <2 x half> <half 1.0, half 1.0>, %x
@@ -3020,7 +3020,7 @@ define <2 x half> @v_rcp_v2f16_ulp25(<2 x half> %x) {
; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v1
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_rcp_f32_e32 v3, v3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_mix_f32 v5, -v0, v2, v4 op_sel_hi:[1,0,0]
; GFX11-NEXT: v_fma_mix_f32 v6, -v0, v3, v4 op_sel:[1,0,0] op_sel_hi:[1,0,0]
; GFX11-NEXT: v_fma_f32 v5, v5, v2, v2
@@ -3094,7 +3094,7 @@ define <2 x half> @v_fdiv_v2f16_afn_ulp25(<2 x half> %a, <2 x half> %b) {
; GFX11-NEXT: v_rcp_f16_e32 v1, v1
; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX11-NEXT: v_rcp_f16_e32 v2, v2
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1
; GFX11-NEXT: v_mul_f16_e32 v1, v3, v2
; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1
@@ -3212,7 +3212,7 @@ define <2 x half> @v_fdiv_v2f16_arcp_ulp25(<2 x half> %a, <2 x half> %b) {
; GFX11-NEXT: v_rcp_f16_e32 v1, v1
; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX11-NEXT: v_rcp_f16_e32 v2, v2
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1
; GFX11-NEXT: v_mul_f16_e32 v1, v3, v2
; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1
@@ -3274,7 +3274,7 @@ define <2 x half> @v_fdiv_v2f16_arcp_afn_ulp25(<2 x half> %a, <2 x half> %b) {
; GFX11-NEXT: v_rcp_f16_e32 v1, v1
; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX11-NEXT: v_rcp_f16_e32 v2, v2
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1
; GFX11-NEXT: v_mul_f16_e32 v1, v3, v2
; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1
@@ -3445,7 +3445,7 @@ define amdgpu_ps i16 @s_fdiv_f16(i16 inreg %a.arg, i16 inreg %b.arg) {
; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s1
; GFX11-NEXT: v_cvt_f32_f16_e32 v1, s0
; GFX11-NEXT: v_rcp_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v1, v1, v0
; GFX11-NEXT: v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]
; GFX11-NEXT: v_fmac_f32_e32 v1, v2, v0
@@ -3523,7 +3523,7 @@ define amdgpu_ps i16 @s_fdiv_f16_arcp(i16 inreg %a.arg, i16 inreg %b.arg) {
; GFX11-LABEL: s_fdiv_f16_arcp:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_rcp_f16_e32 v0, s1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f16_e32 v0, s0, v0
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: ; return to shader part epilog
@@ -3562,7 +3562,7 @@ define amdgpu_ps i16 @s_fdiv_f16_afn(i16 inreg %a.arg, i16 inreg %b.arg) {
; GFX11-LABEL: s_fdiv_f16_afn:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_rcp_f16_e32 v0, s1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f16_e32 v0, s0, v0
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: ; return to shader part epilog
@@ -3883,7 +3883,7 @@ define amdgpu_ps i32 @s_fdiv_v2f16(i32 inreg %a.arg, i32 inreg %b.arg) {
; GFX11-NEXT: v_cvt_f32_f16_e32 v3, s3
; GFX11-NEXT: v_rcp_f32_e32 v0, v0
; GFX11-NEXT: v_rcp_f32_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_dual_mul_f32 v2, v2, v0 :: v_dual_mul_f32 v3, v3, v1
; GFX11-NEXT: v_fma_mix_f32 v4, -s1, v2, s0 op_sel_hi:[1,0,1]
; GFX11-NEXT: v_fma_mix_f32 v5, -s2, v3, s3 op_sel_hi:[1,0,1]
@@ -3963,7 +3963,7 @@ define amdgpu_ps i16 @s_rcp_f16(i16 inreg %a.arg) {
; GFX11-LABEL: s_rcp_f16:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_rcp_f16_e32 v0, s0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: ; return to shader part epilog
%a = bitcast i16 %a.arg to half
@@ -4027,7 +4027,7 @@ define amdgpu_ps i16 @s_neg_rcp_f16(i16 inreg %a.arg) {
; GFX11-LABEL: s_neg_rcp_f16:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_rcp_f16_e64 v0, -s0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: ; return to shader part epilog
%a = bitcast i16 %a.arg to half
@@ -4097,7 +4097,7 @@ define amdgpu_ps i16 @s_rsq_f16(i16 inreg %a.arg) {
; GFX11-LABEL: s_rsq_f16:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_rsq_f16_e32 v0, s0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: ; return to shader part epilog
%a = bitcast i16 %a.arg to half
@@ -4384,12 +4384,12 @@ define amdgpu_ps i32 @s_rsq_v2f16(i32 inreg %a.arg) {
; GFX11-NEXT: v_sqrt_f16_e32 v0, s0
; GFX11-NEXT: v_sqrt_f16_e32 v1, s1
; GFX11-NEXT: v_mov_b32_e32 v4, -1.0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v0
; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v1
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_rcp_f32_e32 v3, v3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_mix_f32 v5, v0, v2, v4 op_sel_hi:[1,0,0]
; GFX11-NEXT: v_fma_mix_f32 v6, v1, v3, v4 op_sel_hi:[1,0,0]
; GFX11-NEXT: v_fma_f32 v5, v5, v2, -v2
@@ -4540,7 +4540,7 @@ define half @v_neg_rsq_f16(half %a) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_sqrt_f16_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_rcp_f16_e64 v0, -v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%sqrt = call contract half @llvm.sqrt.f16(half %a)
@@ -4615,7 +4615,7 @@ define { half, half } @v_rsq_f16_multi_use(half %a) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_sqrt_f16_e32 v2, v0
; GFX11-NEXT: v_rsq_f16_e32 v1, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mov_b32_e32 v0, v2
; GFX11-NEXT: s_setpc_b64 s[30:31]
%sqrt = call contract half @llvm.sqrt.f16(half %a)
@@ -4689,7 +4689,7 @@ define half @v_rsq_f16_missing_contract0(half %a) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_sqrt_f16_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_rcp_f16_e32 v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%sqrt = call half @llvm.sqrt.f16(half %a)
@@ -4761,7 +4761,7 @@ define half @v_rsq_f16_missing_contract1(half %a) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_sqrt_f16_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_rcp_f16_e32 v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%sqrt = call contract half @llvm.sqrt.f16(half %a)
@@ -4833,7 +4833,7 @@ define half @v_neg_rsq_f16_missing_contract0(half %a) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_sqrt_f16_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_rcp_f16_e64 v0, -v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%sqrt = call half @llvm.sqrt.f16(half %a)
@@ -4905,7 +4905,7 @@ define half @v_neg_rsq_f16_missing_contract1(half %a) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_sqrt_f16_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_rcp_f16_e64 v0, -v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%sqrt = call contract half @llvm.sqrt.f16(half %a)
@@ -4977,7 +4977,7 @@ define half @v_neg_rsq_f16_fabs(half %a) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_sqrt_f16_e64 v0, |v0|
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_rcp_f16_e64 v0, -v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%a.fabs = call half @llvm.fabs.f16(half %a)
@@ -5112,7 +5112,7 @@ define half @v_neg_rsq_f16_arcp(half %a) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_sqrt_f16_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_rcp_f16_e64 v0, -v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%sqrt = call contract half @llvm.sqrt.f16(half %a)
@@ -5178,7 +5178,7 @@ define half @v_rsq_f16_afn_nocontract(half %a) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_sqrt_f16_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_rcp_f16_e32 v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%sqrt = call half @llvm.sqrt.f16(half %a)
@@ -5452,12 +5452,12 @@ define <2 x half> @v_rsq_v2f16(<2 x half> %a) {
; GFX11-NEXT: v_sqrt_f16_e32 v0, v0
; GFX11-NEXT: v_mov_b32_e32 v4, 1.0
; GFX11-NEXT: v_sqrt_f16_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v0
; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v1
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_rcp_f32_e32 v3, v3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_mix_f32 v5, -v0, v2, v4 op_sel_hi:[1,0,0]
; GFX11-NEXT: v_fma_mix_f32 v6, -v1, v3, v4 op_sel_hi:[1,0,0]
; GFX11-NEXT: v_fma_f32 v5, v5, v2, v2
@@ -5745,12 +5745,12 @@ define <2 x half> @v_neg_rsq_v2f16(<2 x half> %a) {
; GFX11-NEXT: v_sqrt_f16_e32 v0, v0
; GFX11-NEXT: v_mov_b32_e32 v4, -1.0
; GFX11-NEXT: v_sqrt_f16_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v0
; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v1
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_rcp_f32_e32 v3, v3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_mix_f32 v5, v0, v2, v4 op_sel_hi:[1,0,0]
; GFX11-NEXT: v_fma_mix_f32 v6, v1, v3, v4 op_sel_hi:[1,0,0]
; GFX11-NEXT: v_fma_f32 v5, v5, v2, -v2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
index 3ea918ecef843..b54cf77d79cad 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
@@ -161,7 +161,7 @@ define float @v_fdiv_f32(float %a, float %b) {
; GFX11-IEEE-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v3, v2
-; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-IEEE-NEXT: v_fma_f32 v4, -v2, v3, 1.0
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v3, v4, v3
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -183,7 +183,7 @@ define float @v_fdiv_f32(float %a, float %b) {
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-FLUSH-NEXT: s_denorm_mode 3
-; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -363,7 +363,7 @@ define float @v_fdiv_f32_dynamic_denorm(float %a, float %b) #0 {
; GFX11-IEEE-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-IEEE-NEXT: s_denorm_mode 15
-; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v3
@@ -387,7 +387,7 @@ define float @v_fdiv_f32_dynamic_denorm(float %a, float %b) #0 {
; GFX11-FLUSH-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-FLUSH-NEXT: s_denorm_mode 3
-; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
@@ -425,7 +425,7 @@ define float @v_fdiv_f32_afn(float %a, float %b) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_rcp_f32_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv afn float %a, %b
@@ -498,7 +498,7 @@ define float @v_fdiv_f32_ulp25(float %a, float %b) {
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-IEEE-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_ldexp_f32 v0, v2, v0
@@ -513,7 +513,7 @@ define float @v_fdiv_f32_ulp25(float %a, float %b) {
; GFX11-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v2
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v1, v1
-; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX11-FLUSH-NEXT: v_mul_f32_e32 v0, v2, v0
; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]
@@ -625,7 +625,7 @@ define float @v_fdiv_f32_dynamic_25ulp(float %x, float %y) #0 {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v0, v2, v0
@@ -782,7 +782,7 @@ define float @v_rcp_f32(float %x) {
; GFX11-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v2, v1
-; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-IEEE-NEXT: v_fma_f32 v3, -v1, v2, 1.0
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v2, v3, v2
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -804,7 +804,7 @@ define float @v_rcp_f32(float %x) {
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v2, v1
; GFX11-FLUSH-NEXT: s_denorm_mode 3
-; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v2, v4, v2
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -966,7 +966,7 @@ define float @v_rcp_f32_arcp(float %x) {
; GFX11-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v2, v1
-; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-IEEE-NEXT: v_fma_f32 v3, -v1, v2, 1.0
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v2, v3, v2
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -988,7 +988,7 @@ define float @v_rcp_f32_arcp(float %x) {
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v2, v1
; GFX11-FLUSH-NEXT: s_denorm_mode 3
-; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v2, v4, v2
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1072,7 +1072,7 @@ define float @v_rcp_f32_ulp25(float %x) {
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v1, v1
; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v0, 0, v0
-; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-IEEE-NEXT: v_ldexp_f32 v0, v1, v0
; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]
;
@@ -1104,7 +1104,7 @@ define float @v_fdiv_f32_afn_ulp25(float %a, float %b) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_rcp_f32_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv afn float %a, %b, !fpmath !0
@@ -1159,7 +1159,7 @@ define float @v_fdiv_f32_arcp_ulp25(float %a, float %b) {
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v1, 0, v1
-; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-IEEE-NEXT: v_ldexp_f32 v1, v2, v1
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_mul_f32_e32 v0, v0, v1
@@ -1169,7 +1169,7 @@ define float @v_fdiv_f32_arcp_ulp25(float %a, float %b) {
; GFX11-FLUSH: ; %bb.0:
; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v1, v1
-; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv arcp float %a, %b, !fpmath !0
@@ -1421,7 +1421,7 @@ define <2 x float> @v_fdiv_v2f32(<2 x float> %a, <2 x float> %b) {
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v6, v4
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v7, v5
-; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-IEEE-NEXT: v_fma_f32 v8, -v4, v6, 1.0
; GFX11-IEEE-NEXT: v_fma_f32 v9, -v5, v7, 1.0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
@@ -1456,7 +1456,7 @@ define <2 x float> @v_fdiv_v2f32(<2 x float> %a, <2 x float> %b) {
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v5, v4
; GFX11-FLUSH-NEXT: s_denorm_mode 3
-; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v7, v5
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1474,7 +1474,7 @@ define <2 x float> @v_fdiv_v2f32(<2 x float> %a, <2 x float> %b) {
; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v2, v0
; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, v1, v3, v1
; GFX11-FLUSH-NEXT: s_denorm_mode 3
-; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FLUSH-NEXT: v_fma_f32 v4, -v6, v5, 1.0
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v4, v5
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1516,7 +1516,7 @@ define <2 x float> @v_fdiv_v2f32_afn(<2 x float> %a, <2 x float> %b) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_rcp_f32_e32 v3, v3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv afn <2 x float> %a, %b
@@ -1627,7 +1627,7 @@ define <2 x float> @v_fdiv_v2f32_ulp25(<2 x float> %a, <2 x float> %b) {
; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v2, v6, v2
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v3, v7, v3
-; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-IEEE-NEXT: v_dual_mul_f32 v0, v0, v4 :: v_dual_mul_f32 v1, v1, v5
; GFX11-IEEE-NEXT: v_ldexp_f32 v0, v0, v2
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -1647,7 +1647,7 @@ define <2 x float> @v_fdiv_v2f32_ulp25(<2 x float> %a, <2 x float> %b) {
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v3
-; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FLUSH-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3
; GFX11-FLUSH-NEXT: v_dual_mul_f32 v0, v4, v0 :: v_dual_mul_f32 v1, v5, v1
; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]
@@ -1900,7 +1900,7 @@ define <2 x float> @v_rcp_v2f32(<2 x float> %x) {
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v4, v2
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v5, v3
-; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.0
; GFX11-IEEE-NEXT: v_fma_f32 v7, -v3, v5, 1.0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
@@ -1935,7 +1935,7 @@ define <2 x float> @v_rcp_v2f32(<2 x float> %x) {
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-FLUSH-NEXT: s_denorm_mode 3
-; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1953,7 +1953,7 @@ define <2 x float> @v_rcp_v2f32(<2 x float> %x) {
; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
; GFX11-FLUSH-NEXT: s_denorm_mode 3
-; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v4, v3, 1.0
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -2216,7 +2216,7 @@ define <2 x float> @v_rcp_v2f32_arcp(<2 x float> %x) {
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v4, v2
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v5, v3
-; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.0
; GFX11-IEEE-NEXT: v_fma_f32 v7, -v3, v5, 1.0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
@@ -2251,7 +2251,7 @@ define <2 x float> @v_rcp_v2f32_arcp(<2 x float> %x) {
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-FLUSH-NEXT: s_denorm_mode 3
-; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -2269,7 +2269,7 @@ define <2 x float> @v_rcp_v2f32_arcp(<2 x float> %x) {
; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
; GFX11-FLUSH-NEXT: s_denorm_mode 3
-; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v4, v3, 1.0
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -2375,7 +2375,7 @@ define <2 x float> @v_rcp_v2f32_ulp25(<2 x float> %x) {
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v0, 0, v0
; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v1, 0, v1
-; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-IEEE-NEXT: v_ldexp_f32 v0, v2, v0
; GFX11-IEEE-NEXT: v_ldexp_f32 v1, v3, v1
; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]
@@ -2414,7 +2414,7 @@ define <2 x float> @v_fdiv_v2f32_afn_ulp25(<2 x float> %a, <2 x float> %b) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_rcp_f32_e32 v3, v3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv afn <2 x float> %a, %b, !fpmath !0
@@ -2492,7 +2492,7 @@ define <2 x float> @v_fdiv_v2f32_arcp_ulp25(<2 x float> %a, <2 x float> %b) {
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v2, 0, v2
; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v3, 0, v3
-; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-IEEE-NEXT: v_ldexp_f32 v2, v4, v2
; GFX11-IEEE-NEXT: v_ldexp_f32 v3, v5, v3
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -2504,7 +2504,7 @@ define <2 x float> @v_fdiv_v2f32_arcp_ulp25(<2 x float> %a, <2 x float> %b) {
; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v3
-; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FLUSH-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3
; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv arcp <2 x float> %a, %b, !fpmath !0
@@ -2535,7 +2535,7 @@ define <2 x float> @v_fdiv_v2f32_arcp_afn_ulp25(<2 x float> %a, <2 x float> %b)
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_rcp_f32_e32 v3, v3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv afn arcp <2 x float> %a, %b, !fpmath !0
@@ -2768,7 +2768,7 @@ define float @v_fdiv_f32_dynamic__nnan_ninf(float %x, float %y, float %z) #0 {
; GFX11-IEEE-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-IEEE-NEXT: s_denorm_mode 15
-; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v3
@@ -2792,7 +2792,7 @@ define float @v_fdiv_f32_dynamic__nnan_ninf(float %x, float %y, float %z) #0 {
; GFX11-FLUSH-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-FLUSH-NEXT: s_denorm_mode 3
-; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
@@ -2919,7 +2919,7 @@ define float @v_fdiv_f32_dynamic_25ulp__nnan_ninf(float %x, float %y, float %z)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v0, v2, v0
@@ -3042,7 +3042,7 @@ define float @v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user(float %x, fl
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f32_e32 v3, v3
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v3, v4, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v0, v3, v0
@@ -3293,7 +3293,7 @@ define float @v_fdiv_neglhs_f32_dynamic(float %x, float %y) #0 {
; GFX11-IEEE-NEXT: v_div_scale_f32 v2, vcc_lo, v2, v1, v2
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v4, v3
; GFX11-IEEE-NEXT: s_denorm_mode 15
-; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v4, v5, v4
@@ -3319,7 +3319,7 @@ define float @v_fdiv_neglhs_f32_dynamic(float %x, float %y) #0 {
; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, v2, v1, v2
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v4, v3
; GFX11-FLUSH-NEXT: s_denorm_mode 3
-; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v4
@@ -3447,7 +3447,7 @@ define float @v_fdiv_neglhs_f32_dynamic_25ulp(float %x, float %y) #0 {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v0, v2, v0
@@ -3697,7 +3697,7 @@ define float @v_fdiv_negrhs_f32_dynamic(float %x, float %y) #0 {
; GFX11-IEEE-NEXT: v_div_scale_f32 v2, vcc_lo, v0, v2, v0
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v4, v3
; GFX11-IEEE-NEXT: s_denorm_mode 15
-; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v4, v5, v4
@@ -3723,7 +3723,7 @@ define float @v_fdiv_negrhs_f32_dynamic(float %x, float %y) #0 {
; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, v0, v2, v0
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v4, v3
; GFX11-FLUSH-NEXT: s_denorm_mode 3
-; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v4
@@ -3983,7 +3983,7 @@ define float @v_fdiv_f32_constrhs0_dynamic(float %x) #0 {
; GFX11-IEEE-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v2, v1
; GFX11-IEEE-NEXT: s_denorm_mode 15
-; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v2, v4, v2
@@ -4007,7 +4007,7 @@ define float @v_fdiv_f32_constrhs0_dynamic(float %x) #0 {
; GFX11-FLUSH-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v2, v1
; GFX11-FLUSH-NEXT: s_denorm_mode 3
-; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v2, v4, v2
@@ -4112,7 +4112,7 @@ define float @v_fdiv_f32_constrhs0_dynamic_25ulp(float %x) #0 {
; GFX11-NEXT: v_rcp_f32_e32 v1, 0x3f40e400
; GFX11-NEXT: v_frexp_mant_f32_e32 v2, v0
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_dual_mul_f32 v1, v2, v1 :: v_dual_add_nc_u32 v0, -14, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v0, v1, v0
@@ -4361,7 +4361,7 @@ define float @v_fdiv_f32_constlhs0_dynamic(float %x) #0 {
; GFX11-IEEE-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v2, v1
; GFX11-IEEE-NEXT: s_denorm_mode 15
-; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v2, v4, v2
@@ -4385,7 +4385,7 @@ define float @v_fdiv_f32_constlhs0_dynamic(float %x) #0 {
; GFX11-FLUSH-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v2, v1
; GFX11-FLUSH-NEXT: s_denorm_mode 3
-; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v2, v4, v2
@@ -4495,7 +4495,7 @@ define float @v_fdiv_f32_constlhs0_dynamic_25ulp(float %x) #0 {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f32_e32 v1, v1
; GFX11-NEXT: v_sub_nc_u32_e32 v0, 14, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v1, 0x3f40e400, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v0, v1, v0
@@ -4734,7 +4734,7 @@ define float @v_fdiv_f32_dynamic_nodenorm_x(float nofpclass(sub) %x, float %y) #
; GFX11-IEEE-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-IEEE-NEXT: s_denorm_mode 15
-; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v3
@@ -4758,7 +4758,7 @@ define float @v_fdiv_f32_dynamic_nodenorm_x(float nofpclass(sub) %x, float %y) #
; GFX11-FLUSH-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-FLUSH-NEXT: s_denorm_mode 3
-; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
@@ -4885,7 +4885,7 @@ define float @v_fdiv_f32_dynamic_25ulp_nodenorm_x(float nofpclass(sub) %x, float
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v0, v2, v0
@@ -5123,7 +5123,7 @@ define float @v_fdiv_f32_dynamic_nodenorm_y(float %x, float nofpclass(sub) %y) #
; GFX11-IEEE-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-IEEE-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-IEEE-NEXT: s_denorm_mode 15
-; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v3
@@ -5147,7 +5147,7 @@ define float @v_fdiv_f32_dynamic_nodenorm_y(float %x, float nofpclass(sub) %y) #
; GFX11-FLUSH-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-FLUSH-NEXT: s_denorm_mode 3
-; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3
@@ -5274,7 +5274,7 @@ define float @v_fdiv_f32_dynamic_25ulp_nodenorm_y(float %x, float nofpclass(sub)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v0, v2, v0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
index ea149cc2f4a9e..31fc1ee538957 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
@@ -89,7 +89,7 @@ define double @v_fdiv_f64(double %a, double %b) {
; GFX11-NEXT: v_div_scale_f64 v[10:11], vcc_lo, v[0:1], v[2:3], v[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f64_e32 v[6:7], v[4:5]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX11-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -137,7 +137,7 @@ define double @v_fdiv_f64_afn(double %a, double %b) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
@@ -228,7 +228,7 @@ define double @v_fdiv_f64_ulp25(double %a, double %b) {
; GFX11-NEXT: v_div_scale_f64 v[10:11], vcc_lo, v[0:1], v[2:3], v[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f64_e32 v[6:7], v[4:5]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX11-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -321,7 +321,7 @@ define double @v_rcp_f64(double %x) {
; GFX11-NEXT: v_div_scale_f64 v[8:9], vcc_lo, 1.0, v[0:1], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; GFX11-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -414,7 +414,7 @@ define double @v_rcp_f64_arcp(double %x) {
; GFX11-NEXT: v_div_scale_f64 v[8:9], vcc_lo, 1.0, v[0:1], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; GFX11-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -460,7 +460,7 @@ define double @v_rcp_f64_arcp_afn(double %x) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
@@ -551,7 +551,7 @@ define double @v_rcp_f64_ulp25(double %x) {
; GFX11-NEXT: v_div_scale_f64 v[8:9], vcc_lo, 1.0, v[0:1], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; GFX11-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -599,7 +599,7 @@ define double @v_fdiv_f64_afn_ulp25(double %a, double %b) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
@@ -690,7 +690,7 @@ define double @v_fdiv_f64_arcp_ulp25(double %a, double %b) {
; GFX11-NEXT: v_div_scale_f64 v[10:11], vcc_lo, v[0:1], v[2:3], v[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f64_e32 v[6:7], v[4:5]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX11-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -835,7 +835,7 @@ define <2 x double> @v_fdiv_v2f64(<2 x double> %a, <2 x double> %b) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_rcp_f64_e32 v[12:13], v[8:9]
; GFX11-NEXT: v_rcp_f64_e32 v[14:15], v[10:11]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
; GFX11-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -914,7 +914,7 @@ define <2 x double> @v_fdiv_v2f64_afn(<2 x double> %a, <2 x double> %b) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_rcp_f64_e32 v[8:9], v[4:5]
; GFX11-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0
; GFX11-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -1068,7 +1068,7 @@ define <2 x double> @v_fdiv_v2f64_ulp25(<2 x double> %a, <2 x double> %b) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_rcp_f64_e32 v[12:13], v[8:9]
; GFX11-NEXT: v_rcp_f64_e32 v[14:15], v[10:11]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
; GFX11-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -1228,7 +1228,7 @@ define <2 x double> @v_rcp_v2f64(<2 x double> %x) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_rcp_f64_e32 v[8:9], v[4:5]
; GFX11-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0
; GFX11-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -1388,7 +1388,7 @@ define <2 x double> @v_rcp_v2f64_arcp(<2 x double> %x) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_rcp_f64_e32 v[8:9], v[4:5]
; GFX11-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0
; GFX11-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -1463,7 +1463,7 @@ define <2 x double> @v_rcp_v2f64_arcp_afn(<2 x double> %x) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_rcp_f64_e32 v[4:5], v[0:1]
; GFX11-NEXT: v_rcp_f64_e32 v[6:7], v[2:3]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f64 v[8:9], -v[0:1], v[4:5], 1.0
; GFX11-NEXT: v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -1615,7 +1615,7 @@ define <2 x double> @v_rcp_v2f64_ulp25(<2 x double> %x) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_rcp_f64_e32 v[8:9], v[4:5]
; GFX11-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0
; GFX11-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -1694,7 +1694,7 @@ define <2 x double> @v_fdiv_v2f64_afn_ulp25(<2 x double> %a, <2 x double> %b) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_rcp_f64_e32 v[8:9], v[4:5]
; GFX11-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0
; GFX11-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -1848,7 +1848,7 @@ define <2 x double> @v_fdiv_v2f64_arcp_ulp25(<2 x double> %a, <2 x double> %b) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_rcp_f64_e32 v[12:13], v[8:9]
; GFX11-NEXT: v_rcp_f64_e32 v[14:15], v[10:11]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
; GFX11-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -1927,7 +1927,7 @@ define <2 x double> @v_fdiv_v2f64_arcp_afn_ulp25(<2 x double> %a, <2 x double> %
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_rcp_f64_e32 v[8:9], v[4:5]
; GFX11-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f64 v[12:13], -v[4:5], v[8:9], 1.0
; GFX11-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
index 2356dad5275c9..13d6597bd78f1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
@@ -2848,7 +2848,7 @@ define void @store_load_v3i32_unaligned(ptr addrspace(5) nocapture %arg) {
; GFX12-NEXT: s_mov_b32 s2, 3
; GFX12-NEXT: s_mov_b32 s1, 2
; GFX12-NEXT: s_mov_b32 s0, 1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v2, s1
; GFX12-NEXT: v_mov_b32_e32 v1, s0
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -3229,7 +3229,7 @@ define void @store_load_v4i32_unaligned(ptr addrspace(5) nocapture %arg) {
; GFX12-NEXT: s_mov_b32 s2, 3
; GFX12-NEXT: s_mov_b32 s1, 2
; GFX12-NEXT: s_mov_b32 s0, 1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v4, s3 :: v_dual_mov_b32 v3, s2
; GFX12-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
; GFX12-NEXT: s_wait_storecnt 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
index 8a260926d0a4f..ebc28cb005538 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
@@ -161,7 +161,7 @@ define amdgpu_ps void @s_fneg_f64_salu_use(double inreg %in, i32 inreg %val, ptr
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT: v_readfirstlane_b32 s1, v3
; GFX12-NEXT: s_cselect_b64 s[0:1], s[0:1], 0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX12-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
index 99261cc269858..98a26a4e672b9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
@@ -109,7 +109,7 @@ define float @v_pow_f32(float %x, float %y) {
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_log_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
@@ -119,7 +119,7 @@ define float @v_pow_f32(float %x, float %y) {
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%pow = call float @llvm.pow.f32(float %x, float %y)
@@ -287,7 +287,7 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX11-NEXT: v_ldexp_f32 v1, v1, v5
; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s0
; GFX11-NEXT: v_log_f32_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_dual_sub_f32 v1, v1, v5 :: v_dual_lshlrev_b32 v4, 5, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_ldexp_f32 v0, v0, v4
@@ -298,7 +298,7 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, s0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_dual_sub_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v3
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v2
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0
@@ -306,13 +306,13 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX11-NEXT: v_exp_f32_e32 v1, v1
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_ldexp_f32 v1, v1, v3
; GFX11-NEXT: v_add_f32_e32 v0, v0, v2
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_ldexp_f32 v0, v0, v2
; GFX11-NEXT: s_setpc_b64 s[30:31]
%pow = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> %y)
@@ -377,7 +377,7 @@ define half @v_pow_f16(half %x, half %y) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1
@@ -391,7 +391,7 @@ define half @v_pow_f16(half %x, half %y) {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1
@@ -496,7 +496,7 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v1.l
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.h
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.l
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -519,7 +519,7 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -530,7 +530,7 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: v_exp_f16_e32 v1, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_exp_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -641,7 +641,7 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.l
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -666,7 +666,7 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_log_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX11-FAKE16-NEXT: v_dual_mul_dx9_zero_f32 v1, v2, v1 :: v_dual_mul_dx9_zero_f32 v0, v0, v3
@@ -676,7 +676,7 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_exp_f16_e32 v1, v1
; GFX11-FAKE16-NEXT: v_exp_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
@@ -789,7 +789,7 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v1.l
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.h
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.l
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -812,7 +812,7 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v3
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
@@ -824,7 +824,7 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: v_exp_f16_e32 v1, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_exp_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -946,7 +946,7 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v1.l
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.h
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.l
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -972,7 +972,7 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v3
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -983,7 +983,7 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: v_exp_f16_e32 v1, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_exp_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -1102,7 +1102,7 @@ define float @v_pow_f32_fabs_lhs(float %x, float %y) {
; GFX11-NEXT: v_ldexp_f32 v0, |v0|, v2
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
; GFX11-NEXT: v_log_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1
@@ -1112,7 +1112,7 @@ define float @v_pow_f32_fabs_lhs(float %x, float %y) {
; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: v_exp_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fabs.x = call float @llvm.fabs.f32(float %x)
@@ -1223,7 +1223,7 @@ define float @v_pow_f32_fabs_rhs(float %x, float %y) {
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_log_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, v0, |v1|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
@@ -1233,7 +1233,7 @@ define float @v_pow_f32_fabs_rhs(float %x, float %y) {
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fabs.y = call float @llvm.fabs.f32(float %y)
@@ -1344,7 +1344,7 @@ define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) {
; GFX11-NEXT: v_ldexp_f32 v0, |v0|, v2
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
; GFX11-NEXT: v_log_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, v0, |v1|
@@ -1354,7 +1354,7 @@ define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) {
; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: v_exp_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fabs.x = call float @llvm.fabs.f32(float %x)
@@ -1461,7 +1461,7 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v1, s0, v1
; GFX11-NEXT: v_log_f32_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_sub_f32_e32 v1, v1, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
@@ -1471,7 +1471,7 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: v_exp_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
; GFX11-NEXT: ; return to shader part epilog
%pow = call float @llvm.pow.f32(float %x, float %y)
@@ -1576,7 +1576,7 @@ define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) {
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_log_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, s0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
@@ -1586,7 +1586,7 @@ define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) {
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
; GFX11-NEXT: ; return to shader part epilog
%pow = call float @llvm.pow.f32(float %x, float %y)
@@ -1691,7 +1691,7 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v0, s0, v0
; GFX11-NEXT: v_log_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, s1, v0
@@ -1701,7 +1701,7 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: v_exp_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
; GFX11-NEXT: ; return to shader part epilog
%pow = call float @llvm.pow.f32(float %x, float %y)
@@ -1811,7 +1811,7 @@ define float @v_pow_f32_fneg_lhs(float %x, float %y) {
; GFX11-NEXT: v_ldexp_f32 v0, -v0, v2
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
; GFX11-NEXT: v_log_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1
@@ -1821,7 +1821,7 @@ define float @v_pow_f32_fneg_lhs(float %x, float %y) {
; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: v_exp_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.x = fneg float %x
@@ -1932,7 +1932,7 @@ define float @v_pow_f32_fneg_rhs(float %x, float %y) {
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_log_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, v0, -v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
@@ -1942,7 +1942,7 @@ define float @v_pow_f32_fneg_rhs(float %x, float %y) {
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.y = fneg float %y
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
index 715a7778351cc..54efb26ae1e01 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
@@ -133,7 +133,7 @@ define amdgpu_ps i7 @s_fshl_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_lshr_b32 s1, s1, 1
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
@@ -298,7 +298,7 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX11-NEXT: v_lshrrev_b16 v1, 1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v3
@@ -1560,7 +1560,7 @@ define amdgpu_ps i24 @s_fshl_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt)
; GFX11-NEXT: s_bfe_u32 s1, s1, 0x170001
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1720,7 +1720,7 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX11-NEXT: v_bfe_u32 v1, v1, 1, 23
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -2201,7 +2201,7 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX11-NEXT: s_and_b32 s5, s5, 0xff
; GFX11-NEXT: s_or_b32 s4, s4, s11
; GFX11-NEXT: s_lshl_b32 s5, s5, 8
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-NEXT: s_and_b32 s13, s13, 0xff
; GFX11-NEXT: s_or_b32 s5, s12, s5
@@ -2504,7 +2504,7 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX11-NEXT: v_bfe_u32 v3, v3, 1, 23
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX11-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll
index 4255d03c158e1..ec74b8882ea58 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll
@@ -9,7 +9,7 @@ define amdgpu_ps void @uniform_fshr_i32(i32 inreg %lhs, i32 inreg %rhs, i32 inre
; CHECK-NEXT: v_alignbit_b32 v2, s0, s1, v2
; CHECK-NEXT: v_readfirstlane_b32 s0, v2
; CHECK-NEXT: s_add_co_i32 s0, s0, s0
-; CHECK-NEXT: s_wait_alu 0xfffe
+; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0)
; CHECK-NEXT: v_mov_b32_e32 v2, s0
; CHECK-NEXT: flat_store_b32 v[0:1], v2
; CHECK-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
index 5aa5a6716c152..1e762f9a927f8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
@@ -134,7 +134,7 @@ define amdgpu_ps i7 @s_fshr_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX11-NEXT: s_and_b32 s1, s1, 0x7f
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -299,7 +299,7 @@ define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX11-NEXT: v_and_b32_e32 v1, 0x7f, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1576,7 +1576,7 @@ define amdgpu_ps i24 @s_fshr_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt)
; GFX11-NEXT: s_lshl_b32 s0, s0, 1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1741,7 +1741,7 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX11-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -2222,7 +2222,7 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX11-NEXT: s_and_b32 s5, s5, 0xff
; GFX11-NEXT: s_or_b32 s4, s4, s15
; GFX11-NEXT: s_lshl_b32 s5, s5, 8
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-NEXT: s_and_b32 s17, s17, 0xff
; GFX11-NEXT: s_or_b32 s5, s16, s5
@@ -2531,7 +2531,7 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX11-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX11-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_dual_mul_f32 v6, 0x4f7ffffe, v6 :: v_dual_lshlrev_b32 v1, 1, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cvt_u32_f32_e32 v6, v6
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
index 390f62d8193f7..714e8e465d3c6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
@@ -16,7 +16,7 @@ define amdgpu_kernel void @test_wave32(i32 %arg0, [8 x i32], i32 %saved) {
; GFX10-NEXT: .LBB0_2: ; %bb
; GFX10-NEXT: s_load_dword s0, s[8:9], 0x24
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: global_store_dword v[0:1], v0, off
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
index cbf17bd71a69e..c23afeb63a06a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
@@ -202,7 +202,7 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_vgpr_descr(i32 %node_ptr,
; GFX1013-NEXT: ; implicit-def: $vgpr11
; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10
; GFX1013-NEXT: ; implicit-def: $vgpr13_vgpr14
-; GFX1013-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1013-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1013-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1013-NEXT: s_cbranch_execnz .LBB6_1
; GFX1013-NEXT: ; %bb.2:
@@ -318,7 +318,7 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16_vgpr_descr(i32 %node_p
; GFX1013-NEXT: ; implicit-def: $vgpr9
; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX1013-NEXT: ; implicit-def: $vgpr11_vgpr12
-; GFX1013-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1013-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1013-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1013-NEXT: s_cbranch_execnz .LBB7_1
; GFX1013-NEXT: ; %bb.2:
@@ -433,7 +433,7 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_vgpr_descr(i64 %node_ptr
; GFX1013-NEXT: ; implicit-def: $vgpr12
; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11
; GFX1013-NEXT: ; implicit-def: $vgpr14_vgpr15
-; GFX1013-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1013-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1013-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1013-NEXT: s_cbranch_execnz .LBB8_1
; GFX1013-NEXT: ; %bb.2:
@@ -551,7 +551,7 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16_vgpr_descr(i64 %node
; GFX1013-NEXT: ; implicit-def: $vgpr10
; GFX1013-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8
; GFX1013-NEXT: ; implicit-def: $vgpr12_vgpr13
-; GFX1013-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1013-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1013-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1013-NEXT: s_cbranch_execnz .LBB9_1
; GFX1013-NEXT: ; %bb.2:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
index 50377e995b83f..26cdbb11d27d6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
@@ -171,7 +171,7 @@ define float @v_rsq_clamp_undef_f32() #0 {
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_s_rsq_f32 s0, s0
; GFX12-NEXT: v_mov_b32_e32 v0, 0xff7fffff
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_minmax_num_f32 v0, s0, 0x7f7fffff, v0
; GFX12-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
index fe002d69faf66..46070dd5d8c68 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
@@ -44,7 +44,7 @@ define i16 @v_powi_f16(i16 %l, i32 %r) {
; GFX11-TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v0.l
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.h
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
@@ -60,7 +60,7 @@ define i16 @v_powi_f16(i16 %l, i32 %r) {
; GFX11-FAKE16-NEXT: v_cvt_f32_i32_e32 v1, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1
@@ -137,7 +137,7 @@ define float @v_powi_f32(float %l, i32 %r) {
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_log_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
@@ -147,7 +147,7 @@ define float @v_powi_f32(float %l, i32 %r) {
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%res = call float @llvm.powi.f32.i32(float %l, i32 %r)
@@ -224,7 +224,7 @@ define float @v_powi_neg1_f32(float %l) {
; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f32_e32 v2, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v3, -v1, v2, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v2, v3, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -300,7 +300,7 @@ define float @v_powi_neg2_f32(float %l) {
; GFX11-NEXT: v_div_scale_f32 v1, null, v0, v0, 1.0
; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
; GFX11-NEXT: v_rcp_f32_e32 v2, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v3, -v1, v2, 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fmac_f32_e32 v2, v3, v2
@@ -477,7 +477,7 @@ define float @v_powi_neg128_f32(float %l) {
; GFX11-NEXT: v_div_scale_f32 v1, null, v0, v0, 1.0
; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
; GFX11-NEXT: v_rcp_f32_e32 v2, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v3, -v1, v2, 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fmac_f32_e32 v2, v3, v2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform-in-vgpr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform-in-vgpr.ll
index f12ec4dff8549..6b4008fcd1e4d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform-in-vgpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform-in-vgpr.ll
@@ -299,7 +299,7 @@ define amdgpu_ps void @sextload_and_zextload_P3_i8(ptr addrspace(3) inreg %ptra,
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: v_readfirstlane_b32 s1, v2
; GFX12-NEXT: s_add_co_i32 s0, s0, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v1, s0
; GFX12-NEXT: ds_store_b32 v0, v1
; GFX12-NEXT: s_endpgm
@@ -338,7 +338,7 @@ define amdgpu_ps void @sextload_and_zextload_P3_i16(ptr addrspace(3) inreg %ptra
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: v_readfirstlane_b32 s1, v2
; GFX12-NEXT: s_add_co_i32 s0, s0, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v1, s0
; GFX12-NEXT: ds_store_b32 v0, v1
; GFX12-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
index ba7fb1b119c96..1462b5965c0ab 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
@@ -1202,10 +1202,10 @@ define i128 @v_mul_i128(i128 %num, i128 %den) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_mad_co_u64_u32 v[12:13], vcc_lo, v8, v5, v[1:2]
; GFX12-NEXT: v_mad_co_u64_u32 v[1:2], s0, v9, v4, v[12:13]
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v7, s0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v6, vcc_lo
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_mad_co_u64_u32 v[5:6], null, v10, v5, v[3:4]
@@ -2774,38 +2774,38 @@ define i256 @v_mul_i256(i256 %num, i256 %den) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-NEXT: v_mad_co_u64_u32 v[5:6], null, v18, v12, v[3:4]
; GFX12-NEXT: v_mad_co_u64_u32 v[3:4], s0, v17, v11, v[1:2]
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v7, 0, 1, s0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-NEXT: v_mad_co_u64_u32 v[1:2], null, v19, v11, v[5:6]
; GFX12-NEXT: v_mad_co_u64_u32 v[5:6], vcc_lo, v18, v10, v[3:4]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
; GFX12-NEXT: v_mad_co_u64_u32 v[3:4], null, v20, v10, v[1:2]
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_mad_co_u64_u32 v[1:2], vcc_lo, v19, v9, v[5:6]
; GFX12-NEXT: v_mad_co_u64_u32 v[23:24], null, v21, v9, v[3:4]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v7, vcc_lo
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-NEXT: v_mad_co_u64_u32 v[4:5], vcc_lo, v20, v8, v[1:2]
; GFX12-NEXT: v_mad_co_u64_u32 v[6:7], null, v0, v8, v[23:24]
; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], s0, v17, v9, v[25:26]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v25, null, 0, v3, vcc_lo
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v28, 0, 1, s0
; GFX12-NEXT: v_mul_lo_u32 v26, v21, v10
; GFX12-NEXT: v_mad_co_u64_u32 v[23:24], vcc_lo, v16, v13, v[5:6]
; GFX12-NEXT: v_mad_co_u64_u32 v[2:3], s0, v18, v8, v[0:1]
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v28, null, 0, v28, s0
; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v16, v8, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-NEXT: v_mad_co_u64_u32 v[5:6], s1, v17, v12, v[23:24]
; GFX12-NEXT: v_mad_co_u64_u32 v[23:24], s2, v16, v11, v[3:4]
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v14, 0, 1, s2
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-NEXT: v_mad_co_u64_u32 v[3:4], s0, v18, v11, v[5:6]
@@ -2814,31 +2814,31 @@ define i256 @v_mul_i256(i256 %num, i256 %den) {
; GFX12-NEXT: v_mul_lo_u32 v24, v18, v13
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_mad_co_u64_u32 v[11:12], s3, v19, v10, v[3:4]
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v10, null, 0, v14, s2
; GFX12-NEXT: v_mad_co_u64_u32 v[3:4], s2, v18, v9, v[5:6]
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v14, null, 0, v10, s2
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-NEXT: v_mad_co_u64_u32 v[5:6], s2, v20, v9, v[11:12]
; GFX12-NEXT: v_mad_co_u64_u32 v[10:11], s4, v16, v9, v[1:2]
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v9, 0, 1, s4
; GFX12-NEXT: v_mad_co_u64_u32 v[12:13], s4, v19, v8, v[3:4]
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v16, null, 0, v14, s4
; GFX12-NEXT: v_mad_co_u64_u32 v[14:15], s4, v21, v8, v[5:6]
; GFX12-NEXT: v_mad_co_u64_u32 v[1:2], s5, v17, v8, v[10:11]
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, s5, v9, v12, s5
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v4, s5, v28, v13, s5
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v5, s5, v16, v14, s5
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v6, s5, v25, v15, s5
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v30, s5
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v31, s4
@@ -2848,7 +2848,7 @@ define i256 @v_mul_i256(i256 %num, i256 %den) {
; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v29, s0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v26, s1
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v27, vcc_lo
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_mad_co_u64_u32 v[7:8], null, v22, v8, v[7:8]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll
index 9aaa9635a7da1..e450da73ab47d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll
@@ -491,7 +491,7 @@ define amdgpu_cs void @loop_with_2breaks(ptr addrspace(1) %x, ptr addrspace(1) %
; OLD_RBS-NEXT: s_branch .LBB16_3
; OLD_RBS-NEXT: .LBB16_1: ; %Flow3
; OLD_RBS-NEXT: ; in Loop: Header=BB16_3 Depth=1
-; OLD_RBS-NEXT: s_waitcnt_depctr 0xffe3
+; OLD_RBS-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; OLD_RBS-NEXT: s_or_b32 exec_lo, exec_lo, s3
; OLD_RBS-NEXT: s_andn2_b32 s1, s1, exec_lo
; OLD_RBS-NEXT: s_and_b32 s3, exec_lo, s4
@@ -553,7 +553,7 @@ define amdgpu_cs void @loop_with_2breaks(ptr addrspace(1) %x, ptr addrspace(1) %
; NEW_RBS-NEXT: s_branch .LBB16_3
; NEW_RBS-NEXT: .LBB16_1: ; %Flow3
; NEW_RBS-NEXT: ; in Loop: Header=BB16_3 Depth=1
-; NEW_RBS-NEXT: s_waitcnt_depctr 0xffe3
+; NEW_RBS-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; NEW_RBS-NEXT: s_or_b32 exec_lo, exec_lo, s7
; NEW_RBS-NEXT: s_andn2_b32 s2, s5, exec_lo
; NEW_RBS-NEXT: s_and_b32 s3, exec_lo, s6
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
index 8b5958daac168..e2fb704599250 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
@@ -50,7 +50,7 @@ define i16 @s_sub_i16(i16 inreg %a, i16 inreg %b) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_sub_co_i32 s0, s0, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
%c = sub i16 %a, %b
@@ -145,7 +145,7 @@ define i32 @s_sub_i32(i32 inreg %a, i32 inreg %b) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_sub_co_i32 s0, s0, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
%c = sub i32 %a, %b
@@ -299,7 +299,7 @@ define i64 @s_sub_i64(i64 inreg %a, i64 inreg %b) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_sub_nc_u64 s[0:1], s[0:1], s[2:3]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-NEXT: s_setpc_b64 s[30:31]
%c = sub i64 %a, %b
@@ -350,7 +350,7 @@ define i64 @v_sub_i64(i64 %a, i64 %b) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_sub_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
%c = sub i64 %a, %b
@@ -438,7 +438,7 @@ define void @s_usubo_usube(i64 inreg %a, i64 inreg %b, ptr addrspace(1) %res, pt
; GFX12-NEXT: s_sub_co_u32 s0, s0, s2
; GFX12-NEXT: s_sub_co_ci_u32 s1, s1, s3
; GFX12-NEXT: s_cselect_b32 s2, 1, 0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v5, s1 :: v_dual_mov_b32 v4, s0
; GFX12-NEXT: v_mov_b32_e32 v6, s2
; GFX12-NEXT: global_store_b64 v[0:1], v[4:5], off
@@ -518,9 +518,9 @@ define void @v_usubo_usube(i64 %a, i64 %b, ptr addrspace(1) %res, ptr addrspace(
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX12-NEXT: global_store_b64 v[4:5], v[0:1], off
; GFX12-NEXT: global_store_b32 v[6:7], v2, off
diff --git a/llvm/test/CodeGen/AMDGPU/add_i1.ll b/llvm/test/CodeGen/AMDGPU/add_i1.ll
index ca605986da941..ac5386bdfc06f 100644
--- a/llvm/test/CodeGen/AMDGPU/add_i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/add_i1.ll
@@ -171,7 +171,7 @@ define amdgpu_kernel void @add_i1_cf(ptr addrspace(1) %out, ptr addrspace(1) %a,
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3] glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_andn2_b32 s2, s4, exec_lo
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll b/llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll
index 356bf4b3cac28..56e2f55d958a1 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll
@@ -16,10 +16,10 @@ define amdgpu_gfx void @basic_test(i32 %x, i32 inreg %c, ptr addrspace(1) %ptr)
; DAGISEL-NEXT: s_mov_b32 s33, s32
; DAGISEL-NEXT: s_or_saveexec_b32 s1, -1
; DAGISEL-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: s_mov_b32 exec_lo, s1
; DAGISEL-NEXT: v_writelane_b32 v42, s0, 2
-; DAGISEL-NEXT: s_clause 0x1
+; DAGISEL-NEXT: s_clause 0x1 ; 8-byte Folded Spill
; DAGISEL-NEXT: scratch_store_b32 off, v40, s33 offset:4
; DAGISEL-NEXT: scratch_store_b32 off, v41, s33
; DAGISEL-NEXT: v_dual_mov_b32 v41, v2 :: v_dual_mov_b32 v40, v1
@@ -29,10 +29,10 @@ define amdgpu_gfx void @basic_test(i32 %x, i32 inreg %c, ptr addrspace(1) %ptr)
; DAGISEL-NEXT: s_mov_b32 s0, good_callee at abs32@lo
; DAGISEL-NEXT: s_add_co_i32 s32, s32, 16
; DAGISEL-NEXT: v_writelane_b32 v42, s31, 1
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
; DAGISEL-NEXT: global_store_b32 v[40:41], v0, off
-; DAGISEL-NEXT: s_clause 0x1
+; DAGISEL-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; DAGISEL-NEXT: scratch_load_b32 v41, off, s33
; DAGISEL-NEXT: scratch_load_b32 v40, off, s33 offset:4
; DAGISEL-NEXT: v_readlane_b32 s31, v42, 1
@@ -41,11 +41,11 @@ define amdgpu_gfx void @basic_test(i32 %x, i32 inreg %c, ptr addrspace(1) %ptr)
; DAGISEL-NEXT: v_readlane_b32 s0, v42, 2
; DAGISEL-NEXT: s_or_saveexec_b32 s1, -1
; DAGISEL-NEXT: scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: s_mov_b32 exec_lo, s1
; DAGISEL-NEXT: s_mov_b32 s33, s0
; DAGISEL-NEXT: s_wait_loadcnt 0x0
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-LABEL: basic_test:
@@ -59,10 +59,10 @@ define amdgpu_gfx void @basic_test(i32 %x, i32 inreg %c, ptr addrspace(1) %ptr)
; GISEL-NEXT: s_mov_b32 s33, s32
; GISEL-NEXT: s_or_saveexec_b32 s1, -1
; GISEL-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: s_mov_b32 exec_lo, s1
; GISEL-NEXT: v_writelane_b32 v42, s0, 2
-; GISEL-NEXT: s_clause 0x1
+; GISEL-NEXT: s_clause 0x1 ; 8-byte Folded Spill
; GISEL-NEXT: scratch_store_b32 off, v40, s33 offset:4
; GISEL-NEXT: scratch_store_b32 off, v41, s33
; GISEL-NEXT: v_dual_mov_b32 v40, v1 :: v_dual_mov_b32 v41, v2
@@ -72,10 +72,10 @@ define amdgpu_gfx void @basic_test(i32 %x, i32 inreg %c, ptr addrspace(1) %ptr)
; GISEL-NEXT: s_mov_b32 s1, good_callee at abs32@hi
; GISEL-NEXT: s_add_co_i32 s32, s32, 16
; GISEL-NEXT: v_writelane_b32 v42, s31, 1
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GISEL-NEXT: global_store_b32 v[40:41], v0, off
-; GISEL-NEXT: s_clause 0x1
+; GISEL-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GISEL-NEXT: scratch_load_b32 v41, off, s33
; GISEL-NEXT: scratch_load_b32 v40, off, s33 offset:4
; GISEL-NEXT: v_readlane_b32 s31, v42, 1
@@ -84,11 +84,11 @@ define amdgpu_gfx void @basic_test(i32 %x, i32 inreg %c, ptr addrspace(1) %ptr)
; GISEL-NEXT: v_readlane_b32 s0, v42, 2
; GISEL-NEXT: s_or_saveexec_b32 s1, -1
; GISEL-NEXT: scratch_load_b32 v42, off, s33 offset:8 ; 4-byte Folded Reload
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: s_mov_b32 exec_lo, s1
; GISEL-NEXT: s_mov_b32 s33, s0
; GISEL-NEXT: s_wait_loadcnt 0x0
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: s_setpc_b64 s[30:31]
%y = add i32 %x, 13
%ret = call i32(ptr, ...) @llvm.amdgcn.call.whole.wave(ptr @good_callee, i32 %x, i32 %y, i32 inreg %c)
@@ -107,7 +107,7 @@ define amdgpu_gfx i32 @tail_call_from_gfx(i32 %x, i32 inreg %c) {
; DAGISEL-NEXT: v_add_nc_u32_e32 v1, 13, v0
; DAGISEL-NEXT: s_mov_b32 s1, good_callee at abs32@hi
; DAGISEL-NEXT: s_mov_b32 s0, good_callee at abs32@lo
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: s_setpc_b64 s[0:1]
;
; GISEL-LABEL: tail_call_from_gfx:
@@ -120,7 +120,7 @@ define amdgpu_gfx i32 @tail_call_from_gfx(i32 %x, i32 inreg %c) {
; GISEL-NEXT: v_add_nc_u32_e32 v1, 13, v0
; GISEL-NEXT: s_mov_b32 s36, good_callee at abs32@lo
; GISEL-NEXT: s_mov_b32 s37, good_callee at abs32@hi
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: s_setpc_b64 s[36:37]
%y = add i32 %x, 13
%ret = tail call i32(ptr, ...) @llvm.amdgcn.call.whole.wave(ptr @good_callee, i32 %x, i32 %y, i32 inreg %c)
@@ -136,7 +136,7 @@ define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x,
; DAGISEL-NEXT: s_wait_bvhcnt 0x0
; DAGISEL-NEXT: s_wait_kmcnt 0x0
; DAGISEL-NEXT: s_xor_saveexec_b32 s0, -1
-; DAGISEL-NEXT: s_clause 0x1f
+; DAGISEL-NEXT: s_clause 0x1f ; 128-byte Folded Spill
; DAGISEL-NEXT: scratch_store_b32 off, v0, s32
; DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4
; DAGISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8
@@ -169,7 +169,7 @@ define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x,
; DAGISEL-NEXT: scratch_store_b32 off, v29, s32 offset:116
; DAGISEL-NEXT: scratch_store_b32 off, v30, s32 offset:120
; DAGISEL-NEXT: scratch_store_b32 off, v31, s32 offset:124
-; DAGISEL-NEXT: s_clause 0x1f
+; DAGISEL-NEXT: s_clause 0x1f ; 128-byte Folded Spill
; DAGISEL-NEXT: scratch_store_b32 off, v32, s32 offset:128
; DAGISEL-NEXT: scratch_store_b32 off, v33, s32 offset:132
; DAGISEL-NEXT: scratch_store_b32 off, v34, s32 offset:136
@@ -202,7 +202,7 @@ define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x,
; DAGISEL-NEXT: scratch_store_b32 off, v85, s32 offset:244
; DAGISEL-NEXT: scratch_store_b32 off, v86, s32 offset:248
; DAGISEL-NEXT: scratch_store_b32 off, v87, s32 offset:252
-; DAGISEL-NEXT: s_clause 0x1f
+; DAGISEL-NEXT: s_clause 0x1f ; 128-byte Folded Spill
; DAGISEL-NEXT: scratch_store_b32 off, v96, s32 offset:256
; DAGISEL-NEXT: scratch_store_b32 off, v97, s32 offset:260
; DAGISEL-NEXT: scratch_store_b32 off, v98, s32 offset:264
@@ -235,7 +235,7 @@ define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x,
; DAGISEL-NEXT: scratch_store_b32 off, v149, s32 offset:372
; DAGISEL-NEXT: scratch_store_b32 off, v150, s32 offset:376
; DAGISEL-NEXT: scratch_store_b32 off, v151, s32 offset:380
-; DAGISEL-NEXT: s_clause 0x1f
+; DAGISEL-NEXT: s_clause 0x1f ; 128-byte Folded Spill
; DAGISEL-NEXT: scratch_store_b32 off, v160, s32 offset:384
; DAGISEL-NEXT: scratch_store_b32 off, v161, s32 offset:388
; DAGISEL-NEXT: scratch_store_b32 off, v162, s32 offset:392
@@ -268,7 +268,7 @@ define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x,
; DAGISEL-NEXT: scratch_store_b32 off, v213, s32 offset:500
; DAGISEL-NEXT: scratch_store_b32 off, v214, s32 offset:504
; DAGISEL-NEXT: scratch_store_b32 off, v215, s32 offset:508
-; DAGISEL-NEXT: s_clause 0xf
+; DAGISEL-NEXT: s_clause 0xf ; 64-byte Folded Spill
; DAGISEL-NEXT: scratch_store_b32 off, v224, s32 offset:512
; DAGISEL-NEXT: scratch_store_b32 off, v225, s32 offset:516
; DAGISEL-NEXT: scratch_store_b32 off, v226, s32 offset:520
@@ -289,9 +289,9 @@ define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x,
; DAGISEL-NEXT: v_add_nc_u32_e32 v1, 13, v0
; DAGISEL-NEXT: s_mov_b32 s37, good_callee at abs32@hi
; DAGISEL-NEXT: s_mov_b32 s36, good_callee at abs32@lo
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: s_xor_b32 exec_lo, s0, -1
-; DAGISEL-NEXT: s_clause 0x1f
+; DAGISEL-NEXT: s_clause 0x1f ; 128-byte Folded Reload
; DAGISEL-NEXT: scratch_load_b32 v0, off, s32
; DAGISEL-NEXT: scratch_load_b32 v1, off, s32 offset:4
; DAGISEL-NEXT: scratch_load_b32 v2, off, s32 offset:8
@@ -324,7 +324,7 @@ define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x,
; DAGISEL-NEXT: scratch_load_b32 v29, off, s32 offset:116
; DAGISEL-NEXT: scratch_load_b32 v30, off, s32 offset:120
; DAGISEL-NEXT: scratch_load_b32 v31, off, s32 offset:124
-; DAGISEL-NEXT: s_clause 0x1f
+; DAGISEL-NEXT: s_clause 0x1f ; 128-byte Folded Reload
; DAGISEL-NEXT: scratch_load_b32 v32, off, s32 offset:128
; DAGISEL-NEXT: scratch_load_b32 v33, off, s32 offset:132
; DAGISEL-NEXT: scratch_load_b32 v34, off, s32 offset:136
@@ -357,7 +357,7 @@ define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x,
; DAGISEL-NEXT: scratch_load_b32 v85, off, s32 offset:244
; DAGISEL-NEXT: scratch_load_b32 v86, off, s32 offset:248
; DAGISEL-NEXT: scratch_load_b32 v87, off, s32 offset:252
-; DAGISEL-NEXT: s_clause 0x1f
+; DAGISEL-NEXT: s_clause 0x1f ; 128-byte Folded Reload
; DAGISEL-NEXT: scratch_load_b32 v96, off, s32 offset:256
; DAGISEL-NEXT: scratch_load_b32 v97, off, s32 offset:260
; DAGISEL-NEXT: scratch_load_b32 v98, off, s32 offset:264
@@ -390,7 +390,7 @@ define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x,
; DAGISEL-NEXT: scratch_load_b32 v149, off, s32 offset:372
; DAGISEL-NEXT: scratch_load_b32 v150, off, s32 offset:376
; DAGISEL-NEXT: scratch_load_b32 v151, off, s32 offset:380
-; DAGISEL-NEXT: s_clause 0x1f
+; DAGISEL-NEXT: s_clause 0x1f ; 128-byte Folded Reload
; DAGISEL-NEXT: scratch_load_b32 v160, off, s32 offset:384
; DAGISEL-NEXT: scratch_load_b32 v161, off, s32 offset:388
; DAGISEL-NEXT: scratch_load_b32 v162, off, s32 offset:392
@@ -423,7 +423,7 @@ define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x,
; DAGISEL-NEXT: scratch_load_b32 v213, off, s32 offset:500
; DAGISEL-NEXT: scratch_load_b32 v214, off, s32 offset:504
; DAGISEL-NEXT: scratch_load_b32 v215, off, s32 offset:508
-; DAGISEL-NEXT: s_clause 0xf
+; DAGISEL-NEXT: s_clause 0xf ; 64-byte Folded Reload
; DAGISEL-NEXT: scratch_load_b32 v224, off, s32 offset:512
; DAGISEL-NEXT: scratch_load_b32 v225, off, s32 offset:516
; DAGISEL-NEXT: scratch_load_b32 v226, off, s32 offset:520
@@ -451,7 +451,7 @@ define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x,
; GISEL-NEXT: s_wait_bvhcnt 0x0
; GISEL-NEXT: s_wait_kmcnt 0x0
; GISEL-NEXT: s_xor_saveexec_b32 s0, -1
-; GISEL-NEXT: s_clause 0x1f
+; GISEL-NEXT: s_clause 0x1f ; 128-byte Folded Spill
; GISEL-NEXT: scratch_store_b32 off, v0, s32
; GISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4
; GISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8
@@ -484,7 +484,7 @@ define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x,
; GISEL-NEXT: scratch_store_b32 off, v29, s32 offset:116
; GISEL-NEXT: scratch_store_b32 off, v30, s32 offset:120
; GISEL-NEXT: scratch_store_b32 off, v31, s32 offset:124
-; GISEL-NEXT: s_clause 0x1f
+; GISEL-NEXT: s_clause 0x1f ; 128-byte Folded Spill
; GISEL-NEXT: scratch_store_b32 off, v32, s32 offset:128
; GISEL-NEXT: scratch_store_b32 off, v33, s32 offset:132
; GISEL-NEXT: scratch_store_b32 off, v34, s32 offset:136
@@ -517,7 +517,7 @@ define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x,
; GISEL-NEXT: scratch_store_b32 off, v85, s32 offset:244
; GISEL-NEXT: scratch_store_b32 off, v86, s32 offset:248
; GISEL-NEXT: scratch_store_b32 off, v87, s32 offset:252
-; GISEL-NEXT: s_clause 0x1f
+; GISEL-NEXT: s_clause 0x1f ; 128-byte Folded Spill
; GISEL-NEXT: scratch_store_b32 off, v96, s32 offset:256
; GISEL-NEXT: scratch_store_b32 off, v97, s32 offset:260
; GISEL-NEXT: scratch_store_b32 off, v98, s32 offset:264
@@ -550,7 +550,7 @@ define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x,
; GISEL-NEXT: scratch_store_b32 off, v149, s32 offset:372
; GISEL-NEXT: scratch_store_b32 off, v150, s32 offset:376
; GISEL-NEXT: scratch_store_b32 off, v151, s32 offset:380
-; GISEL-NEXT: s_clause 0x1f
+; GISEL-NEXT: s_clause 0x1f ; 128-byte Folded Spill
; GISEL-NEXT: scratch_store_b32 off, v160, s32 offset:384
; GISEL-NEXT: scratch_store_b32 off, v161, s32 offset:388
; GISEL-NEXT: scratch_store_b32 off, v162, s32 offset:392
@@ -583,7 +583,7 @@ define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x,
; GISEL-NEXT: scratch_store_b32 off, v213, s32 offset:500
; GISEL-NEXT: scratch_store_b32 off, v214, s32 offset:504
; GISEL-NEXT: scratch_store_b32 off, v215, s32 offset:508
-; GISEL-NEXT: s_clause 0xf
+; GISEL-NEXT: s_clause 0xf ; 64-byte Folded Spill
; GISEL-NEXT: scratch_store_b32 off, v224, s32 offset:512
; GISEL-NEXT: scratch_store_b32 off, v225, s32 offset:516
; GISEL-NEXT: scratch_store_b32 off, v226, s32 offset:520
@@ -604,9 +604,9 @@ define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x,
; GISEL-NEXT: v_add_nc_u32_e32 v1, 13, v0
; GISEL-NEXT: s_mov_b32 s36, good_callee at abs32@lo
; GISEL-NEXT: s_mov_b32 s37, good_callee at abs32@hi
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: s_xor_b32 exec_lo, s0, -1
-; GISEL-NEXT: s_clause 0x1f
+; GISEL-NEXT: s_clause 0x1f ; 128-byte Folded Reload
; GISEL-NEXT: scratch_load_b32 v0, off, s32
; GISEL-NEXT: scratch_load_b32 v1, off, s32 offset:4
; GISEL-NEXT: scratch_load_b32 v2, off, s32 offset:8
@@ -639,7 +639,7 @@ define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x,
; GISEL-NEXT: scratch_load_b32 v29, off, s32 offset:116
; GISEL-NEXT: scratch_load_b32 v30, off, s32 offset:120
; GISEL-NEXT: scratch_load_b32 v31, off, s32 offset:124
-; GISEL-NEXT: s_clause 0x1f
+; GISEL-NEXT: s_clause 0x1f ; 128-byte Folded Reload
; GISEL-NEXT: scratch_load_b32 v32, off, s32 offset:128
; GISEL-NEXT: scratch_load_b32 v33, off, s32 offset:132
; GISEL-NEXT: scratch_load_b32 v34, off, s32 offset:136
@@ -672,7 +672,7 @@ define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x,
; GISEL-NEXT: scratch_load_b32 v85, off, s32 offset:244
; GISEL-NEXT: scratch_load_b32 v86, off, s32 offset:248
; GISEL-NEXT: scratch_load_b32 v87, off, s32 offset:252
-; GISEL-NEXT: s_clause 0x1f
+; GISEL-NEXT: s_clause 0x1f ; 128-byte Folded Reload
; GISEL-NEXT: scratch_load_b32 v96, off, s32 offset:256
; GISEL-NEXT: scratch_load_b32 v97, off, s32 offset:260
; GISEL-NEXT: scratch_load_b32 v98, off, s32 offset:264
@@ -705,7 +705,7 @@ define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x,
; GISEL-NEXT: scratch_load_b32 v149, off, s32 offset:372
; GISEL-NEXT: scratch_load_b32 v150, off, s32 offset:376
; GISEL-NEXT: scratch_load_b32 v151, off, s32 offset:380
-; GISEL-NEXT: s_clause 0x1f
+; GISEL-NEXT: s_clause 0x1f ; 128-byte Folded Reload
; GISEL-NEXT: scratch_load_b32 v160, off, s32 offset:384
; GISEL-NEXT: scratch_load_b32 v161, off, s32 offset:388
; GISEL-NEXT: scratch_load_b32 v162, off, s32 offset:392
@@ -738,7 +738,7 @@ define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x,
; GISEL-NEXT: scratch_load_b32 v213, off, s32 offset:500
; GISEL-NEXT: scratch_load_b32 v214, off, s32 offset:504
; GISEL-NEXT: scratch_load_b32 v215, off, s32 offset:508
-; GISEL-NEXT: s_clause 0xf
+; GISEL-NEXT: s_clause 0xf ; 64-byte Folded Reload
; GISEL-NEXT: scratch_load_b32 v224, off, s32 offset:512
; GISEL-NEXT: scratch_load_b32 v225, off, s32 offset:516
; GISEL-NEXT: scratch_load_b32 v226, off, s32 offset:520
@@ -776,7 +776,7 @@ define amdgpu_gfx void @ret_void(i32 %x) {
; DAGISEL-NEXT: s_mov_b32 s33, s32
; DAGISEL-NEXT: s_or_saveexec_b32 s1, -1
; DAGISEL-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: s_mov_b32 exec_lo, s1
; DAGISEL-NEXT: v_writelane_b32 v40, s0, 2
; DAGISEL-NEXT: s_mov_b32 s1, void_callee at abs32@hi
@@ -784,7 +784,7 @@ define amdgpu_gfx void @ret_void(i32 %x) {
; DAGISEL-NEXT: s_add_co_i32 s32, s32, 16
; DAGISEL-NEXT: v_writelane_b32 v40, s30, 0
; DAGISEL-NEXT: v_writelane_b32 v40, s31, 1
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
; DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; DAGISEL-NEXT: v_readlane_b32 s31, v40, 1
@@ -793,11 +793,11 @@ define amdgpu_gfx void @ret_void(i32 %x) {
; DAGISEL-NEXT: v_readlane_b32 s0, v40, 2
; DAGISEL-NEXT: s_or_saveexec_b32 s1, -1
; DAGISEL-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: s_mov_b32 exec_lo, s1
; DAGISEL-NEXT: s_mov_b32 s33, s0
; DAGISEL-NEXT: s_wait_loadcnt 0x0
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-LABEL: ret_void:
@@ -811,7 +811,7 @@ define amdgpu_gfx void @ret_void(i32 %x) {
; GISEL-NEXT: s_mov_b32 s33, s32
; GISEL-NEXT: s_or_saveexec_b32 s1, -1
; GISEL-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: s_mov_b32 exec_lo, s1
; GISEL-NEXT: v_writelane_b32 v40, s0, 2
; GISEL-NEXT: s_mov_b32 s0, void_callee at abs32@lo
@@ -819,7 +819,7 @@ define amdgpu_gfx void @ret_void(i32 %x) {
; GISEL-NEXT: s_add_co_i32 s32, s32, 16
; GISEL-NEXT: v_writelane_b32 v40, s30, 0
; GISEL-NEXT: v_writelane_b32 v40, s31, 1
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-NEXT: v_readlane_b32 s31, v40, 1
@@ -828,11 +828,11 @@ define amdgpu_gfx void @ret_void(i32 %x) {
; GISEL-NEXT: v_readlane_b32 s0, v40, 2
; GISEL-NEXT: s_or_saveexec_b32 s1, -1
; GISEL-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: s_mov_b32 exec_lo, s1
; GISEL-NEXT: s_mov_b32 s33, s0
; GISEL-NEXT: s_wait_loadcnt 0x0
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: s_setpc_b64 s[30:31]
call void(ptr, ...) @llvm.amdgcn.call.whole.wave(ptr @void_callee, i32 %x)
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn-cs-chain-intrinsic-dyn-vgpr-w32.ll b/llvm/test/CodeGen/AMDGPU/amdgcn-cs-chain-intrinsic-dyn-vgpr-w32.ll
index 3e80a58bda4a0..5d8bebe89dd94 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn-cs-chain-intrinsic-dyn-vgpr-w32.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn-cs-chain-intrinsic-dyn-vgpr-w32.ll
@@ -23,10 +23,10 @@ define amdgpu_cs_chain void @dynamic_vgprs(i32 inreg %exec, <3 x i32> inreg %sgp
; GISEL-GFX12-NEXT: s_mov_b32 s8, retry_vgpr_alloc at abs32@lo
; GISEL-GFX12-NEXT: s_mov_b32 s9, retry_vgpr_alloc at abs32@hi
; GISEL-GFX12-NEXT: s_alloc_vgpr s4
-; GISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; GISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX12-NEXT: s_cselect_b64 s[6:7], s[6:7], s[8:9]
; GISEL-GFX12-NEXT: s_cselect_b32 exec_lo, s5, -1
-; GISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; GISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX12-NEXT: s_setpc_b64 s[6:7]
;
; DAGISEL-GFX12-LABEL: dynamic_vgprs:
@@ -45,10 +45,10 @@ define amdgpu_cs_chain void @dynamic_vgprs(i32 inreg %exec, <3 x i32> inreg %sgp
; DAGISEL-GFX12-NEXT: s_mov_b32 s1, s2
; DAGISEL-GFX12-NEXT: s_mov_b32 s2, s3
; DAGISEL-GFX12-NEXT: s_alloc_vgpr s4
-; DAGISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; DAGISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-GFX12-NEXT: s_cselect_b64 s[8:9], s[8:9], s[6:7]
; DAGISEL-GFX12-NEXT: s_cselect_b32 exec_lo, s5, -1
-; DAGISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; DAGISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-GFX12-NEXT: s_setpc_b64 s[8:9]
call void(ptr, i32, <3 x i32>, { i32, ptr addrspace(5), i32, i32 }, i32, ...) @llvm.amdgcn.cs.chain(ptr @callee, i32 %exec, <3 x i32> inreg %sgpr, { i32, ptr addrspace(5), i32, i32 } %vgpr, i32 1, i32 inreg %num_vgpr, i32 inreg -1, ptr @retry_vgpr_alloc)
unreachable
@@ -67,10 +67,10 @@ define amdgpu_cs_chain void @constants(<3 x i32> inreg %sgpr, { i32, ptr addrspa
; GISEL-GFX12-NEXT: s_mov_b32 s6, retry_vgpr_alloc at abs32@lo
; GISEL-GFX12-NEXT: s_mov_b32 s7, retry_vgpr_alloc at abs32@hi
; GISEL-GFX12-NEXT: s_alloc_vgpr 64
-; GISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; GISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX12-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7]
; GISEL-GFX12-NEXT: s_cselect_b32 exec_lo, 7, -1
-; GISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; GISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX12-NEXT: s_setpc_b64 s[4:5]
;
; DAGISEL-GFX12-LABEL: constants:
@@ -85,10 +85,10 @@ define amdgpu_cs_chain void @constants(<3 x i32> inreg %sgpr, { i32, ptr addrspa
; DAGISEL-GFX12-NEXT: s_mov_b32 s7, callee at abs32@hi
; DAGISEL-GFX12-NEXT: s_mov_b32 s6, callee at abs32@lo
; DAGISEL-GFX12-NEXT: s_alloc_vgpr 64
-; DAGISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; DAGISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-GFX12-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5]
; DAGISEL-GFX12-NEXT: s_cselect_b32 exec_lo, 7, -1
-; DAGISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; DAGISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-GFX12-NEXT: s_setpc_b64 s[6:7]
call void(ptr, i32, <3 x i32>, { i32, ptr addrspace(5), i32, i32 }, i32, ...) @llvm.amdgcn.cs.chain(ptr @callee, i32 7, <3 x i32> inreg %sgpr, { i32, ptr addrspace(5), i32, i32 } %vgpr, i32 1, i32 inreg 64, i32 inreg -1, ptr @retry_vgpr_alloc)
unreachable
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-branch-weight-metadata.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-branch-weight-metadata.ll
index 9666085341d83..c4ea1bbace8ce 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-branch-weight-metadata.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-branch-weight-metadata.ll
@@ -179,7 +179,7 @@ define void @divergent_br_no_metadata(i32 noundef inreg %value, ptr addrspace(8)
; GFX1010-NEXT: s_mov_b32 s4, s17
; GFX1010-NEXT: buffer_store_dword v0, v1, s[4:7], 0 offen
; GFX1010-NEXT: .LBB3_2: ; %if.end
-; GFX1010-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010-NEXT: s_or_b32 exec_lo, exec_lo, s8
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1010-NEXT: s_setpc_b64 s[30:31]
@@ -250,7 +250,7 @@ define void @divergent_br_same_weight(i32 noundef inreg %value, ptr addrspace(8)
; GFX1010-NEXT: s_mov_b32 s4, s17
; GFX1010-NEXT: buffer_store_dword v0, v1, s[4:7], 0 offen
; GFX1010-NEXT: .LBB4_2: ; %if.end
-; GFX1010-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010-NEXT: s_or_b32 exec_lo, exec_lo, s8
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1010-NEXT: s_setpc_b64 s[30:31]
@@ -319,7 +319,7 @@ define void @divergent_br_then_likely(i32 noundef inreg %value, ptr addrspace(8)
; GFX1010-NEXT: s_mov_b32 s4, s17
; GFX1010-NEXT: buffer_store_dword v0, v1, s[4:7], 0 offen
; GFX1010-NEXT: ; %bb.2: ; %if.end
-; GFX1010-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010-NEXT: s_or_b32 exec_lo, exec_lo, s8
; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1010-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll
index 7669ae21f6635..b5ebca1846807 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll
@@ -18,9 +18,9 @@ define amdgpu_cs_chain void @test_alloca() {
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v0, 0
; GFX12-NEXT: s_mov_b32 s32, 16
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 s0, s32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_i32 s32, s0, 0x200
; GFX12-NEXT: scratch_store_b32 off, v0, s0
; GFX12-NEXT: s_endpgm
@@ -54,13 +54,13 @@ define amdgpu_cs_chain void @test_alloca_var_uniform(i32 inreg %count) {
; GFX12-NEXT: s_lshl2_add_u32 s0, s0, 15
; GFX12-NEXT: v_mov_b32_e32 v0, 0
; GFX12-NEXT: s_mov_b32 s32, 16
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_b32 s0, s0, -16
; GFX12-NEXT: s_mov_b32 s1, s32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_lshl_b32 s0, s0, 5
; GFX12-NEXT: scratch_store_b32 off, v0, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_i32 s32, s1, s0
; GFX12-NEXT: s_endpgm
;
@@ -96,19 +96,19 @@ define amdgpu_cs_chain void @test_alloca_var(i32 %count) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_and_b32 v1, -16, v0
; GFX12-NEXT: .LBB2_1: ; =>This Inner Loop Header: Depth=1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_ctz_i32_b32 s2, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_readlane_b32 s3, v1, s2
; GFX12-NEXT: s_bitset0_b32 s1, s2
; GFX12-NEXT: s_max_u32 s0, s0, s3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_cmp_lg_u32 s1, 0
; GFX12-NEXT: s_cbranch_scc1 .LBB2_1
; GFX12-NEXT: ; %bb.2:
; GFX12-NEXT: s_mov_b32 s1, s32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_lshl_add_u32 v1, s0, 5, s1
; GFX12-NEXT: scratch_store_b32 off, v0, s1
; GFX12-NEXT: v_readfirstlane_b32 s32, v1
@@ -151,21 +151,21 @@ define amdgpu_cs_chain void @test_alloca_and_call() {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_getpc_b64 s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_sext_i32_i16 s1, s1
; GFX12-NEXT: s_add_co_u32 s0, s0, foo at gotpcrel32@lo+12
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_ci_u32 s1, s1, foo at gotpcrel32@hi+24
; GFX12-NEXT: v_mov_b32_e32 v0, 0
; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX12-NEXT: s_mov_b32 s32, 16
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 s2, s32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_i32 s32, s2, 0x200
; GFX12-NEXT: scratch_store_b32 off, v0, s2
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX12-NEXT: s_endpgm
;
@@ -203,24 +203,24 @@ define amdgpu_cs_chain void @test_alloca_and_call_var_uniform(i32 inreg %count)
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_getpc_b64 s[2:3]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_sext_i32_i16 s3, s3
; GFX12-NEXT: s_add_co_u32 s2, s2, foo at gotpcrel32@lo+12
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_ci_u32 s3, s3, foo at gotpcrel32@hi+24
; GFX12-NEXT: s_lshl2_add_u32 s0, s0, 15
; GFX12-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
; GFX12-NEXT: v_mov_b32_e32 v0, 0
; GFX12-NEXT: s_mov_b32 s32, 16
; GFX12-NEXT: s_and_b32 s0, s0, -16
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 s1, s32
; GFX12-NEXT: s_lshl_b32 s0, s0, 5
; GFX12-NEXT: scratch_store_b32 off, v0, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_i32 s32, s1, s0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX12-NEXT: s_endpgm
;
@@ -263,22 +263,22 @@ define amdgpu_cs_chain void @test_alloca_and_call_var(i32 %count) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_and_b32 v1, -16, v0
; GFX12-NEXT: .LBB5_1: ; =>This Inner Loop Header: Depth=1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_ctz_i32_b32 s2, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_readlane_b32 s3, v1, s2
; GFX12-NEXT: s_bitset0_b32 s1, s2
; GFX12-NEXT: s_max_u32 s0, s0, s3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_cmp_lg_u32 s1, 0
; GFX12-NEXT: s_cbranch_scc1 .LBB5_1
; GFX12-NEXT: ; %bb.2:
; GFX12-NEXT: s_getpc_b64 s[2:3]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_sext_i32_i16 s3, s3
; GFX12-NEXT: s_add_co_u32 s2, s2, foo at gotpcrel32@lo+12
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_ci_u32 s3, s3, foo at gotpcrel32@hi+24
; GFX12-NEXT: s_mov_b32 s1, s32
; GFX12-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
@@ -286,7 +286,7 @@ define amdgpu_cs_chain void @test_alloca_and_call_var(i32 %count) {
; GFX12-NEXT: scratch_store_b32 off, v0, s1
; GFX12-NEXT: v_readfirstlane_b32 s32, v1
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX12-NEXT: s_endpgm
;
@@ -334,18 +334,18 @@ define amdgpu_cs_chain void @test_call_and_alloca() {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_getpc_b64 s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_sext_i32_i16 s1, s1
; GFX12-NEXT: s_add_co_u32 s0, s0, foo at gotpcrel32@lo+12
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_ci_u32 s1, s1, foo at gotpcrel32@hi+24
; GFX12-NEXT: s_mov_b32 s32, 16
; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX12-NEXT: s_mov_b32 s4, s32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_i32 s32, s4, 0x200
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX12-NEXT: v_mov_b32_e32 v0, 0
; GFX12-NEXT: scratch_store_b32 off, v0, s4
@@ -385,23 +385,23 @@ define amdgpu_cs_chain void @test_call_and_alloca_var_uniform(i32 inreg %count)
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_getpc_b64 s[2:3]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_sext_i32_i16 s3, s3
; GFX12-NEXT: s_add_co_u32 s2, s2, foo at gotpcrel32@lo+12
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_ci_u32 s3, s3, foo at gotpcrel32@hi+24
; GFX12-NEXT: s_lshl2_add_u32 s0, s0, 15
; GFX12-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
; GFX12-NEXT: s_mov_b32 s32, 16
; GFX12-NEXT: s_and_b32 s0, s0, -16
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 s4, s32
; GFX12-NEXT: s_lshl_b32 s0, s0, 5
; GFX12-NEXT: v_mov_b32_e32 v40, 0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_i32 s32, s4, s0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX12-NEXT: scratch_store_b32 off, v40, s4
; GFX12-NEXT: s_endpgm
@@ -445,22 +445,22 @@ define amdgpu_cs_chain void @test_call_and_alloca_var(i32 %count) {
; GFX12-NEXT: s_mov_b32 s32, 16
; GFX12-NEXT: v_and_b32_e32 v0, -16, v0
; GFX12-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_ctz_i32_b32 s2, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_readlane_b32 s3, v0, s2
; GFX12-NEXT: s_bitset0_b32 s1, s2
; GFX12-NEXT: s_max_u32 s0, s0, s3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_cmp_lg_u32 s1, 0
; GFX12-NEXT: s_cbranch_scc1 .LBB8_1
; GFX12-NEXT: ; %bb.2:
; GFX12-NEXT: s_getpc_b64 s[2:3]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_sext_i32_i16 s3, s3
; GFX12-NEXT: s_add_co_u32 s2, s2, foo at gotpcrel32@lo+12
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_ci_u32 s3, s3, foo at gotpcrel32@hi+24
; GFX12-NEXT: s_mov_b32 s4, s32
; GFX12-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
@@ -468,7 +468,7 @@ define amdgpu_cs_chain void @test_call_and_alloca_var(i32 %count) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_readfirstlane_b32 s32, v0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX12-NEXT: scratch_store_b32 off, v40, s4
; GFX12-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/atomic-optimizer-strict-wqm.ll b/llvm/test/CodeGen/AMDGPU/atomic-optimizer-strict-wqm.ll
index e03c9ca34b825..a8f62c8c863db 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic-optimizer-strict-wqm.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic-optimizer-strict-wqm.ll
@@ -15,7 +15,7 @@ define amdgpu_ps void @main(i32 %arg) {
; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: s_branch .LBB0_2
; GFX10-NEXT: .LBB0_1: ; in Loop: Header=BB0_2 Depth=1
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GFX10-NEXT: s_and_b32 s0, exec_lo, vcc_lo
; GFX10-NEXT: s_or_b32 s2, s0, s2
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
index 01f4414b930e1..d142f4f734890 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
@@ -117,7 +117,7 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX10W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W64-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc
; GFX10W64-NEXT: .LBB0_2:
-; GFX10W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W64-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W64-NEXT: s_waitcnt vmcnt(0)
@@ -144,7 +144,7 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX10W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W32-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc
; GFX10W32-NEXT: .LBB0_2:
-; GFX10W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX10W32-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W32-NEXT: s_waitcnt vmcnt(0)
@@ -227,9 +227,9 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W64-NEXT: ; %bb.1:
; GFX12W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34
; GFX12W64-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: s_mul_i32 s2, s2, 5
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: v_mov_b32_e32 v1, s2
; GFX12W64-NEXT: s_wait_kmcnt 0x0
; GFX12W64-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
@@ -239,7 +239,7 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W64-NEXT: s_wait_loadcnt 0x0
; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1
; GFX12W64-NEXT: v_mov_b32_e32 v1, 0
-; GFX12W64-NEXT: s_wait_alu 0xf1ff
+; GFX12W64-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12W64-NEXT: v_mad_u32_u24 v0, v0, 5, s2
; GFX12W64-NEXT: s_wait_kmcnt 0x0
@@ -258,9 +258,9 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W32-NEXT: ; %bb.1:
; GFX12W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34
; GFX12W32-NEXT: s_bcnt1_i32_b32 s1, s1
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_mul_i32 s1, s1, 5
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: v_mov_b32_e32 v1, s1
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
@@ -389,7 +389,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX10W64-NEXT: v_mov_b32_e32 v1, s2
; GFX10W64-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc
; GFX10W64-NEXT: .LBB1_2:
-; GFX10W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W64-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W64-NEXT: s_waitcnt vmcnt(0)
@@ -417,7 +417,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX10W32-NEXT: v_mov_b32_e32 v1, s2
; GFX10W32-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc
; GFX10W32-NEXT: .LBB1_2:
-; GFX10W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX10W32-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; GFX10W32-NEXT: s_waitcnt vmcnt(0)
@@ -505,9 +505,9 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34
; GFX12W64-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX12W64-NEXT: s_wait_kmcnt 0x0
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: s_mul_i32 s2, s6, s2
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: v_mov_b32_e32 v1, s2
; GFX12W64-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
; GFX12W64-NEXT: .LBB1_2:
@@ -516,7 +516,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W64-NEXT: s_wait_loadcnt 0x0
; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1
; GFX12W64-NEXT: s_wait_kmcnt 0x0
-; GFX12W64-NEXT: s_wait_alu 0xf1ff
+; GFX12W64-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12W64-NEXT: v_mad_co_u64_u32 v[0:1], null, s6, v0, s[2:3]
; GFX12W64-NEXT: v_mov_b32_e32 v1, 0
@@ -537,9 +537,9 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34
; GFX12W32-NEXT: s_bcnt1_i32_b32 s2, s2
; GFX12W32-NEXT: s_wait_kmcnt 0x0
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_mul_i32 s2, s0, s2
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: v_mov_b32_e32 v1, s2
; GFX12W32-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
; GFX12W32-NEXT: .LBB1_2:
@@ -710,7 +710,7 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX10W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W64-NEXT: buffer_atomic_add v0, off, s[8:11], 0 glc
; GFX10W64-NEXT: .LBB2_4:
-; GFX10W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W64-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W64-NEXT: s_waitcnt vmcnt(0)
@@ -748,7 +748,7 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX10W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W32-NEXT: buffer_atomic_add v0, off, s[8:11], 0 glc
; GFX10W32-NEXT: .LBB2_4:
-; GFX10W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX10W32-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W32-NEXT: s_waitcnt vmcnt(0)
@@ -851,7 +851,7 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W64-NEXT: .LBB2_1: ; %ComputeLoop
; GFX12W64-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12W64-NEXT: s_ctz_i32_b64 s3, s[0:1]
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: v_readlane_b32 s8, v1, s3
; GFX12W64-NEXT: v_writelane_b32 v0, s2, s3
; GFX12W64-NEXT: s_lshl_b64 s[6:7], 1, s3
@@ -879,7 +879,7 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W64-NEXT: s_wait_loadcnt 0x0
; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1
; GFX12W64-NEXT: v_mov_b32_e32 v1, 0
-; GFX12W64-NEXT: s_wait_alu 0xf1ff
+; GFX12W64-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12W64-NEXT: v_add_nc_u32_e32 v0, s2, v0
; GFX12W64-NEXT: s_wait_kmcnt 0x0
@@ -894,14 +894,14 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: ; implicit-def: $vgpr0
; GFX12W32-NEXT: .LBB2_1: ; %ComputeLoop
; GFX12W32-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_ctz_i32_b32 s2, s1
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: v_readlane_b32 s3, v1, s2
; GFX12W32-NEXT: v_writelane_b32 v0, s0, s2
; GFX12W32-NEXT: s_lshl_b32 s2, 1, s2
; GFX12W32-NEXT: s_add_co_i32 s0, s0, s3
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_and_not1_b32 s1, s1, s2
; GFX12W32-NEXT: s_cbranch_scc1 .LBB2_1
; GFX12W32-NEXT: ; %bb.2: ; %ComputeEnd
@@ -910,7 +910,7 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX12W32-NEXT: ; implicit-def: $vgpr1
; GFX12W32-NEXT: s_and_saveexec_b32 s1, vcc_lo
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_xor_b32 s1, exec_lo, s1
; GFX12W32-NEXT: s_cbranch_execz .LBB2_4
; GFX12W32-NEXT: ; %bb.3:
@@ -919,12 +919,12 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
; GFX12W32-NEXT: .LBB2_4:
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12W32-NEXT: s_wait_loadcnt 0x0
; GFX12W32-NEXT: v_readfirstlane_b32 s2, v1
-; GFX12W32-NEXT: s_wait_alu 0xf1ff
+; GFX12W32-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12W32-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s2, v0
; GFX12W32-NEXT: s_wait_kmcnt 0x0
@@ -1097,7 +1097,7 @@ define amdgpu_kernel void @struct_add_i32_varying_vdata(ptr addrspace(1) %out, p
; GFX10W64-NEXT: v_mov_b32_e32 v2, s3
; GFX10W64-NEXT: buffer_atomic_add v0, v2, s[8:11], 0 idxen glc
; GFX10W64-NEXT: .LBB3_4:
-; GFX10W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W64-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W64-NEXT: s_waitcnt vmcnt(0)
@@ -1138,7 +1138,7 @@ define amdgpu_kernel void @struct_add_i32_varying_vdata(ptr addrspace(1) %out, p
; GFX10W32-NEXT: v_mov_b32_e32 v2, s2
; GFX10W32-NEXT: buffer_atomic_add v0, v2, s[8:11], 0 idxen glc
; GFX10W32-NEXT: .LBB3_4:
-; GFX10W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX10W32-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W32-NEXT: s_waitcnt vmcnt(0)
@@ -1246,7 +1246,7 @@ define amdgpu_kernel void @struct_add_i32_varying_vdata(ptr addrspace(1) %out, p
; GFX12W64-NEXT: .LBB3_1: ; %ComputeLoop
; GFX12W64-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12W64-NEXT: s_ctz_i32_b64 s3, s[0:1]
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: v_readlane_b32 s8, v1, s3
; GFX12W64-NEXT: v_writelane_b32 v0, s2, s3
; GFX12W64-NEXT: s_lshl_b64 s[6:7], 1, s3
@@ -1277,7 +1277,7 @@ define amdgpu_kernel void @struct_add_i32_varying_vdata(ptr addrspace(1) %out, p
; GFX12W64-NEXT: s_wait_loadcnt 0x0
; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1
; GFX12W64-NEXT: v_mov_b32_e32 v1, 0
-; GFX12W64-NEXT: s_wait_alu 0xf1ff
+; GFX12W64-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12W64-NEXT: v_add_nc_u32_e32 v0, s2, v0
; GFX12W64-NEXT: s_wait_kmcnt 0x0
@@ -1292,14 +1292,14 @@ define amdgpu_kernel void @struct_add_i32_varying_vdata(ptr addrspace(1) %out, p
; GFX12W32-NEXT: ; implicit-def: $vgpr0
; GFX12W32-NEXT: .LBB3_1: ; %ComputeLoop
; GFX12W32-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_ctz_i32_b32 s2, s1
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: v_readlane_b32 s3, v1, s2
; GFX12W32-NEXT: v_writelane_b32 v0, s0, s2
; GFX12W32-NEXT: s_lshl_b32 s2, 1, s2
; GFX12W32-NEXT: s_add_co_i32 s0, s0, s3
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_and_not1_b32 s1, s1, s2
; GFX12W32-NEXT: s_cbranch_scc1 .LBB3_1
; GFX12W32-NEXT: ; %bb.2: ; %ComputeEnd
@@ -1308,7 +1308,7 @@ define amdgpu_kernel void @struct_add_i32_varying_vdata(ptr addrspace(1) %out, p
; GFX12W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX12W32-NEXT: ; implicit-def: $vgpr1
; GFX12W32-NEXT: s_and_saveexec_b32 s1, vcc_lo
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_xor_b32 s1, exec_lo, s1
; GFX12W32-NEXT: s_cbranch_execz .LBB3_4
; GFX12W32-NEXT: ; %bb.3:
@@ -1319,12 +1319,12 @@ define amdgpu_kernel void @struct_add_i32_varying_vdata(ptr addrspace(1) %out, p
; GFX12W32-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s2
; GFX12W32-NEXT: buffer_atomic_add_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
; GFX12W32-NEXT: .LBB3_4:
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12W32-NEXT: s_wait_loadcnt 0x0
; GFX12W32-NEXT: v_readfirstlane_b32 s2, v1
-; GFX12W32-NEXT: s_wait_alu 0xf1ff
+; GFX12W32-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12W32-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s2, v0
; GFX12W32-NEXT: s_wait_kmcnt 0x0
@@ -1383,7 +1383,7 @@ define amdgpu_kernel void @add_i32_varying_offset(ptr addrspace(1) %out, ptr add
; GFX10-NEXT: v_mov_b32_e32 v1, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: buffer_atomic_add v1, v0, s[0:3], 0 offen glc
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1552,7 +1552,7 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX10W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W64-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc
; GFX10W64-NEXT: .LBB5_2:
-; GFX10W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W64-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W64-NEXT: s_waitcnt vmcnt(0)
@@ -1580,7 +1580,7 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX10W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W32-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc
; GFX10W32-NEXT: .LBB5_2:
-; GFX10W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX10W32-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W32-NEXT: s_waitcnt vmcnt(0)
@@ -1666,9 +1666,9 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W64-NEXT: ; %bb.1:
; GFX12W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34
; GFX12W64-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: s_mul_i32 s2, s2, 5
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: v_mov_b32_e32 v1, s2
; GFX12W64-NEXT: s_wait_kmcnt 0x0
; GFX12W64-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
@@ -1679,7 +1679,7 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1
; GFX12W64-NEXT: v_mul_u32_u24_e32 v0, 5, v0
; GFX12W64-NEXT: v_mov_b32_e32 v1, 0
-; GFX12W64-NEXT: s_wait_alu 0xf1ff
+; GFX12W64-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12W64-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX12W64-NEXT: s_wait_kmcnt 0x0
@@ -1698,9 +1698,9 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W32-NEXT: ; %bb.1:
; GFX12W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34
; GFX12W32-NEXT: s_bcnt1_i32_b32 s1, s1
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_mul_i32 s1, s1, 5
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: v_mov_b32_e32 v1, s1
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
@@ -1830,7 +1830,7 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX10W64-NEXT: v_mov_b32_e32 v1, s2
; GFX10W64-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc
; GFX10W64-NEXT: .LBB6_2:
-; GFX10W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W64-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W64-NEXT: s_waitcnt lgkmcnt(0)
@@ -1859,7 +1859,7 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX10W32-NEXT: v_mov_b32_e32 v1, s2
; GFX10W32-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc
; GFX10W32-NEXT: .LBB6_2:
-; GFX10W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX10W32-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; GFX10W32-NEXT: s_waitcnt lgkmcnt(0)
@@ -1949,9 +1949,9 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34
; GFX12W64-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX12W64-NEXT: s_wait_kmcnt 0x0
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: s_mul_i32 s2, s6, s2
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: v_mov_b32_e32 v1, s2
; GFX12W64-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
; GFX12W64-NEXT: .LBB6_2:
@@ -1962,7 +1962,7 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W64-NEXT: s_wait_loadcnt 0x0
; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1
; GFX12W64-NEXT: v_mov_b32_e32 v1, 0
-; GFX12W64-NEXT: s_wait_alu 0xf1ff
+; GFX12W64-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12W64-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX12W64-NEXT: global_store_b32 v1, v0, s[0:1]
@@ -1982,9 +1982,9 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34
; GFX12W32-NEXT: s_bcnt1_i32_b32 s2, s2
; GFX12W32-NEXT: s_wait_kmcnt 0x0
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_mul_i32 s2, s0, s2
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: v_mov_b32_e32 v1, s2
; GFX12W32-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
; GFX12W32-NEXT: .LBB6_2:
@@ -1995,7 +1995,7 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W32-NEXT: s_wait_loadcnt 0x0
; GFX12W32-NEXT: v_readfirstlane_b32 s0, v1
; GFX12W32-NEXT: v_mov_b32_e32 v1, 0
-; GFX12W32-NEXT: s_wait_alu 0xf1ff
+; GFX12W32-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12W32-NEXT: v_sub_nc_u32_e32 v0, s0, v0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[2:3]
@@ -2157,7 +2157,7 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX10W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W64-NEXT: buffer_atomic_sub v0, off, s[8:11], 0 glc
; GFX10W64-NEXT: .LBB7_4:
-; GFX10W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W64-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W64-NEXT: s_waitcnt vmcnt(0)
@@ -2195,7 +2195,7 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX10W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W32-NEXT: buffer_atomic_sub v0, off, s[8:11], 0 glc
; GFX10W32-NEXT: .LBB7_4:
-; GFX10W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX10W32-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W32-NEXT: s_waitcnt vmcnt(0)
@@ -2299,7 +2299,7 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W64-NEXT: .LBB7_1: ; %ComputeLoop
; GFX12W64-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12W64-NEXT: s_ctz_i32_b64 s3, s[0:1]
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: v_readlane_b32 s8, v1, s3
; GFX12W64-NEXT: v_writelane_b32 v0, s2, s3
; GFX12W64-NEXT: s_lshl_b64 s[6:7], 1, s3
@@ -2327,7 +2327,7 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W64-NEXT: s_wait_loadcnt 0x0
; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1
; GFX12W64-NEXT: v_mov_b32_e32 v1, 0
-; GFX12W64-NEXT: s_wait_alu 0xf1ff
+; GFX12W64-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12W64-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX12W64-NEXT: s_wait_kmcnt 0x0
@@ -2342,14 +2342,14 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: ; implicit-def: $vgpr0
; GFX12W32-NEXT: .LBB7_1: ; %ComputeLoop
; GFX12W32-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_ctz_i32_b32 s2, s1
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: v_readlane_b32 s3, v1, s2
; GFX12W32-NEXT: v_writelane_b32 v0, s0, s2
; GFX12W32-NEXT: s_lshl_b32 s2, 1, s2
; GFX12W32-NEXT: s_add_co_i32 s0, s0, s3
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_and_not1_b32 s1, s1, s2
; GFX12W32-NEXT: s_cbranch_scc1 .LBB7_1
; GFX12W32-NEXT: ; %bb.2: ; %ComputeEnd
@@ -2358,7 +2358,7 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX12W32-NEXT: ; implicit-def: $vgpr1
; GFX12W32-NEXT: s_and_saveexec_b32 s1, vcc_lo
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_xor_b32 s1, exec_lo, s1
; GFX12W32-NEXT: s_cbranch_execz .LBB7_4
; GFX12W32-NEXT: ; %bb.3:
@@ -2367,13 +2367,13 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
; GFX12W32-NEXT: .LBB7_4:
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12W32-NEXT: s_wait_loadcnt 0x0
; GFX12W32-NEXT: v_readfirstlane_b32 s2, v1
; GFX12W32-NEXT: v_mov_b32_e32 v1, 0
-; GFX12W32-NEXT: s_wait_alu 0xf1ff
+; GFX12W32-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12W32-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX12W32-NEXT: s_wait_kmcnt 0x0
@@ -2432,7 +2432,7 @@ define amdgpu_kernel void @sub_i32_varying_offset(ptr addrspace(1) %out, ptr add
; GFX10-NEXT: v_mov_b32_e32 v1, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: buffer_atomic_sub v1, v0, s[0:3], 0 offen glc
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
index 50e28a7245db8..12cb8d2f6fb51 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
@@ -151,7 +151,7 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1064-NEXT: buffer_gl1_inv
; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: .LBB0_2:
-; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: v_readfirstlane_b32 s2, v1
@@ -184,7 +184,7 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1032-NEXT: buffer_gl1_inv
; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: .LBB0_2:
-; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_readfirstlane_b32 s2, v1
@@ -275,10 +275,10 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1264-NEXT: ; %bb.1:
; GFX1264-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GFX1264-NEXT: s_mov_b32 s11, 0x31016000
-; GFX1264-NEXT: s_wait_alu 0xfffe
+; GFX1264-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264-NEXT: s_mul_i32 s6, s6, 5
; GFX1264-NEXT: s_mov_b32 s10, -1
-; GFX1264-NEXT: s_wait_alu 0xfffe
+; GFX1264-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264-NEXT: v_mov_b32_e32 v1, s6
; GFX1264-NEXT: s_wait_kmcnt 0x0
; GFX1264-NEXT: s_mov_b32 s8, s2
@@ -462,7 +462,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1064-NEXT: buffer_gl1_inv
; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: .LBB1_2:
-; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: v_readfirstlane_b32 s2, v1
@@ -497,7 +497,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1032-NEXT: buffer_gl1_inv
; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: .LBB1_2:
-; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_readfirstlane_b32 s2, v1
@@ -597,10 +597,10 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1264-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GFX1264-NEXT: s_mov_b32 s15, 0x31016000
; GFX1264-NEXT: s_wait_kmcnt 0x0
-; GFX1264-NEXT: s_wait_alu 0xfffe
+; GFX1264-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264-NEXT: s_mul_i32 s6, s8, s6
; GFX1264-NEXT: s_mov_b32 s14, -1
-; GFX1264-NEXT: s_wait_alu 0xfffe
+; GFX1264-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264-NEXT: v_mov_b32_e32 v1, s6
; GFX1264-NEXT: s_mov_b32 s12, s2
; GFX1264-NEXT: s_mov_b32 s13, s3
@@ -634,10 +634,10 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1232-NEXT: s_bcnt1_i32_b32 s6, s6
; GFX1232-NEXT: s_mov_b32 s11, 0x31016000
; GFX1232-NEXT: s_wait_kmcnt 0x0
-; GFX1232-NEXT: s_wait_alu 0xfffe
+; GFX1232-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-NEXT: s_mul_i32 s6, s4, s6
; GFX1232-NEXT: s_mov_b32 s10, -1
-; GFX1232-NEXT: s_wait_alu 0xfffe
+; GFX1232-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-NEXT: v_mov_b32_e32 v1, s6
; GFX1232-NEXT: s_mov_b32 s8, s2
; GFX1232-NEXT: s_mov_b32 s9, s3
@@ -831,7 +831,7 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1064_ITERATIVE-NEXT: buffer_gl1_inv
; GFX1064_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1064_ITERATIVE-NEXT: .LBB2_4:
-; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_ITERATIVE-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v0
@@ -875,7 +875,7 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1032_ITERATIVE-NEXT: buffer_gl1_inv
; GFX1032_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1032_ITERATIVE-NEXT: .LBB2_4:
-; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_ITERATIVE-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v0
@@ -988,12 +988,12 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1264_ITERATIVE-NEXT: .LBB2_1: ; %ComputeLoop
; GFX1264_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1264_ITERATIVE-NEXT: s_ctz_i32_b64 s2, s[0:1]
-; GFX1264_ITERATIVE-NEXT: s_wait_alu 0xfffe
+; GFX1264_ITERATIVE-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264_ITERATIVE-NEXT: v_readlane_b32 s7, v1, s2
; GFX1264_ITERATIVE-NEXT: v_writelane_b32 v0, s6, s2
; GFX1264_ITERATIVE-NEXT: s_lshl_b64 s[2:3], 1, s2
; GFX1264_ITERATIVE-NEXT: s_add_co_i32 s6, s6, s7
-; GFX1264_ITERATIVE-NEXT: s_wait_alu 0xfffe
+; GFX1264_ITERATIVE-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264_ITERATIVE-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[2:3]
; GFX1264_ITERATIVE-NEXT: s_cbranch_scc1 .LBB2_1
; GFX1264_ITERATIVE-NEXT: ; %bb.2: ; %ComputeEnd
@@ -1022,7 +1022,7 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1264_ITERATIVE-NEXT: s_wait_kmcnt 0x0
; GFX1264_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v1
; GFX1264_ITERATIVE-NEXT: s_mov_b32 s3, 0x31016000
-; GFX1264_ITERATIVE-NEXT: s_wait_alu 0xf1ff
+; GFX1264_ITERATIVE-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1264_ITERATIVE-NEXT: v_add_nc_u32_e32 v0, s2, v0
; GFX1264_ITERATIVE-NEXT: s_mov_b32 s2, -1
; GFX1264_ITERATIVE-NEXT: buffer_store_b32 v0, off, s[0:3], null
@@ -1036,14 +1036,14 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1232_ITERATIVE-NEXT: ; implicit-def: $vgpr0
; GFX1232_ITERATIVE-NEXT: .LBB2_1: ; %ComputeLoop
; GFX1232_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1232_ITERATIVE-NEXT: s_wait_alu 0xfffe
+; GFX1232_ITERATIVE-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232_ITERATIVE-NEXT: s_ctz_i32_b32 s1, s0
-; GFX1232_ITERATIVE-NEXT: s_wait_alu 0xfffe
+; GFX1232_ITERATIVE-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232_ITERATIVE-NEXT: v_readlane_b32 s2, v1, s1
; GFX1232_ITERATIVE-NEXT: v_writelane_b32 v0, s6, s1
; GFX1232_ITERATIVE-NEXT: s_lshl_b32 s1, 1, s1
; GFX1232_ITERATIVE-NEXT: s_add_co_i32 s6, s6, s2
-; GFX1232_ITERATIVE-NEXT: s_wait_alu 0xfffe
+; GFX1232_ITERATIVE-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232_ITERATIVE-NEXT: s_and_not1_b32 s0, s0, s1
; GFX1232_ITERATIVE-NEXT: s_cbranch_scc1 .LBB2_1
; GFX1232_ITERATIVE-NEXT: ; %bb.2: ; %ComputeEnd
@@ -1244,7 +1244,7 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1064_DPP-NEXT: buffer_gl1_inv
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB2_2:
-; GFX1064_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_DPP-NEXT: s_or_b64 exec, exec, s[8:9]
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: v_readfirstlane_b32 s2, v0
@@ -1294,7 +1294,7 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1032_DPP-NEXT: buffer_gl1_inv
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB2_2:
-; GFX1032_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_DPP-NEXT: s_or_b32 exec_lo, exec_lo, s8
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: v_readfirstlane_b32 s2, v0
@@ -1472,7 +1472,7 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1264_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1264_DPP-NEXT: s_mov_b32 s4, s9
; GFX1264_DPP-NEXT: v_writelane_b32 v3, s8, 48
-; GFX1264_DPP-NEXT: s_wait_alu 0xfffe
+; GFX1264_DPP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264_DPP-NEXT: s_mov_b64 exec, s[6:7]
; GFX1264_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1264_DPP-NEXT: s_mov_b32 s6, -1
@@ -1489,13 +1489,13 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1264_DPP-NEXT: s_wait_loadcnt 0x0
; GFX1264_DPP-NEXT: global_inv scope:SCOPE_DEV
; GFX1264_DPP-NEXT: .LBB2_2:
-; GFX1264_DPP-NEXT: s_wait_alu 0xfffe
+; GFX1264_DPP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264_DPP-NEXT: s_or_b64 exec, exec, s[8:9]
; GFX1264_DPP-NEXT: s_wait_kmcnt 0x0
; GFX1264_DPP-NEXT: v_readfirstlane_b32 s2, v0
; GFX1264_DPP-NEXT: v_mov_b32_e32 v0, v3
; GFX1264_DPP-NEXT: s_mov_b32 s3, 0x31016000
-; GFX1264_DPP-NEXT: s_wait_alu 0xf1ff
+; GFX1264_DPP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1264_DPP-NEXT: v_add_nc_u32_e32 v0, s2, v0
; GFX1264_DPP-NEXT: s_mov_b32 s2, s6
@@ -1538,7 +1538,7 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1232_DPP-NEXT: s_and_saveexec_b32 s8, vcc_lo
; GFX1232_DPP-NEXT: s_cbranch_execz .LBB2_2
; GFX1232_DPP-NEXT: ; %bb.1:
-; GFX1232_DPP-NEXT: s_wait_alu 0xfffe
+; GFX1232_DPP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232_DPP-NEXT: v_mov_b32_e32 v0, s4
; GFX1232_DPP-NEXT: s_mov_b32 s7, 0x31016000
; GFX1232_DPP-NEXT: s_wait_kmcnt 0x0
@@ -1704,7 +1704,7 @@ define amdgpu_kernel void @add_i64_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1064-NEXT: buffer_gl1_inv
; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: .LBB3_2:
-; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: v_readfirstlane_b32 s3, v1
@@ -1739,7 +1739,7 @@ define amdgpu_kernel void @add_i64_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1032-NEXT: buffer_gl1_inv
; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: .LBB3_2:
-; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_readfirstlane_b32 s3, v1
@@ -1836,10 +1836,10 @@ define amdgpu_kernel void @add_i64_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1264-NEXT: ; %bb.1:
; GFX1264-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GFX1264-NEXT: v_mov_b32_e32 v1, 0
-; GFX1264-NEXT: s_wait_alu 0xfffe
+; GFX1264-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264-NEXT: s_mul_i32 s6, s6, 5
; GFX1264-NEXT: s_mov_b32 s11, 0x31016000
-; GFX1264-NEXT: s_wait_alu 0xfffe
+; GFX1264-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264-NEXT: v_mov_b32_e32 v0, s6
; GFX1264-NEXT: s_mov_b32 s10, -1
; GFX1264-NEXT: s_wait_kmcnt 0x0
@@ -2058,7 +2058,7 @@ define amdgpu_kernel void @add_i64_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1064-NEXT: buffer_gl1_inv
; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: .LBB4_2:
-; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: v_readfirstlane_b32 s3, v1
@@ -2099,7 +2099,7 @@ define amdgpu_kernel void @add_i64_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1032-NEXT: buffer_gl1_inv
; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: .LBB4_2:
-; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_readfirstlane_b32 s3, v1
@@ -2217,7 +2217,7 @@ define amdgpu_kernel void @add_i64_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1264-NEXT: s_wait_kmcnt 0x0
; GFX1264-NEXT: s_mul_u64 s[8:9], s[4:5], s[10:11]
; GFX1264-NEXT: s_mov_b32 s11, 0x31016000
-; GFX1264-NEXT: s_wait_alu 0xfffe
+; GFX1264-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264-NEXT: v_mov_b32_e32 v0, s8
; GFX1264-NEXT: v_mov_b32_e32 v1, s9
; GFX1264-NEXT: s_mov_b32 s10, -1
@@ -2256,10 +2256,10 @@ define amdgpu_kernel void @add_i64_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1232-NEXT: s_bcnt1_i32_b32 s6, s6
; GFX1232-NEXT: s_mov_b32 s15, 0x31016000
; GFX1232-NEXT: s_wait_kmcnt 0x0
-; GFX1232-NEXT: s_wait_alu 0xfffe
+; GFX1232-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-NEXT: s_mul_u64 s[6:7], s[4:5], s[6:7]
; GFX1232-NEXT: s_mov_b32 s14, -1
-; GFX1232-NEXT: s_wait_alu 0xfffe
+; GFX1232-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
; GFX1232-NEXT: s_mov_b32 s12, s2
; GFX1232-NEXT: s_mov_b32 s13, s3
@@ -2484,7 +2484,7 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1064_ITERATIVE-NEXT: buffer_gl1_inv
; GFX1064_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1064_ITERATIVE-NEXT: .LBB5_4:
-; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_ITERATIVE-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v3
@@ -2535,7 +2535,7 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1032_ITERATIVE-NEXT: buffer_gl1_inv
; GFX1032_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1032_ITERATIVE-NEXT: .LBB5_4:
-; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_ITERATIVE-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v3
@@ -2667,13 +2667,13 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1264_ITERATIVE-NEXT: .LBB5_1: ; %ComputeLoop
; GFX1264_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1264_ITERATIVE-NEXT: s_ctz_i32_b64 s8, s[0:1]
-; GFX1264_ITERATIVE-NEXT: s_wait_alu 0xfffe
+; GFX1264_ITERATIVE-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264_ITERATIVE-NEXT: v_readlane_b32 s3, v2, s8
; GFX1264_ITERATIVE-NEXT: v_readlane_b32 s2, v3, s8
; GFX1264_ITERATIVE-NEXT: v_writelane_b32 v1, s7, s8
; GFX1264_ITERATIVE-NEXT: v_writelane_b32 v0, s6, s8
; GFX1264_ITERATIVE-NEXT: s_lshl_b64 s[8:9], 1, s8
-; GFX1264_ITERATIVE-NEXT: s_wait_alu 0xfffe
+; GFX1264_ITERATIVE-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264_ITERATIVE-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[8:9]
; GFX1264_ITERATIVE-NEXT: s_add_nc_u64 s[6:7], s[6:7], s[2:3]
; GFX1264_ITERATIVE-NEXT: s_cbranch_scc1 .LBB5_1
@@ -2720,15 +2720,15 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1232_ITERATIVE-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1232_ITERATIVE-NEXT: .LBB5_1: ; %ComputeLoop
; GFX1232_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1232_ITERATIVE-NEXT: s_wait_alu 0xfffe
+; GFX1232_ITERATIVE-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232_ITERATIVE-NEXT: s_ctz_i32_b32 s1, s0
-; GFX1232_ITERATIVE-NEXT: s_wait_alu 0xfffe
+; GFX1232_ITERATIVE-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232_ITERATIVE-NEXT: v_readlane_b32 s3, v2, s1
; GFX1232_ITERATIVE-NEXT: v_readlane_b32 s2, v3, s1
; GFX1232_ITERATIVE-NEXT: v_writelane_b32 v1, s7, s1
; GFX1232_ITERATIVE-NEXT: v_writelane_b32 v0, s6, s1
; GFX1232_ITERATIVE-NEXT: s_lshl_b32 s1, 1, s1
-; GFX1232_ITERATIVE-NEXT: s_wait_alu 0xfffe
+; GFX1232_ITERATIVE-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232_ITERATIVE-NEXT: s_and_not1_b32 s0, s0, s1
; GFX1232_ITERATIVE-NEXT: s_add_nc_u64 s[6:7], s[6:7], s[2:3]
; GFX1232_ITERATIVE-NEXT: s_cbranch_scc1 .LBB5_1
@@ -3040,7 +3040,7 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1064_DPP-NEXT: buffer_gl1_inv
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB5_2:
-; GFX1064_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_DPP-NEXT: s_or_b64 exec, exec, s[8:9]
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: v_readfirstlane_b32 s2, v8
@@ -3125,7 +3125,7 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1032_DPP-NEXT: buffer_gl1_inv
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB5_2:
-; GFX1032_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_DPP-NEXT: s_or_b32 exec_lo, exec_lo, s8
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: v_readfirstlane_b32 s2, v9
@@ -3154,19 +3154,19 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v3, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:8 row_mask:0xf bank_mask:0xf
@@ -3174,7 +3174,7 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v5, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v5, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_permlanex16_b32 v4, v1, -1, -1
@@ -3189,7 +3189,7 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v2, s2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
@@ -3243,7 +3243,7 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1164_DPP-NEXT: v_readfirstlane_b32 s3, v7
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_add_co_u32 v6, vcc, s2, v8
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: s_mov_b32 s2, s6
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v7, null, s3, v9, vcc
; GFX1164_DPP-NEXT: s_mov_b32 s3, 0x31016000
@@ -3353,20 +3353,20 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1264_DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1264_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
-; GFX1264_DPP-NEXT: s_wait_alu 0xfffd
+; GFX1264_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1264_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
; GFX1264_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1264_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1264_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
-; GFX1264_DPP-NEXT: s_wait_alu 0xfffd
+; GFX1264_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1264_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
; GFX1264_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1264_DPP-NEXT: v_mov_b32_e32 v3, 0
; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1264_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:8 row_mask:0xf bank_mask:0xf
; GFX1264_DPP-NEXT: v_permlanex16_b32 v5, v2, -1, -1
-; GFX1264_DPP-NEXT: s_wait_alu 0xfffd
+; GFX1264_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1264_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
; GFX1264_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v5, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
@@ -3374,7 +3374,7 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1264_DPP-NEXT: v_permlanex16_b32 v4, v1, -1, -1
; GFX1264_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
-; GFX1264_DPP-NEXT: s_wait_alu 0xfffd
+; GFX1264_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1264_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
; GFX1264_DPP-NEXT: v_mov_b32_e32 v3, 0
@@ -3383,11 +3383,11 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1264_DPP-NEXT: v_mov_b32_e32 v4, s2
; GFX1264_DPP-NEXT: v_readlane_b32 s2, v2, 31
; GFX1264_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
-; GFX1264_DPP-NEXT: s_wait_alu 0xf1ff
+; GFX1264_DPP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1264_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v2, s2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
; GFX1264_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX1264_DPP-NEXT: s_wait_alu 0xfffd
+; GFX1264_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1264_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
; GFX1264_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1264_DPP-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@@ -3414,7 +3414,7 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1264_DPP-NEXT: s_mov_b64 s[4:5], s[6:7]
; GFX1264_DPP-NEXT: v_writelane_b32 v4, s10, 48
; GFX1264_DPP-NEXT: v_writelane_b32 v5, s11, 48
-; GFX1264_DPP-NEXT: s_wait_alu 0xfffe
+; GFX1264_DPP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264_DPP-NEXT: s_mov_b64 exec, s[8:9]
; GFX1264_DPP-NEXT: s_mov_b32 s6, -1
; GFX1264_DPP-NEXT: s_mov_b64 s[8:9], exec
@@ -3432,18 +3432,18 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1264_DPP-NEXT: s_wait_loadcnt 0x0
; GFX1264_DPP-NEXT: global_inv scope:SCOPE_DEV
; GFX1264_DPP-NEXT: .LBB5_2:
-; GFX1264_DPP-NEXT: s_wait_alu 0xfffe
+; GFX1264_DPP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264_DPP-NEXT: s_or_b64 exec, exec, s[8:9]
; GFX1264_DPP-NEXT: s_wait_kmcnt 0x0
; GFX1264_DPP-NEXT: v_readfirstlane_b32 s2, v6
; GFX1264_DPP-NEXT: v_mov_b32_e32 v8, v4
; GFX1264_DPP-NEXT: v_mov_b32_e32 v9, v5
; GFX1264_DPP-NEXT: v_readfirstlane_b32 s3, v7
-; GFX1264_DPP-NEXT: s_wait_alu 0xf1ff
+; GFX1264_DPP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1264_DPP-NEXT: v_add_co_u32 v6, vcc, s2, v8
; GFX1264_DPP-NEXT: s_mov_b32 s2, s6
-; GFX1264_DPP-NEXT: s_wait_alu 0xfffd
+; GFX1264_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1264_DPP-NEXT: v_add_co_ci_u32_e64 v7, null, s3, v9, vcc
; GFX1264_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1264_DPP-NEXT: buffer_store_b64 v[6:7], off, s[0:3], null
@@ -3468,20 +3468,20 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1232_DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1232_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
-; GFX1232_DPP-NEXT: s_wait_alu 0xfffd
+; GFX1232_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1232_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
; GFX1232_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1232_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1232_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
-; GFX1232_DPP-NEXT: s_wait_alu 0xfffd
+; GFX1232_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1232_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc_lo
; GFX1232_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc_lo, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1232_DPP-NEXT: v_mov_b32_e32 v3, 0
; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1232_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:8 row_mask:0xf bank_mask:0xf
; GFX1232_DPP-NEXT: v_permlanex16_b32 v5, v2, -1, -1
-; GFX1232_DPP-NEXT: s_wait_alu 0xfffd
+; GFX1232_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1232_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
; GFX1232_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc_lo, v5, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
@@ -3521,7 +3521,7 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1232_DPP-NEXT: s_wait_loadcnt 0x0
; GFX1232_DPP-NEXT: global_inv scope:SCOPE_DEV
; GFX1232_DPP-NEXT: .LBB5_2:
-; GFX1232_DPP-NEXT: s_wait_alu 0xfffe
+; GFX1232_DPP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232_DPP-NEXT: s_or_b32 exec_lo, exec_lo, s8
; GFX1232_DPP-NEXT: s_wait_kmcnt 0x0
; GFX1232_DPP-NEXT: v_readfirstlane_b32 s2, v8
@@ -3531,7 +3531,7 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1232_DPP-NEXT: v_add_co_u32 v8, vcc_lo, s2, v10
; GFX1232_DPP-NEXT: s_mov_b32 s2, s6
-; GFX1232_DPP-NEXT: s_wait_alu 0xfffd
+; GFX1232_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1232_DPP-NEXT: v_add_co_ci_u32_e64 v9, null, s3, v11, vcc_lo
; GFX1232_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1232_DPP-NEXT: buffer_store_b64 v[8:9], off, s[0:3], null
@@ -3908,10 +3908,10 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1264-NEXT: ; %bb.1:
; GFX1264-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GFX1264-NEXT: s_mov_b32 s11, 0x31016000
-; GFX1264-NEXT: s_wait_alu 0xfffe
+; GFX1264-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264-NEXT: s_mul_i32 s6, s6, 5
; GFX1264-NEXT: s_mov_b32 s10, -1
-; GFX1264-NEXT: s_wait_alu 0xfffe
+; GFX1264-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264-NEXT: v_mov_b32_e32 v1, s6
; GFX1264-NEXT: s_wait_kmcnt 0x0
; GFX1264-NEXT: s_mov_b32 s8, s2
@@ -4348,10 +4348,10 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1264-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GFX1264-NEXT: s_mov_b32 s15, 0x31016000
; GFX1264-NEXT: s_wait_kmcnt 0x0
-; GFX1264-NEXT: s_wait_alu 0xfffe
+; GFX1264-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264-NEXT: s_mul_i32 s6, s8, s6
; GFX1264-NEXT: s_mov_b32 s14, -1
-; GFX1264-NEXT: s_wait_alu 0xfffe
+; GFX1264-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264-NEXT: v_mov_b32_e32 v1, s6
; GFX1264-NEXT: s_mov_b32 s12, s2
; GFX1264-NEXT: s_mov_b32 s13, s3
@@ -4385,10 +4385,10 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1232-NEXT: s_bcnt1_i32_b32 s6, s6
; GFX1232-NEXT: s_mov_b32 s11, 0x31016000
; GFX1232-NEXT: s_wait_kmcnt 0x0
-; GFX1232-NEXT: s_wait_alu 0xfffe
+; GFX1232-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-NEXT: s_mul_i32 s6, s4, s6
; GFX1232-NEXT: s_mov_b32 s10, -1
-; GFX1232-NEXT: s_wait_alu 0xfffe
+; GFX1232-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-NEXT: v_mov_b32_e32 v1, s6
; GFX1232-NEXT: s_mov_b32 s8, s2
; GFX1232-NEXT: s_mov_b32 s9, s3
@@ -4850,12 +4850,12 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1264_ITERATIVE-NEXT: .LBB8_1: ; %ComputeLoop
; GFX1264_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1264_ITERATIVE-NEXT: s_ctz_i32_b64 s2, s[0:1]
-; GFX1264_ITERATIVE-NEXT: s_wait_alu 0xfffe
+; GFX1264_ITERATIVE-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264_ITERATIVE-NEXT: v_readlane_b32 s7, v1, s2
; GFX1264_ITERATIVE-NEXT: v_writelane_b32 v0, s6, s2
; GFX1264_ITERATIVE-NEXT: s_lshl_b64 s[2:3], 1, s2
; GFX1264_ITERATIVE-NEXT: s_add_co_i32 s6, s6, s7
-; GFX1264_ITERATIVE-NEXT: s_wait_alu 0xfffe
+; GFX1264_ITERATIVE-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264_ITERATIVE-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[2:3]
; GFX1264_ITERATIVE-NEXT: s_cbranch_scc1 .LBB8_1
; GFX1264_ITERATIVE-NEXT: ; %bb.2: ; %ComputeEnd
@@ -4884,7 +4884,7 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1264_ITERATIVE-NEXT: s_wait_kmcnt 0x0
; GFX1264_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v1
; GFX1264_ITERATIVE-NEXT: s_mov_b32 s3, 0x31016000
-; GFX1264_ITERATIVE-NEXT: s_wait_alu 0xf1ff
+; GFX1264_ITERATIVE-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1264_ITERATIVE-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX1264_ITERATIVE-NEXT: s_mov_b32 s2, -1
; GFX1264_ITERATIVE-NEXT: buffer_store_b32 v0, off, s[0:3], null
@@ -4898,14 +4898,14 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1232_ITERATIVE-NEXT: ; implicit-def: $vgpr0
; GFX1232_ITERATIVE-NEXT: .LBB8_1: ; %ComputeLoop
; GFX1232_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1232_ITERATIVE-NEXT: s_wait_alu 0xfffe
+; GFX1232_ITERATIVE-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232_ITERATIVE-NEXT: s_ctz_i32_b32 s1, s0
-; GFX1232_ITERATIVE-NEXT: s_wait_alu 0xfffe
+; GFX1232_ITERATIVE-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232_ITERATIVE-NEXT: v_readlane_b32 s2, v1, s1
; GFX1232_ITERATIVE-NEXT: v_writelane_b32 v0, s6, s1
; GFX1232_ITERATIVE-NEXT: s_lshl_b32 s1, 1, s1
; GFX1232_ITERATIVE-NEXT: s_add_co_i32 s6, s6, s2
-; GFX1232_ITERATIVE-NEXT: s_wait_alu 0xfffe
+; GFX1232_ITERATIVE-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232_ITERATIVE-NEXT: s_and_not1_b32 s0, s0, s1
; GFX1232_ITERATIVE-NEXT: s_cbranch_scc1 .LBB8_1
; GFX1232_ITERATIVE-NEXT: ; %bb.2: ; %ComputeEnd
@@ -5439,7 +5439,7 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1264_DPP-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1264_DPP-NEXT: s_mov_b32 s4, s9
; GFX1264_DPP-NEXT: v_writelane_b32 v3, s8, 48
-; GFX1264_DPP-NEXT: s_wait_alu 0xfffe
+; GFX1264_DPP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264_DPP-NEXT: s_mov_b64 exec, s[6:7]
; GFX1264_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX1264_DPP-NEXT: s_mov_b32 s6, -1
@@ -5456,13 +5456,13 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1264_DPP-NEXT: s_wait_loadcnt 0x0
; GFX1264_DPP-NEXT: global_inv scope:SCOPE_DEV
; GFX1264_DPP-NEXT: .LBB8_2:
-; GFX1264_DPP-NEXT: s_wait_alu 0xfffe
+; GFX1264_DPP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264_DPP-NEXT: s_or_b64 exec, exec, s[8:9]
; GFX1264_DPP-NEXT: s_wait_kmcnt 0x0
; GFX1264_DPP-NEXT: v_readfirstlane_b32 s2, v0
; GFX1264_DPP-NEXT: v_mov_b32_e32 v0, v3
; GFX1264_DPP-NEXT: s_mov_b32 s3, 0x31016000
-; GFX1264_DPP-NEXT: s_wait_alu 0xf1ff
+; GFX1264_DPP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1264_DPP-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX1264_DPP-NEXT: s_mov_b32 s2, s6
@@ -5505,7 +5505,7 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1232_DPP-NEXT: s_and_saveexec_b32 s8, vcc_lo
; GFX1232_DPP-NEXT: s_cbranch_execz .LBB8_2
; GFX1232_DPP-NEXT: ; %bb.1:
-; GFX1232_DPP-NEXT: s_wait_alu 0xfffe
+; GFX1232_DPP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232_DPP-NEXT: v_mov_b32_e32 v0, s4
; GFX1232_DPP-NEXT: s_mov_b32 s7, 0x31016000
; GFX1232_DPP-NEXT: s_wait_kmcnt 0x0
@@ -5861,7 +5861,7 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1164-NEXT: buffer_gl1_inv
; GFX1164-NEXT: buffer_gl0_inv
; GFX1164-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[7:8]
-; GFX1164-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GFX1164-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1164-NEXT: s_and_not1_b64 exec, exec, s[10:11]
@@ -5958,10 +5958,10 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1264-NEXT: ; %bb.1:
; GFX1264-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GFX1264-NEXT: v_mov_b32_e32 v1, 0
-; GFX1264-NEXT: s_wait_alu 0xfffe
+; GFX1264-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264-NEXT: s_mul_i32 s6, s6, 5
; GFX1264-NEXT: s_mov_b32 s11, 0x31016000
-; GFX1264-NEXT: s_wait_alu 0xfffe
+; GFX1264-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264-NEXT: v_mov_b32_e32 v0, s6
; GFX1264-NEXT: s_mov_b32 s10, -1
; GFX1264-NEXT: s_wait_kmcnt 0x0
@@ -6389,7 +6389,7 @@ define amdgpu_kernel void @sub_i64_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1164-NEXT: buffer_gl1_inv
; GFX1164-NEXT: buffer_gl0_inv
; GFX1164-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[7:8]
-; GFX1164-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164-NEXT: s_or_b64 s[12:13], vcc, s[12:13]
; GFX1164-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1164-NEXT: s_and_not1_b64 exec, exec, s[12:13]
@@ -6403,7 +6403,7 @@ define amdgpu_kernel void @sub_i64_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1164-NEXT: v_mad_u64_u32 v[2:3], null, s8, v4, 0
; GFX1164-NEXT: v_readfirstlane_b32 s2, v0
; GFX1164-NEXT: v_readfirstlane_b32 s3, v1
-; GFX1164-NEXT: s_waitcnt_depctr 0xfff
+; GFX1164-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1164-NEXT: v_mad_u64_u32 v[5:6], null, s9, v4, v[3:4]
; GFX1164-NEXT: v_sub_co_u32 v0, vcc, s2, v2
; GFX1164-NEXT: s_mov_b32 s2, -1
@@ -6497,7 +6497,7 @@ define amdgpu_kernel void @sub_i64_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1264-NEXT: s_wait_kmcnt 0x0
; GFX1264-NEXT: s_mul_u64 s[8:9], s[4:5], s[10:11]
; GFX1264-NEXT: s_mov_b32 s11, 0x31016000
-; GFX1264-NEXT: s_wait_alu 0xfffe
+; GFX1264-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264-NEXT: v_mov_b32_e32 v0, s8
; GFX1264-NEXT: v_mov_b32_e32 v1, s9
; GFX1264-NEXT: s_mov_b32 s10, -1
@@ -6538,10 +6538,10 @@ define amdgpu_kernel void @sub_i64_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1232-NEXT: s_bcnt1_i32_b32 s6, s6
; GFX1232-NEXT: s_mov_b32 s15, 0x31016000
; GFX1232-NEXT: s_wait_kmcnt 0x0
-; GFX1232-NEXT: s_wait_alu 0xfffe
+; GFX1232-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-NEXT: s_mul_u64 s[6:7], s[4:5], s[6:7]
; GFX1232-NEXT: s_mov_b32 s14, -1
-; GFX1232-NEXT: s_wait_alu 0xfffe
+; GFX1232-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
; GFX1232-NEXT: s_mov_b32 s12, s2
; GFX1232-NEXT: s_mov_b32 s13, s3
@@ -6989,7 +6989,7 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1164_ITERATIVE-NEXT: buffer_gl1_inv
; GFX1164_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1164_ITERATIVE-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[8:9]
-; GFX1164_ITERATIVE-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_ITERATIVE-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_ITERATIVE-NEXT: s_or_b64 s[12:13], vcc, s[12:13]
; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1164_ITERATIVE-NEXT: s_and_not1_b64 exec, exec, s[12:13]
@@ -7095,13 +7095,13 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1264_ITERATIVE-NEXT: .LBB11_1: ; %ComputeLoop
; GFX1264_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1264_ITERATIVE-NEXT: s_ctz_i32_b64 s8, s[0:1]
-; GFX1264_ITERATIVE-NEXT: s_wait_alu 0xfffe
+; GFX1264_ITERATIVE-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264_ITERATIVE-NEXT: v_readlane_b32 s3, v2, s8
; GFX1264_ITERATIVE-NEXT: v_readlane_b32 s2, v3, s8
; GFX1264_ITERATIVE-NEXT: v_writelane_b32 v1, s7, s8
; GFX1264_ITERATIVE-NEXT: v_writelane_b32 v0, s6, s8
; GFX1264_ITERATIVE-NEXT: s_lshl_b64 s[8:9], 1, s8
-; GFX1264_ITERATIVE-NEXT: s_wait_alu 0xfffe
+; GFX1264_ITERATIVE-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264_ITERATIVE-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[8:9]
; GFX1264_ITERATIVE-NEXT: s_add_nc_u64 s[6:7], s[6:7], s[2:3]
; GFX1264_ITERATIVE-NEXT: s_cbranch_scc1 .LBB11_1
@@ -7148,15 +7148,15 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1232_ITERATIVE-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX1232_ITERATIVE-NEXT: .LBB11_1: ; %ComputeLoop
; GFX1232_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1232_ITERATIVE-NEXT: s_wait_alu 0xfffe
+; GFX1232_ITERATIVE-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232_ITERATIVE-NEXT: s_ctz_i32_b32 s1, s0
-; GFX1232_ITERATIVE-NEXT: s_wait_alu 0xfffe
+; GFX1232_ITERATIVE-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232_ITERATIVE-NEXT: v_readlane_b32 s3, v2, s1
; GFX1232_ITERATIVE-NEXT: v_readlane_b32 s2, v3, s1
; GFX1232_ITERATIVE-NEXT: v_writelane_b32 v1, s7, s1
; GFX1232_ITERATIVE-NEXT: v_writelane_b32 v0, s6, s1
; GFX1232_ITERATIVE-NEXT: s_lshl_b32 s1, 1, s1
-; GFX1232_ITERATIVE-NEXT: s_wait_alu 0xfffe
+; GFX1232_ITERATIVE-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232_ITERATIVE-NEXT: s_and_not1_b32 s0, s0, s1
; GFX1232_ITERATIVE-NEXT: s_add_nc_u64 s[6:7], s[6:7], s[2:3]
; GFX1232_ITERATIVE-NEXT: s_cbranch_scc1 .LBB11_1
@@ -7676,19 +7676,19 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v3, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:8 row_mask:0xf bank_mask:0xf
@@ -7696,7 +7696,7 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v5, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v5, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_permlanex16_b32 v4, v1, -1, -1
@@ -7711,7 +7711,7 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v2, s2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
@@ -7761,7 +7761,7 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1164_DPP-NEXT: v_mov_b32_e32 v10, v6
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_sub_co_u32 v8, vcc, v10, s8
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_subrev_co_ci_u32_e64 v9, null, s9, v11, vcc
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v6, v8
@@ -7773,7 +7773,7 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1164_DPP-NEXT: buffer_gl1_inv
; GFX1164_DPP-NEXT: buffer_gl0_inv
; GFX1164_DPP-NEXT: v_cmp_eq_u64_e32 vcc, v[6:7], v[10:11]
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: s_or_b64 s[12:13], vcc, s[12:13]
; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1164_DPP-NEXT: s_and_not1_b64 exec, exec, s[12:13]
@@ -7790,7 +7790,7 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1164_DPP-NEXT: v_readfirstlane_b32 s3, v7
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_sub_co_u32 v6, vcc, s2, v8
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: s_mov_b32 s2, -1
; GFX1164_DPP-NEXT: v_sub_co_ci_u32_e64 v7, null, s3, v9, vcc
; GFX1164_DPP-NEXT: s_mov_b32 s3, 0x31016000
@@ -7922,20 +7922,20 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1264_DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1264_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
-; GFX1264_DPP-NEXT: s_wait_alu 0xfffd
+; GFX1264_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1264_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
; GFX1264_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1264_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1264_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
-; GFX1264_DPP-NEXT: s_wait_alu 0xfffd
+; GFX1264_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1264_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
; GFX1264_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1264_DPP-NEXT: v_mov_b32_e32 v3, 0
; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1264_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:8 row_mask:0xf bank_mask:0xf
; GFX1264_DPP-NEXT: v_permlanex16_b32 v5, v2, -1, -1
-; GFX1264_DPP-NEXT: s_wait_alu 0xfffd
+; GFX1264_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1264_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
; GFX1264_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v5, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
@@ -7943,7 +7943,7 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1264_DPP-NEXT: v_permlanex16_b32 v4, v1, -1, -1
; GFX1264_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
-; GFX1264_DPP-NEXT: s_wait_alu 0xfffd
+; GFX1264_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1264_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
; GFX1264_DPP-NEXT: v_mov_b32_e32 v3, 0
@@ -7952,11 +7952,11 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1264_DPP-NEXT: v_mov_b32_e32 v4, s2
; GFX1264_DPP-NEXT: v_readlane_b32 s2, v2, 31
; GFX1264_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
-; GFX1264_DPP-NEXT: s_wait_alu 0xf1ff
+; GFX1264_DPP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1264_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v2, s2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
; GFX1264_DPP-NEXT: v_mov_b32_e32 v4, 0
-; GFX1264_DPP-NEXT: s_wait_alu 0xfffd
+; GFX1264_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1264_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
; GFX1264_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1264_DPP-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@@ -7983,7 +7983,7 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1264_DPP-NEXT: s_mov_b64 s[4:5], s[6:7]
; GFX1264_DPP-NEXT: v_writelane_b32 v4, s10, 48
; GFX1264_DPP-NEXT: v_writelane_b32 v5, s11, 48
-; GFX1264_DPP-NEXT: s_wait_alu 0xfffe
+; GFX1264_DPP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264_DPP-NEXT: s_mov_b64 exec, s[8:9]
; GFX1264_DPP-NEXT: s_mov_b32 s6, -1
; GFX1264_DPP-NEXT: s_mov_b64 s[8:9], exec
@@ -8001,18 +8001,18 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1264_DPP-NEXT: s_wait_loadcnt 0x0
; GFX1264_DPP-NEXT: global_inv scope:SCOPE_DEV
; GFX1264_DPP-NEXT: .LBB11_2:
-; GFX1264_DPP-NEXT: s_wait_alu 0xfffe
+; GFX1264_DPP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264_DPP-NEXT: s_or_b64 exec, exec, s[8:9]
; GFX1264_DPP-NEXT: s_wait_kmcnt 0x0
; GFX1264_DPP-NEXT: v_readfirstlane_b32 s2, v6
; GFX1264_DPP-NEXT: v_mov_b32_e32 v8, v4
; GFX1264_DPP-NEXT: v_mov_b32_e32 v9, v5
; GFX1264_DPP-NEXT: v_readfirstlane_b32 s3, v7
-; GFX1264_DPP-NEXT: s_wait_alu 0xf1ff
+; GFX1264_DPP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1264_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1264_DPP-NEXT: v_sub_co_u32 v6, vcc, s2, v8
; GFX1264_DPP-NEXT: s_mov_b32 s2, s6
-; GFX1264_DPP-NEXT: s_wait_alu 0xfffd
+; GFX1264_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1264_DPP-NEXT: v_sub_co_ci_u32_e64 v7, null, s3, v9, vcc
; GFX1264_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1264_DPP-NEXT: buffer_store_b64 v[6:7], off, s[0:3], null
@@ -8037,20 +8037,20 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1232_DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1232_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
-; GFX1232_DPP-NEXT: s_wait_alu 0xfffd
+; GFX1232_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1232_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
; GFX1232_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1232_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1232_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
-; GFX1232_DPP-NEXT: s_wait_alu 0xfffd
+; GFX1232_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1232_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc_lo
; GFX1232_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc_lo, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
; GFX1232_DPP-NEXT: v_mov_b32_e32 v3, 0
; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1232_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:8 row_mask:0xf bank_mask:0xf
; GFX1232_DPP-NEXT: v_permlanex16_b32 v5, v2, -1, -1
-; GFX1232_DPP-NEXT: s_wait_alu 0xfffd
+; GFX1232_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1232_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
; GFX1232_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc_lo, v5, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
@@ -8090,7 +8090,7 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1232_DPP-NEXT: s_wait_loadcnt 0x0
; GFX1232_DPP-NEXT: global_inv scope:SCOPE_DEV
; GFX1232_DPP-NEXT: .LBB11_2:
-; GFX1232_DPP-NEXT: s_wait_alu 0xfffe
+; GFX1232_DPP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232_DPP-NEXT: s_or_b32 exec_lo, exec_lo, s8
; GFX1232_DPP-NEXT: s_wait_kmcnt 0x0
; GFX1232_DPP-NEXT: v_readfirstlane_b32 s2, v8
@@ -8100,7 +8100,7 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1232_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1232_DPP-NEXT: v_sub_co_u32 v8, vcc_lo, s2, v10
; GFX1232_DPP-NEXT: s_mov_b32 s2, s6
-; GFX1232_DPP-NEXT: s_wait_alu 0xfffd
+; GFX1232_DPP-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1232_DPP-NEXT: v_sub_co_ci_u32_e64 v9, null, s3, v11, vcc_lo
; GFX1232_DPP-NEXT: s_mov_b32 s3, 0x31016000
; GFX1232_DPP-NEXT: buffer_store_b64 v[8:9], off, s[0:3], null
@@ -8650,7 +8650,7 @@ define amdgpu_kernel void @uniform_or_i8(ptr addrspace(1) %result, ptr addrspace
; GFX1264-TRUE16-NEXT: s_mov_b32 s10, -1
; GFX1264-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1264-TRUE16-NEXT: v_cndmask_b16 v0.l, s12, 0, vcc
-; GFX1264-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX1264-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1264-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1264-TRUE16-NEXT: v_or_b16 v0.l, s0, v0.l
; GFX1264-TRUE16-NEXT: buffer_store_b8 v0, off, s[8:11], null
@@ -8708,7 +8708,7 @@ define amdgpu_kernel void @uniform_or_i8(ptr addrspace(1) %result, ptr addrspace
; GFX1264-FAKE16-NEXT: s_mov_b32 s10, -1
; GFX1264-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1264-FAKE16-NEXT: v_cndmask_b32_e64 v0, s12, 0, vcc
-; GFX1264-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX1264-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1264-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1264-FAKE16-NEXT: v_or_b32_e32 v0, s0, v0
; GFX1264-FAKE16-NEXT: buffer_store_b8 v0, off, s[8:11], null
@@ -8764,7 +8764,7 @@ define amdgpu_kernel void @uniform_or_i8(ptr addrspace(1) %result, ptr addrspace
; GFX1232-TRUE16-NEXT: s_mov_b32 s10, -1
; GFX1232-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1232-TRUE16-NEXT: v_cndmask_b16 v0.l, s1, 0, vcc_lo
-; GFX1232-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX1232-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1232-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1232-TRUE16-NEXT: v_or_b16 v0.l, s0, v0.l
; GFX1232-TRUE16-NEXT: buffer_store_b8 v0, off, s[8:11], null
@@ -8820,7 +8820,7 @@ define amdgpu_kernel void @uniform_or_i8(ptr addrspace(1) %result, ptr addrspace
; GFX1232-FAKE16-NEXT: s_mov_b32 s10, -1
; GFX1232-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1232-FAKE16-NEXT: v_cndmask_b32_e64 v0, s1, 0, vcc_lo
-; GFX1232-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX1232-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1232-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1232-FAKE16-NEXT: v_or_b32_e32 v0, s0, v0
; GFX1232-FAKE16-NEXT: buffer_store_b8 v0, off, s[8:11], null
@@ -9160,7 +9160,7 @@ define amdgpu_kernel void @uniform_add_i8(ptr addrspace(1) %result, ptr addrspac
; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164-TRUE16-NEXT: v_add_nc_u32_e32 v0, s14, v1
; GFX1164-TRUE16-NEXT: v_and_b32_e32 v0, s12, v0
-; GFX1164-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1164-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1164-TRUE16-NEXT: v_and_or_b32 v0, v1, s13, v0
; GFX1164-TRUE16-NEXT: v_mov_b32_e32 v3, v1
; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -9225,7 +9225,7 @@ define amdgpu_kernel void @uniform_add_i8(ptr addrspace(1) %result, ptr addrspac
; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164-FAKE16-NEXT: v_add_nc_u32_e32 v0, s14, v1
; GFX1164-FAKE16-NEXT: v_and_b32_e32 v0, s12, v0
-; GFX1164-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1164-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1164-FAKE16-NEXT: v_and_or_b32 v0, v1, s13, v0
; GFX1164-FAKE16-NEXT: v_mov_b32_e32 v3, v1
; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -9399,7 +9399,7 @@ define amdgpu_kernel void @uniform_add_i8(ptr addrspace(1) %result, ptr addrspac
; GFX1264-TRUE16-NEXT: s_load_b32 s3, s[4:5], 0x0
; GFX1264-TRUE16-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GFX1264-TRUE16-NEXT: s_lshl_b32 s11, s2, 3
-; GFX1264-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1264-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264-TRUE16-NEXT: s_mul_i32 s2, s10, s6
; GFX1264-TRUE16-NEXT: s_lshl_b32 s12, 0xff, s11
; GFX1264-TRUE16-NEXT: s_and_b32 s2, s2, 0xff
@@ -9424,7 +9424,7 @@ define amdgpu_kernel void @uniform_add_i8(ptr addrspace(1) %result, ptr addrspac
; GFX1264-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
; GFX1264-TRUE16-NEXT: v_mov_b32_e32 v1, v2
; GFX1264-TRUE16-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
-; GFX1264-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1264-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264-TRUE16-NEXT: s_and_not1_b64 exec, exec, s[2:3]
; GFX1264-TRUE16-NEXT: s_cbranch_execnz .LBB13_2
; GFX1264-TRUE16-NEXT: ; %bb.3: ; %atomicrmw.end
@@ -9437,7 +9437,7 @@ define amdgpu_kernel void @uniform_add_i8(ptr addrspace(1) %result, ptr addrspac
; GFX1264-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1264-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1264-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
-; GFX1264-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX1264-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1264-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1264-TRUE16-NEXT: v_mad_u16 v0.l, s10, v4.l, s2
; GFX1264-TRUE16-NEXT: s_mov_b32 s2, -1
@@ -9465,7 +9465,7 @@ define amdgpu_kernel void @uniform_add_i8(ptr addrspace(1) %result, ptr addrspac
; GFX1264-FAKE16-NEXT: s_load_b32 s3, s[4:5], 0x0
; GFX1264-FAKE16-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GFX1264-FAKE16-NEXT: s_lshl_b32 s11, s2, 3
-; GFX1264-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1264-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264-FAKE16-NEXT: s_mul_i32 s2, s10, s6
; GFX1264-FAKE16-NEXT: s_lshl_b32 s12, 0xff, s11
; GFX1264-FAKE16-NEXT: s_and_b32 s2, s2, 0xff
@@ -9490,7 +9490,7 @@ define amdgpu_kernel void @uniform_add_i8(ptr addrspace(1) %result, ptr addrspac
; GFX1264-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
; GFX1264-FAKE16-NEXT: v_mov_b32_e32 v1, v2
; GFX1264-FAKE16-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
-; GFX1264-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1264-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264-FAKE16-NEXT: s_and_not1_b64 exec, exec, s[2:3]
; GFX1264-FAKE16-NEXT: s_cbranch_execnz .LBB13_2
; GFX1264-FAKE16-NEXT: ; %bb.3: ; %atomicrmw.end
@@ -9503,7 +9503,7 @@ define amdgpu_kernel void @uniform_add_i8(ptr addrspace(1) %result, ptr addrspac
; GFX1264-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1264-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1264-FAKE16-NEXT: v_readfirstlane_b32 s2, v0
-; GFX1264-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX1264-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1264-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1264-FAKE16-NEXT: v_mad_u16 v0, s10, v4, s2
; GFX1264-FAKE16-NEXT: s_mov_b32 s2, -1
@@ -9531,13 +9531,13 @@ define amdgpu_kernel void @uniform_add_i8(ptr addrspace(1) %result, ptr addrspac
; GFX1232-TRUE16-NEXT: s_load_b32 s7, s[4:5], 0x0
; GFX1232-TRUE16-NEXT: s_bcnt1_i32_b32 s6, s6
; GFX1232-TRUE16-NEXT: s_lshl_b32 s2, s2, 3
-; GFX1232-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1232-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-TRUE16-NEXT: s_mul_i32 s6, s8, s6
; GFX1232-TRUE16-NEXT: s_lshl_b32 s3, 0xff, s2
-; GFX1232-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1232-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-TRUE16-NEXT: s_and_b32 s6, s6, 0xff
; GFX1232-TRUE16-NEXT: s_not_b32 s11, s3
-; GFX1232-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1232-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-TRUE16-NEXT: s_lshl_b32 s12, s6, s2
; GFX1232-TRUE16-NEXT: s_mov_b32 s6, -1
; GFX1232-TRUE16-NEXT: s_wait_kmcnt 0x0
@@ -9556,7 +9556,7 @@ define amdgpu_kernel void @uniform_add_i8(ptr addrspace(1) %result, ptr addrspac
; GFX1232-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX1232-TRUE16-NEXT: v_mov_b32_e32 v1, v2
; GFX1232-TRUE16-NEXT: s_or_b32 s10, vcc_lo, s10
-; GFX1232-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1232-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s10
; GFX1232-TRUE16-NEXT: s_cbranch_execnz .LBB13_2
; GFX1232-TRUE16-NEXT: ; %bb.3: ; %atomicrmw.end
@@ -9569,7 +9569,7 @@ define amdgpu_kernel void @uniform_add_i8(ptr addrspace(1) %result, ptr addrspac
; GFX1232-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1232-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1232-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
-; GFX1232-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX1232-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1232-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1232-TRUE16-NEXT: v_mad_u16 v0.l, s8, v4.l, s2
; GFX1232-TRUE16-NEXT: s_mov_b32 s2, -1
@@ -9597,13 +9597,13 @@ define amdgpu_kernel void @uniform_add_i8(ptr addrspace(1) %result, ptr addrspac
; GFX1232-FAKE16-NEXT: s_load_b32 s7, s[4:5], 0x0
; GFX1232-FAKE16-NEXT: s_bcnt1_i32_b32 s6, s6
; GFX1232-FAKE16-NEXT: s_lshl_b32 s2, s2, 3
-; GFX1232-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1232-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-FAKE16-NEXT: s_mul_i32 s6, s8, s6
; GFX1232-FAKE16-NEXT: s_lshl_b32 s3, 0xff, s2
-; GFX1232-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1232-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-FAKE16-NEXT: s_and_b32 s6, s6, 0xff
; GFX1232-FAKE16-NEXT: s_not_b32 s11, s3
-; GFX1232-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1232-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-FAKE16-NEXT: s_lshl_b32 s12, s6, s2
; GFX1232-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX1232-FAKE16-NEXT: s_wait_kmcnt 0x0
@@ -9622,7 +9622,7 @@ define amdgpu_kernel void @uniform_add_i8(ptr addrspace(1) %result, ptr addrspac
; GFX1232-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX1232-FAKE16-NEXT: v_mov_b32_e32 v1, v2
; GFX1232-FAKE16-NEXT: s_or_b32 s10, vcc_lo, s10
-; GFX1232-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1232-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s10
; GFX1232-FAKE16-NEXT: s_cbranch_execnz .LBB13_2
; GFX1232-FAKE16-NEXT: ; %bb.3: ; %atomicrmw.end
@@ -9635,7 +9635,7 @@ define amdgpu_kernel void @uniform_add_i8(ptr addrspace(1) %result, ptr addrspac
; GFX1232-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1232-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1232-FAKE16-NEXT: v_readfirstlane_b32 s2, v0
-; GFX1232-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX1232-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1232-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1232-FAKE16-NEXT: v_mad_u16 v0, s8, v4, s2
; GFX1232-FAKE16-NEXT: s_mov_b32 s2, -1
@@ -9962,7 +9962,7 @@ define amdgpu_kernel void @uniform_xchg_i8(ptr addrspace(1) %result, ptr addrspa
; GFX1264-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
; GFX1264-NEXT: v_mov_b32_e32 v1, v2
; GFX1264-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
-; GFX1264-NEXT: s_wait_alu 0xfffe
+; GFX1264-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264-NEXT: s_and_not1_b64 exec, exec, s[2:3]
; GFX1264-NEXT: s_cbranch_execnz .LBB14_1
; GFX1264-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10003,7 +10003,7 @@ define amdgpu_kernel void @uniform_xchg_i8(ptr addrspace(1) %result, ptr addrspa
; GFX1232-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX1232-NEXT: v_mov_b32_e32 v1, v2
; GFX1232-NEXT: s_or_b32 s9, vcc_lo, s9
-; GFX1232-NEXT: s_wait_alu 0xfffe
+; GFX1232-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-NEXT: s_and_not1_b32 exec_lo, exec_lo, s9
; GFX1232-NEXT: s_cbranch_execnz .LBB14_1
; GFX1232-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10553,7 +10553,7 @@ define amdgpu_kernel void @uniform_or_i16(ptr addrspace(1) %result, ptr addrspac
; GFX1264-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1264-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1264-TRUE16-NEXT: v_cndmask_b16 v0.l, s12, 0, vcc
-; GFX1264-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX1264-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1264-TRUE16-NEXT: v_or_b16 v0.l, s0, v0.l
; GFX1264-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], null
; GFX1264-TRUE16-NEXT: s_endpgm
@@ -10610,7 +10610,7 @@ define amdgpu_kernel void @uniform_or_i16(ptr addrspace(1) %result, ptr addrspac
; GFX1264-FAKE16-NEXT: s_mov_b32 s10, -1
; GFX1264-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1264-FAKE16-NEXT: v_cndmask_b32_e64 v0, s12, 0, vcc
-; GFX1264-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX1264-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1264-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1264-FAKE16-NEXT: v_or_b32_e32 v0, s0, v0
; GFX1264-FAKE16-NEXT: buffer_store_b16 v0, off, s[8:11], null
@@ -10666,7 +10666,7 @@ define amdgpu_kernel void @uniform_or_i16(ptr addrspace(1) %result, ptr addrspac
; GFX1232-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1232-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1232-TRUE16-NEXT: v_cndmask_b16 v0.l, s1, 0, vcc_lo
-; GFX1232-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX1232-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1232-TRUE16-NEXT: v_or_b16 v0.l, s0, v0.l
; GFX1232-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], null
; GFX1232-TRUE16-NEXT: s_endpgm
@@ -10721,7 +10721,7 @@ define amdgpu_kernel void @uniform_or_i16(ptr addrspace(1) %result, ptr addrspac
; GFX1232-FAKE16-NEXT: s_mov_b32 s10, -1
; GFX1232-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1232-FAKE16-NEXT: v_cndmask_b32_e64 v0, s1, 0, vcc_lo
-; GFX1232-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX1232-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1232-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1232-FAKE16-NEXT: v_or_b32_e32 v0, s0, v0
; GFX1232-FAKE16-NEXT: buffer_store_b16 v0, off, s[8:11], null
@@ -11061,7 +11061,7 @@ define amdgpu_kernel void @uniform_add_i16(ptr addrspace(1) %result, ptr addrspa
; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164-TRUE16-NEXT: v_add_nc_u32_e32 v0, s14, v1
; GFX1164-TRUE16-NEXT: v_and_b32_e32 v0, s12, v0
-; GFX1164-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1164-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1164-TRUE16-NEXT: v_and_or_b32 v0, v1, s13, v0
; GFX1164-TRUE16-NEXT: v_mov_b32_e32 v3, v1
; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -11125,7 +11125,7 @@ define amdgpu_kernel void @uniform_add_i16(ptr addrspace(1) %result, ptr addrspa
; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164-FAKE16-NEXT: v_add_nc_u32_e32 v0, s14, v1
; GFX1164-FAKE16-NEXT: v_and_b32_e32 v0, s12, v0
-; GFX1164-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1164-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1164-FAKE16-NEXT: v_and_or_b32 v0, v1, s13, v0
; GFX1164-FAKE16-NEXT: v_mov_b32_e32 v3, v1
; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -11298,7 +11298,7 @@ define amdgpu_kernel void @uniform_add_i16(ptr addrspace(1) %result, ptr addrspa
; GFX1264-TRUE16-NEXT: s_load_b32 s3, s[4:5], 0x0
; GFX1264-TRUE16-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GFX1264-TRUE16-NEXT: s_lshl_b32 s11, s2, 3
-; GFX1264-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1264-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264-TRUE16-NEXT: s_mul_i32 s2, s10, s6
; GFX1264-TRUE16-NEXT: s_lshl_b32 s12, 0xffff, s11
; GFX1264-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff
@@ -11323,7 +11323,7 @@ define amdgpu_kernel void @uniform_add_i16(ptr addrspace(1) %result, ptr addrspa
; GFX1264-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
; GFX1264-TRUE16-NEXT: v_mov_b32_e32 v1, v2
; GFX1264-TRUE16-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
-; GFX1264-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1264-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264-TRUE16-NEXT: s_and_not1_b64 exec, exec, s[2:3]
; GFX1264-TRUE16-NEXT: s_cbranch_execnz .LBB16_2
; GFX1264-TRUE16-NEXT: ; %bb.3: ; %atomicrmw.end
@@ -11336,7 +11336,7 @@ define amdgpu_kernel void @uniform_add_i16(ptr addrspace(1) %result, ptr addrspa
; GFX1264-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1264-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1264-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
-; GFX1264-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX1264-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1264-TRUE16-NEXT: v_mad_u16 v0.l, s10, v4.l, s2
; GFX1264-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX1264-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
@@ -11363,7 +11363,7 @@ define amdgpu_kernel void @uniform_add_i16(ptr addrspace(1) %result, ptr addrspa
; GFX1264-FAKE16-NEXT: s_load_b32 s3, s[4:5], 0x0
; GFX1264-FAKE16-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
; GFX1264-FAKE16-NEXT: s_lshl_b32 s11, s2, 3
-; GFX1264-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1264-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264-FAKE16-NEXT: s_mul_i32 s2, s10, s6
; GFX1264-FAKE16-NEXT: s_lshl_b32 s12, 0xffff, s11
; GFX1264-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff
@@ -11388,7 +11388,7 @@ define amdgpu_kernel void @uniform_add_i16(ptr addrspace(1) %result, ptr addrspa
; GFX1264-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
; GFX1264-FAKE16-NEXT: v_mov_b32_e32 v1, v2
; GFX1264-FAKE16-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
-; GFX1264-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1264-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264-FAKE16-NEXT: s_and_not1_b64 exec, exec, s[2:3]
; GFX1264-FAKE16-NEXT: s_cbranch_execnz .LBB16_2
; GFX1264-FAKE16-NEXT: ; %bb.3: ; %atomicrmw.end
@@ -11401,7 +11401,7 @@ define amdgpu_kernel void @uniform_add_i16(ptr addrspace(1) %result, ptr addrspa
; GFX1264-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1264-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1264-FAKE16-NEXT: v_readfirstlane_b32 s2, v0
-; GFX1264-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX1264-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1264-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1264-FAKE16-NEXT: v_mad_u16 v0, s10, v4, s2
; GFX1264-FAKE16-NEXT: s_mov_b32 s2, -1
@@ -11429,13 +11429,13 @@ define amdgpu_kernel void @uniform_add_i16(ptr addrspace(1) %result, ptr addrspa
; GFX1232-TRUE16-NEXT: s_load_b32 s7, s[4:5], 0x0
; GFX1232-TRUE16-NEXT: s_bcnt1_i32_b32 s6, s6
; GFX1232-TRUE16-NEXT: s_lshl_b32 s2, s2, 3
-; GFX1232-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1232-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-TRUE16-NEXT: s_mul_i32 s6, s8, s6
; GFX1232-TRUE16-NEXT: s_lshl_b32 s3, 0xffff, s2
-; GFX1232-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1232-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-TRUE16-NEXT: s_and_b32 s6, s6, 0xffff
; GFX1232-TRUE16-NEXT: s_not_b32 s11, s3
-; GFX1232-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1232-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-TRUE16-NEXT: s_lshl_b32 s12, s6, s2
; GFX1232-TRUE16-NEXT: s_mov_b32 s6, -1
; GFX1232-TRUE16-NEXT: s_wait_kmcnt 0x0
@@ -11454,7 +11454,7 @@ define amdgpu_kernel void @uniform_add_i16(ptr addrspace(1) %result, ptr addrspa
; GFX1232-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX1232-TRUE16-NEXT: v_mov_b32_e32 v1, v2
; GFX1232-TRUE16-NEXT: s_or_b32 s10, vcc_lo, s10
-; GFX1232-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1232-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s10
; GFX1232-TRUE16-NEXT: s_cbranch_execnz .LBB16_2
; GFX1232-TRUE16-NEXT: ; %bb.3: ; %atomicrmw.end
@@ -11467,7 +11467,7 @@ define amdgpu_kernel void @uniform_add_i16(ptr addrspace(1) %result, ptr addrspa
; GFX1232-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1232-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1232-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
-; GFX1232-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX1232-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1232-TRUE16-NEXT: v_mad_u16 v0.l, s8, v4.l, s2
; GFX1232-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX1232-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
@@ -11494,13 +11494,13 @@ define amdgpu_kernel void @uniform_add_i16(ptr addrspace(1) %result, ptr addrspa
; GFX1232-FAKE16-NEXT: s_load_b32 s7, s[4:5], 0x0
; GFX1232-FAKE16-NEXT: s_bcnt1_i32_b32 s6, s6
; GFX1232-FAKE16-NEXT: s_lshl_b32 s2, s2, 3
-; GFX1232-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1232-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-FAKE16-NEXT: s_mul_i32 s6, s8, s6
; GFX1232-FAKE16-NEXT: s_lshl_b32 s3, 0xffff, s2
-; GFX1232-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1232-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-FAKE16-NEXT: s_and_b32 s6, s6, 0xffff
; GFX1232-FAKE16-NEXT: s_not_b32 s11, s3
-; GFX1232-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1232-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-FAKE16-NEXT: s_lshl_b32 s12, s6, s2
; GFX1232-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX1232-FAKE16-NEXT: s_wait_kmcnt 0x0
@@ -11519,7 +11519,7 @@ define amdgpu_kernel void @uniform_add_i16(ptr addrspace(1) %result, ptr addrspa
; GFX1232-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX1232-FAKE16-NEXT: v_mov_b32_e32 v1, v2
; GFX1232-FAKE16-NEXT: s_or_b32 s10, vcc_lo, s10
-; GFX1232-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1232-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s10
; GFX1232-FAKE16-NEXT: s_cbranch_execnz .LBB16_2
; GFX1232-FAKE16-NEXT: ; %bb.3: ; %atomicrmw.end
@@ -11532,7 +11532,7 @@ define amdgpu_kernel void @uniform_add_i16(ptr addrspace(1) %result, ptr addrspa
; GFX1232-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1232-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1232-FAKE16-NEXT: v_readfirstlane_b32 s2, v0
-; GFX1232-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX1232-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1232-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1232-FAKE16-NEXT: v_mad_u16 v0, s8, v4, s2
; GFX1232-FAKE16-NEXT: s_mov_b32 s2, -1
@@ -11859,7 +11859,7 @@ define amdgpu_kernel void @uniform_xchg_i16(ptr addrspace(1) %result, ptr addrsp
; GFX1264-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
; GFX1264-NEXT: v_mov_b32_e32 v1, v2
; GFX1264-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
-; GFX1264-NEXT: s_wait_alu 0xfffe
+; GFX1264-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264-NEXT: s_and_not1_b64 exec, exec, s[2:3]
; GFX1264-NEXT: s_cbranch_execnz .LBB17_1
; GFX1264-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11900,7 +11900,7 @@ define amdgpu_kernel void @uniform_xchg_i16(ptr addrspace(1) %result, ptr addrsp
; GFX1232-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX1232-NEXT: v_mov_b32_e32 v1, v2
; GFX1232-NEXT: s_or_b32 s9, vcc_lo, s9
-; GFX1232-NEXT: s_wait_alu 0xfffe
+; GFX1232-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-NEXT: s_and_not1_b32 exec_lo, exec_lo, s9
; GFX1232-NEXT: s_cbranch_execnz .LBB17_1
; GFX1232-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12348,7 +12348,7 @@ define amdgpu_kernel void @uniform_fadd_f16(ptr addrspace(1) %result, ptr addrsp
; GFX1264-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
; GFX1264-TRUE16-NEXT: v_mov_b32_e32 v1, v2
; GFX1264-TRUE16-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
-; GFX1264-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1264-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264-TRUE16-NEXT: s_and_not1_b64 exec, exec, s[2:3]
; GFX1264-TRUE16-NEXT: s_cbranch_execnz .LBB18_1
; GFX1264-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12395,7 +12395,7 @@ define amdgpu_kernel void @uniform_fadd_f16(ptr addrspace(1) %result, ptr addrsp
; GFX1264-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
; GFX1264-FAKE16-NEXT: v_mov_b32_e32 v1, v2
; GFX1264-FAKE16-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
-; GFX1264-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1264-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1264-FAKE16-NEXT: s_and_not1_b64 exec, exec, s[2:3]
; GFX1264-FAKE16-NEXT: s_cbranch_execnz .LBB18_1
; GFX1264-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12441,7 +12441,7 @@ define amdgpu_kernel void @uniform_fadd_f16(ptr addrspace(1) %result, ptr addrsp
; GFX1232-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX1232-TRUE16-NEXT: v_mov_b32_e32 v1, v2
; GFX1232-TRUE16-NEXT: s_or_b32 s9, vcc_lo, s9
-; GFX1232-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1232-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s9
; GFX1232-TRUE16-NEXT: s_cbranch_execnz .LBB18_1
; GFX1232-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12487,7 +12487,7 @@ define amdgpu_kernel void @uniform_fadd_f16(ptr addrspace(1) %result, ptr addrsp
; GFX1232-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX1232-FAKE16-NEXT: v_mov_b32_e32 v1, v2
; GFX1232-FAKE16-NEXT: s_or_b32 s9, vcc_lo, s9
-; GFX1232-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1232-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s9
; GFX1232-FAKE16-NEXT: s_cbranch_execnz .LBB18_1
; GFX1232-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12784,7 +12784,7 @@ define amdgpu_kernel void @uniform_fadd_bf16(ptr addrspace(1) %result, ptr addrs
; GFX1164-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
; GFX1164-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX1164-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
-; GFX1164-TRUE16-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164-TRUE16-NEXT: v_mov_b32_e32 v1, v2
; GFX1164-TRUE16-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX1164-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -12841,7 +12841,7 @@ define amdgpu_kernel void @uniform_fadd_bf16(ptr addrspace(1) %result, ptr addrs
; GFX1164-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
; GFX1164-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX1164-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
-; GFX1164-FAKE16-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164-FAKE16-NEXT: v_mov_b32_e32 v1, v2
; GFX1164-FAKE16-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX1164-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -12997,7 +12997,7 @@ define amdgpu_kernel void @uniform_fadd_bf16(ptr addrspace(1) %result, ptr addrs
; GFX1264-TRUE16-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX1264-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1264-TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
-; GFX1264-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1264-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1264-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
; GFX1264-TRUE16-NEXT: v_mov_b16_e32 v2.h, 0
; GFX1264-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -13054,7 +13054,7 @@ define amdgpu_kernel void @uniform_fadd_bf16(ptr addrspace(1) %result, ptr addrs
; GFX1264-FAKE16-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX1264-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1264-FAKE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
-; GFX1264-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1264-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1264-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
; GFX1264-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1264-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
@@ -13110,7 +13110,7 @@ define amdgpu_kernel void @uniform_fadd_bf16(ptr addrspace(1) %result, ptr addrs
; GFX1232-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX1232-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1232-TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
-; GFX1232-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1232-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1232-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
; GFX1232-TRUE16-NEXT: v_mov_b16_e32 v2.h, 0
; GFX1232-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -13124,7 +13124,7 @@ define amdgpu_kernel void @uniform_fadd_bf16(ptr addrspace(1) %result, ptr addrs
; GFX1232-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX1232-TRUE16-NEXT: v_mov_b32_e32 v1, v2
; GFX1232-TRUE16-NEXT: s_or_b32 s3, vcc_lo, s3
-; GFX1232-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1232-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s3
; GFX1232-TRUE16-NEXT: s_cbranch_execnz .LBB19_1
; GFX1232-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13166,7 +13166,7 @@ define amdgpu_kernel void @uniform_fadd_bf16(ptr addrspace(1) %result, ptr addrs
; GFX1232-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX1232-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1232-FAKE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
-; GFX1232-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1232-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1232-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
; GFX1232-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1232-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
@@ -13179,7 +13179,7 @@ define amdgpu_kernel void @uniform_fadd_bf16(ptr addrspace(1) %result, ptr addrs
; GFX1232-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX1232-FAKE16-NEXT: v_mov_b32_e32 v1, v2
; GFX1232-FAKE16-NEXT: s_or_b32 s3, vcc_lo, s3
-; GFX1232-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1232-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s3
; GFX1232-FAKE16-NEXT: s_cbranch_execnz .LBB19_1
; GFX1232-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13516,7 +13516,7 @@ define amdgpu_kernel void @uniform_fadd_v2f16(ptr addrspace(1) %result, ptr addr
; GFX1232-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX1232-NEXT: v_mov_b32_e32 v1, v2
; GFX1232-NEXT: s_or_b32 s9, vcc_lo, s9
-; GFX1232-NEXT: s_wait_alu 0xfffe
+; GFX1232-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-NEXT: s_and_not1_b32 exec_lo, exec_lo, s9
; GFX1232-NEXT: s_cbranch_execnz .LBB20_1
; GFX1232-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13823,7 +13823,7 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1164-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX1164-TRUE16-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX1164-TRUE16-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164-TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc
; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
@@ -13832,7 +13832,7 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX1164-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
; GFX1164-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX1164-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
-; GFX1164-TRUE16-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164-TRUE16-NEXT: v_mov_b32_e32 v1, v2
; GFX1164-TRUE16-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GFX1164-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -13881,7 +13881,7 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX1164-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX1164-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX1164-FAKE16-NEXT: v_cmp_u_f32_e64 s[0:1], v0, v0
-; GFX1164-FAKE16-NEXT: s_waitcnt_depctr 0xf1ff
+; GFX1164-FAKE16-NEXT: s_waitcnt_depctr depctr_va_sdst(0)
; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc
; GFX1164-FAKE16-NEXT: v_cndmask_b32_e64 v0, v3, v5, s[0:1]
@@ -13892,7 +13892,7 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX1164-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
; GFX1164-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX1164-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
-; GFX1164-FAKE16-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164-FAKE16-NEXT: v_mov_b32_e32 v1, v2
; GFX1164-FAKE16-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX1164-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -14052,11 +14052,11 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX1264-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v2
; GFX1264-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX1264-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX1264-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1264-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1264-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1264-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX1264-TRUE16-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX1264-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1264-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1264-TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc
; GFX1264-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
; GFX1264-TRUE16-NEXT: v_mov_b32_e32 v3, v1
@@ -14110,10 +14110,10 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX1264-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX1264-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX1264-FAKE16-NEXT: v_cmp_u_f32_e64 s[0:1], v0, v0
-; GFX1264-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1264-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1264-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1264-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc
-; GFX1264-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX1264-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1264-FAKE16-NEXT: v_cndmask_b32_e64 v0, v3, v5, s[0:1]
; GFX1264-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1264-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x7060302
@@ -14166,11 +14166,11 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX1232-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v2
; GFX1232-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX1232-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX1232-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1232-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1232-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1232-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1232-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX1232-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1232-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1232-TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc_lo
; GFX1232-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
; GFX1232-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -14180,7 +14180,7 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX1232-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX1232-TRUE16-NEXT: v_mov_b32_e32 v1, v2
; GFX1232-TRUE16-NEXT: s_or_b32 s8, vcc_lo, s8
-; GFX1232-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1232-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s8
; GFX1232-TRUE16-NEXT: s_cbranch_execnz .LBB21_1
; GFX1232-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14223,10 +14223,10 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX1232-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX1232-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX1232-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v0, v0
-; GFX1232-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1232-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1232-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1232-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc_lo
-; GFX1232-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX1232-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1232-FAKE16-NEXT: v_cndmask_b32_e64 v0, v3, v5, s0
; GFX1232-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1232-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x7060302
@@ -14236,7 +14236,7 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX1232-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX1232-FAKE16-NEXT: v_mov_b32_e32 v1, v2
; GFX1232-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX1232-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1232-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1232-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX1232-FAKE16-NEXT: s_cbranch_execnz .LBB21_1
; GFX1232-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
index a9938f17dacb7..785aee07a990e 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
@@ -123,7 +123,7 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out) {
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: .LBB0_2:
-; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064-NEXT: v_readfirstlane_b32 s2, v1
@@ -151,7 +151,7 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out) {
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: .LBB0_2:
-; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032-NEXT: v_readfirstlane_b32 s2, v1
@@ -338,7 +338,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, i32 %additive)
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: .LBB1_2:
-; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064-NEXT: v_readfirstlane_b32 s2, v1
@@ -368,7 +368,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, i32 %additive)
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: .LBB1_2:
-; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1032-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x24
; GFX1032-NEXT: v_readfirstlane_b32 s2, v1
@@ -598,7 +598,7 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1064_ITERATIVE-NEXT: .LBB2_4:
-; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_ITERATIVE-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v0
@@ -637,7 +637,7 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1032_ITERATIVE-NEXT: .LBB2_4:
-; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_ITERATIVE-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1032_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v0
@@ -874,7 +874,7 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB2_2:
-; GFX1064_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_DPP-NEXT: v_readfirstlane_b32 s3, v0
@@ -917,7 +917,7 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB2_2:
-; GFX1032_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_DPP-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1032_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_DPP-NEXT: v_readfirstlane_b32 s3, v0
@@ -957,7 +957,7 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v1, 47
; GFX1164_DPP-NEXT: v_readlane_b32 s6, v1, 63
; GFX1164_DPP-NEXT: v_writelane_b32 v3, s3, 32
@@ -1393,7 +1393,7 @@ define amdgpu_kernel void @add_i32_varying_nouse() {
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164_DPP-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
@@ -1561,7 +1561,7 @@ define amdgpu_kernel void @add_i64_constant(ptr addrspace(1) %out) {
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: .LBB4_2:
-; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064-NEXT: v_readfirstlane_b32 s3, v1
@@ -1590,7 +1590,7 @@ define amdgpu_kernel void @add_i64_constant(ptr addrspace(1) %out) {
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: .LBB4_2:
-; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032-NEXT: v_readfirstlane_b32 s3, v1
@@ -1813,7 +1813,7 @@ define amdgpu_kernel void @add_i64_uniform(ptr addrspace(1) %out, i64 %additive)
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: .LBB5_2:
-; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: v_readfirstlane_b32 s5, v1
; GFX1064-NEXT: v_readfirstlane_b32 s4, v0
@@ -1848,7 +1848,7 @@ define amdgpu_kernel void @add_i64_uniform(ptr addrspace(1) %out, i64 %additive)
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: .LBB5_2:
-; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX1032-NEXT: v_readfirstlane_b32 s5, v1
; GFX1032-NEXT: v_readfirstlane_b32 s4, v0
@@ -2120,7 +2120,7 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1064_ITERATIVE-NEXT: .LBB6_4:
-; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_ITERATIVE-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX1064_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v3
@@ -2166,7 +2166,7 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1032_ITERATIVE-NEXT: .LBB6_4:
-; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_ITERATIVE-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX1032_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v3
@@ -2531,7 +2531,7 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB6_2:
-; GFX1064_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_DPP-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX1064_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_DPP-NEXT: v_readfirstlane_b32 s3, v9
@@ -2610,7 +2610,7 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB6_2:
-; GFX1032_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_DPP-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GFX1032_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_DPP-NEXT: v_readfirstlane_b32 s3, v9
@@ -2641,19 +2641,19 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v3, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:8 row_mask:0xf bank_mask:0xf
@@ -2661,7 +2661,7 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v5, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v5, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_permlanex16_b32 v4, v1, -1, -1
@@ -2676,13 +2676,13 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v2, s2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v2, 15
; GFX1164_DPP-NEXT: v_mov_b32_dpp v6, v1 row_shr:1 row_mask:0xf bank_mask:0xf
@@ -2707,7 +2707,7 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_writelane_b32 v6, s9, 48
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[6:7]
; GFX1164_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: s_mov_b32 s2, -1
; GFX1164_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
; GFX1164_DPP-NEXT: s_and_saveexec_b64 s[6:7], vcc
@@ -3296,26 +3296,26 @@ define amdgpu_kernel void @add_i64_varying_nouse() {
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_xmask:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_xmask:2 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_xmask:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_xmask:4 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v3, v3 row_xmask:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_xmask:8 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_permlanex16_b32 v3, v2, 0, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
; GFX1164_DPP-NEXT: v_add_co_u32 v2, vcc, v2, v3
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_permlanex16_b32 v4, v1, 0, 0
; GFX1164_DPP-NEXT: v_permlane64_b32 v3, v2
@@ -3327,7 +3327,7 @@ define amdgpu_kernel void @add_i64_varying_nouse() {
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX1164_DPP-NEXT: v_add_co_u32 v2, vcc, v2, v3
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffc
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v3, null, v1, v4, vcc
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: v_mov_b32_e32 v5, v2
@@ -3506,7 +3506,7 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out) {
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: .LBB8_2:
-; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064-NEXT: v_readfirstlane_b32 s2, v1
@@ -3535,7 +3535,7 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out) {
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: .LBB8_2:
-; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032-NEXT: v_readfirstlane_b32 s2, v1
@@ -3727,7 +3727,7 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, i32 %subitive)
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: .LBB9_2:
-; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
@@ -3758,7 +3758,7 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, i32 %subitive)
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: .LBB9_2:
-; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1032-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x24
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
@@ -3990,7 +3990,7 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1064_ITERATIVE-NEXT: .LBB10_4:
-; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_ITERATIVE-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v0
@@ -4029,7 +4029,7 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1032_ITERATIVE-NEXT: .LBB10_4:
-; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_ITERATIVE-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1032_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v0
@@ -4266,7 +4266,7 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB10_2:
-; GFX1064_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_DPP-NEXT: v_readfirstlane_b32 s3, v0
@@ -4309,7 +4309,7 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB10_2:
-; GFX1032_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_DPP-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1032_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_DPP-NEXT: v_readfirstlane_b32 s3, v0
@@ -4349,7 +4349,7 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v1, 47
; GFX1164_DPP-NEXT: v_readlane_b32 s6, v1, 63
; GFX1164_DPP-NEXT: v_writelane_b32 v3, s3, 32
@@ -4785,7 +4785,7 @@ define amdgpu_kernel void @sub_i32_varying_nouse() {
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164_DPP-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
@@ -4955,7 +4955,7 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out) {
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: .LBB12_2:
-; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064-NEXT: v_readfirstlane_b32 s2, v0
@@ -4987,7 +4987,7 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out) {
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: .LBB12_2:
-; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032-NEXT: v_readfirstlane_b32 s2, v0
@@ -5221,7 +5221,7 @@ define amdgpu_kernel void @sub_i64_uniform(ptr addrspace(1) %out, i64 %subitive)
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: .LBB13_2:
-; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: v_mad_u64_u32 v[3:4], s[4:5], s2, v2, 0
@@ -5258,7 +5258,7 @@ define amdgpu_kernel void @sub_i64_uniform(ptr addrspace(1) %out, i64 %subitive)
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: .LBB13_2:
-; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_mad_u64_u32 v[3:4], s2, s2, v2, 0
@@ -5302,7 +5302,7 @@ define amdgpu_kernel void @sub_i64_uniform(ptr addrspace(1) %out, i64 %subitive)
; GFX1164-NEXT: v_mad_u64_u32 v[3:4], null, s2, v2, 0
; GFX1164-NEXT: v_readfirstlane_b32 s2, v0
; GFX1164-NEXT: v_readfirstlane_b32 s4, v1
-; GFX1164-NEXT: s_waitcnt_depctr 0xfff
+; GFX1164-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1164-NEXT: v_mad_u64_u32 v[5:6], null, s3, v2, v[4:5]
; GFX1164-NEXT: v_sub_co_u32 v0, vcc, s2, v3
; GFX1164-NEXT: s_mov_b32 s3, 0x31016000
@@ -5534,7 +5534,7 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1064_ITERATIVE-NEXT: .LBB14_4:
-; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_ITERATIVE-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX1064_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v3
@@ -5580,7 +5580,7 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1032_ITERATIVE-NEXT: .LBB14_4:
-; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_ITERATIVE-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX1032_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v3
@@ -5945,7 +5945,7 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB14_2:
-; GFX1064_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_DPP-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX1064_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_DPP-NEXT: v_readfirstlane_b32 s3, v9
@@ -6024,7 +6024,7 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB14_2:
-; GFX1032_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_DPP-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GFX1032_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_DPP-NEXT: v_readfirstlane_b32 s3, v9
@@ -6055,19 +6055,19 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v3, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:8 row_mask:0xf bank_mask:0xf
@@ -6075,7 +6075,7 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v5, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_mov_b32_e32 v5, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_permlanex16_b32 v4, v1, -1, -1
@@ -6090,13 +6090,13 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v2, s2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v2, 15
; GFX1164_DPP-NEXT: v_mov_b32_dpp v6, v1 row_shr:1 row_mask:0xf bank_mask:0xf
@@ -6121,7 +6121,7 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_writelane_b32 v6, s9, 48
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[6:7]
; GFX1164_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: s_mov_b32 s2, -1
; GFX1164_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
; GFX1164_DPP-NEXT: s_and_saveexec_b64 s[6:7], vcc
@@ -6383,7 +6383,7 @@ define amdgpu_kernel void @and_i32_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1064_ITERATIVE-NEXT: .LBB15_4:
-; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_ITERATIVE-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v0
@@ -6422,7 +6422,7 @@ define amdgpu_kernel void @and_i32_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1032_ITERATIVE-NEXT: .LBB15_4:
-; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_ITERATIVE-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1032_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v0
@@ -6659,7 +6659,7 @@ define amdgpu_kernel void @and_i32_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB15_2:
-; GFX1064_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_DPP-NEXT: v_readfirstlane_b32 s3, v0
@@ -6702,7 +6702,7 @@ define amdgpu_kernel void @and_i32_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB15_2:
-; GFX1032_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_DPP-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1032_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_DPP-NEXT: v_readfirstlane_b32 s3, v0
@@ -6742,7 +6742,7 @@ define amdgpu_kernel void @and_i32_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v1, 47
; GFX1164_DPP-NEXT: v_readlane_b32 s6, v1, 63
; GFX1164_DPP-NEXT: v_writelane_b32 v3, s3, 32
@@ -7004,7 +7004,7 @@ define amdgpu_kernel void @and_i64_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1064_ITERATIVE-NEXT: .LBB16_4:
-; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_ITERATIVE-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX1064_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v4
@@ -7049,7 +7049,7 @@ define amdgpu_kernel void @and_i64_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1032_ITERATIVE-NEXT: .LBB16_4:
-; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_ITERATIVE-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX1032_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v4
@@ -7344,7 +7344,7 @@ define amdgpu_kernel void @and_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB16_2:
-; GFX1064_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_DPP-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX1064_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_DPP-NEXT: v_readfirstlane_b32 s3, v8
@@ -7403,7 +7403,7 @@ define amdgpu_kernel void @and_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB16_2:
-; GFX1032_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_DPP-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GFX1032_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_DPP-NEXT: v_readfirstlane_b32 s3, v8
@@ -7460,7 +7460,7 @@ define amdgpu_kernel void @and_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_readlane_b32 s3, v2, 15
; GFX1164_DPP-NEXT: v_readlane_b32 s6, v1, 31
@@ -7732,7 +7732,7 @@ define amdgpu_kernel void @or_i32_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1064_ITERATIVE-NEXT: .LBB17_4:
-; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_ITERATIVE-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v0
@@ -7771,7 +7771,7 @@ define amdgpu_kernel void @or_i32_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1032_ITERATIVE-NEXT: .LBB17_4:
-; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_ITERATIVE-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1032_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v0
@@ -8008,7 +8008,7 @@ define amdgpu_kernel void @or_i32_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB17_2:
-; GFX1064_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_DPP-NEXT: v_readfirstlane_b32 s3, v0
@@ -8051,7 +8051,7 @@ define amdgpu_kernel void @or_i32_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB17_2:
-; GFX1032_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_DPP-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1032_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_DPP-NEXT: v_readfirstlane_b32 s3, v0
@@ -8091,7 +8091,7 @@ define amdgpu_kernel void @or_i32_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v1, 47
; GFX1164_DPP-NEXT: v_readlane_b32 s6, v1, 63
; GFX1164_DPP-NEXT: v_writelane_b32 v3, s3, 32
@@ -8352,7 +8352,7 @@ define amdgpu_kernel void @or_i64_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1064_ITERATIVE-NEXT: .LBB18_4:
-; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_ITERATIVE-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX1064_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v4
@@ -8397,7 +8397,7 @@ define amdgpu_kernel void @or_i64_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1032_ITERATIVE-NEXT: .LBB18_4:
-; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_ITERATIVE-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX1032_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v4
@@ -8692,7 +8692,7 @@ define amdgpu_kernel void @or_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB18_2:
-; GFX1064_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_DPP-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX1064_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_DPP-NEXT: v_readfirstlane_b32 s3, v8
@@ -8751,7 +8751,7 @@ define amdgpu_kernel void @or_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB18_2:
-; GFX1032_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_DPP-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GFX1032_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_DPP-NEXT: v_readfirstlane_b32 s3, v8
@@ -8808,7 +8808,7 @@ define amdgpu_kernel void @or_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_readlane_b32 s3, v2, 15
; GFX1164_DPP-NEXT: v_readlane_b32 s6, v1, 31
@@ -9080,7 +9080,7 @@ define amdgpu_kernel void @xor_i32_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1064_ITERATIVE-NEXT: .LBB19_4:
-; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_ITERATIVE-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v0
@@ -9119,7 +9119,7 @@ define amdgpu_kernel void @xor_i32_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1032_ITERATIVE-NEXT: .LBB19_4:
-; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_ITERATIVE-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1032_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v0
@@ -9356,7 +9356,7 @@ define amdgpu_kernel void @xor_i32_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB19_2:
-; GFX1064_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_DPP-NEXT: v_readfirstlane_b32 s3, v0
@@ -9399,7 +9399,7 @@ define amdgpu_kernel void @xor_i32_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB19_2:
-; GFX1032_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_DPP-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1032_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_DPP-NEXT: v_readfirstlane_b32 s3, v0
@@ -9439,7 +9439,7 @@ define amdgpu_kernel void @xor_i32_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v1, 47
; GFX1164_DPP-NEXT: v_readlane_b32 s6, v1, 63
; GFX1164_DPP-NEXT: v_writelane_b32 v3, s3, 32
@@ -9700,7 +9700,7 @@ define amdgpu_kernel void @xor_i64_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1064_ITERATIVE-NEXT: .LBB20_4:
-; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_ITERATIVE-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX1064_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v4
@@ -9745,7 +9745,7 @@ define amdgpu_kernel void @xor_i64_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1032_ITERATIVE-NEXT: .LBB20_4:
-; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_ITERATIVE-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX1032_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v4
@@ -10040,7 +10040,7 @@ define amdgpu_kernel void @xor_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB20_2:
-; GFX1064_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_DPP-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX1064_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_DPP-NEXT: v_readfirstlane_b32 s3, v8
@@ -10099,7 +10099,7 @@ define amdgpu_kernel void @xor_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB20_2:
-; GFX1032_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_DPP-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GFX1032_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_DPP-NEXT: v_readfirstlane_b32 s3, v8
@@ -10156,7 +10156,7 @@ define amdgpu_kernel void @xor_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_readlane_b32 s3, v2, 15
; GFX1164_DPP-NEXT: v_readlane_b32 s6, v1, 31
@@ -10428,7 +10428,7 @@ define amdgpu_kernel void @max_i32_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1064_ITERATIVE-NEXT: .LBB21_4:
-; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_ITERATIVE-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v0
@@ -10467,7 +10467,7 @@ define amdgpu_kernel void @max_i32_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1032_ITERATIVE-NEXT: .LBB21_4:
-; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_ITERATIVE-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1032_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v0
@@ -10704,7 +10704,7 @@ define amdgpu_kernel void @max_i32_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB21_2:
-; GFX1064_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_DPP-NEXT: v_readfirstlane_b32 s3, v0
@@ -10747,7 +10747,7 @@ define amdgpu_kernel void @max_i32_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB21_2:
-; GFX1032_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_DPP-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1032_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_DPP-NEXT: v_readfirstlane_b32 s3, v0
@@ -10787,7 +10787,7 @@ define amdgpu_kernel void @max_i32_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v1, 47
; GFX1164_DPP-NEXT: v_readlane_b32 s6, v1, 63
; GFX1164_DPP-NEXT: v_writelane_b32 v3, s3, 32
@@ -10994,7 +10994,7 @@ define amdgpu_kernel void @max_i64_constant(ptr addrspace(1) %out) {
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: .LBB22_2:
-; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064-NEXT: v_readfirstlane_b32 s3, v1
@@ -11025,7 +11025,7 @@ define amdgpu_kernel void @max_i64_constant(ptr addrspace(1) %out) {
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: .LBB22_2:
-; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032-NEXT: v_readfirstlane_b32 s3, v1
@@ -11066,7 +11066,7 @@ define amdgpu_kernel void @max_i64_constant(ptr addrspace(1) %out) {
; GFX1164-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc
; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1]
-; GFX1164-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc
; GFX1164-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc
; GFX1164-NEXT: s_mov_b32 s3, 0x31016000
@@ -11315,7 +11315,7 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1064_ITERATIVE-NEXT: .LBB23_4:
-; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_ITERATIVE-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX1064_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_ITERATIVE-NEXT: v_readfirstlane_b32 s3, v4
@@ -11365,7 +11365,7 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1032_ITERATIVE-NEXT: .LBB23_4:
-; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_ITERATIVE-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX1032_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_ITERATIVE-NEXT: v_readfirstlane_b32 s3, v4
@@ -11773,7 +11773,7 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB23_2:
-; GFX1064_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_DPP-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX1064_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_DPP-NEXT: s_mov_b32 null, 0
@@ -11858,7 +11858,7 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB23_2:
-; GFX1032_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_DPP-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GFX1032_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_DPP-NEXT: s_mov_b32 null, 0
@@ -11898,7 +11898,7 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v1 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_cmp_gt_i64_e32 vcc, v[1:2], v[5:6]
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX1164_DPP-NEXT: v_bfrev_b32_e32 v6, 1
@@ -11908,7 +11908,7 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:4 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_cmp_gt_i64_e32 vcc, v[1:2], v[3:4]
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX1164_DPP-NEXT: v_bfrev_b32_e32 v4, 1
@@ -11918,7 +11918,7 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v1 row_shr:8 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_cmp_gt_i64_e32 vcc, v[1:2], v[5:6]
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX1164_DPP-NEXT: v_permlanex16_b32 v5, v2, -1, -1
@@ -11928,7 +11928,7 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1164_DPP-NEXT: v_cmp_gt_i64_e32 vcc, v[1:2], v[3:4]
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX1164_DPP-NEXT: v_bfrev_b32_e32 v4, 1
@@ -11945,7 +11945,7 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_bfrev_b32_e32 v5, 1
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_cmp_gt_i64_e32 vcc, v[1:2], v[3:4]
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
@@ -11953,7 +11953,7 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v2, 15
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
@@ -11978,7 +11978,7 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_writelane_b32 v4, s9, 48
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[6:7]
; GFX1164_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: s_mov_b32 s2, -1
; GFX1164_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
; GFX1164_DPP-NEXT: s_and_saveexec_b64 s[6:7], vcc
@@ -12253,7 +12253,7 @@ define amdgpu_kernel void @min_i32_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1064_ITERATIVE-NEXT: .LBB24_4:
-; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_ITERATIVE-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v0
@@ -12292,7 +12292,7 @@ define amdgpu_kernel void @min_i32_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1032_ITERATIVE-NEXT: .LBB24_4:
-; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_ITERATIVE-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1032_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v0
@@ -12529,7 +12529,7 @@ define amdgpu_kernel void @min_i32_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB24_2:
-; GFX1064_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_DPP-NEXT: v_readfirstlane_b32 s3, v0
@@ -12572,7 +12572,7 @@ define amdgpu_kernel void @min_i32_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB24_2:
-; GFX1032_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_DPP-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1032_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_DPP-NEXT: v_readfirstlane_b32 s3, v0
@@ -12612,7 +12612,7 @@ define amdgpu_kernel void @min_i32_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v1, 47
; GFX1164_DPP-NEXT: v_readlane_b32 s6, v1, 63
; GFX1164_DPP-NEXT: v_writelane_b32 v3, s3, 32
@@ -12819,7 +12819,7 @@ define amdgpu_kernel void @min_i64_constant(ptr addrspace(1) %out) {
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: .LBB25_2:
-; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064-NEXT: v_readfirstlane_b32 s3, v1
@@ -12850,7 +12850,7 @@ define amdgpu_kernel void @min_i64_constant(ptr addrspace(1) %out) {
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: .LBB25_2:
-; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032-NEXT: v_readfirstlane_b32 s3, v1
@@ -12891,7 +12891,7 @@ define amdgpu_kernel void @min_i64_constant(ptr addrspace(1) %out) {
; GFX1164-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc
; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
-; GFX1164-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc
; GFX1164-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc
; GFX1164-NEXT: s_mov_b32 s3, 0x31016000
@@ -13140,7 +13140,7 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1064_ITERATIVE-NEXT: .LBB26_4:
-; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_ITERATIVE-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX1064_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_ITERATIVE-NEXT: v_readfirstlane_b32 s3, v4
@@ -13190,7 +13190,7 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1032_ITERATIVE-NEXT: .LBB26_4:
-; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_ITERATIVE-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX1032_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_ITERATIVE-NEXT: v_readfirstlane_b32 s3, v4
@@ -13598,7 +13598,7 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB26_2:
-; GFX1064_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_DPP-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX1064_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_DPP-NEXT: s_mov_b32 null, 0
@@ -13683,7 +13683,7 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB26_2:
-; GFX1032_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_DPP-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GFX1032_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_DPP-NEXT: s_mov_b32 null, 0
@@ -13723,7 +13723,7 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v1 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_cmp_lt_i64_e32 vcc, v[1:2], v[5:6]
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX1164_DPP-NEXT: v_bfrev_b32_e32 v6, -2
@@ -13733,7 +13733,7 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:4 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_cmp_lt_i64_e32 vcc, v[1:2], v[3:4]
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX1164_DPP-NEXT: v_bfrev_b32_e32 v4, -2
@@ -13743,7 +13743,7 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v1 row_shr:8 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_cmp_lt_i64_e32 vcc, v[1:2], v[5:6]
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX1164_DPP-NEXT: v_permlanex16_b32 v5, v2, -1, -1
@@ -13753,7 +13753,7 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1164_DPP-NEXT: v_cmp_lt_i64_e32 vcc, v[1:2], v[3:4]
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX1164_DPP-NEXT: v_bfrev_b32_e32 v4, -2
@@ -13770,7 +13770,7 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_bfrev_b32_e32 v5, -2
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_cmp_lt_i64_e32 vcc, v[1:2], v[3:4]
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, -1
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
@@ -13778,7 +13778,7 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v2, 15
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
@@ -13803,7 +13803,7 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_writelane_b32 v4, s9, 48
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[6:7]
; GFX1164_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: s_mov_b32 s2, -1
; GFX1164_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
; GFX1164_DPP-NEXT: s_and_saveexec_b64 s[6:7], vcc
@@ -14078,7 +14078,7 @@ define amdgpu_kernel void @umax_i32_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1064_ITERATIVE-NEXT: .LBB27_4:
-; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_ITERATIVE-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v0
@@ -14117,7 +14117,7 @@ define amdgpu_kernel void @umax_i32_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1032_ITERATIVE-NEXT: .LBB27_4:
-; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_ITERATIVE-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1032_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v0
@@ -14354,7 +14354,7 @@ define amdgpu_kernel void @umax_i32_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB27_2:
-; GFX1064_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_DPP-NEXT: v_readfirstlane_b32 s3, v0
@@ -14397,7 +14397,7 @@ define amdgpu_kernel void @umax_i32_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB27_2:
-; GFX1032_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_DPP-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1032_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_DPP-NEXT: v_readfirstlane_b32 s3, v0
@@ -14437,7 +14437,7 @@ define amdgpu_kernel void @umax_i32_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v1, 47
; GFX1164_DPP-NEXT: v_readlane_b32 s6, v1, 63
; GFX1164_DPP-NEXT: v_writelane_b32 v3, s3, 32
@@ -14640,7 +14640,7 @@ define amdgpu_kernel void @umax_i64_constant(ptr addrspace(1) %out) {
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: .LBB28_2:
-; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064-NEXT: v_readfirstlane_b32 s3, v1
@@ -14671,7 +14671,7 @@ define amdgpu_kernel void @umax_i64_constant(ptr addrspace(1) %out) {
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: .LBB28_2:
-; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032-NEXT: v_readfirstlane_b32 s3, v1
@@ -14712,7 +14712,7 @@ define amdgpu_kernel void @umax_i64_constant(ptr addrspace(1) %out) {
; GFX1164-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc
; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1]
-; GFX1164-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc
; GFX1164-NEXT: v_cndmask_b32_e64 v1, 0, s3, vcc
; GFX1164-NEXT: s_mov_b32 s3, 0x31016000
@@ -14957,7 +14957,7 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1064_ITERATIVE-NEXT: .LBB29_4:
-; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_ITERATIVE-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX1064_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_ITERATIVE-NEXT: v_readfirstlane_b32 s3, v4
@@ -15006,7 +15006,7 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1032_ITERATIVE-NEXT: .LBB29_4:
-; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_ITERATIVE-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX1032_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_ITERATIVE-NEXT: v_readfirstlane_b32 s3, v4
@@ -15414,7 +15414,7 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB29_2:
-; GFX1064_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_DPP-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX1064_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_DPP-NEXT: s_mov_b32 null, 0
@@ -15499,7 +15499,7 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB29_2:
-; GFX1032_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_DPP-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GFX1032_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_DPP-NEXT: s_mov_b32 null, 0
@@ -15539,7 +15539,7 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v1 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[1:2], v[5:6]
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX1164_DPP-NEXT: v_mov_b32_e32 v6, 0
@@ -15549,7 +15549,7 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:4 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[1:2], v[3:4]
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
@@ -15559,7 +15559,7 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v1 row_shr:8 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[1:2], v[5:6]
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX1164_DPP-NEXT: v_permlanex16_b32 v5, v2, -1, -1
@@ -15569,7 +15569,7 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1164_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[1:2], v[3:4]
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
@@ -15586,7 +15586,7 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_mov_b32_e32 v5, 0
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_cmp_gt_u64_e32 vcc, v[1:2], v[3:4]
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
@@ -15594,7 +15594,7 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v2, 15
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
@@ -15619,7 +15619,7 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_writelane_b32 v4, s9, 48
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[6:7]
; GFX1164_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: s_mov_b32 s2, -1
; GFX1164_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
; GFX1164_DPP-NEXT: s_and_saveexec_b64 s[6:7], vcc
@@ -15888,7 +15888,7 @@ define amdgpu_kernel void @umin_i32_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1064_ITERATIVE-NEXT: .LBB30_4:
-; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_ITERATIVE-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v0
@@ -15927,7 +15927,7 @@ define amdgpu_kernel void @umin_i32_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1032_ITERATIVE-NEXT: .LBB30_4:
-; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_ITERATIVE-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1032_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v0
@@ -16164,7 +16164,7 @@ define amdgpu_kernel void @umin_i32_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB30_2:
-; GFX1064_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_DPP-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_DPP-NEXT: v_readfirstlane_b32 s3, v0
@@ -16207,7 +16207,7 @@ define amdgpu_kernel void @umin_i32_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB30_2:
-; GFX1032_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_DPP-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1032_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_DPP-NEXT: v_readfirstlane_b32 s3, v0
@@ -16247,7 +16247,7 @@ define amdgpu_kernel void @umin_i32_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v1, 47
; GFX1164_DPP-NEXT: v_readlane_b32 s6, v1, 63
; GFX1164_DPP-NEXT: v_writelane_b32 v3, s3, 32
@@ -16451,7 +16451,7 @@ define amdgpu_kernel void @umin_i64_constant(ptr addrspace(1) %out) {
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: buffer_gl0_inv
; GFX1064-NEXT: .LBB31_2:
-; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064-NEXT: v_readfirstlane_b32 s3, v1
@@ -16482,7 +16482,7 @@ define amdgpu_kernel void @umin_i64_constant(ptr addrspace(1) %out) {
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: buffer_gl0_inv
; GFX1032-NEXT: .LBB31_2:
-; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032-NEXT: v_readfirstlane_b32 s3, v1
@@ -16523,7 +16523,7 @@ define amdgpu_kernel void @umin_i64_constant(ptr addrspace(1) %out) {
; GFX1164-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc
; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1]
-; GFX1164-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc
; GFX1164-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc
; GFX1164-NEXT: s_mov_b32 s3, 0x31016000
@@ -16768,7 +16768,7 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1064_ITERATIVE-NEXT: .LBB32_4:
-; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_ITERATIVE-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX1064_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_ITERATIVE-NEXT: v_readfirstlane_b32 s3, v4
@@ -16817,7 +16817,7 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_ITERATIVE-NEXT: buffer_gl0_inv
; GFX1032_ITERATIVE-NEXT: .LBB32_4:
-; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_ITERATIVE-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_ITERATIVE-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX1032_ITERATIVE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_ITERATIVE-NEXT: v_readfirstlane_b32 s3, v4
@@ -17223,7 +17223,7 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1064_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064_DPP-NEXT: buffer_gl0_inv
; GFX1064_DPP-NEXT: .LBB32_2:
-; GFX1064_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064_DPP-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX1064_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1064_DPP-NEXT: s_mov_b32 null, 0
@@ -17308,7 +17308,7 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1032_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032_DPP-NEXT: buffer_gl0_inv
; GFX1032_DPP-NEXT: .LBB32_2:
-; GFX1032_DPP-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032_DPP-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032_DPP-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GFX1032_DPP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX1032_DPP-NEXT: s_mov_b32 null, 0
@@ -17348,7 +17348,7 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v1 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_cmp_lt_u64_e32 vcc, v[1:2], v[5:6]
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX1164_DPP-NEXT: v_mov_b32_e32 v6, -1
@@ -17358,7 +17358,7 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v1 row_shr:4 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_cmp_lt_u64_e32 vcc, v[1:2], v[3:4]
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, -1
@@ -17368,7 +17368,7 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v1 row_shr:8 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_cmp_lt_u64_e32 vcc, v[1:2], v[5:6]
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX1164_DPP-NEXT: v_permlanex16_b32 v5, v2, -1, -1
@@ -17378,7 +17378,7 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
; GFX1164_DPP-NEXT: v_cmp_lt_u64_e32 vcc, v[1:2], v[3:4]
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, -1
@@ -17395,7 +17395,7 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_mov_b32_e32 v5, -1
; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1164_DPP-NEXT: v_cmp_lt_u64_e32 vcc, v[1:2], v[3:4]
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, -1
; GFX1164_DPP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
@@ -17403,7 +17403,7 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164_DPP-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX1164_DPP-NEXT: v_readlane_b32 s2, v2, 15
; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
@@ -17428,7 +17428,7 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1164_DPP-NEXT: v_writelane_b32 v4, s9, 48
; GFX1164_DPP-NEXT: s_mov_b64 exec, s[6:7]
; GFX1164_DPP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
-; GFX1164_DPP-NEXT: s_waitcnt_depctr 0xfffd
+; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX1164_DPP-NEXT: s_mov_b32 s2, -1
; GFX1164_DPP-NEXT: ; implicit-def: $vgpr7_vgpr8
; GFX1164_DPP-NEXT: s_and_saveexec_b64 s[6:7], vcc
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
index 62f09deeb9b08..40a271d08abb5 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
@@ -104,7 +104,7 @@ define amdgpu_ps void @add_i32_constant(ptr addrspace(8) inreg %out, ptr addrspa
; GFX1064-NEXT: v_mov_b32_e32 v1, s12
; GFX1064-NEXT: buffer_atomic_add v1, off, s[4:7], 0 glc
; GFX1064-NEXT: .LBB0_3:
-; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064-NEXT: s_or_b64 exec, exec, s[10:11]
; GFX1064-NEXT: s_waitcnt vmcnt(0)
; GFX1064-NEXT: v_readfirstlane_b32 s4, v1
@@ -139,7 +139,7 @@ define amdgpu_ps void @add_i32_constant(ptr addrspace(8) inreg %out, ptr addrspa
; GFX1032-NEXT: v_mov_b32_e32 v1, s10
; GFX1032-NEXT: buffer_atomic_add v1, off, s[4:7], 0 glc
; GFX1032-NEXT: .LBB0_3:
-; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s9
; GFX1032-NEXT: s_waitcnt vmcnt(0)
; GFX1032-NEXT: v_readfirstlane_b32 s4, v1
@@ -413,7 +413,7 @@ define amdgpu_ps void @add_i32_varying(ptr addrspace(8) inreg %out, ptr addrspac
; GFX1064-NEXT: v_mov_b32_e32 v0, s12
; GFX1064-NEXT: buffer_atomic_add v0, off, s[4:7], 0 glc
; GFX1064-NEXT: .LBB1_3:
-; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064-NEXT: s_or_b64 exec, exec, s[10:11]
; GFX1064-NEXT: s_waitcnt vmcnt(0)
; GFX1064-NEXT: v_readfirstlane_b32 s4, v0
@@ -463,7 +463,7 @@ define amdgpu_ps void @add_i32_varying(ptr addrspace(8) inreg %out, ptr addrspac
; GFX1032-NEXT: v_mov_b32_e32 v0, s11
; GFX1032-NEXT: buffer_atomic_add v0, off, s[4:7], 0 glc
; GFX1032-NEXT: .LBB1_3:
-; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s9
; GFX1032-NEXT: s_waitcnt vmcnt(0)
; GFX1032-NEXT: v_readfirstlane_b32 s4, v0
@@ -515,7 +515,7 @@ define amdgpu_ps void @add_i32_varying(ptr addrspace(8) inreg %out, ptr addrspac
; GFX1164-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1164-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-NEXT: s_or_saveexec_b64 s[10:11], -1
-; GFX1164-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-NEXT: v_readlane_b32 s12, v1, 63
; GFX1164-NEXT: v_readlane_b32 s14, v1, 47
; GFX1164-NEXT: v_writelane_b32 v3, s13, 32
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
index 9afc0c62e846e..42c6e2d7f7ae1 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
@@ -116,7 +116,7 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX10W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W64-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc
; GFX10W64-NEXT: .LBB0_2:
-; GFX10W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W64-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W64-NEXT: s_waitcnt vmcnt(0)
@@ -143,7 +143,7 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX10W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W32-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc
; GFX10W32-NEXT: .LBB0_2:
-; GFX10W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX10W32-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W32-NEXT: s_waitcnt vmcnt(0)
@@ -226,9 +226,9 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W64-NEXT: ; %bb.1:
; GFX12W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34
; GFX12W64-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: s_mul_i32 s2, s2, 5
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: v_mov_b32_e32 v1, s2
; GFX12W64-NEXT: s_wait_kmcnt 0x0
; GFX12W64-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
@@ -238,7 +238,7 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W64-NEXT: s_wait_loadcnt 0x0
; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1
; GFX12W64-NEXT: v_mov_b32_e32 v1, 0
-; GFX12W64-NEXT: s_wait_alu 0xf1ff
+; GFX12W64-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12W64-NEXT: v_mad_u32_u24 v0, v0, 5, s2
; GFX12W64-NEXT: s_wait_kmcnt 0x0
@@ -257,9 +257,9 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W32-NEXT: ; %bb.1:
; GFX12W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34
; GFX12W32-NEXT: s_bcnt1_i32_b32 s1, s1
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_mul_i32 s1, s1, 5
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: v_mov_b32_e32 v1, s1
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
@@ -388,7 +388,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX10W64-NEXT: v_mov_b32_e32 v1, s2
; GFX10W64-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc
; GFX10W64-NEXT: .LBB1_2:
-; GFX10W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W64-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W64-NEXT: s_waitcnt vmcnt(0)
@@ -416,7 +416,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX10W32-NEXT: v_mov_b32_e32 v1, s2
; GFX10W32-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc
; GFX10W32-NEXT: .LBB1_2:
-; GFX10W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX10W32-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; GFX10W32-NEXT: s_waitcnt vmcnt(0)
@@ -504,9 +504,9 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34
; GFX12W64-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX12W64-NEXT: s_wait_kmcnt 0x0
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: s_mul_i32 s2, s6, s2
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: v_mov_b32_e32 v1, s2
; GFX12W64-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
; GFX12W64-NEXT: .LBB1_2:
@@ -515,7 +515,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W64-NEXT: s_wait_loadcnt 0x0
; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1
; GFX12W64-NEXT: s_wait_kmcnt 0x0
-; GFX12W64-NEXT: s_wait_alu 0xf1ff
+; GFX12W64-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12W64-NEXT: v_mad_co_u64_u32 v[0:1], null, s6, v0, s[2:3]
; GFX12W64-NEXT: v_mov_b32_e32 v1, 0
@@ -536,9 +536,9 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34
; GFX12W32-NEXT: s_bcnt1_i32_b32 s2, s2
; GFX12W32-NEXT: s_wait_kmcnt 0x0
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_mul_i32 s2, s0, s2
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: v_mov_b32_e32 v1, s2
; GFX12W32-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
; GFX12W32-NEXT: .LBB1_2:
@@ -709,7 +709,7 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX10W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W64-NEXT: buffer_atomic_add v0, off, s[8:11], 0 glc
; GFX10W64-NEXT: .LBB2_4:
-; GFX10W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W64-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W64-NEXT: s_waitcnt vmcnt(0)
@@ -747,7 +747,7 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX10W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W32-NEXT: buffer_atomic_add v0, off, s[8:11], 0 glc
; GFX10W32-NEXT: .LBB2_4:
-; GFX10W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX10W32-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W32-NEXT: s_waitcnt vmcnt(0)
@@ -850,7 +850,7 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W64-NEXT: .LBB2_1: ; %ComputeLoop
; GFX12W64-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12W64-NEXT: s_ctz_i32_b64 s3, s[0:1]
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: v_readlane_b32 s8, v1, s3
; GFX12W64-NEXT: v_writelane_b32 v0, s2, s3
; GFX12W64-NEXT: s_lshl_b64 s[6:7], 1, s3
@@ -878,7 +878,7 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W64-NEXT: s_wait_loadcnt 0x0
; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1
; GFX12W64-NEXT: v_mov_b32_e32 v1, 0
-; GFX12W64-NEXT: s_wait_alu 0xf1ff
+; GFX12W64-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12W64-NEXT: v_add_nc_u32_e32 v0, s2, v0
; GFX12W64-NEXT: s_wait_kmcnt 0x0
@@ -893,14 +893,14 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: ; implicit-def: $vgpr0
; GFX12W32-NEXT: .LBB2_1: ; %ComputeLoop
; GFX12W32-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_ctz_i32_b32 s2, s1
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: v_readlane_b32 s3, v1, s2
; GFX12W32-NEXT: v_writelane_b32 v0, s0, s2
; GFX12W32-NEXT: s_lshl_b32 s2, 1, s2
; GFX12W32-NEXT: s_add_co_i32 s0, s0, s3
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_and_not1_b32 s1, s1, s2
; GFX12W32-NEXT: s_cbranch_scc1 .LBB2_1
; GFX12W32-NEXT: ; %bb.2: ; %ComputeEnd
@@ -909,7 +909,7 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX12W32-NEXT: ; implicit-def: $vgpr1
; GFX12W32-NEXT: s_and_saveexec_b32 s1, vcc_lo
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_xor_b32 s1, exec_lo, s1
; GFX12W32-NEXT: s_cbranch_execz .LBB2_4
; GFX12W32-NEXT: ; %bb.3:
@@ -918,12 +918,12 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
; GFX12W32-NEXT: .LBB2_4:
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12W32-NEXT: s_wait_loadcnt 0x0
; GFX12W32-NEXT: v_readfirstlane_b32 s2, v1
-; GFX12W32-NEXT: s_wait_alu 0xf1ff
+; GFX12W32-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12W32-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s2, v0
; GFX12W32-NEXT: s_wait_kmcnt 0x0
@@ -982,7 +982,7 @@ define amdgpu_kernel void @add_i32_varying_offset(ptr addrspace(1) %out, ptr add
; GFX10-NEXT: v_mov_b32_e32 v1, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: buffer_atomic_add v1, v0, s[0:3], 0 offen glc
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1151,7 +1151,7 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX10W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W64-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc
; GFX10W64-NEXT: .LBB4_2:
-; GFX10W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W64-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W64-NEXT: s_waitcnt vmcnt(0)
@@ -1179,7 +1179,7 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX10W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W32-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc
; GFX10W32-NEXT: .LBB4_2:
-; GFX10W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX10W32-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W32-NEXT: s_waitcnt vmcnt(0)
@@ -1265,9 +1265,9 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W64-NEXT: ; %bb.1:
; GFX12W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34
; GFX12W64-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: s_mul_i32 s2, s2, 5
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: v_mov_b32_e32 v1, s2
; GFX12W64-NEXT: s_wait_kmcnt 0x0
; GFX12W64-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
@@ -1278,7 +1278,7 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1
; GFX12W64-NEXT: v_mul_u32_u24_e32 v0, 5, v0
; GFX12W64-NEXT: v_mov_b32_e32 v1, 0
-; GFX12W64-NEXT: s_wait_alu 0xf1ff
+; GFX12W64-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12W64-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX12W64-NEXT: s_wait_kmcnt 0x0
@@ -1297,9 +1297,9 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W32-NEXT: ; %bb.1:
; GFX12W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34
; GFX12W32-NEXT: s_bcnt1_i32_b32 s1, s1
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_mul_i32 s1, s1, 5
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: v_mov_b32_e32 v1, s1
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
@@ -1429,7 +1429,7 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX10W64-NEXT: v_mov_b32_e32 v1, s2
; GFX10W64-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc
; GFX10W64-NEXT: .LBB5_2:
-; GFX10W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W64-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W64-NEXT: s_waitcnt lgkmcnt(0)
@@ -1458,7 +1458,7 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX10W32-NEXT: v_mov_b32_e32 v1, s2
; GFX10W32-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc
; GFX10W32-NEXT: .LBB5_2:
-; GFX10W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX10W32-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; GFX10W32-NEXT: s_waitcnt lgkmcnt(0)
@@ -1548,9 +1548,9 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34
; GFX12W64-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX12W64-NEXT: s_wait_kmcnt 0x0
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: s_mul_i32 s2, s6, s2
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: v_mov_b32_e32 v1, s2
; GFX12W64-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
; GFX12W64-NEXT: .LBB5_2:
@@ -1561,7 +1561,7 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W64-NEXT: s_wait_loadcnt 0x0
; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1
; GFX12W64-NEXT: v_mov_b32_e32 v1, 0
-; GFX12W64-NEXT: s_wait_alu 0xf1ff
+; GFX12W64-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12W64-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX12W64-NEXT: global_store_b32 v1, v0, s[0:1]
@@ -1581,9 +1581,9 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34
; GFX12W32-NEXT: s_bcnt1_i32_b32 s2, s2
; GFX12W32-NEXT: s_wait_kmcnt 0x0
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_mul_i32 s2, s0, s2
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: v_mov_b32_e32 v1, s2
; GFX12W32-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
; GFX12W32-NEXT: .LBB5_2:
@@ -1594,7 +1594,7 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W32-NEXT: s_wait_loadcnt 0x0
; GFX12W32-NEXT: v_readfirstlane_b32 s0, v1
; GFX12W32-NEXT: v_mov_b32_e32 v1, 0
-; GFX12W32-NEXT: s_wait_alu 0xf1ff
+; GFX12W32-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12W32-NEXT: v_sub_nc_u32_e32 v0, s0, v0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[2:3]
@@ -1756,7 +1756,7 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX10W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W64-NEXT: buffer_atomic_sub v0, off, s[8:11], 0 glc
; GFX10W64-NEXT: .LBB6_4:
-; GFX10W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W64-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W64-NEXT: s_waitcnt vmcnt(0)
@@ -1794,7 +1794,7 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX10W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W32-NEXT: buffer_atomic_sub v0, off, s[8:11], 0 glc
; GFX10W32-NEXT: .LBB6_4:
-; GFX10W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX10W32-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W32-NEXT: s_waitcnt vmcnt(0)
@@ -1898,7 +1898,7 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W64-NEXT: .LBB6_1: ; %ComputeLoop
; GFX12W64-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12W64-NEXT: s_ctz_i32_b64 s3, s[0:1]
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: v_readlane_b32 s8, v1, s3
; GFX12W64-NEXT: v_writelane_b32 v0, s2, s3
; GFX12W64-NEXT: s_lshl_b64 s[6:7], 1, s3
@@ -1926,7 +1926,7 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W64-NEXT: s_wait_loadcnt 0x0
; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1
; GFX12W64-NEXT: v_mov_b32_e32 v1, 0
-; GFX12W64-NEXT: s_wait_alu 0xf1ff
+; GFX12W64-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12W64-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX12W64-NEXT: s_wait_kmcnt 0x0
@@ -1941,14 +1941,14 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: ; implicit-def: $vgpr0
; GFX12W32-NEXT: .LBB6_1: ; %ComputeLoop
; GFX12W32-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_ctz_i32_b32 s2, s1
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: v_readlane_b32 s3, v1, s2
; GFX12W32-NEXT: v_writelane_b32 v0, s0, s2
; GFX12W32-NEXT: s_lshl_b32 s2, 1, s2
; GFX12W32-NEXT: s_add_co_i32 s0, s0, s3
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_and_not1_b32 s1, s1, s2
; GFX12W32-NEXT: s_cbranch_scc1 .LBB6_1
; GFX12W32-NEXT: ; %bb.2: ; %ComputeEnd
@@ -1957,7 +1957,7 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX12W32-NEXT: ; implicit-def: $vgpr1
; GFX12W32-NEXT: s_and_saveexec_b32 s1, vcc_lo
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_xor_b32 s1, exec_lo, s1
; GFX12W32-NEXT: s_cbranch_execz .LBB6_4
; GFX12W32-NEXT: ; %bb.3:
@@ -1966,13 +1966,13 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
; GFX12W32-NEXT: .LBB6_4:
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12W32-NEXT: s_wait_loadcnt 0x0
; GFX12W32-NEXT: v_readfirstlane_b32 s2, v1
; GFX12W32-NEXT: v_mov_b32_e32 v1, 0
-; GFX12W32-NEXT: s_wait_alu 0xf1ff
+; GFX12W32-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12W32-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX12W32-NEXT: s_wait_kmcnt 0x0
@@ -2031,7 +2031,7 @@ define amdgpu_kernel void @sub_i32_varying_offset(ptr addrspace(1) %out, ptr add
; GFX10-NEXT: v_mov_b32_e32 v1, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: buffer_atomic_sub v1, v0, s[0:3], 0 offen glc
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
index 10fd34f08b83e..45b47a1f389e5 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
@@ -120,7 +120,7 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX10W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W64-NEXT: buffer_atomic_add v1, v2, s[8:11], 0 idxen glc
; GFX10W64-NEXT: .LBB0_2:
-; GFX10W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W64-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W64-NEXT: s_waitcnt vmcnt(0)
@@ -148,7 +148,7 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX10W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W32-NEXT: buffer_atomic_add v1, v2, s[8:11], 0 idxen glc
; GFX10W32-NEXT: .LBB0_2:
-; GFX10W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX10W32-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W32-NEXT: s_waitcnt vmcnt(0)
@@ -234,9 +234,9 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34
; GFX12W64-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX12W64-NEXT: v_mov_b32_e32 v2, 0
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: s_mul_i32 s2, s2, 5
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: v_mov_b32_e32 v1, s2
; GFX12W64-NEXT: s_wait_kmcnt 0x0
; GFX12W64-NEXT: buffer_atomic_add_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
@@ -246,7 +246,7 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W64-NEXT: s_wait_loadcnt 0x0
; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1
; GFX12W64-NEXT: v_mov_b32_e32 v1, 0
-; GFX12W64-NEXT: s_wait_alu 0xf1ff
+; GFX12W64-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12W64-NEXT: v_mad_u32_u24 v0, v0, 5, s2
; GFX12W64-NEXT: s_wait_kmcnt 0x0
@@ -265,9 +265,9 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W32-NEXT: ; %bb.1:
; GFX12W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34
; GFX12W32-NEXT: s_bcnt1_i32_b32 s1, s1
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_mul_i32 s1, s1, 5
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: buffer_atomic_add_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
@@ -400,7 +400,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX10W64-NEXT: v_mov_b32_e32 v1, s2
; GFX10W64-NEXT: buffer_atomic_add v1, v2, s[8:11], 0 idxen glc
; GFX10W64-NEXT: .LBB1_2:
-; GFX10W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W64-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W64-NEXT: s_waitcnt vmcnt(0)
@@ -429,7 +429,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX10W32-NEXT: v_mov_b32_e32 v1, s2
; GFX10W32-NEXT: buffer_atomic_add v1, v2, s[8:11], 0 idxen glc
; GFX10W32-NEXT: .LBB1_2:
-; GFX10W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX10W32-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; GFX10W32-NEXT: s_waitcnt vmcnt(0)
@@ -520,9 +520,9 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W64-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX12W64-NEXT: v_mov_b32_e32 v2, 0
; GFX12W64-NEXT: s_wait_kmcnt 0x0
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: s_mul_i32 s2, s6, s2
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: v_mov_b32_e32 v1, s2
; GFX12W64-NEXT: buffer_atomic_add_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
; GFX12W64-NEXT: .LBB1_2:
@@ -531,7 +531,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W64-NEXT: s_wait_loadcnt 0x0
; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1
; GFX12W64-NEXT: s_wait_kmcnt 0x0
-; GFX12W64-NEXT: s_wait_alu 0xf1ff
+; GFX12W64-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12W64-NEXT: v_mad_co_u64_u32 v[0:1], null, s6, v0, s[2:3]
; GFX12W64-NEXT: v_mov_b32_e32 v1, 0
@@ -552,9 +552,9 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34
; GFX12W32-NEXT: s_bcnt1_i32_b32 s2, s2
; GFX12W32-NEXT: s_wait_kmcnt 0x0
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_mul_i32 s2, s0, s2
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
; GFX12W32-NEXT: buffer_atomic_add_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
; GFX12W32-NEXT: .LBB1_2:
@@ -729,7 +729,7 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX10W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W64-NEXT: buffer_atomic_add v0, v2, s[8:11], 0 idxen glc
; GFX10W64-NEXT: .LBB2_4:
-; GFX10W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W64-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W64-NEXT: s_waitcnt vmcnt(0)
@@ -768,7 +768,7 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX10W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W32-NEXT: buffer_atomic_add v0, v2, s[8:11], 0 idxen glc
; GFX10W32-NEXT: .LBB2_4:
-; GFX10W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX10W32-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W32-NEXT: s_waitcnt vmcnt(0)
@@ -872,7 +872,7 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W64-NEXT: .LBB2_1: ; %ComputeLoop
; GFX12W64-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12W64-NEXT: s_ctz_i32_b64 s3, s[0:1]
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: v_readlane_b32 s8, v1, s3
; GFX12W64-NEXT: v_writelane_b32 v0, s2, s3
; GFX12W64-NEXT: s_lshl_b64 s[6:7], 1, s3
@@ -901,7 +901,7 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W64-NEXT: s_wait_loadcnt 0x0
; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1
; GFX12W64-NEXT: v_mov_b32_e32 v1, 0
-; GFX12W64-NEXT: s_wait_alu 0xf1ff
+; GFX12W64-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12W64-NEXT: v_add_nc_u32_e32 v0, s2, v0
; GFX12W64-NEXT: s_wait_kmcnt 0x0
@@ -916,14 +916,14 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: ; implicit-def: $vgpr0
; GFX12W32-NEXT: .LBB2_1: ; %ComputeLoop
; GFX12W32-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_ctz_i32_b32 s2, s1
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: v_readlane_b32 s3, v1, s2
; GFX12W32-NEXT: v_writelane_b32 v0, s0, s2
; GFX12W32-NEXT: s_lshl_b32 s2, 1, s2
; GFX12W32-NEXT: s_add_co_i32 s0, s0, s3
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_and_not1_b32 s1, s1, s2
; GFX12W32-NEXT: s_cbranch_scc1 .LBB2_1
; GFX12W32-NEXT: ; %bb.2: ; %ComputeEnd
@@ -932,7 +932,7 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX12W32-NEXT: ; implicit-def: $vgpr1
; GFX12W32-NEXT: s_and_saveexec_b32 s1, vcc_lo
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_xor_b32 s1, exec_lo, s1
; GFX12W32-NEXT: s_cbranch_execz .LBB2_4
; GFX12W32-NEXT: ; %bb.3:
@@ -941,12 +941,12 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: buffer_atomic_add_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
; GFX12W32-NEXT: .LBB2_4:
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12W32-NEXT: s_wait_loadcnt 0x0
; GFX12W32-NEXT: v_readfirstlane_b32 s2, v1
-; GFX12W32-NEXT: s_wait_alu 0xf1ff
+; GFX12W32-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12W32-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s2, v0
; GFX12W32-NEXT: s_wait_kmcnt 0x0
@@ -1005,7 +1005,7 @@ define amdgpu_kernel void @add_i32_varying_vindex(ptr addrspace(1) %out, ptr add
; GFX10-NEXT: v_mov_b32_e32 v1, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: buffer_atomic_add v1, v0, s[0:3], 0 idxen glc
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1128,7 +1128,7 @@ define amdgpu_kernel void @add_i32_varying_offset(ptr addrspace(1) %out, ptr add
; GFX10-NEXT: v_mov_b32_e32 v2, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: buffer_atomic_add v2, v[0:1], s[0:3], 0 idxen offen glc
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1306,7 +1306,7 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX10W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W64-NEXT: buffer_atomic_sub v1, v2, s[8:11], 0 idxen glc
; GFX10W64-NEXT: .LBB5_2:
-; GFX10W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W64-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W64-NEXT: s_waitcnt vmcnt(0)
@@ -1335,7 +1335,7 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX10W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W32-NEXT: buffer_atomic_sub v1, v2, s[8:11], 0 idxen glc
; GFX10W32-NEXT: .LBB5_2:
-; GFX10W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX10W32-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W32-NEXT: s_waitcnt vmcnt(0)
@@ -1424,9 +1424,9 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34
; GFX12W64-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX12W64-NEXT: v_mov_b32_e32 v2, 0
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: s_mul_i32 s2, s2, 5
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: v_mov_b32_e32 v1, s2
; GFX12W64-NEXT: s_wait_kmcnt 0x0
; GFX12W64-NEXT: buffer_atomic_sub_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
@@ -1437,7 +1437,7 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1
; GFX12W64-NEXT: v_mul_u32_u24_e32 v0, 5, v0
; GFX12W64-NEXT: v_mov_b32_e32 v1, 0
-; GFX12W64-NEXT: s_wait_alu 0xf1ff
+; GFX12W64-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12W64-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX12W64-NEXT: s_wait_kmcnt 0x0
@@ -1456,9 +1456,9 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W32-NEXT: ; %bb.1:
; GFX12W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34
; GFX12W32-NEXT: s_bcnt1_i32_b32 s1, s1
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_mul_i32 s1, s1, 5
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: buffer_atomic_sub_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
@@ -1592,7 +1592,7 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX10W64-NEXT: v_mov_b32_e32 v1, s2
; GFX10W64-NEXT: buffer_atomic_sub v1, v2, s[8:11], 0 idxen glc
; GFX10W64-NEXT: .LBB6_2:
-; GFX10W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W64-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W64-NEXT: s_waitcnt lgkmcnt(0)
@@ -1622,7 +1622,7 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX10W32-NEXT: v_mov_b32_e32 v1, s2
; GFX10W32-NEXT: buffer_atomic_sub v1, v2, s[8:11], 0 idxen glc
; GFX10W32-NEXT: .LBB6_2:
-; GFX10W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX10W32-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; GFX10W32-NEXT: s_waitcnt lgkmcnt(0)
@@ -1715,9 +1715,9 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W64-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX12W64-NEXT: v_mov_b32_e32 v2, 0
; GFX12W64-NEXT: s_wait_kmcnt 0x0
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: s_mul_i32 s2, s6, s2
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: v_mov_b32_e32 v1, s2
; GFX12W64-NEXT: buffer_atomic_sub_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
; GFX12W64-NEXT: .LBB6_2:
@@ -1728,7 +1728,7 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W64-NEXT: s_wait_loadcnt 0x0
; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1
; GFX12W64-NEXT: v_mov_b32_e32 v1, 0
-; GFX12W64-NEXT: s_wait_alu 0xf1ff
+; GFX12W64-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12W64-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX12W64-NEXT: global_store_b32 v1, v0, s[0:1]
@@ -1748,9 +1748,9 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34
; GFX12W32-NEXT: s_bcnt1_i32_b32 s2, s2
; GFX12W32-NEXT: s_wait_kmcnt 0x0
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_mul_i32 s2, s0, s2
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
; GFX12W32-NEXT: buffer_atomic_sub_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
; GFX12W32-NEXT: .LBB6_2:
@@ -1761,7 +1761,7 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W32-NEXT: s_wait_loadcnt 0x0
; GFX12W32-NEXT: v_readfirstlane_b32 s0, v1
; GFX12W32-NEXT: v_mov_b32_e32 v1, 0
-; GFX12W32-NEXT: s_wait_alu 0xf1ff
+; GFX12W32-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12W32-NEXT: v_sub_nc_u32_e32 v0, s0, v0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[2:3]
@@ -1927,7 +1927,7 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX10W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W64-NEXT: buffer_atomic_sub v0, v2, s[8:11], 0 idxen glc
; GFX10W64-NEXT: .LBB7_4:
-; GFX10W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W64-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W64-NEXT: s_waitcnt vmcnt(0)
@@ -1966,7 +1966,7 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX10W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX10W32-NEXT: buffer_atomic_sub v0, v2, s[8:11], 0 idxen glc
; GFX10W32-NEXT: .LBB7_4:
-; GFX10W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX10W32-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10W32-NEXT: s_waitcnt vmcnt(0)
@@ -2071,7 +2071,7 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W64-NEXT: .LBB7_1: ; %ComputeLoop
; GFX12W64-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12W64-NEXT: s_ctz_i32_b64 s3, s[0:1]
-; GFX12W64-NEXT: s_wait_alu 0xfffe
+; GFX12W64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W64-NEXT: v_readlane_b32 s8, v1, s3
; GFX12W64-NEXT: v_writelane_b32 v0, s2, s3
; GFX12W64-NEXT: s_lshl_b64 s[6:7], 1, s3
@@ -2100,7 +2100,7 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W64-NEXT: s_wait_loadcnt 0x0
; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1
; GFX12W64-NEXT: v_mov_b32_e32 v1, 0
-; GFX12W64-NEXT: s_wait_alu 0xf1ff
+; GFX12W64-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12W64-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX12W64-NEXT: s_wait_kmcnt 0x0
@@ -2115,14 +2115,14 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: ; implicit-def: $vgpr0
; GFX12W32-NEXT: .LBB7_1: ; %ComputeLoop
; GFX12W32-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_ctz_i32_b32 s2, s1
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: v_readlane_b32 s3, v1, s2
; GFX12W32-NEXT: v_writelane_b32 v0, s0, s2
; GFX12W32-NEXT: s_lshl_b32 s2, 1, s2
; GFX12W32-NEXT: s_add_co_i32 s0, s0, s3
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_and_not1_b32 s1, s1, s2
; GFX12W32-NEXT: s_cbranch_scc1 .LBB7_1
; GFX12W32-NEXT: ; %bb.2: ; %ComputeEnd
@@ -2131,7 +2131,7 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX12W32-NEXT: ; implicit-def: $vgpr1
; GFX12W32-NEXT: s_and_saveexec_b32 s1, vcc_lo
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_xor_b32 s1, exec_lo, s1
; GFX12W32-NEXT: s_cbranch_execz .LBB7_4
; GFX12W32-NEXT: ; %bb.3:
@@ -2140,13 +2140,13 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: buffer_atomic_sub_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
; GFX12W32-NEXT: .LBB7_4:
-; GFX12W32-NEXT: s_wait_alu 0xfffe
+; GFX12W32-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12W32-NEXT: s_wait_loadcnt 0x0
; GFX12W32-NEXT: v_readfirstlane_b32 s2, v1
; GFX12W32-NEXT: v_mov_b32_e32 v1, 0
-; GFX12W32-NEXT: s_wait_alu 0xf1ff
+; GFX12W32-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12W32-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX12W32-NEXT: s_wait_kmcnt 0x0
@@ -2205,7 +2205,7 @@ define amdgpu_kernel void @sub_i32_varying_vindex(ptr addrspace(1) %out, ptr add
; GFX10-NEXT: v_mov_b32_e32 v1, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: buffer_atomic_sub v1, v0, s[0:3], 0 idxen glc
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -2328,7 +2328,7 @@ define amdgpu_kernel void @sub_i32_varying_offset(ptr addrspace(1) %out, ptr add
; GFX10-NEXT: v_mov_b32_e32 v2, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: buffer_atomic_sub v2, v[0:1], s[0:3], 0 idxen offen glc
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll b/llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
index 89c3e8d615efd..e7adfa01b6633 100644
--- a/llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
@@ -653,50 +653,50 @@ define i64 @optnone_atomicrmw_add_i64_expand(i64 %val) #1 {
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX1200-NEXT: s_getpc_b64 s[2:3]
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_sext_i32_i16 s3, s3
; GFX1200-NEXT: s_add_co_u32 s2, s2, global at rel32@lo+12
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_ci_u32 s3, s3, global at rel32@hi+24
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cmp_eq_u32 s3, s1
; GFX1200-NEXT: s_cselect_b32 s0, -1, 0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; GFX1200-NEXT: s_mov_b32 s0, -1
; GFX1200-NEXT: s_mov_b32 s1, 1
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_cmp_ne_u32_e64 s1, v2, s1
; GFX1200-NEXT: s_and_b32 vcc_lo, exec_lo, s1
; GFX1200-NEXT: ; implicit-def: $vgpr3_vgpr4
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cbranch_vccnz .LBB4_3
; GFX1200-NEXT: .LBB4_1: ; %Flow
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; GFX1200-NEXT: s_mov_b32 s0, 1
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_cmp_ne_u32_e64 s0, v2, s0
; GFX1200-NEXT: s_and_b32 vcc_lo, exec_lo, s0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cbranch_vccnz .LBB4_4
; GFX1200-NEXT: ; %bb.2: ; %atomicrmw.private
; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT: scratch_load_b64 v[3:4], off, s0
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: v_add_co_u32 v0, s0, v3, v0
-; GFX1200-NEXT: s_wait_alu 0xf1ff
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_add_co_ci_u32_e64 v1, s0, v4, v1, s0
; GFX1200-NEXT: scratch_store_b64 off, v[0:1], s0
; GFX1200-NEXT: s_branch .LBB4_4
; GFX1200-NEXT: .LBB4_3: ; %atomicrmw.global
; GFX1200-NEXT: s_getpc_b64 s[0:1]
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_sext_i32_i16 s1, s1
; GFX1200-NEXT: s_add_co_u32 s0, s0, global at rel32@lo+12
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_ci_u32 s1, s1, global at rel32@hi+24
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_mov_b32_e32 v3, s1
; GFX1200-NEXT: v_mov_b32_e32 v2, s0
; GFX1200-NEXT: flat_atomic_add_u64 v[3:4], v[2:3], v[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
@@ -706,7 +706,7 @@ define i64 @optnone_atomicrmw_add_i64_expand(i64 %val) #1 {
; GFX1200-NEXT: ; %bb.5: ; %atomicrmw.end
; GFX1200-NEXT: s_mov_b32 s0, 32
; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1200-NEXT: s_wait_alu 0xf1fe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0) depctr_va_sdst(0)
; GFX1200-NEXT: v_lshrrev_b64 v[1:2], s0, v[3:4]
; GFX1200-NEXT: v_mov_b32_e32 v0, v3
; GFX1200-NEXT: s_setpc_b64 s[30:31]
@@ -1038,23 +1038,23 @@ define double @optnone_atomicrmw_fadd_f64_expand(double %val) #1 {
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX1200-NEXT: s_getpc_b64 s[2:3]
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_sext_i32_i16 s3, s3
; GFX1200-NEXT: s_add_co_u32 s2, s2, global at rel32@lo+12
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_ci_u32 s3, s3, global at rel32@hi+24
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cmp_eq_u32 s3, s1
; GFX1200-NEXT: s_cselect_b32 s0, -1, 0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; GFX1200-NEXT: s_mov_b32 s0, -1
; GFX1200-NEXT: s_mov_b32 s1, 1
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_cmp_ne_u32_e64 s1, v2, s1
; GFX1200-NEXT: s_and_b32 vcc_lo, exec_lo, s1
; GFX1200-NEXT: ; implicit-def: $vgpr3_vgpr4
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cbranch_vccnz .LBB5_2
; GFX1200-NEXT: s_branch .LBB5_3
; GFX1200-NEXT: .LBB5_1: ; %atomicrmw.private
@@ -1065,21 +1065,21 @@ define double @optnone_atomicrmw_fadd_f64_expand(double %val) #1 {
; GFX1200-NEXT: s_branch .LBB5_6
; GFX1200-NEXT: .LBB5_2: ; %atomicrmw.global
; GFX1200-NEXT: s_getpc_b64 s[0:1]
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_sext_i32_i16 s1, s1
; GFX1200-NEXT: s_add_co_u32 s0, s0, global at rel32@lo+12
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_ci_u32 s1, s1, global at rel32@hi+24
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_mov_b32_e32 v3, s1
; GFX1200-NEXT: v_mov_b32_e32 v2, s0
; GFX1200-NEXT: flat_load_b64 v[3:4], v[2:3]
; GFX1200-NEXT: s_mov_b32 s0, 0
; GFX1200-NEXT: s_branch .LBB5_4
; GFX1200-NEXT: .LBB5_3: ; %Flow
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_b32 vcc_lo, exec_lo, s0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cbranch_vccnz .LBB5_1
; GFX1200-NEXT: s_branch .LBB5_6
; GFX1200-NEXT: .LBB5_4: ; %atomicrmw.start
@@ -1089,19 +1089,19 @@ define double @optnone_atomicrmw_fadd_f64_expand(double %val) #1 {
; GFX1200-NEXT: v_mov_b32_e32 v5, v3
; GFX1200-NEXT: v_add_f64_e64 v[3:4], v[5:6], v[0:1]
; GFX1200-NEXT: s_getpc_b64 s[2:3]
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_sext_i32_i16 s3, s3
; GFX1200-NEXT: s_add_co_u32 s2, s2, global at rel32@lo+12
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_ci_u32 s3, s3, global at rel32@hi+24
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_mov_b32_e32 v8, s3
; GFX1200-NEXT: v_mov_b32_e32 v7, s2
; GFX1200-NEXT: flat_atomic_cmpswap_b64 v[3:4], v[7:8], v[3:6] th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1200-NEXT: v_cmp_eq_u64_e64 s1, v[3:4], v[5:6]
; GFX1200-NEXT: s_or_b32 s0, s1, s0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX1200-NEXT: s_cbranch_execnz .LBB5_4
; GFX1200-NEXT: ; %bb.5: ; %atomicrmw.end1
@@ -1111,7 +1111,7 @@ define double @optnone_atomicrmw_fadd_f64_expand(double %val) #1 {
; GFX1200-NEXT: .LBB5_6: ; %atomicrmw.phi
; GFX1200-NEXT: ; %bb.7: ; %atomicrmw.end
; GFX1200-NEXT: s_mov_b32 s0, 32
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_lshrrev_b64 v[1:2], s0, v[3:4]
; GFX1200-NEXT: v_mov_b32_e32 v0, v3
; GFX1200-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
index 583b6fe0a81ca..554f40b5bfdfa 100644
--- a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
+++ b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
@@ -341,7 +341,7 @@ define void @call_with_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_xor_saveexec_b32 s16, -1
; GFX10-NEXT: buffer_store_dword v3, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s16
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: s_getpc_b64 s[16:17]
@@ -357,7 +357,7 @@ define void @call_with_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #0 {
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10-NEXT: buffer_load_dword v3, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s4
; GFX10-NEXT: s_mov_b32 s33, s18
; GFX10-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll
index ecb13739f9378..6b0424e50983e 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16.ll
@@ -4530,7 +4530,7 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_xor_saveexec_b32 s16, -1
; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s16
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: s_getpc_b64 s[16:17]
@@ -4548,7 +4548,7 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) {
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s4
; GFX10-NEXT: s_mov_b32 s33, s18
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -4788,7 +4788,7 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_xor_saveexec_b32 s16, -1
; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s16
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: s_getpc_b64 s[16:17]
@@ -4806,7 +4806,7 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) {
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s4
; GFX10-NEXT: s_mov_b32 s33, s18
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -5058,7 +5058,7 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_xor_saveexec_b32 s16, -1
; GFX10-NEXT: buffer_store_dword v3, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s16
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: s_getpc_b64 s[16:17]
@@ -5078,7 +5078,7 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) {
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10-NEXT: buffer_load_dword v3, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s4
; GFX10-NEXT: s_mov_b32 s33, s18
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -5350,7 +5350,7 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_xor_saveexec_b32 s16, -1
; GFX10-NEXT: buffer_store_dword v3, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s16
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: s_getpc_b64 s[16:17]
@@ -5370,7 +5370,7 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) {
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10-NEXT: buffer_load_dword v3, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s4
; GFX10-NEXT: s_mov_b32 s33, s18
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -5686,7 +5686,7 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_xor_saveexec_b32 s16, -1
; GFX10-NEXT: buffer_store_dword v5, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s16
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: s_getpc_b64 s[16:17]
@@ -5710,7 +5710,7 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) {
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10-NEXT: buffer_load_dword v5, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s4
; GFX10-NEXT: s_mov_b32 s33, s18
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -6127,7 +6127,7 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_xor_saveexec_b32 s16, -1
; GFX10-NEXT: buffer_store_dword v9, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s16
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: s_getpc_b64 s[16:17]
@@ -6159,7 +6159,7 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) {
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10-NEXT: buffer_load_dword v9, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s4
; GFX10-NEXT: s_mov_b32 s33, s18
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -21101,7 +21101,7 @@ define bfloat @v_fdiv_bf16(bfloat %a, bfloat %b) {
; GFX11TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, v2, v0, v2
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_rcp_f32_e32 v3, v1
-; GFX11TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11TRUE16-NEXT: v_fma_f32 v4, -v1, v3, 1.0
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v3, v4, v3
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -21131,7 +21131,7 @@ define bfloat @v_fdiv_bf16(bfloat %a, bfloat %b) {
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
; GFX11FAKE16-NEXT: v_rcp_f32_e32 v3, v2
-; GFX11FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11FAKE16-NEXT: v_fma_f32 v4, -v2, v3, 1.0
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_fmac_f32_e32 v3, v4, v3
@@ -30908,7 +30908,7 @@ define bfloat @v_sqrt_bf16(bfloat %a) {
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_sqrt_f32_e32 v1, v0
-; GFX11TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v1
; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v3, 1, v1
; GFX11TRUE16-NEXT: v_fma_f32 v4, -v2, v1, v0
@@ -30945,7 +30945,7 @@ define bfloat @v_sqrt_bf16(bfloat %a) {
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_sqrt_f32_e32 v1, v0
-; GFX11FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v2, -1, v1
; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v3, 1, v1
; GFX11FAKE16-NEXT: v_fma_f32 v4, -v2, v1, v0
@@ -31440,7 +31440,7 @@ define bfloat @v_log_bf16(bfloat %a) {
; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v1, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11TRUE16-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX11TRUE16-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -31471,7 +31471,7 @@ define bfloat @v_log_bf16(bfloat %a) {
; GFX11FAKE16-NEXT: v_ldexp_f32 v0, v0, v1
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11FAKE16-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX11FAKE16-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -31669,7 +31669,7 @@ define bfloat @v_log2_bf16(bfloat %a) {
; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11TRUE16-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
@@ -31692,7 +31692,7 @@ define bfloat @v_log2_bf16(bfloat %a) {
; GFX11FAKE16-NEXT: v_ldexp_f32 v0, v0, v2
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11FAKE16-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
@@ -31899,7 +31899,7 @@ define bfloat @v_log10_bf16(bfloat %a) {
; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v1, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11TRUE16-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX11TRUE16-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -31930,7 +31930,7 @@ define bfloat @v_log10_bf16(bfloat %a) {
; GFX11FAKE16-NEXT: v_ldexp_f32 v0, v0, v1
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11FAKE16-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX11FAKE16-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -32197,7 +32197,7 @@ define bfloat @v_exp_bf16(bfloat %a) {
; GFX11TRUE16-NEXT: v_add_f32_e32 v0, v0, v2
; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v3
; GFX11TRUE16-NEXT: v_exp_f32_e32 v0, v0
-; GFX11TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v2
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo
@@ -32229,7 +32229,7 @@ define bfloat @v_exp_bf16(bfloat %a) {
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_add_f32_e32 v1, v1, v3
; GFX11FAKE16-NEXT: v_exp_f32_e32 v1, v1
-; GFX11FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11FAKE16-NEXT: v_ldexp_f32 v1, v1, v2
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
@@ -32433,7 +32433,7 @@ define bfloat @v_exp2_bf16(bfloat %a) {
; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_exp_f32_e32 v0, v0
-; GFX11TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v1
; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
@@ -32456,7 +32456,7 @@ define bfloat @v_exp2_bf16(bfloat %a) {
; GFX11FAKE16-NEXT: v_add_f32_e32 v0, v0, v2
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_exp_f32_e32 v0, v0
-; GFX11FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11FAKE16-NEXT: v_ldexp_f32 v0, v0, v1
; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
@@ -32671,7 +32671,7 @@ define bfloat @v_exp10_bf16(bfloat %a) {
; GFX11TRUE16-NEXT: v_add_f32_e32 v0, v0, v2
; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v3
; GFX11TRUE16-NEXT: v_exp_f32_e32 v0, v0
-; GFX11TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v2
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo
@@ -32703,7 +32703,7 @@ define bfloat @v_exp10_bf16(bfloat %a) {
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_add_f32_e32 v1, v1, v3
; GFX11FAKE16-NEXT: v_exp_f32_e32 v1, v1
-; GFX11FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11FAKE16-NEXT: v_ldexp_f32 v1, v1, v2
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
diff --git a/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll b/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
index f6149cf9caf7c..155e54baf15a1 100644
--- a/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
+++ b/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
@@ -54,10 +54,10 @@ define amdgpu_kernel void @uniform_conditional_max_short_forward_branch(ptr addr
; GFX11-NEXT: ; %bb.3: ; %bb
; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: .Lpost_getpc0:
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: s_add_u32 s2, s2, (.LBB0_2-.Lpost_getpc0)&4294967295
; GFX11-NEXT: s_addc_u32 s3, s3, (.LBB0_2-.Lpost_getpc0)>>32
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: s_setpc_b64 s[2:3]
; GFX11-NEXT: .LBB0_1: ; %bb2
; GFX11-NEXT: ;;#ASMSTART
@@ -84,10 +84,10 @@ define amdgpu_kernel void @uniform_conditional_max_short_forward_branch(ptr addr
; GFX12-NEXT: ; %bb.3: ; %bb
; GFX12-NEXT: s_getpc_b64 s[2:3]
; GFX12-NEXT: .Lpost_getpc0:
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_u32 s2, s2, (.LBB0_2-.Lpost_getpc0)&4294967295
; GFX12-NEXT: s_add_co_ci_u32 s3, s3, (.LBB0_2-.Lpost_getpc0)>>32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[2:3]
; GFX12-NEXT: .LBB0_1: ; %bb2
; GFX12-NEXT: ;;#ASMSTART
@@ -160,10 +160,10 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_branch(ptr addrs
; GFX11-NEXT: ; %bb.3: ; %bb0
; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: .Lpost_getpc1:
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: s_add_u32 s2, s2, (.LBB1_2-.Lpost_getpc1)&4294967295
; GFX11-NEXT: s_addc_u32 s3, s3, (.LBB1_2-.Lpost_getpc1)>>32
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: s_setpc_b64 s[2:3]
; GFX11-NEXT: .LBB1_1: ; %bb2
; GFX11-NEXT: ;;#ASMSTART
@@ -190,10 +190,10 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_branch(ptr addrs
; GFX12-NEXT: ; %bb.3: ; %bb0
; GFX12-NEXT: s_getpc_b64 s[2:3]
; GFX12-NEXT: .Lpost_getpc1:
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_u32 s2, s2, (.LBB1_2-.Lpost_getpc1)&4294967295
; GFX12-NEXT: s_add_co_ci_u32 s3, s3, (.LBB1_2-.Lpost_getpc1)>>32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[2:3]
; GFX12-NEXT: .LBB1_1: ; %bb2
; GFX12-NEXT: ;;#ASMSTART
@@ -269,10 +269,10 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_vcnd_branch(ptr
; GFX11-NEXT: ; %bb.3: ; %bb0
; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: .Lpost_getpc2:
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: s_add_u32 s2, s2, (.LBB2_2-.Lpost_getpc2)&4294967295
; GFX11-NEXT: s_addc_u32 s3, s3, (.LBB2_2-.Lpost_getpc2)>>32
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: s_setpc_b64 s[2:3]
; GFX11-NEXT: .LBB2_1: ; %bb2
; GFX11-NEXT: ;;#ASMSTART
@@ -300,10 +300,10 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_vcnd_branch(ptr
; GFX12-NEXT: ; %bb.3: ; %bb0
; GFX12-NEXT: s_getpc_b64 s[2:3]
; GFX12-NEXT: .Lpost_getpc2:
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_u32 s2, s2, (.LBB2_2-.Lpost_getpc2)&4294967295
; GFX12-NEXT: s_add_co_ci_u32 s3, s3, (.LBB2_2-.Lpost_getpc2)>>32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[2:3]
; GFX12-NEXT: .LBB2_1: ; %bb2
; GFX12-NEXT: ;;#ASMSTART
@@ -393,10 +393,10 @@ define amdgpu_kernel void @min_long_forward_vbranch(ptr addrspace(1) %arg) #0 {
; GFX11-NEXT: ; %bb.3: ; %bb
; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: .Lpost_getpc3:
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: s_add_u32 s2, s2, (.LBB3_2-.Lpost_getpc3)&4294967295
; GFX11-NEXT: s_addc_u32 s3, s3, (.LBB3_2-.Lpost_getpc3)>>32
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: s_setpc_b64 s[2:3]
; GFX11-NEXT: .LBB3_1: ; %bb2
; GFX11-NEXT: ;;#ASMSTART
@@ -422,7 +422,7 @@ define amdgpu_kernel void @min_long_forward_vbranch(ptr addrspace(1) %arg) #0 {
; GFX12-NEXT: global_load_b32 v2, v0, s[0:1] scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_add_co_u32 v0, s0, s0, v0
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, s1, 0, s0
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: v_cmpx_ne_u32_e32 0, v2
@@ -430,10 +430,10 @@ define amdgpu_kernel void @min_long_forward_vbranch(ptr addrspace(1) %arg) #0 {
; GFX12-NEXT: ; %bb.3: ; %bb
; GFX12-NEXT: s_getpc_b64 s[2:3]
; GFX12-NEXT: .Lpost_getpc3:
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_u32 s2, s2, (.LBB3_2-.Lpost_getpc3)&4294967295
; GFX12-NEXT: s_add_co_ci_u32 s3, s3, (.LBB3_2-.Lpost_getpc3)>>32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[2:3]
; GFX12-NEXT: .LBB3_1: ; %bb2
; GFX12-NEXT: ;;#ASMSTART
@@ -444,7 +444,7 @@ define amdgpu_kernel void @min_long_forward_vbranch(ptr addrspace(1) %arg) #0 {
; GFX12-NEXT: v_nop_e64
; GFX12-NEXT: ;;#ASMEND
; GFX12-NEXT: .LBB3_2: ; %bb3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: global_store_b32 v[0:1], v2, off scope:SCOPE_SYS
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -513,10 +513,10 @@ define amdgpu_kernel void @long_backward_sbranch(ptr addrspace(1) %arg) #0 {
; GFX11-NEXT: ; in Loop: Header=BB4_1 Depth=1
; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: .Lpost_getpc4:
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: s_add_u32 s2, s2, (.LBB4_1-.Lpost_getpc4)&4294967295
; GFX11-NEXT: s_addc_u32 s3, s3, (.LBB4_1-.Lpost_getpc4)>>32
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: s_setpc_b64 s[2:3]
; GFX11-NEXT: .LBB4_2: ; %bb3
; GFX11-NEXT: s_endpgm
@@ -539,10 +539,10 @@ define amdgpu_kernel void @long_backward_sbranch(ptr addrspace(1) %arg) #0 {
; GFX12-NEXT: ; in Loop: Header=BB4_1 Depth=1
; GFX12-NEXT: s_getpc_b64 s[2:3]
; GFX12-NEXT: .Lpost_getpc4:
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_u32 s2, s2, (.LBB4_1-.Lpost_getpc4)&4294967295
; GFX12-NEXT: s_add_co_ci_u32 s3, s3, (.LBB4_1-.Lpost_getpc4)>>32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[2:3]
; GFX12-NEXT: .LBB4_2: ; %bb3
; GFX12-NEXT: s_endpgm
@@ -654,18 +654,18 @@ define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr add
; GFX11-NEXT: ; %bb.7: ; %bb3
; GFX11-NEXT: s_getpc_b64 s[0:1]
; GFX11-NEXT: .Lpost_getpc6:
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: s_add_u32 s0, s0, (.LBB5_2-.Lpost_getpc6)&4294967295
; GFX11-NEXT: s_addc_u32 s1, s1, (.LBB5_2-.Lpost_getpc6)>>32
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: s_setpc_b64 s[0:1]
; GFX11-NEXT: .LBB5_5: ; %bb3
; GFX11-NEXT: s_getpc_b64 s[0:1]
; GFX11-NEXT: .Lpost_getpc5:
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: s_add_u32 s0, s0, (.LBB5_3-.Lpost_getpc5)&4294967295
; GFX11-NEXT: s_addc_u32 s1, s1, (.LBB5_3-.Lpost_getpc5)>>32
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: s_setpc_b64 s[0:1]
;
; GFX12-LABEL: uniform_unconditional_min_long_forward_branch:
@@ -678,10 +678,10 @@ define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr add
; GFX12-NEXT: ; %bb.7: ; %bb0
; GFX12-NEXT: s_getpc_b64 s[0:1]
; GFX12-NEXT: .Lpost_getpc6:
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_u32 s0, s0, (.LBB5_4-.Lpost_getpc6)&4294967295
; GFX12-NEXT: s_add_co_ci_u32 s1, s1, (.LBB5_4-.Lpost_getpc6)>>32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[0:1]
; GFX12-NEXT: .LBB5_1: ; %Flow
; GFX12-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
@@ -708,18 +708,18 @@ define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr add
; GFX12-NEXT: ; %bb.9: ; %bb3
; GFX12-NEXT: s_getpc_b64 s[0:1]
; GFX12-NEXT: .Lpost_getpc7:
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_u32 s0, s0, (.LBB5_2-.Lpost_getpc7)&4294967295
; GFX12-NEXT: s_add_co_ci_u32 s1, s1, (.LBB5_2-.Lpost_getpc7)>>32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[0:1]
; GFX12-NEXT: .LBB5_5: ; %bb3
; GFX12-NEXT: s_getpc_b64 s[0:1]
; GFX12-NEXT: .Lpost_getpc5:
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_u32 s0, s0, (.LBB5_3-.Lpost_getpc5)&4294967295
; GFX12-NEXT: s_add_co_ci_u32 s1, s1, (.LBB5_3-.Lpost_getpc5)>>32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[0:1]
bb0:
%tmp = icmp ne i32 %arg1, 0
@@ -784,10 +784,10 @@ define amdgpu_kernel void @uniform_unconditional_min_long_backward_branch(ptr ad
; GFX11-NEXT: ; in Loop: Header=BB6_1 Depth=1
; GFX11-NEXT: s_getpc_b64 s[0:1]
; GFX11-NEXT: .Lpost_getpc7:
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: s_add_u32 s0, s0, (.LBB6_1-.Lpost_getpc7)&4294967295
; GFX11-NEXT: s_addc_u32 s1, s1, (.LBB6_1-.Lpost_getpc7)>>32
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: s_setpc_b64 s[0:1]
; GFX11-NEXT: .LBB6_2: ; %DummyReturnBlock
; GFX11-NEXT: s_endpgm
@@ -808,10 +808,10 @@ define amdgpu_kernel void @uniform_unconditional_min_long_backward_branch(ptr ad
; GFX12-NEXT: ; in Loop: Header=BB6_1 Depth=1
; GFX12-NEXT: s_getpc_b64 s[0:1]
; GFX12-NEXT: .Lpost_getpc8:
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_u32 s0, s0, (.LBB6_1-.Lpost_getpc8)&4294967295
; GFX12-NEXT: s_add_co_ci_u32 s1, s1, (.LBB6_1-.Lpost_getpc8)>>32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[0:1]
; GFX12-NEXT: .LBB6_2: ; %DummyReturnBlock
; GFX12-NEXT: s_endpgm
@@ -891,10 +891,10 @@ define amdgpu_kernel void @expand_requires_expand(i32 %cond0) #0 {
; GFX11-NEXT: ; %bb.5: ; %Flow
; GFX11-NEXT: s_getpc_b64 s[0:1]
; GFX11-NEXT: .Lpost_getpc8:
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: s_add_u32 s0, s0, (.LBB7_4-.Lpost_getpc8)&4294967295
; GFX11-NEXT: s_addc_u32 s1, s1, (.LBB7_4-.Lpost_getpc8)>>32
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: s_setpc_b64 s[0:1]
; GFX11-NEXT: .LBB7_3: ; %bb2
; GFX11-NEXT: ;;#ASMSTART
@@ -933,10 +933,10 @@ define amdgpu_kernel void @expand_requires_expand(i32 %cond0) #0 {
; GFX12-NEXT: ; %bb.5: ; %Flow
; GFX12-NEXT: s_getpc_b64 s[0:1]
; GFX12-NEXT: .Lpost_getpc9:
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_u32 s0, s0, (.LBB7_4-.Lpost_getpc9)&4294967295
; GFX12-NEXT: s_add_co_ci_u32 s1, s1, (.LBB7_4-.Lpost_getpc9)>>32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[0:1]
; GFX12-NEXT: .LBB7_3: ; %bb2
; GFX12-NEXT: ;;#ASMSTART
@@ -1152,10 +1152,10 @@ define amdgpu_kernel void @analyze_mask_branch() #0 {
; GFX11-NEXT: ; %bb.6: ; %Flow1
; GFX11-NEXT: s_getpc_b64 s[0:1]
; GFX11-NEXT: .Lpost_getpc9:
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: s_add_u32 s0, s0, (.LBB9_5-.Lpost_getpc9)&4294967295
; GFX11-NEXT: s_addc_u32 s1, s1, (.LBB9_5-.Lpost_getpc9)>>32
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: s_setpc_b64 s[0:1]
; GFX11-NEXT: .LBB9_3: ; %loop.preheader
; GFX11-NEXT: s_and_b64 vcc, exec, 0
@@ -1177,10 +1177,10 @@ define amdgpu_kernel void @analyze_mask_branch() #0 {
; GFX11-NEXT: ; in Loop: Header=BB9_4 Depth=1
; GFX11-NEXT: s_getpc_b64 s[0:1]
; GFX11-NEXT: .Lpost_getpc10:
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: s_add_u32 s0, s0, (.LBB9_4-.Lpost_getpc10)&4294967295
; GFX11-NEXT: s_addc_u32 s1, s1, (.LBB9_4-.Lpost_getpc10)>>32
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: s_setpc_b64 s[0:1]
; GFX11-NEXT: .LBB9_5: ; %UnifiedReturnBlock
; GFX11-NEXT: s_endpgm
@@ -1204,10 +1204,10 @@ define amdgpu_kernel void @analyze_mask_branch() #0 {
; GFX12-NEXT: ; %bb.6: ; %Flow1
; GFX12-NEXT: s_getpc_b64 s[0:1]
; GFX12-NEXT: .Lpost_getpc10:
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_u32 s0, s0, (.LBB9_5-.Lpost_getpc10)&4294967295
; GFX12-NEXT: s_add_co_ci_u32 s1, s1, (.LBB9_5-.Lpost_getpc10)>>32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[0:1]
; GFX12-NEXT: .LBB9_3: ; %loop.preheader
; GFX12-NEXT: s_mov_b32 vcc_lo, 0
@@ -1228,10 +1228,10 @@ define amdgpu_kernel void @analyze_mask_branch() #0 {
; GFX12-NEXT: ; in Loop: Header=BB9_4 Depth=1
; GFX12-NEXT: s_getpc_b64 s[0:1]
; GFX12-NEXT: .Lpost_getpc11:
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_u32 s0, s0, (.LBB9_4-.Lpost_getpc11)&4294967295
; GFX12-NEXT: s_add_co_ci_u32 s1, s1, (.LBB9_4-.Lpost_getpc11)>>32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[0:1]
; GFX12-NEXT: .LBB9_5: ; %UnifiedReturnBlock
; GFX12-NEXT: s_endpgm
@@ -1340,10 +1340,10 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32
; GFX11-NEXT: ; %bb.8: ; %bb
; GFX11-NEXT: s_getpc_b64 s[8:9]
; GFX11-NEXT: .Lpost_getpc11:
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: s_add_u32 s8, s8, (.LBB10_2-.Lpost_getpc11)&4294967295
; GFX11-NEXT: s_addc_u32 s9, s9, (.LBB10_2-.Lpost_getpc11)>>32
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: s_setpc_b64 s[8:9]
; GFX11-NEXT: .LBB10_1: ; %bb13
; GFX11-NEXT: ;;#ASMSTART
@@ -1408,10 +1408,10 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32
; GFX12-NEXT: ; %bb.18: ; %bb
; GFX12-NEXT: s_getpc_b64 s[10:11]
; GFX12-NEXT: .Lpost_getpc17:
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_u32 s10, s10, (.LBB10_4-.Lpost_getpc17)&4294967295
; GFX12-NEXT: s_add_co_ci_u32 s11, s11, (.LBB10_4-.Lpost_getpc17)>>32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[10:11]
; GFX12-NEXT: .LBB10_1: ; %Flow
; GFX12-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s7
@@ -1419,10 +1419,10 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32
; GFX12-NEXT: ; %bb.10: ; %Flow
; GFX12-NEXT: s_getpc_b64 s[8:9]
; GFX12-NEXT: .Lpost_getpc13:
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_u32 s8, s8, (.LBB10_5-.Lpost_getpc13)&4294967295
; GFX12-NEXT: s_add_co_ci_u32 s9, s9, (.LBB10_5-.Lpost_getpc13)>>32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[8:9]
; GFX12-NEXT: .LBB10_2: ; %Flow5
; GFX12-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
@@ -1430,10 +1430,10 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32
; GFX12-NEXT: ; %bb.12: ; %Flow5
; GFX12-NEXT: s_getpc_b64 s[0:1]
; GFX12-NEXT: .Lpost_getpc14:
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_u32 s0, s0, (.LBB10_6-.Lpost_getpc14)&4294967295
; GFX12-NEXT: s_add_co_ci_u32 s1, s1, (.LBB10_6-.Lpost_getpc14)>>32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[0:1]
; GFX12-NEXT: .LBB10_3: ; %bb14
; GFX12-NEXT: s_cmp_lt_i32 s1, 9
@@ -1448,10 +1448,10 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32
; GFX12-NEXT: ; %bb.8: ; %bb14
; GFX12-NEXT: s_getpc_b64 s[0:1]
; GFX12-NEXT: .Lpost_getpc12:
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_u32 s0, s0, (.LBB10_7-.Lpost_getpc12)&4294967295
; GFX12-NEXT: s_add_co_ci_u32 s1, s1, (.LBB10_7-.Lpost_getpc12)>>32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[0:1]
; GFX12-NEXT: .LBB10_4: ; %bb13
; GFX12-NEXT: s_mov_b32 s0, s8
@@ -1465,10 +1465,10 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32
; GFX12-NEXT: ; %bb.14: ; %bb13
; GFX12-NEXT: s_getpc_b64 s[8:9]
; GFX12-NEXT: .Lpost_getpc15:
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_u32 s8, s8, (.LBB10_2-.Lpost_getpc15)&4294967295
; GFX12-NEXT: s_add_co_ci_u32 s9, s9, (.LBB10_2-.Lpost_getpc15)>>32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[8:9]
; GFX12-NEXT: .LBB10_5: ; %bb9
; GFX12-NEXT: s_cmp_lt_i32 s3, 11
@@ -1482,10 +1482,10 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32
; GFX12-NEXT: ; %bb.16: ; %bb9
; GFX12-NEXT: s_getpc_b64 s[8:9]
; GFX12-NEXT: .Lpost_getpc16:
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_u32 s8, s8, (.LBB10_3-.Lpost_getpc16)&4294967295
; GFX12-NEXT: s_add_co_ci_u32 s9, s9, (.LBB10_3-.Lpost_getpc16)>>32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[8:9]
; GFX12-NEXT: .LBB10_6:
; GFX12-NEXT: ; implicit-def: $vgpr0
@@ -1496,7 +1496,7 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32
; GFX12-NEXT: v_mov_b32_e32 v1, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1]
; GFX12-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX12-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
index ca50835018824..efb75e95212b2 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
@@ -379,12 +379,12 @@ define float @buffer_fat_ptr_agent_atomic_fadd_ret_f32__offset__waterfall__amdgp
; GFX12-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: buffer_atomic_add_f32 v5, v4, s[4:7], null offen offset:1024 th:TH_ATOMIC_RETURN
@@ -473,7 +473,7 @@ define float @buffer_fat_ptr_agent_atomic_fadd_ret_f32__offset__waterfall__amdgp
; GFX10-NEXT: s_and_b32 s4, vcc_lo, s4
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: buffer_load_dword v8, v4, s[8:11], 0 offen offset:1024
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB2_1
; GFX10-NEXT: ; %bb.2:
@@ -499,7 +499,7 @@ define float @buffer_fat_ptr_agent_atomic_fadd_ret_f32__offset__waterfall__amdgp
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_atomic_cmpswap v[6:7], v4, s[8:11], 0 offen offset:1024 glc
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB2_4
; GFX10-NEXT: ; %bb.5: ; in Loop: Header=BB2_3 Depth=1
@@ -510,7 +510,7 @@ define float @buffer_fat_ptr_agent_atomic_fadd_ret_f32__offset__waterfall__amdgp
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s5
; GFX10-NEXT: s_cbranch_execnz .LBB2_3
; GFX10-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -1853,7 +1853,7 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
; GFX12-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; GFX12-NEXT: s_cbranch_execnz .LBB8_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2095,7 +2095,7 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[4:5]
; GFX12-NEXT: v_dual_mov_b32 v4, v7 :: v_dual_mov_b32 v5, v8
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; GFX12-NEXT: s_cbranch_execnz .LBB9_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2317,12 +2317,12 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__waterfall__amdg
; GFX12-NEXT: v_readfirstlane_b32 s5, v10
; GFX12-NEXT: v_readfirstlane_b32 s6, v7
; GFX12-NEXT: v_readfirstlane_b32 s7, v8
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[9:10]
; GFX12-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[7:8]
; GFX12-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: buffer_load_b64 v[13:14], v4, s[4:7], null offen offset:2048
@@ -2347,12 +2347,12 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__waterfall__amdg
; GFX12-NEXT: v_readfirstlane_b32 s5, v10
; GFX12-NEXT: v_readfirstlane_b32 s6, v7
; GFX12-NEXT: v_readfirstlane_b32 s7, v8
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[9:10]
; GFX12-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[7:8]
; GFX12-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v4, s[4:7], null offen offset:2048 th:TH_ATOMIC_RETURN
@@ -2365,7 +2365,7 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__waterfall__amdg
; GFX12-NEXT: v_dual_mov_b32 v14, v1 :: v_dual_mov_b32 v13, v0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB10_3
; GFX12-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -2489,7 +2489,7 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__waterfall__amdg
; GFX10-NEXT: s_and_b32 s4, vcc_lo, s4
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: buffer_load_dwordx2 v[13:14], v4, s[8:11], 0 offen offset:2048
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB10_1
; GFX10-NEXT: ; %bb.2:
@@ -2517,7 +2517,7 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__waterfall__amdg
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v4, s[8:11], 0 offen offset:2048 glc
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB10_4
; GFX10-NEXT: ; %bb.5: ; in Loop: Header=BB10_3 Depth=1
@@ -2529,7 +2529,7 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__waterfall__amdg
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s5
; GFX10-NEXT: s_cbranch_execnz .LBB10_3
; GFX10-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -2846,7 +2846,7 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_remot
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
; GFX12-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; GFX12-NEXT: s_cbranch_execnz .LBB11_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3107,7 +3107,7 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
; GFX12-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; GFX12-NEXT: s_cbranch_execnz .LBB12_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3336,14 +3336,14 @@ define half @buffer_fat_ptr_agent_atomic_fadd_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_addk_co_i32 s16, 0x200
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, -4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, s4
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, 3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_lshl_b32 s4, s4, 3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX12-TRUE16-NEXT: buffer_load_b32 v2, v5, s[0:3], null offen
; GFX12-TRUE16-NEXT: s_not_b32 s6, s5
@@ -3357,7 +3357,7 @@ define half @buffer_fat_ptr_agent_atomic_fadd_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add_f16_e32 v1.l, v1.l, v0.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, s4, v1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v1, v2, s6, v1
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
@@ -3367,7 +3367,7 @@ define half @buffer_fat_ptr_agent_atomic_fadd_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v2
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v3
; GFX12-TRUE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB13_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3384,14 +3384,14 @@ define half @buffer_fat_ptr_agent_atomic_fadd_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_addk_co_i32 s16, 0x200
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, -4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v5, s4
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, 3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s4, s4, 3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX12-FAKE16-NEXT: buffer_load_b32 v2, v5, s[0:3], null offen
; GFX12-FAKE16-NEXT: s_not_b32 s6, s5
@@ -3406,7 +3406,7 @@ define half @buffer_fat_ptr_agent_atomic_fadd_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v1, s4, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_and_or_b32 v1, v2, s6, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
@@ -3416,7 +3416,7 @@ define half @buffer_fat_ptr_agent_atomic_fadd_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v2
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, v3
; GFX12-FAKE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB13_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3775,14 +3775,14 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_f16__offset__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_addk_co_i32 s16, 0x200
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, -4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, s4
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, 3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_lshl_b32 s4, s4, 3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX12-TRUE16-NEXT: buffer_load_b32 v2, v3, s[0:3], null offen
; GFX12-TRUE16-NEXT: s_not_b32 s6, s5
@@ -3796,7 +3796,7 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_f16__offset__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add_f16_e32 v1.l, v1.l, v0.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, s4, v1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_and_or_b32 v1, v2, s6, v1
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1
@@ -3806,7 +3806,7 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_f16__offset__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v4
; GFX12-TRUE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB14_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3822,14 +3822,14 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_f16__offset__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_addk_co_i32 s16, 0x200
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, -4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, s4
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, 3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s4, s4, 3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX12-FAKE16-NEXT: buffer_load_b32 v2, v3, s[0:3], null offen
; GFX12-FAKE16-NEXT: s_not_b32 s6, s5
@@ -3844,7 +3844,7 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_f16__offset__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v1, s4, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_and_or_b32 v1, v2, s6, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1
@@ -3854,7 +3854,7 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_f16__offset__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, v4
; GFX12-FAKE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB14_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4214,12 +4214,12 @@ define half @buffer_fat_ptr_agent_atomic_fadd_ret_f16__offset__waterfall__amdgpu
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: buffer_load_b32 v7, v10, s[4:7], null offen
@@ -4248,12 +4248,12 @@ define half @buffer_fat_ptr_agent_atomic_fadd_ret_f16__offset__waterfall__amdgpu
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[8:9], v10, s[4:7], null offen th:TH_ATOMIC_RETURN
@@ -4266,7 +4266,7 @@ define half @buffer_fat_ptr_agent_atomic_fadd_ret_f16__offset__waterfall__amdgpu
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v7, v8
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB15_3
; GFX12-TRUE16-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -4296,12 +4296,12 @@ define half @buffer_fat_ptr_agent_atomic_fadd_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: buffer_load_b32 v7, v10, s[4:7], null offen
@@ -4331,12 +4331,12 @@ define half @buffer_fat_ptr_agent_atomic_fadd_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[8:9], v10, s[4:7], null offen th:TH_ATOMIC_RETURN
@@ -4349,7 +4349,7 @@ define half @buffer_fat_ptr_agent_atomic_fadd_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v7, v8
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB15_3
; GFX12-FAKE16-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -4599,7 +4599,7 @@ define half @buffer_fat_ptr_agent_atomic_fadd_ret_f16__offset__waterfall__amdgpu
; GFX10-NEXT: s_and_b32 s4, vcc_lo, s4
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: buffer_load_dword v7, v10, s[8:11], 0 offen
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB15_1
; GFX10-NEXT: ; %bb.2:
@@ -4628,7 +4628,7 @@ define half @buffer_fat_ptr_agent_atomic_fadd_ret_f16__offset__waterfall__amdgpu
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_atomic_cmpswap v[8:9], v10, s[8:11], 0 offen glc
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB15_4
; GFX10-NEXT: ; %bb.5: ; in Loop: Header=BB15_3 Depth=1
@@ -4639,7 +4639,7 @@ define half @buffer_fat_ptr_agent_atomic_fadd_ret_f16__offset__waterfall__amdgpu
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s5
; GFX10-NEXT: s_cbranch_execnz .LBB15_3
; GFX10-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -5003,14 +5003,14 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__amdgpu_no_fine
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_addk_co_i32 s16, 0x200
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, -4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, s4
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, 3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_lshl_b32 s4, s4, 3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX12-TRUE16-NEXT: buffer_load_b32 v2, v5, s[0:3], null offen
; GFX12-TRUE16-NEXT: s_not_b32 s6, s5
@@ -5031,13 +5031,13 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__amdgpu_no_fine
; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, s4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_and_or_b32 v1, v2, s6, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
@@ -5047,7 +5047,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__amdgpu_no_fine
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v2
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v3
; GFX12-TRUE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB16_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5065,14 +5065,14 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__amdgpu_no_fine
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_addk_co_i32 s16, 0x200
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, -4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, s4
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, 3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s4, s4, 3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX12-FAKE16-NEXT: buffer_load_b32 v1, v4, s[0:3], null offen
; GFX12-FAKE16-NEXT: s_not_b32 s6, s5
@@ -5090,13 +5090,13 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__amdgpu_no_fine
; GFX12-FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-FAKE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, s4, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_and_or_b32 v0, v1, s6, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
@@ -5106,7 +5106,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__amdgpu_no_fine
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v2
; GFX12-FAKE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB16_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5524,14 +5524,14 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_bf16__offset__amdgpu_no_fine
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_addk_co_i32 s16, 0x200
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, -4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, s4
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, 3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_lshl_b32 s4, s4, 3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX12-TRUE16-NEXT: buffer_load_b32 v2, v3, s[0:3], null offen
; GFX12-TRUE16-NEXT: s_not_b32 s6, s5
@@ -5552,13 +5552,13 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_bf16__offset__amdgpu_no_fine
; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v1, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, s4, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_and_or_b32 v1, v2, s6, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1
@@ -5568,7 +5568,7 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_bf16__offset__amdgpu_no_fine
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v4
; GFX12-TRUE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB17_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5585,14 +5585,14 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_bf16__offset__amdgpu_no_fine
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_addk_co_i32 s16, 0x200
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, -4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s4
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, 3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s4, s4, 3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX12-FAKE16-NEXT: buffer_load_b32 v1, v2, s[0:3], null offen
; GFX12-FAKE16-NEXT: s_not_b32 s6, s5
@@ -5610,13 +5610,13 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_bf16__offset__amdgpu_no_fine
; GFX12-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-FAKE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, s4, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_and_or_b32 v0, v1, s6, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
@@ -5626,7 +5626,7 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_bf16__offset__amdgpu_no_fine
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v1
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v4
; GFX12-FAKE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB17_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6045,12 +6045,12 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__waterfall__amd
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: buffer_load_b32 v7, v10, s[4:7], null offen
@@ -6076,7 +6076,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__waterfall__amd
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v12, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v6.h
@@ -6091,12 +6091,12 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__waterfall__amd
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[8:9], v10, s[4:7], null offen th:TH_ATOMIC_RETURN
@@ -6109,7 +6109,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__waterfall__amd
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v7, v8
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB18_3
; GFX12-TRUE16-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -6139,12 +6139,12 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__waterfall__amd
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: buffer_load_b32 v6, v8, s[4:7], null offen
@@ -6169,7 +6169,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__waterfall__amd
; GFX12-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v5, v11, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
@@ -6185,12 +6185,12 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__waterfall__amd
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v8, s[4:7], null offen th:TH_ATOMIC_RETURN
@@ -6203,7 +6203,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__waterfall__amd
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v4
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB18_3
; GFX12-FAKE16-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -6486,7 +6486,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__waterfall__amd
; GFX10-NEXT: s_and_b32 s4, vcc_lo, s4
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: buffer_load_dword v6, v8, s[8:11], 0 offen
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB18_1
; GFX10-NEXT: ; %bb.2:
@@ -6521,7 +6521,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__waterfall__amd
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_atomic_cmpswap v[4:5], v8, s[8:11], 0 offen glc
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB18_4
; GFX10-NEXT: ; %bb.5: ; in Loop: Header=BB18_3 Depth=1
@@ -6532,7 +6532,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__waterfall__amd
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s5
; GFX10-NEXT: s_cbranch_execnz .LBB18_3
; GFX10-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -7389,12 +7389,12 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fadd_ret_v2f16__offset__waterfall
; GFX12-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: buffer_atomic_pk_add_f16 v5, v4, s[4:7], null offen offset:1024 th:TH_ATOMIC_RETURN
@@ -7517,7 +7517,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fadd_ret_v2f16__offset__waterfall
; GFX10-NEXT: s_and_b32 s4, vcc_lo, s4
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: buffer_load_dword v8, v4, s[8:11], 0 offen offset:1024
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB21_1
; GFX10-NEXT: ; %bb.2:
@@ -7543,7 +7543,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fadd_ret_v2f16__offset__waterfall
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_atomic_cmpswap v[6:7], v4, s[8:11], 0 offen offset:1024 glc
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB21_4
; GFX10-NEXT: ; %bb.5: ; in Loop: Header=BB21_3 Depth=1
@@ -7554,7 +7554,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fadd_ret_v2f16__offset__waterfall
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s5
; GFX10-NEXT: s_cbranch_execnz .LBB21_3
; GFX10-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -9746,12 +9746,12 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__waterf
; GFX12-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: buffer_atomic_pk_add_bf16 v5, v4, s[4:7], null offen offset:1024 th:TH_ATOMIC_RETURN
@@ -10026,7 +10026,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__waterf
; GFX10-NEXT: s_and_b32 s4, vcc_lo, s4
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: buffer_load_dword v7, v4, s[8:11], 0 offen offset:1024
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB28_1
; GFX10-NEXT: ; %bb.2:
@@ -10068,7 +10068,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__waterf
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_atomic_cmpswap v[5:6], v4, s[8:11], 0 offen offset:1024 glc
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB28_4
; GFX10-NEXT: ; %bb.5: ; in Loop: Header=BB28_3 Depth=1
@@ -10079,7 +10079,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__waterf
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s5
; GFX10-NEXT: s_cbranch_execnz .LBB28_3
; GFX10-NEXT: ; %bb.6: ; %atomicrmw.end
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
index 1a4140cd0912b..f3bf8c664f7a6 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
@@ -370,12 +370,12 @@ define float @buffer_fat_ptr_agent_atomic_fmax_ret_f32__offset__waterfall__amdgp
; GFX12-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: buffer_atomic_max_num_f32 v5, v4, s[4:7], null offen offset:1024 th:TH_ATOMIC_RETURN
@@ -498,7 +498,7 @@ define float @buffer_fat_ptr_agent_atomic_fmax_ret_f32__offset__waterfall__amdgp
; GFX10-NEXT: buffer_atomic_fmax v5, v4, s[8:11], 0 offen offset:1024 glc
; GFX10-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX10-NEXT: ; implicit-def: $vgpr4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB2_1
; GFX10-NEXT: ; %bb.2:
@@ -1196,7 +1196,7 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; GFX12-NEXT: s_cbranch_execnz .LBB5_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1378,7 +1378,7 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
; GFX12-NEXT: v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; GFX12-NEXT: s_cbranch_execnz .LBB6_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1547,12 +1547,12 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__waterfall__amdg
; GFX12-NEXT: v_readfirstlane_b32 s5, v10
; GFX12-NEXT: v_readfirstlane_b32 s6, v7
; GFX12-NEXT: v_readfirstlane_b32 s7, v8
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[9:10]
; GFX12-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[7:8]
; GFX12-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: buffer_load_b64 v[13:14], v4, s[4:7], null offen offset:2048
@@ -1579,12 +1579,12 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__waterfall__amdg
; GFX12-NEXT: v_readfirstlane_b32 s5, v10
; GFX12-NEXT: v_readfirstlane_b32 s6, v7
; GFX12-NEXT: v_readfirstlane_b32 s7, v8
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[9:10]
; GFX12-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[7:8]
; GFX12-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v4, s[4:7], null offen offset:2048 th:TH_ATOMIC_RETURN
@@ -1597,7 +1597,7 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__waterfall__amdg
; GFX12-NEXT: v_dual_mov_b32 v14, v1 :: v_dual_mov_b32 v13, v0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB7_3
; GFX12-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -1722,7 +1722,7 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__waterfall__amdg
; GFX10-NEXT: buffer_atomic_fmax_x2 v[5:6], v4, s[8:11], 0 offen offset:2048 glc
; GFX10-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX10-NEXT: ; implicit-def: $vgpr4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB7_1
; GFX10-NEXT: ; %bb.2:
@@ -1980,7 +1980,7 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__amdgpu_no_remot
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; GFX12-NEXT: s_cbranch_execnz .LBB8_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2246,7 +2246,7 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; GFX12-NEXT: s_cbranch_execnz .LBB9_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2414,14 +2414,14 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_addk_co_i32 s16, 0x200
; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, -4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, s4
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, 3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_lshl_b32 s4, s4, 3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX12-TRUE16-NEXT: buffer_load_b32 v2, v5, s[0:3], null offen
; GFX12-TRUE16-NEXT: s_not_b32 s6, s5
@@ -2437,7 +2437,7 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v0.h, v0.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, s4, v1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_and_or_b32 v1, v2, s6, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
@@ -2447,7 +2447,7 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v2
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v3
; GFX12-TRUE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB10_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2465,14 +2465,14 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_addk_co_i32 s16, 0x200
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v0, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, -4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, s4
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, 3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s4, s4, 3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX12-FAKE16-NEXT: buffer_load_b32 v1, v4, s[0:3], null offen
; GFX12-FAKE16-NEXT: s_not_b32 s6, s5
@@ -2488,7 +2488,7 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, s4, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v0, v1, s6, v0
; GFX12-FAKE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
@@ -2498,7 +2498,7 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v2
; GFX12-FAKE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB10_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2874,14 +2874,14 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_f16__offset__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_addk_co_i32 s16, 0x200
; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, -4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, s4
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, 3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_lshl_b32 s4, s4, 3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX12-TRUE16-NEXT: buffer_load_b32 v2, v3, s[0:3], null offen
; GFX12-TRUE16-NEXT: s_not_b32 s6, s5
@@ -2897,7 +2897,7 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_f16__offset__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v0.h, v0.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, s4, v1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_and_or_b32 v1, v2, s6, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1
@@ -2907,7 +2907,7 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_f16__offset__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v4
; GFX12-TRUE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB11_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2924,14 +2924,14 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_f16__offset__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_addk_co_i32 s16, 0x200
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v0, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, -4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s4
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, 3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s4, s4, 3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX12-FAKE16-NEXT: buffer_load_b32 v1, v2, s[0:3], null offen
; GFX12-FAKE16-NEXT: s_not_b32 s6, s5
@@ -2947,7 +2947,7 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_f16__offset__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, s4, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v0, v1, s6, v0
; GFX12-FAKE16-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
@@ -2957,7 +2957,7 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_f16__offset__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v1
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v4
; GFX12-FAKE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB11_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3333,12 +3333,12 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: buffer_load_b32 v6, v10, s[4:7], null offen
@@ -3370,12 +3370,12 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[7:8], v10, s[4:7], null offen th:TH_ATOMIC_RETURN
@@ -3388,7 +3388,7 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v7
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB12_3
; GFX12-TRUE16-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -3418,12 +3418,12 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: buffer_load_b32 v6, v8, s[4:7], null offen
@@ -3456,12 +3456,12 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v8, s[4:7], null offen th:TH_ATOMIC_RETURN
@@ -3474,7 +3474,7 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v4
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB12_3
; GFX12-FAKE16-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -3732,7 +3732,7 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX10-NEXT: s_and_b32 s4, vcc_lo, s4
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: buffer_load_dword v6, v8, s[8:11], 0 offen
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB12_1
; GFX10-NEXT: ; %bb.2:
@@ -3763,7 +3763,7 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_atomic_cmpswap v[4:5], v8, s[8:11], 0 offen glc
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB12_4
; GFX10-NEXT: ; %bb.5: ; in Loop: Header=BB12_3 Depth=1
@@ -3774,7 +3774,7 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s5
; GFX10-NEXT: s_cbranch_execnz .LBB12_3
; GFX10-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -4144,14 +4144,14 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__amdgpu_no_fine
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_addk_co_i32 s16, 0x200
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, -4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, s4
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, 3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_lshl_b32 s4, s4, 3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX12-TRUE16-NEXT: buffer_load_b32 v2, v5, s[0:3], null offen
; GFX12-TRUE16-NEXT: s_not_b32 s6, s5
@@ -4172,13 +4172,13 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__amdgpu_no_fine
; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, s4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_and_or_b32 v1, v2, s6, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
@@ -4188,7 +4188,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__amdgpu_no_fine
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v2
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v3
; GFX12-TRUE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB13_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4206,14 +4206,14 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__amdgpu_no_fine
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_addk_co_i32 s16, 0x200
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, -4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, s4
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, 3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s4, s4, 3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX12-FAKE16-NEXT: buffer_load_b32 v1, v4, s[0:3], null offen
; GFX12-FAKE16-NEXT: s_not_b32 s6, s5
@@ -4231,13 +4231,13 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__amdgpu_no_fine
; GFX12-FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-FAKE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, s4, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_and_or_b32 v0, v1, s6, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
@@ -4247,7 +4247,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__amdgpu_no_fine
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v2
; GFX12-FAKE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB13_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4667,14 +4667,14 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_bf16__offset__amdgpu_no_fine
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_addk_co_i32 s16, 0x200
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, -4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, s4
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, 3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_lshl_b32 s4, s4, 3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX12-TRUE16-NEXT: buffer_load_b32 v2, v3, s[0:3], null offen
; GFX12-TRUE16-NEXT: s_not_b32 s6, s5
@@ -4695,13 +4695,13 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_bf16__offset__amdgpu_no_fine
; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v1, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, s4, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_and_or_b32 v1, v2, s6, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1
@@ -4711,7 +4711,7 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_bf16__offset__amdgpu_no_fine
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v4
; GFX12-TRUE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB14_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4728,14 +4728,14 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_bf16__offset__amdgpu_no_fine
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_addk_co_i32 s16, 0x200
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, -4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s4
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, 3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s4, s4, 3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX12-FAKE16-NEXT: buffer_load_b32 v1, v2, s[0:3], null offen
; GFX12-FAKE16-NEXT: s_not_b32 s6, s5
@@ -4753,13 +4753,13 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_bf16__offset__amdgpu_no_fine
; GFX12-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-FAKE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, s4, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_and_or_b32 v0, v1, s6, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
@@ -4769,7 +4769,7 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_bf16__offset__amdgpu_no_fine
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v1
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v4
; GFX12-FAKE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB14_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5190,12 +5190,12 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__waterfall__amd
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: buffer_load_b32 v7, v10, s[4:7], null offen
@@ -5221,7 +5221,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__waterfall__amd
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v12, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v6.h
@@ -5236,12 +5236,12 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__waterfall__amd
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[8:9], v10, s[4:7], null offen th:TH_ATOMIC_RETURN
@@ -5254,7 +5254,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__waterfall__amd
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v7, v8
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB15_3
; GFX12-TRUE16-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -5284,12 +5284,12 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__waterfall__amd
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: buffer_load_b32 v6, v8, s[4:7], null offen
@@ -5314,7 +5314,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__waterfall__amd
; GFX12-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v5, v11, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
@@ -5330,12 +5330,12 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__waterfall__amd
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v8, s[4:7], null offen th:TH_ATOMIC_RETURN
@@ -5348,7 +5348,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__waterfall__amd
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v4
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB15_3
; GFX12-FAKE16-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -5631,7 +5631,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__waterfall__amd
; GFX10-NEXT: s_and_b32 s4, vcc_lo, s4
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: buffer_load_dword v6, v8, s[8:11], 0 offen
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB15_1
; GFX10-NEXT: ; %bb.2:
@@ -5666,7 +5666,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__waterfall__amd
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_atomic_cmpswap v[4:5], v8, s[8:11], 0 offen glc
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB15_4
; GFX10-NEXT: ; %bb.5: ; in Loop: Header=BB15_3 Depth=1
@@ -5677,7 +5677,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__waterfall__amd
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s5
; GFX10-NEXT: s_cbranch_execnz .LBB15_3
; GFX10-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -6084,7 +6084,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__amdgpu_no
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v5
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; GFX12-NEXT: s_cbranch_execnz .LBB16_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6394,7 +6394,7 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_v2f16__offset__amdgpu_no_fin
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v1
; GFX12-NEXT: v_mov_b32_e32 v1, v4
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; GFX12-NEXT: s_cbranch_execnz .LBB17_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6684,12 +6684,12 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__waterfall
; GFX12-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: buffer_load_b32 v7, v4, s[4:7], null offen offset:1024
@@ -6716,12 +6716,12 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__waterfall
; GFX12-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: buffer_atomic_cmpswap_b32 v[5:6], v4, s[4:7], null offen offset:1024 th:TH_ATOMIC_RETURN
@@ -6734,7 +6734,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__waterfall
; GFX12-NEXT: v_mov_b32_e32 v7, v5
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB18_3
; GFX12-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -6883,7 +6883,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__waterfall
; GFX10-NEXT: s_and_b32 s4, vcc_lo, s4
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: buffer_load_dword v7, v4, s[8:11], 0 offen offset:1024
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB18_1
; GFX10-NEXT: ; %bb.2:
@@ -6911,7 +6911,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__waterfall
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_atomic_cmpswap v[5:6], v4, s[8:11], 0 offen offset:1024 glc
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB18_4
; GFX10-NEXT: ; %bb.5: ; in Loop: Header=BB18_3 Depth=1
@@ -6922,7 +6922,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__waterfall
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s5
; GFX10-NEXT: s_cbranch_execnz .LBB18_3
; GFX10-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -7305,10 +7305,10 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__amdgpu
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
@@ -7318,7 +7318,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__amdgpu
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v6
; GFX12-TRUE16-NEXT: s_or_b32 s4, vcc_lo, s4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB19_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7352,7 +7352,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__amdgpu
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v7, v9 :: v_dual_lshlrev_b32 v0, 16, v6
; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v0, v0, v2
@@ -7361,7 +7361,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__amdgpu
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v0, v0
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v5, v8, s4
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v1, v0, 0x7060302
@@ -7372,7 +7372,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__amdgpu
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v6
; GFX12-FAKE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB19_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7819,11 +7819,11 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_v2bf16__offset__amdgpu_no_fi
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v6.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -7834,7 +7834,7 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_v2bf16__offset__amdgpu_no_fi
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v1
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, v5
; GFX12-TRUE16-NEXT: s_or_b32 s4, vcc_lo, s4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB20_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7870,10 +7870,10 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_v2bf16__offset__amdgpu_no_fi
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v6, v8, s4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x7060302
@@ -7884,7 +7884,7 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_v2bf16__offset__amdgpu_no_fi
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v1
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v5
; GFX12-FAKE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB20_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8304,12 +8304,12 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__waterf
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: buffer_load_b32 v7, v4, s[4:7], null offen offset:1024
@@ -8338,11 +8338,11 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__waterf
; GFX12-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v6
; GFX12-TRUE16-NEXT: v_add3_u32 v11, v11, v6, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v10, v10, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v10, v12, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v13, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -8354,12 +8354,12 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__waterf
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[5:6], v4, s[4:7], null offen offset:1024 th:TH_ATOMIC_RETURN
@@ -8372,7 +8372,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__waterf
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v7, v5
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB21_3
; GFX12-TRUE16-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -8394,12 +8394,12 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__waterf
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: buffer_load_b32 v7, v4, s[4:7], null offen offset:1024
@@ -8428,11 +8428,11 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__waterf
; GFX12-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v6
; GFX12-FAKE16-NEXT: v_add3_u32 v11, v11, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v10, v10, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v10, v12, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v11, v13, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v6, v6, v5, 0x7060302
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -8444,12 +8444,12 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__waterf
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[5:6], v4, s[4:7], null offen offset:1024 th:TH_ATOMIC_RETURN
@@ -8462,7 +8462,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__waterf
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v7, v5
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB21_3
; GFX12-FAKE16-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -8730,7 +8730,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__waterf
; GFX10-NEXT: s_and_b32 s4, vcc_lo, s4
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: buffer_load_dword v7, v4, s[8:11], 0 offen offset:1024
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB21_1
; GFX10-NEXT: ; %bb.2:
@@ -8772,7 +8772,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__waterf
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_atomic_cmpswap v[5:6], v4, s[8:11], 0 offen offset:1024 glc
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB21_4
; GFX10-NEXT: ; %bb.5: ; in Loop: Header=BB21_3 Depth=1
@@ -8783,7 +8783,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__waterf
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s5
; GFX10-NEXT: s_cbranch_execnz .LBB21_3
; GFX10-NEXT: ; %bb.6: ; %atomicrmw.end
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
index 671f42c6efd27..d1dc76f321375 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
@@ -370,12 +370,12 @@ define float @buffer_fat_ptr_agent_atomic_fmin_ret_f32__offset__waterfall__amdgp
; GFX12-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: buffer_atomic_min_num_f32 v5, v4, s[4:7], null offen offset:1024 th:TH_ATOMIC_RETURN
@@ -498,7 +498,7 @@ define float @buffer_fat_ptr_agent_atomic_fmin_ret_f32__offset__waterfall__amdgp
; GFX10-NEXT: buffer_atomic_fmin v5, v4, s[8:11], 0 offen offset:1024 glc
; GFX10-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX10-NEXT: ; implicit-def: $vgpr4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB2_1
; GFX10-NEXT: ; %bb.2:
@@ -1196,7 +1196,7 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; GFX12-NEXT: s_cbranch_execnz .LBB5_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1378,7 +1378,7 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
; GFX12-NEXT: v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; GFX12-NEXT: s_cbranch_execnz .LBB6_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1547,12 +1547,12 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__waterfall__amdg
; GFX12-NEXT: v_readfirstlane_b32 s5, v10
; GFX12-NEXT: v_readfirstlane_b32 s6, v7
; GFX12-NEXT: v_readfirstlane_b32 s7, v8
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[9:10]
; GFX12-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[7:8]
; GFX12-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: buffer_load_b64 v[13:14], v4, s[4:7], null offen offset:2048
@@ -1579,12 +1579,12 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__waterfall__amdg
; GFX12-NEXT: v_readfirstlane_b32 s5, v10
; GFX12-NEXT: v_readfirstlane_b32 s6, v7
; GFX12-NEXT: v_readfirstlane_b32 s7, v8
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[9:10]
; GFX12-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[7:8]
; GFX12-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v4, s[4:7], null offen offset:2048 th:TH_ATOMIC_RETURN
@@ -1597,7 +1597,7 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__waterfall__amdg
; GFX12-NEXT: v_dual_mov_b32 v14, v1 :: v_dual_mov_b32 v13, v0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB7_3
; GFX12-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -1722,7 +1722,7 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__waterfall__amdg
; GFX10-NEXT: buffer_atomic_fmin_x2 v[5:6], v4, s[8:11], 0 offen offset:2048 glc
; GFX10-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX10-NEXT: ; implicit-def: $vgpr4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB7_1
; GFX10-NEXT: ; %bb.2:
@@ -1980,7 +1980,7 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__amdgpu_no_remot
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; GFX12-NEXT: s_cbranch_execnz .LBB8_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2246,7 +2246,7 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__amdgpu_no_fine_
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; GFX12-NEXT: s_cbranch_execnz .LBB9_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2414,14 +2414,14 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_addk_co_i32 s16, 0x200
; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, -4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, s4
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, 3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_lshl_b32 s4, s4, 3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX12-TRUE16-NEXT: buffer_load_b32 v2, v5, s[0:3], null offen
; GFX12-TRUE16-NEXT: s_not_b32 s6, s5
@@ -2437,7 +2437,7 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v0.h, v0.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, s4, v1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_and_or_b32 v1, v2, s6, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
@@ -2447,7 +2447,7 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v2
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v3
; GFX12-TRUE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB10_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2465,14 +2465,14 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_addk_co_i32 s16, 0x200
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v5, v0, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, -4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, s4
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, 3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s4, s4, 3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX12-FAKE16-NEXT: buffer_load_b32 v1, v4, s[0:3], null offen
; GFX12-FAKE16-NEXT: s_not_b32 s6, s5
@@ -2488,7 +2488,7 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, s4, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v0, v1, s6, v0
; GFX12-FAKE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
@@ -2498,7 +2498,7 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v2
; GFX12-FAKE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB10_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2874,14 +2874,14 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_f16__offset__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_addk_co_i32 s16, 0x200
; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, -4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, s4
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, 3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_lshl_b32 s4, s4, 3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX12-TRUE16-NEXT: buffer_load_b32 v2, v3, s[0:3], null offen
; GFX12-TRUE16-NEXT: s_not_b32 s6, s5
@@ -2897,7 +2897,7 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_f16__offset__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v1.l, v0.h, v0.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, s4, v1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_and_or_b32 v1, v2, s6, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1
@@ -2907,7 +2907,7 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_f16__offset__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v4
; GFX12-TRUE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB11_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2924,14 +2924,14 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_f16__offset__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_addk_co_i32 s16, 0x200
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v3, v0, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, -4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s4
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, 3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s4, s4, 3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX12-FAKE16-NEXT: buffer_load_b32 v1, v2, s[0:3], null offen
; GFX12-FAKE16-NEXT: s_not_b32 s6, s5
@@ -2947,7 +2947,7 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_f16__offset__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, s4, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_and_or_b32 v0, v1, s6, v0
; GFX12-FAKE16-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
@@ -2957,7 +2957,7 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_f16__offset__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v1
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v4
; GFX12-FAKE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB11_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3333,12 +3333,12 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: buffer_load_b32 v6, v10, s[4:7], null offen
@@ -3370,12 +3370,12 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[7:8], v10, s[4:7], null offen th:TH_ATOMIC_RETURN
@@ -3388,7 +3388,7 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v7
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB12_3
; GFX12-TRUE16-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -3418,12 +3418,12 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: buffer_load_b32 v6, v8, s[4:7], null offen
@@ -3456,12 +3456,12 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v8, s[4:7], null offen th:TH_ATOMIC_RETURN
@@ -3474,7 +3474,7 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v4
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB12_3
; GFX12-FAKE16-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -3732,7 +3732,7 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX10-NEXT: s_and_b32 s4, vcc_lo, s4
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: buffer_load_dword v6, v8, s[8:11], 0 offen
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB12_1
; GFX10-NEXT: ; %bb.2:
@@ -3763,7 +3763,7 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_atomic_cmpswap v[4:5], v8, s[8:11], 0 offen glc
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB12_4
; GFX10-NEXT: ; %bb.5: ; in Loop: Header=BB12_3 Depth=1
@@ -3774,7 +3774,7 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s5
; GFX10-NEXT: s_cbranch_execnz .LBB12_3
; GFX10-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -4144,14 +4144,14 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__amdgpu_no_fine
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_addk_co_i32 s16, 0x200
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, -4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, s4
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, 3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_lshl_b32 s4, s4, 3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX12-TRUE16-NEXT: buffer_load_b32 v2, v5, s[0:3], null offen
; GFX12-TRUE16-NEXT: s_not_b32 s6, s5
@@ -4172,13 +4172,13 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__amdgpu_no_fine
; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, s4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_and_or_b32 v1, v2, s6, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
@@ -4188,7 +4188,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__amdgpu_no_fine
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v2
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v3
; GFX12-TRUE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB13_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4206,14 +4206,14 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__amdgpu_no_fine
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_addk_co_i32 s16, 0x200
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, -4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, s4
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, 3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s4, s4, 3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX12-FAKE16-NEXT: buffer_load_b32 v1, v4, s[0:3], null offen
; GFX12-FAKE16-NEXT: s_not_b32 s6, s5
@@ -4231,13 +4231,13 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__amdgpu_no_fine
; GFX12-FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-FAKE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, s4, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_and_or_b32 v0, v1, s6, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
@@ -4247,7 +4247,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__amdgpu_no_fine
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v2
; GFX12-FAKE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB13_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4667,14 +4667,14 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_bf16__offset__amdgpu_no_fine
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_addk_co_i32 s16, 0x200
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, -4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, s4
; GFX12-TRUE16-NEXT: s_and_b32 s4, s16, 3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_lshl_b32 s4, s4, 3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX12-TRUE16-NEXT: buffer_load_b32 v2, v3, s[0:3], null offen
; GFX12-TRUE16-NEXT: s_not_b32 s6, s5
@@ -4695,13 +4695,13 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_bf16__offset__amdgpu_no_fine
; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v1, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, s4, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_and_or_b32 v1, v2, s6, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1
@@ -4711,7 +4711,7 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_bf16__offset__amdgpu_no_fine
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v4
; GFX12-TRUE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB14_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4728,14 +4728,14 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_bf16__offset__amdgpu_no_fine
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_addk_co_i32 s16, 0x200
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, -4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s4
; GFX12-FAKE16-NEXT: s_and_b32 s4, s16, 3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s4, s4, 3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_lshl_b32 s5, 0xffff, s4
; GFX12-FAKE16-NEXT: buffer_load_b32 v1, v2, s[0:3], null offen
; GFX12-FAKE16-NEXT: s_not_b32 s6, s5
@@ -4753,13 +4753,13 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_bf16__offset__amdgpu_no_fine
; GFX12-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-FAKE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, s4, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_and_or_b32 v0, v1, s6, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
@@ -4769,7 +4769,7 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_bf16__offset__amdgpu_no_fine
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v1
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v4
; GFX12-FAKE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB14_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5190,12 +5190,12 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__waterfall__amd
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: buffer_load_b32 v7, v10, s[4:7], null offen
@@ -5221,7 +5221,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__waterfall__amd
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v12, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v6.h
@@ -5236,12 +5236,12 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__waterfall__amd
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[8:9], v10, s[4:7], null offen th:TH_ATOMIC_RETURN
@@ -5254,7 +5254,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__waterfall__amd
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v7, v8
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB15_3
; GFX12-TRUE16-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -5284,12 +5284,12 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__waterfall__amd
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: buffer_load_b32 v6, v8, s[4:7], null offen
@@ -5314,7 +5314,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__waterfall__amd
; GFX12-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v5, v11, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
@@ -5330,12 +5330,12 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__waterfall__amd
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[4:5], v8, s[4:7], null offen th:TH_ATOMIC_RETURN
@@ -5348,7 +5348,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__waterfall__amd
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v4
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB15_3
; GFX12-FAKE16-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -5631,7 +5631,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__waterfall__amd
; GFX10-NEXT: s_and_b32 s4, vcc_lo, s4
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: buffer_load_dword v6, v8, s[8:11], 0 offen
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB15_1
; GFX10-NEXT: ; %bb.2:
@@ -5666,7 +5666,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__waterfall__amd
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_atomic_cmpswap v[4:5], v8, s[8:11], 0 offen glc
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB15_4
; GFX10-NEXT: ; %bb.5: ; in Loop: Header=BB15_3 Depth=1
@@ -5677,7 +5677,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__waterfall__amd
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s5
; GFX10-NEXT: s_cbranch_execnz .LBB15_3
; GFX10-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -6084,7 +6084,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__amdgpu_no
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v5
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; GFX12-NEXT: s_cbranch_execnz .LBB16_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6394,7 +6394,7 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_v2f16__offset__amdgpu_no_fin
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v1
; GFX12-NEXT: v_mov_b32_e32 v1, v4
; GFX12-NEXT: s_or_b32 s4, vcc_lo, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; GFX12-NEXT: s_cbranch_execnz .LBB17_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6684,12 +6684,12 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__waterfall
; GFX12-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: buffer_load_b32 v7, v4, s[4:7], null offen offset:1024
@@ -6716,12 +6716,12 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__waterfall
; GFX12-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: buffer_atomic_cmpswap_b32 v[5:6], v4, s[4:7], null offen offset:1024 th:TH_ATOMIC_RETURN
@@ -6734,7 +6734,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__waterfall
; GFX12-NEXT: v_mov_b32_e32 v7, v5
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB18_3
; GFX12-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -6883,7 +6883,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__waterfall
; GFX10-NEXT: s_and_b32 s4, vcc_lo, s4
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: buffer_load_dword v7, v4, s[8:11], 0 offen offset:1024
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB18_1
; GFX10-NEXT: ; %bb.2:
@@ -6911,7 +6911,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__waterfall
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_atomic_cmpswap v[5:6], v4, s[8:11], 0 offen offset:1024 glc
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB18_4
; GFX10-NEXT: ; %bb.5: ; in Loop: Header=BB18_3 Depth=1
@@ -6922,7 +6922,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__waterfall
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s5
; GFX10-NEXT: s_cbranch_execnz .LBB18_3
; GFX10-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -7305,10 +7305,10 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__amdgpu
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
@@ -7318,7 +7318,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__amdgpu
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v6
; GFX12-TRUE16-NEXT: s_or_b32 s4, vcc_lo, s4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB19_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7352,7 +7352,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__amdgpu
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v7, v9 :: v_dual_lshlrev_b32 v0, 16, v6
; GFX12-FAKE16-NEXT: v_min_num_f32_e32 v0, v0, v2
@@ -7361,7 +7361,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__amdgpu
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v0, v0
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v5, v8, s4
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v1, v0, 0x7060302
@@ -7372,7 +7372,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__amdgpu
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v6
; GFX12-FAKE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB19_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7819,11 +7819,11 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_v2bf16__offset__amdgpu_no_fi
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v6.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -7834,7 +7834,7 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_v2bf16__offset__amdgpu_no_fi
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v1
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, v5
; GFX12-TRUE16-NEXT: s_or_b32 s4, vcc_lo, s4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB20_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7870,10 +7870,10 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_v2bf16__offset__amdgpu_no_fi
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s4, v0, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v6, v8, s4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x7060302
@@ -7884,7 +7884,7 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_v2bf16__offset__amdgpu_no_fi
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v1
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v5
; GFX12-FAKE16-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s5
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB20_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8304,12 +8304,12 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__waterf
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: buffer_load_b32 v7, v4, s[4:7], null offen offset:1024
@@ -8338,11 +8338,11 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__waterf
; GFX12-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v6
; GFX12-TRUE16-NEXT: v_add3_u32 v11, v11, v6, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v10, v10, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v10, v12, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v13, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -8354,12 +8354,12 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__waterf
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[5:6], v4, s[4:7], null offen offset:1024 th:TH_ATOMIC_RETURN
@@ -8372,7 +8372,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__waterf
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v7, v5
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB21_3
; GFX12-TRUE16-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -8394,12 +8394,12 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__waterf
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: buffer_load_b32 v7, v4, s[4:7], null offen offset:1024
@@ -8428,11 +8428,11 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__waterf
; GFX12-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v6
; GFX12-FAKE16-NEXT: v_add3_u32 v11, v11, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v10, v10, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v10, v12, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v11, v13, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v6, v6, v5, 0x7060302
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -8444,12 +8444,12 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__waterf
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
; GFX12-FAKE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_saveexec_b32 s0, s0
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[5:6], v4, s[4:7], null offen offset:1024 th:TH_ATOMIC_RETURN
@@ -8462,7 +8462,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__waterf
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v7, v5
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB21_3
; GFX12-FAKE16-NEXT: ; %bb.6: ; %atomicrmw.end
@@ -8730,7 +8730,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__waterf
; GFX10-NEXT: s_and_b32 s4, vcc_lo, s4
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: buffer_load_dword v7, v4, s[8:11], 0 offen offset:1024
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB21_1
; GFX10-NEXT: ; %bb.2:
@@ -8772,7 +8772,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__waterf
; GFX10-NEXT: s_and_saveexec_b32 s4, s4
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_atomic_cmpswap v[5:6], v4, s[8:11], 0 offen offset:1024 glc
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB21_4
; GFX10-NEXT: ; %bb.5: ; in Loop: Header=BB21_3 Depth=1
@@ -8783,7 +8783,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__waterf
; GFX10-NEXT: buffer_gl1_inv
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: s_or_b32 s5, vcc_lo, s5
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s5
; GFX10-NEXT: s_cbranch_execnz .LBB21_3
; GFX10-NEXT: ; %bb.6: ; %atomicrmw.end
diff --git a/llvm/test/CodeGen/AMDGPU/carryout-selection.ll b/llvm/test/CodeGen/AMDGPU/carryout-selection.ll
index a8ef781b62a42..163d7ff9c61fc 100644
--- a/llvm/test/CodeGen/AMDGPU/carryout-selection.ll
+++ b/llvm/test/CodeGen/AMDGPU/carryout-selection.ll
@@ -2906,7 +2906,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fmamk_f32 v0, v1, 0x4f800000, v0
; GFX11-NEXT: v_rcp_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
@@ -3024,7 +3024,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GFX11-NEXT: s_mov_b32 s9, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
diff --git a/llvm/test/CodeGen/AMDGPU/cc-entry.ll b/llvm/test/CodeGen/AMDGPU/cc-entry.ll
index d807f321c4009..6a857ba8e0c2c 100644
--- a/llvm/test/CodeGen/AMDGPU/cc-entry.ll
+++ b/llvm/test/CodeGen/AMDGPU/cc-entry.ll
@@ -30,16 +30,16 @@ define void @caller() {
; CHECK-NEXT: s_mov_b32 s33, s32
; CHECK-NEXT: s_or_saveexec_b32 s1, -1
; CHECK-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
-; CHECK-NEXT: s_wait_alu 0xfffe
+; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0)
; CHECK-NEXT: s_mov_b32 exec_lo, s1
; CHECK-NEXT: s_add_co_i32 s32, s32, 16
; CHECK-NEXT: v_writelane_b32 v40, s0, 2
; CHECK-NEXT: s_mov_b64 s[0:1], s[4:5]
; CHECK-NEXT: s_getpc_b64 s[4:5]
-; CHECK-NEXT: s_wait_alu 0xfffe
+; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0)
; CHECK-NEXT: s_sext_i32_i16 s5, s5
; CHECK-NEXT: s_add_co_u32 s4, s4, entry_fn at gotpcrel32@lo+12
-; CHECK-NEXT: s_wait_alu 0xfffe
+; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0)
; CHECK-NEXT: s_add_co_ci_u32 s5, s5, entry_fn at gotpcrel32@hi+24
; CHECK-NEXT: v_mov_b32_e32 v0, v31
; CHECK-NEXT: s_load_b64 s[4:5], s[4:5], 0x0
@@ -48,7 +48,7 @@ define void @caller() {
; CHECK-NEXT: s_mov_b64 s[6:7], s[10:11]
; CHECK-NEXT: v_writelane_b32 v40, s31, 1
; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: s_wait_alu 0xfffe
+; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0)
; CHECK-NEXT: s_swappc_b64 s[30:31], s[4:5]
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; CHECK-NEXT: v_readlane_b32 s31, v40, 1
@@ -57,11 +57,11 @@ define void @caller() {
; CHECK-NEXT: v_readlane_b32 s0, v40, 2
; CHECK-NEXT: s_or_saveexec_b32 s1, -1
; CHECK-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
-; CHECK-NEXT: s_wait_alu 0xfffe
+; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0)
; CHECK-NEXT: s_mov_b32 exec_lo, s1
; CHECK-NEXT: s_mov_b32 s33, s0
; CHECK-NEXT: s_wait_loadcnt 0x0
-; CHECK-NEXT: s_wait_alu 0xfffe
+; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0)
; CHECK-NEXT: s_setpc_b64 s[30:31]
entry:
call void @entry_fn()
diff --git a/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll b/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
index 687205a11f4bd..c71527c5e3117 100644
--- a/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
+++ b/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
@@ -42,7 +42,7 @@ define <2 x half> @chain_hi_to_lo_private() {
; FLATSCR_GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; FLATSCR_GFX10-NEXT: s_mov_b32 s0, 2
; FLATSCR_GFX10-NEXT: scratch_load_ushort v0, off, s0
-; FLATSCR_GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; FLATSCR_GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; FLATSCR_GFX10-NEXT: s_mov_b32 s0, 0
; FLATSCR_GFX10-NEXT: scratch_load_short_d16_hi v0, off, s0
; FLATSCR_GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -651,7 +651,7 @@ define amdgpu_kernel void @vload2_private(ptr addrspace(1) nocapture readonly %i
; FLATSCR_GFX10-NEXT: scratch_store_short off, v0, s4 offset:2
; FLATSCR_GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; FLATSCR_GFX10-NEXT: global_load_ushort v0, v2, s[0:1] offset:4
-; FLATSCR_GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; FLATSCR_GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; FLATSCR_GFX10-NEXT: s_mov_b32 s0, 0
; FLATSCR_GFX10-NEXT: s_waitcnt vmcnt(0)
; FLATSCR_GFX10-NEXT: scratch_store_short off, v0, s0 offset:4
diff --git a/llvm/test/CodeGen/AMDGPU/code-size-estimate.ll b/llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
index 7ccf26f7eaad3..00da5613820cd 100644
--- a/llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
+++ b/llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
@@ -679,7 +679,7 @@ define double @v_mul_f64_vop2_literal_64(double %x) {
; GFX1200-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
; GFX1200-NEXT: s_mov_b32 s0, 0x66666666 ; encoding: [0xff,0x00,0x80,0xbe,0x66,0x66,0x66,0x66]
; GFX1200-NEXT: s_mov_b32 s1, 0x405ec666 ; encoding: [0xff,0x00,0x81,0xbe,0x66,0xc6,0x5e,0x40]
-; GFX1200-NEXT: s_wait_alu 0xfffe ; encoding: [0xfe,0xff,0x88,0xbf]
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0) ; encoding: [0x9e,0xff,0x88,0xbf]
; GFX1200-NEXT: v_mul_f64_e32 v[0:1], s[0:1], v[0:1] ; encoding: [0x00,0x00,0x00,0x0c]
; GFX1200-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
;
@@ -730,7 +730,7 @@ define i64 @v_add_u64_vop2_literal_32(i64 %x) {
; GFX1200-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
; GFX1200-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
; GFX1200-NEXT: v_add_co_u32 v0, vcc_lo, 0x7b, v0 ; encoding: [0x00,0x6a,0x00,0xd7,0xff,0x00,0x02,0x00,0x7b,0x00,0x00,0x00]
-; GFX1200-NEXT: s_wait_alu 0xfffd ; encoding: [0xfd,0xff,0x88,0xbf]
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0) ; encoding: [0x9d,0xff,0x88,0xbf]
; GFX1200-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo ; encoding: [0x01,0x7c,0x20,0xd5,0x80,0x02,0xaa,0x01]
; GFX1200-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
;
@@ -781,7 +781,7 @@ define i64 @v_add_u64_vop2_literal_64(i64 %x) {
; GFX1200-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
; GFX1200-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
; GFX1200-NEXT: v_add_co_u32 v0, vcc_lo, 0x12345678, v0 ; encoding: [0x00,0x6a,0x00,0xd7,0xff,0x00,0x02,0x00,0x78,0x56,0x34,0x12]
-; GFX1200-NEXT: s_wait_alu 0xfffd ; encoding: [0xfd,0xff,0x88,0xbf]
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0) ; encoding: [0x9d,0xff,0x88,0xbf]
; GFX1200-NEXT: v_add_co_ci_u32_e64 v1, null, 1, v1, vcc_lo ; encoding: [0x01,0x7c,0x20,0xd5,0x81,0x02,0xaa,0x01]
; GFX1200-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x48,0x80,0xbe]
;
diff --git a/llvm/test/CodeGen/AMDGPU/cse-convergent.ll b/llvm/test/CodeGen/AMDGPU/cse-convergent.ll
index f351b8badad16..6b43742b5d892 100644
--- a/llvm/test/CodeGen/AMDGPU/cse-convergent.ll
+++ b/llvm/test/CodeGen/AMDGPU/cse-convergent.ll
@@ -8,7 +8,7 @@ define i32 @test(i32 %val, i32 %cond) {
; GCN-NEXT: s_xor_saveexec_b32 s4, -1
; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GCN-NEXT: s_waitcnt_depctr 0xffe3
+; GCN-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GCN-NEXT: s_mov_b32 exec_lo, s4
; GCN-NEXT: s_or_saveexec_b32 s4, -1
; GCN-NEXT: v_mov_b32_e32 v2, 0
@@ -30,10 +30,10 @@ define i32 @test(i32 %val, i32 %cond) {
; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GCN-NEXT: v_add_nc_u32_e32 v0, v4, v5
; GCN-NEXT: s_xor_saveexec_b32 s4, -1
-; GCN-NEXT: s_clause 0x1
+; GCN-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GCN-NEXT: buffer_load_dword v2, off, s[0:3], s32
; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:4
-; GCN-NEXT: s_waitcnt_depctr 0xffe3
+; GCN-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GCN-NEXT: s_mov_b32 exec_lo, s4
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
index 14897b68bf57b..795f0841cede2 100644
--- a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
+++ b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
@@ -1712,7 +1712,7 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_2_uses(ptr addrspace(1) noalias %o
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_load_dword v0, v0, s[0:1]
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 16, v0
@@ -3025,7 +3025,7 @@ define amdgpu_kernel void @cvt_f32_ubyte0_vector() local_unnamed_addr {
; GFX10-NEXT: global_load_ubyte v2, v0, s[0:1] offset:2
; GFX10-NEXT: global_load_ubyte v3, v0, s[0:1] offset:1
; GFX10-NEXT: global_load_ubyte v4, v0, s[0:1]
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-NEXT: s_waitcnt vmcnt(3)
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, v1
diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
index 9ee41bd1a8b6f..a7a9851cc5c26 100644
--- a/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
+++ b/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
@@ -8,7 +8,7 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 {
; GFX10-NEXT: s_mov_b32 s0, exec_lo
; GFX10-NEXT: s_wqm_b32 exec_lo, exec_lo
; GFX10-NEXT: image_sample v[0:1], v[0:1], s[0:7], s[0:3] dmask:0x3 dim:SQ_RSRC_IMG_2D
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s0
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_clause 0x1
@@ -21,7 +21,7 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 {
; GFX10-NEXT: s_buffer_load_dword s24, s[0:3], 0x5c
; GFX10-NEXT: s_buffer_load_dword s28, s[0:3], 0x7c
; GFX10-NEXT: s_buffer_load_dword s29, s[0:3], 0xc0
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_nop 0
; GFX10-NEXT: s_buffer_load_dwordx4 s[0:3], s[0:3], 0x40
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll b/llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
index bcccf50e3805c..d224cfe27b226 100644
--- a/llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
+++ b/llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
@@ -283,7 +283,7 @@ define amdgpu_gfx void @amdgpu_gfx() #0 {
; CHECK-TRUE16-NEXT: s_mov_b32 s33, s32
; CHECK-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
; CHECK-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 ; 4-byte Folded Spill
-; CHECK-TRUE16-NEXT: s_wait_alu 0xfffe
+; CHECK-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; CHECK-TRUE16-NEXT: s_mov_b32 exec_lo, s1
; CHECK-TRUE16-NEXT: v_writelane_b32 v40, s0, 2
; CHECK-TRUE16-NEXT: v_mov_b16_e32 v0.l, 15
@@ -296,7 +296,7 @@ define amdgpu_gfx void @amdgpu_gfx() #0 {
; CHECK-TRUE16-NEXT: s_wait_storecnt 0x0
; CHECK-TRUE16-NEXT: v_mov_b32_e32 v0, 0x47
; CHECK-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
-; CHECK-TRUE16-NEXT: s_wait_alu 0xfffe
+; CHECK-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; CHECK-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; CHECK-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; CHECK-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
@@ -305,11 +305,11 @@ define amdgpu_gfx void @amdgpu_gfx() #0 {
; CHECK-TRUE16-NEXT: v_readlane_b32 s0, v40, 2
; CHECK-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
; CHECK-TRUE16-NEXT: scratch_load_b32 v40, off, s33 offset:4 ; 4-byte Folded Reload
-; CHECK-TRUE16-NEXT: s_wait_alu 0xfffe
+; CHECK-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; CHECK-TRUE16-NEXT: s_mov_b32 exec_lo, s1
; CHECK-TRUE16-NEXT: s_mov_b32 s33, s0
; CHECK-TRUE16-NEXT: s_wait_loadcnt 0x0
-; CHECK-TRUE16-NEXT: s_wait_alu 0xfffe
+; CHECK-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; CHECK-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; CHECK-FAKE16-LABEL: amdgpu_gfx:
@@ -323,7 +323,7 @@ define amdgpu_gfx void @amdgpu_gfx() #0 {
; CHECK-FAKE16-NEXT: s_mov_b32 s33, s32
; CHECK-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
; CHECK-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 ; 4-byte Folded Spill
-; CHECK-FAKE16-NEXT: s_wait_alu 0xfffe
+; CHECK-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; CHECK-FAKE16-NEXT: s_mov_b32 exec_lo, s1
; CHECK-FAKE16-NEXT: v_writelane_b32 v40, s0, 2
; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 15
@@ -336,7 +336,7 @@ define amdgpu_gfx void @amdgpu_gfx() #0 {
; CHECK-FAKE16-NEXT: s_wait_storecnt 0x0
; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 0x47
; CHECK-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
-; CHECK-FAKE16-NEXT: s_wait_alu 0xfffe
+; CHECK-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; CHECK-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; CHECK-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; CHECK-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
@@ -345,11 +345,11 @@ define amdgpu_gfx void @amdgpu_gfx() #0 {
; CHECK-FAKE16-NEXT: v_readlane_b32 s0, v40, 2
; CHECK-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
; CHECK-FAKE16-NEXT: scratch_load_b32 v40, off, s33 offset:4 ; 4-byte Folded Reload
-; CHECK-FAKE16-NEXT: s_wait_alu 0xfffe
+; CHECK-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; CHECK-FAKE16-NEXT: s_mov_b32 exec_lo, s1
; CHECK-FAKE16-NEXT: s_mov_b32 s33, s0
; CHECK-FAKE16-NEXT: s_wait_loadcnt 0x0
-; CHECK-FAKE16-NEXT: s_wait_alu 0xfffe
+; CHECK-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; CHECK-FAKE16-NEXT: s_setpc_b64 s[30:31]
%local = alloca i32, addrspace(5)
store volatile i8 15, ptr addrspace(5) %local
diff --git a/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll b/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
index 167bcab936a6c..17cc51d08a1e2 100644
--- a/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
@@ -2593,7 +2593,7 @@ define amdgpu_kernel void @fcmp_v2f16_lt(
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v3.l, v2.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -2624,7 +2624,7 @@ define amdgpu_kernel void @fcmp_v2f16_lt(
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-FAKE16-NEXT: s_endpgm
@@ -2788,7 +2788,7 @@ define amdgpu_kernel void @fcmp_v2f16_eq(
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f16_e32 vcc_lo, v3.l, v2.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -2819,7 +2819,7 @@ define amdgpu_kernel void @fcmp_v2f16_eq(
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_f16_e32 vcc_lo, v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-FAKE16-NEXT: s_endpgm
@@ -2982,7 +2982,7 @@ define amdgpu_kernel void @fcmp_v2f16_le(
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v3.l, v2.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -3013,7 +3013,7 @@ define amdgpu_kernel void @fcmp_v2f16_le(
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-FAKE16-NEXT: s_endpgm
@@ -3176,7 +3176,7 @@ define amdgpu_kernel void @fcmp_v2f16_gt(
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v3.l, v2.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -3207,7 +3207,7 @@ define amdgpu_kernel void @fcmp_v2f16_gt(
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-FAKE16-NEXT: s_endpgm
@@ -3371,7 +3371,7 @@ define amdgpu_kernel void @fcmp_v2f16_lg(
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, v3.l, v2.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -3402,7 +3402,7 @@ define amdgpu_kernel void @fcmp_v2f16_lg(
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-FAKE16-NEXT: s_endpgm
@@ -3566,7 +3566,7 @@ define amdgpu_kernel void @fcmp_v2f16_ge(
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v3.l, v2.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -3597,7 +3597,7 @@ define amdgpu_kernel void @fcmp_v2f16_ge(
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-FAKE16-NEXT: s_endpgm
@@ -3761,7 +3761,7 @@ define amdgpu_kernel void @fcmp_v2f16_o(
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v3.l, v2.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -3792,7 +3792,7 @@ define amdgpu_kernel void @fcmp_v2f16_o(
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-FAKE16-NEXT: s_endpgm
@@ -3956,7 +3956,7 @@ define amdgpu_kernel void @fcmp_v2f16_u(
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v3.l, v2.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -3987,7 +3987,7 @@ define amdgpu_kernel void @fcmp_v2f16_u(
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-FAKE16-NEXT: s_endpgm
@@ -4150,7 +4150,7 @@ define amdgpu_kernel void @fcmp_v2f16_nge(
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v3.l, v2.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -4181,7 +4181,7 @@ define amdgpu_kernel void @fcmp_v2f16_nge(
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-FAKE16-NEXT: s_endpgm
@@ -4344,7 +4344,7 @@ define amdgpu_kernel void @fcmp_v2f16_nlg(
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_nlg_f16_e32 vcc_lo, v3.l, v2.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -4375,7 +4375,7 @@ define amdgpu_kernel void @fcmp_v2f16_nlg(
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_nlg_f16_e32 vcc_lo, v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-FAKE16-NEXT: s_endpgm
@@ -4539,7 +4539,7 @@ define amdgpu_kernel void @fcmp_v2f16_ngt(
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v3.l, v2.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -4570,7 +4570,7 @@ define amdgpu_kernel void @fcmp_v2f16_ngt(
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-FAKE16-NEXT: s_endpgm
@@ -4733,7 +4733,7 @@ define amdgpu_kernel void @fcmp_v2f16_nle(
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v3.l, v2.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -4764,7 +4764,7 @@ define amdgpu_kernel void @fcmp_v2f16_nle(
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-FAKE16-NEXT: s_endpgm
@@ -4927,7 +4927,7 @@ define amdgpu_kernel void @fcmp_v2f16_neq(
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_neq_f16_e32 vcc_lo, v3.l, v2.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -4958,7 +4958,7 @@ define amdgpu_kernel void @fcmp_v2f16_neq(
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_neq_f16_e32 vcc_lo, v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-FAKE16-NEXT: s_endpgm
@@ -5121,7 +5121,7 @@ define amdgpu_kernel void @fcmp_v2f16_nlt(
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v3.l, v2.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -5152,7 +5152,7 @@ define amdgpu_kernel void @fcmp_v2f16_nlt(
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX12-FAKE16-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null
; GFX12-FAKE16-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/fdiv.f16.ll b/llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
index 7f6a920d25016..9e527cf38e7ee 100644
--- a/llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
@@ -147,7 +147,7 @@ define amdgpu_kernel void @v_fdiv_f16(
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v3.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v4, v4, v0
; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v4, v2 op_sel_hi:[1,0,1]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -181,7 +181,7 @@ define amdgpu_kernel void @v_fdiv_f16(
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v3, v3
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_mul_f32_e32 v4, v4, v3
; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v4, v1 op_sel_hi:[1,0,1]
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -936,7 +936,7 @@ define amdgpu_kernel void @v_rsq_f16_neg(ptr addrspace(1) %r, ptr addrspace(1) %
; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3] glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_rsq_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
@@ -951,7 +951,7 @@ define amdgpu_kernel void @v_rsq_f16_neg(ptr addrspace(1) %r, ptr addrspace(1) %
; GFX11-FAKE16-NEXT: global_load_u16 v1, v0, s[2:3] glc dlc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_rsq_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v1, 0x8000, v1
; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
@@ -1178,7 +1178,7 @@ define amdgpu_kernel void @v_rsq_f16_missing_contract0(ptr addrspace(1) %r, ptr
; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3] glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_rcp_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
@@ -1193,7 +1193,7 @@ define amdgpu_kernel void @v_rsq_f16_missing_contract0(ptr addrspace(1) %r, ptr
; GFX11-FAKE16-NEXT: global_load_u16 v1, v0, s[2:3] glc dlc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_sqrt_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_rcp_f16_e32 v1, v1
; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
@@ -1296,7 +1296,7 @@ define amdgpu_kernel void @v_rsq_f16_missing_contract1(ptr addrspace(1) %r, ptr
; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3] glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_rcp_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
@@ -1311,7 +1311,7 @@ define amdgpu_kernel void @v_rsq_f16_missing_contract1(ptr addrspace(1) %r, ptr
; GFX11-FAKE16-NEXT: global_load_u16 v1, v0, s[2:3] glc dlc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_sqrt_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_rcp_f16_e32 v1, v1
; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
@@ -1414,7 +1414,7 @@ define amdgpu_kernel void @v_neg_rsq_f16_missing_contract1(ptr addrspace(1) %r,
; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3] glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_rcp_f16_e64 v0.l, -v0.l
; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
@@ -1429,7 +1429,7 @@ define amdgpu_kernel void @v_neg_rsq_f16_missing_contract1(ptr addrspace(1) %r,
; GFX11-FAKE16-NEXT: global_load_u16 v1, v0, s[2:3] glc dlc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_sqrt_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_rcp_f16_e64 v1, -v1
; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
@@ -1539,7 +1539,7 @@ define amdgpu_kernel void @v_fdiv_f16_afn(ptr addrspace(1) %r, ptr addrspace(1)
; GFX11-TRUE16-NEXT: global_load_d16_hi_b16 v0, v1, s[4:5] glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_rcp_f16_e32 v0.h, v0.h
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v0.h
; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
@@ -1558,7 +1558,7 @@ define amdgpu_kernel void @v_fdiv_f16_afn(ptr addrspace(1) %r, ptr addrspace(1)
; GFX11-FAKE16-NEXT: global_load_u16 v2, v0, s[4:5] glc dlc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_rcp_f16_e32 v2, v2
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_mul_f16_e32 v1, v1, v2
; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
@@ -1669,7 +1669,7 @@ define amdgpu_kernel void @v_fdiv_f16_unsafe(ptr addrspace(1) %r, ptr addrspace(
; GFX11-TRUE16-NEXT: global_load_d16_hi_b16 v0, v1, s[4:5] glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_rcp_f16_e32 v0.h, v0.h
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v0.h
; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
@@ -1688,7 +1688,7 @@ define amdgpu_kernel void @v_fdiv_f16_unsafe(ptr addrspace(1) %r, ptr addrspace(
; GFX11-FAKE16-NEXT: global_load_u16 v2, v0, s[4:5] glc dlc
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_rcp_f16_e32 v2, v2
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_mul_f16_e32 v1, v1, v2
; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
@@ -1982,7 +1982,7 @@ define half @v_fdiv_f16_arcp(half %x, half %y) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_rcp_f16_e32 v1.l, v1.l
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1990,7 +1990,7 @@ define half @v_fdiv_f16_arcp(half %x, half %y) {
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_rcp_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv arcp half %x, %y
@@ -2034,7 +2034,7 @@ define half @v_fdiv_f16_afn_nsz(half %x, half %y) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_rcp_f16_e32 v1.l, v1.l
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2042,7 +2042,7 @@ define half @v_fdiv_f16_afn_nsz(half %x, half %y) {
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_rcp_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fdiv = fdiv afn nsz half %x, %y
@@ -2204,7 +2204,7 @@ define <2 x half> @v_rsq_v2f16(<2 x half> %a) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_rsq_f16_e32 v0.h, v0.h
; GFX11-TRUE16-NEXT: v_rsq_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2215,7 +2215,7 @@ define <2 x half> @v_rsq_v2f16(<2 x half> %a) {
; GFX11-FAKE16-NEXT: v_rsq_f16_e32 v0, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_rsq_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX9-IEEE-LABEL: v_rsq_v2f16:
@@ -2414,7 +2414,7 @@ define <2 x half> @v_neg_rsq_v2f16(<2 x half> %a) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_rsq_f16_e32 v0.h, v0.h
; GFX11-TRUE16-NEXT: v_rsq_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, -v0.l, -v0.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2425,7 +2425,7 @@ define <2 x half> @v_neg_rsq_v2f16(<2 x half> %a) {
; GFX11-FAKE16-NEXT: v_rsq_f16_e32 v0, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_rsq_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, -v0, -v1
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX9-IEEE-LABEL: v_neg_rsq_v2f16:
diff --git a/llvm/test/CodeGen/AMDGPU/fdiv.ll b/llvm/test/CodeGen/AMDGPU/fdiv.ll
index 4d448e64f0921..c510c40c8536c 100644
--- a/llvm/test/CodeGen/AMDGPU/fdiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/fdiv.ll
@@ -145,7 +145,7 @@ define amdgpu_kernel void @s_fdiv_f32_ninf(ptr addrspace(1) %out, float %a, floa
; GFX11-NEXT: v_div_scale_f32 v2, vcc_lo, s2, s3, s2
; GFX11-NEXT: v_rcp_f32_e32 v1, v0
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v3, -v0, v1, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v1, v3, v1
; GFX11-NEXT: v_mul_f32_e32 v3, v2, v1
@@ -296,7 +296,7 @@ define amdgpu_kernel void @s_fdiv_f32_ieee(ptr addrspace(1) %out, float %a, floa
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_div_scale_f32 v0, null, s3, s3, s2
; GFX11-NEXT: v_rcp_f32_e32 v1, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v2, -v0, v1, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v1, v2, v1
; GFX11-NEXT: v_div_scale_f32 v2, vcc_lo, s2, s3, s2
@@ -386,7 +386,7 @@ define amdgpu_kernel void @s_fdiv_25ulp_f32(ptr addrspace(1) %out, float %a, flo
; GFX11-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x2f800000, s4
; GFX11-NEXT: v_mul_f32_e32 v1, s3, v0
; GFX11-NEXT: v_rcp_f32_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v1, s2, v1
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX11-NEXT: global_store_b32 v2, v0, s[0:1]
@@ -498,7 +498,7 @@ define amdgpu_kernel void @s_fdiv_25ulp_ieee_f32(ptr addrspace(1) %out, float %a
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v3, s2
; GFX11-NEXT: v_rcp_f32_e32 v0, v0
; GFX11-NEXT: v_sub_nc_u32_e32 v1, v3, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, v2, v0
; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
@@ -561,7 +561,7 @@ define amdgpu_kernel void @s_fdiv_fast_ieee_f32(ptr addrspace(1) %out, float %a,
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_rcp_f32_e32 v0, s3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mul_f32 v0, s2, v0
; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX11-NEXT: s_endpgm
@@ -622,7 +622,7 @@ define amdgpu_kernel void @s_fdiv_f32_fast_math(ptr addrspace(1) %out, float %a,
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_rcp_f32_e32 v0, s3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mul_f32 v0, s2, v0
; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX11-NEXT: s_endpgm
@@ -683,7 +683,7 @@ define amdgpu_kernel void @s_fdiv_ulp25_f32_fast_math(ptr addrspace(1) %out, flo
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_rcp_f32_e32 v0, s3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mul_f32 v0, s2, v0
; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX11-NEXT: s_endpgm
@@ -837,7 +837,7 @@ define amdgpu_kernel void @s_fdiv_f32_arcp_daz(ptr addrspace(1) %out, float %a,
; GFX11-NEXT: v_div_scale_f32 v2, vcc_lo, s2, s3, s2
; GFX11-NEXT: v_rcp_f32_e32 v1, v0
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v3, -v0, v1, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v1, v3, v1
; GFX11-NEXT: v_mul_f32_e32 v3, v2, v1
@@ -907,7 +907,7 @@ define amdgpu_kernel void @s_fdiv_f32_arcp_ninf(ptr addrspace(1) %out, float %a,
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_rcp_f32_e32 v0, s3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mul_f32 v0, s2, v0
; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX11-NEXT: s_endpgm
@@ -1137,7 +1137,7 @@ define amdgpu_kernel void @s_fdiv_v2f32(ptr addrspace(1) %out, <2 x float> %a, <
; GFX11-NEXT: v_div_scale_f32 v2, vcc_lo, s1, s3, s1
; GFX11-NEXT: v_rcp_f32_e32 v1, v0
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v3, -v0, v1, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v1, v3, v1
; GFX11-NEXT: v_mul_f32_e32 v3, v2, v1
@@ -1151,7 +1151,7 @@ define amdgpu_kernel void @s_fdiv_v2f32(ptr addrspace(1) %out, <2 x float> %a, <
; GFX11-NEXT: v_div_fixup_f32 v1, v0, s3, s1
; GFX11-NEXT: v_div_scale_f32 v0, vcc_lo, s0, s2, s0
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v4, -v2, v3, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v3
; GFX11-NEXT: v_mul_f32_e32 v4, v0, v3
@@ -1236,7 +1236,7 @@ define amdgpu_kernel void @s_fdiv_ulp25_v2f32(ptr addrspace(1) %out, <2 x float>
; GFX11-NEXT: v_rcp_f32_e32 v0, s2
; GFX11-NEXT: v_rcp_f32_e32 v1, s3
; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_dual_mul_f32 v0, s0, v0 :: v_dual_mul_f32 v1, s1, v1
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[4:5]
; GFX11-NEXT: s_endpgm
@@ -1312,7 +1312,7 @@ define amdgpu_kernel void @s_fdiv_v2f32_fast_math(ptr addrspace(1) %out, <2 x fl
; GFX11-NEXT: v_rcp_f32_e32 v0, s3
; GFX11-NEXT: v_rcp_f32_e32 v2, s2
; GFX11-NEXT: v_mov_b32_e32 v3, 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_dual_mul_f32 v1, s1, v0 :: v_dual_mul_f32 v0, s0, v2
; GFX11-NEXT: global_store_b64 v3, v[0:1], s[4:5]
; GFX11-NEXT: s_endpgm
@@ -1388,7 +1388,7 @@ define amdgpu_kernel void @s_fdiv_v2f32_arcp_math(ptr addrspace(1) %out, <2 x fl
; GFX11-NEXT: v_rcp_f32_e32 v0, s3
; GFX11-NEXT: v_rcp_f32_e32 v2, s2
; GFX11-NEXT: v_mov_b32_e32 v3, 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_dual_mul_f32 v1, s1, v0 :: v_dual_mul_f32 v0, s0, v2
; GFX11-NEXT: global_store_b64 v3, v[0:1], s[4:5]
; GFX11-NEXT: s_endpgm
@@ -1769,7 +1769,7 @@ define amdgpu_kernel void @s_fdiv_v4f32(ptr addrspace(1) %out, ptr addrspace(1)
; GFX11-NEXT: v_div_scale_f32 v2, vcc_lo, s3, s7, s3
; GFX11-NEXT: v_rcp_f32_e32 v1, v0
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v3, -v0, v1, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v1, v3, v1
; GFX11-NEXT: v_mul_f32_e32 v3, v2, v1
@@ -1783,7 +1783,7 @@ define amdgpu_kernel void @s_fdiv_v4f32(ptr addrspace(1) %out, ptr addrspace(1)
; GFX11-NEXT: v_rcp_f32_e32 v4, v2
; GFX11-NEXT: v_div_fixup_f32 v3, v0, s7, s3
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v0, -v2, v4, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v4, v0, v4
; GFX11-NEXT: v_mul_f32_e32 v0, v1, v4
@@ -1797,7 +1797,7 @@ define amdgpu_kernel void @s_fdiv_v4f32(ptr addrspace(1) %out, ptr addrspace(1)
; GFX11-NEXT: v_rcp_f32_e32 v6, v5
; GFX11-NEXT: v_div_fixup_f32 v2, v0, s6, s2
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v0, -v5, v6, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v6, v0, v6
; GFX11-NEXT: v_mul_f32_e32 v0, v1, v6
@@ -1811,7 +1811,7 @@ define amdgpu_kernel void @s_fdiv_v4f32(ptr addrspace(1) %out, ptr addrspace(1)
; GFX11-NEXT: v_div_fixup_f32 v1, v0, s5, s1
; GFX11-NEXT: v_div_scale_f32 v0, vcc_lo, s0, s4, s0
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v6, -v4, v5, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v5
; GFX11-NEXT: v_mul_f32_e32 v6, v0, v5
@@ -1925,7 +1925,7 @@ define amdgpu_kernel void @s_fdiv_v4f32_fast_math(ptr addrspace(1) %out, ptr add
; GFX11-NEXT: v_rcp_f32_e32 v4, s5
; GFX11-NEXT: v_rcp_f32_e32 v5, s4
; GFX11-NEXT: v_dual_mov_b32 v6, 0 :: v_dual_mul_f32 v3, s3, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_dual_mul_f32 v2, s2, v1 :: v_dual_mul_f32 v1, s1, v4
; GFX11-NEXT: v_mul_f32_e32 v0, s0, v5
; GFX11-NEXT: global_store_b128 v6, v[0:3], s[8:9]
@@ -2031,7 +2031,7 @@ define amdgpu_kernel void @s_fdiv_v4f32_arcp_math(ptr addrspace(1) %out, ptr add
; GFX11-NEXT: v_rcp_f32_e32 v4, s5
; GFX11-NEXT: v_rcp_f32_e32 v5, s4
; GFX11-NEXT: v_dual_mov_b32 v6, 0 :: v_dual_mul_f32 v3, s3, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_dual_mul_f32 v2, s2, v1 :: v_dual_mul_f32 v1, s1, v4
; GFX11-NEXT: v_mul_f32_e32 v0, s0, v5
; GFX11-NEXT: global_store_b128 v6, v[0:3], s[8:9]
@@ -2197,7 +2197,7 @@ define amdgpu_kernel void @s_fdiv_f32_correctly_rounded_divide_sqrt(ptr addrspac
; GFX11-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, s2, 1.0
; GFX11-NEXT: v_rcp_f32_e32 v1, v0
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v3, -v0, v1, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v1, v3, v1
; GFX11-NEXT: v_mul_f32_e32 v3, v2, v1
@@ -2343,7 +2343,7 @@ define amdgpu_kernel void @s_fdiv_f32_denorms_correctly_rounded_divide_sqrt(ptr
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_div_scale_f32 v0, null, s2, s2, 1.0
; GFX11-NEXT: v_rcp_f32_e32 v1, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v2, -v0, v1, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v1, v2, v1
; GFX11-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, s2, 1.0
@@ -2477,7 +2477,7 @@ define float @v_fdiv_f32_dynamic_denorm(float %a, float %b) #2 {
; GFX11-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
@@ -2583,7 +2583,7 @@ define float @v_fdiv_f32_ieee(float %x, float %y) #1 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
; GFX11-NEXT: v_rcp_f32_e32 v3, v2
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v4, -v2, v3, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v3
; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
@@ -2670,7 +2670,7 @@ define float @v_fdiv_f32_ieee_25ulp(float %x, float %y) #1 {
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX11-NEXT: v_ldexp_f32 v0, v2, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -2787,7 +2787,7 @@ define float @v_fdiv_f32_dynamic(float %x, float %y) #2 {
; GFX11-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
@@ -2874,7 +2874,7 @@ define float @v_fdiv_f32_dynamic_25ulp(float %x, float %y) #2 {
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX11-NEXT: v_ldexp_f32 v0, v2, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -2985,7 +2985,7 @@ define float @v_fdiv_f32_daz(float %x, float %y) #0 {
; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
; GFX11-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
@@ -3037,7 +3037,7 @@ define float @v_fdiv_f32_daz_25ulp(float %x, float %y) #0 {
; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s0
; GFX11-NEXT: v_mul_f32_e32 v1, v1, v2
; GFX11-NEXT: v_rcp_f32_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX11-NEXT: v_mul_f32_e32 v0, v2, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -3142,7 +3142,7 @@ define float @v_fdiv_f32_ieee_contractable_user(float %x, float %y, float %z) #1
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_div_scale_f32 v3, null, v1, v1, v0
; GFX11-NEXT: v_rcp_f32_e32 v4, v3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v4, v5, v4
; GFX11-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
@@ -3235,7 +3235,7 @@ define float @v_fdiv_f32_ieee_25ulp_contractable_user(float %x, float %y, float
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: v_rcp_f32_e32 v3, v3
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v3, v4, v3
; GFX11-NEXT: v_ldexp_f32 v0, v3, v0
; GFX11-NEXT: v_add_f32_e32 v0, v0, v2
@@ -3359,7 +3359,7 @@ define float @v_fdiv_f32_dynamic_contractable_user(float %x, float %y, float %z)
; GFX11-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-NEXT: v_rcp_f32_e32 v4, v3
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v6, -v3, v4, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v4, v6, v4
; GFX11-NEXT: v_mul_f32_e32 v6, v5, v4
@@ -3452,7 +3452,7 @@ define float @v_fdiv_f32_dynamic_25ulp_contractable_user(float %x, float %y, flo
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: v_rcp_f32_e32 v3, v3
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v3, v4, v3
; GFX11-NEXT: v_ldexp_f32 v0, v3, v0
; GFX11-NEXT: v_add_f32_e32 v0, v0, v2
@@ -3570,7 +3570,7 @@ define float @v_fdiv_f32_daz_contractable_user(float %x, float %y, float %z) #0
; GFX11-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
; GFX11-NEXT: v_rcp_f32_e32 v4, v3
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v6, -v3, v4, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v4, v6, v4
; GFX11-NEXT: v_mul_f32_e32 v6, v5, v4
@@ -3624,7 +3624,7 @@ define float @v_fdiv_f32_daz_25ulp_contractable_user(float %x, float %y, float %
; GFX11-NEXT: v_cndmask_b32_e64 v3, 1.0, 0x2f800000, s0
; GFX11-NEXT: v_mul_f32_e32 v1, v1, v3
; GFX11-NEXT: v_rcp_f32_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX11-NEXT: v_fma_f32 v0, v3, v0, v2
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -3724,7 +3724,7 @@ define float @v_fdiv_f32_ieee__nnan_ninf(float %x, float %y, float %z) #1 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
; GFX11-NEXT: v_rcp_f32_e32 v3, v2
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v4, -v2, v3, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v3
; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
@@ -3811,7 +3811,7 @@ define float @v_fdiv_f32_ieee_25ulp__nnan_ninf(float %x, float %y, float %z) #1
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX11-NEXT: v_ldexp_f32 v0, v2, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -3928,7 +3928,7 @@ define float @v_fdiv_f32_dynamic__nnan_ninf(float %x, float %y, float %z) #2 {
; GFX11-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
@@ -4015,7 +4015,7 @@ define float @v_fdiv_f32_dynamic_25ulp__nnan_ninf(float %x, float %y, float %z)
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX11-NEXT: v_ldexp_f32 v0, v2, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -4126,7 +4126,7 @@ define float @v_fdiv_f32_daz__nnan_ninf(float %x, float %y, float %z) #0 {
; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
; GFX11-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
@@ -4178,7 +4178,7 @@ define float @v_fdiv_f32_daz_25ulp__nnan_ninf(float %x, float %y, float %z) #0 {
; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s0
; GFX11-NEXT: v_mul_f32_e32 v1, v1, v2
; GFX11-NEXT: v_rcp_f32_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX11-NEXT: v_mul_f32_e32 v0, v2, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -4282,7 +4282,7 @@ define float @v_fdiv_f32_ieee__nnan_ninf_contractable_user(float %x, float %y, f
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_div_scale_f32 v3, null, v1, v1, v0
; GFX11-NEXT: v_rcp_f32_e32 v4, v3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v4, v5, v4
; GFX11-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
@@ -4375,7 +4375,7 @@ define float @v_fdiv_f32_ieee_25ulp__nnan_ninf_contractable_user(float %x, float
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: v_rcp_f32_e32 v3, v3
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v3, v4, v3
; GFX11-NEXT: v_ldexp_f32 v0, v3, v0
; GFX11-NEXT: v_add_f32_e32 v0, v0, v2
@@ -4499,7 +4499,7 @@ define float @v_fdiv_f32_dynamic__nnan_ninf_contractable_user(float %x, float %y
; GFX11-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-NEXT: v_rcp_f32_e32 v4, v3
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v6, -v3, v4, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v4, v6, v4
; GFX11-NEXT: v_mul_f32_e32 v6, v5, v4
@@ -4592,7 +4592,7 @@ define float @v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user(float %x, fl
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: v_rcp_f32_e32 v3, v3
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v3, v4, v3
; GFX11-NEXT: v_ldexp_f32 v0, v3, v0
; GFX11-NEXT: v_add_f32_e32 v0, v0, v2
@@ -4710,7 +4710,7 @@ define float @v_fdiv_f32_daz__nnan_ninf_contractable_user(float %x, float %y, fl
; GFX11-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
; GFX11-NEXT: v_rcp_f32_e32 v4, v3
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v6, -v3, v4, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v4, v6, v4
; GFX11-NEXT: v_mul_f32_e32 v6, v5, v4
@@ -4764,7 +4764,7 @@ define float @v_fdiv_f32_daz_25ulp__nnan_ninf_contractable_user(float %x, float
; GFX11-NEXT: v_cndmask_b32_e64 v3, 1.0, 0x2f800000, s0
; GFX11-NEXT: v_mul_f32_e32 v1, v1, v3
; GFX11-NEXT: v_rcp_f32_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX11-NEXT: v_fma_f32 v0, v3, v0, v2
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -4864,7 +4864,7 @@ define float @v_fdiv_neglhs_f32_ieee(float %x, float %y) #1 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, -v0
; GFX11-NEXT: v_rcp_f32_e32 v3, v2
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v4, -v2, v3, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v3
; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, -v0, v1, -v0
@@ -4952,7 +4952,7 @@ define float @v_fdiv_neglhs_f32_ieee_25ulp(float %x, float %y) #1 {
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX11-NEXT: v_ldexp_f32 v0, v2, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -5070,7 +5070,7 @@ define float @v_fdiv_neglhs_f32_dynamic(float %x, float %y) #2 {
; GFX11-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
@@ -5158,7 +5158,7 @@ define float @v_fdiv_neglhs_f32_dynamic_25ulp(float %x, float %y) #2 {
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX11-NEXT: v_ldexp_f32 v0, v2, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -5270,7 +5270,7 @@ define float @v_fdiv_neglhs_f32_daz(float %x, float %y) #0 {
; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, -v0, v1, -v0
; GFX11-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
@@ -5323,7 +5323,7 @@ define float @v_fdiv_neglhs_f32_daz_25ulp(float %x, float %y) #0 {
; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s0
; GFX11-NEXT: v_mul_f32_e32 v1, v1, v2
; GFX11-NEXT: v_rcp_f32_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e64 v0, -v0, v1
; GFX11-NEXT: v_mul_f32_e32 v0, v2, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -5423,7 +5423,7 @@ define float @v_fdiv_negrhs_f32_ieee(float %x, float %y) #1 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_div_scale_f32 v2, null, -v1, -v1, v0
; GFX11-NEXT: v_rcp_f32_e32 v3, v2
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v4, -v2, v3, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v3
; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, -v1, v0
@@ -5511,7 +5511,7 @@ define float @v_fdiv_negrhs_f32_ieee_25ulp(float %x, float %y) #1 {
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX11-NEXT: v_ldexp_f32 v0, v2, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -5629,7 +5629,7 @@ define float @v_fdiv_negrhs_f32_dynamic(float %x, float %y) #2 {
; GFX11-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
@@ -5717,7 +5717,7 @@ define float @v_fdiv_negrhs_f32_dynamic_25ulp(float %x, float %y) #2 {
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX11-NEXT: v_ldexp_f32 v0, v2, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -5829,7 +5829,7 @@ define float @v_fdiv_negrhs_f32_daz(float %x, float %y) #0 {
; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, -v1, v0
; GFX11-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
@@ -5882,7 +5882,7 @@ define float @v_fdiv_negrhs_f32_daz_25ulp(float %x, float %y) #0 {
; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s0
; GFX11-NEXT: v_mul_f32_e64 v1, -v1, v2
; GFX11-NEXT: v_rcp_f32_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX11-NEXT: v_mul_f32_e32 v0, v2, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -5986,7 +5986,7 @@ define float @v_fdiv_f32_constrhs0_ieee(float %x) #1 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_div_scale_f32 v1, null, 0x4640e400, 0x4640e400, v0
; GFX11-NEXT: v_rcp_f32_e32 v2, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v3, -v1, v2, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v2, v3, v2
; GFX11-NEXT: v_div_scale_f32 v3, vcc_lo, v0, 0x4640e400, v0
@@ -6176,7 +6176,7 @@ define float @v_fdiv_f32_constrhs0_dynamic(float %x) #2 {
; GFX11-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-NEXT: v_rcp_f32_e32 v2, v1
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v4, -v1, v2, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v2, v4, v2
; GFX11-NEXT: v_mul_f32_e32 v4, v3, v2
@@ -6360,7 +6360,7 @@ define float @v_fdiv_f32_constrhs0_daz(float %x) #0 {
; GFX11-NEXT: v_div_scale_f32 v3, vcc_lo, v0, 0x4640e400, v0
; GFX11-NEXT: v_rcp_f32_e32 v2, v1
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v4, -v1, v2, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v2, v4, v2
; GFX11-NEXT: v_mul_f32_e32 v4, v3, v2
@@ -6485,7 +6485,7 @@ define float @v_fdiv_f32_constlhs0_ieee(float %x) #1 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_div_scale_f32 v1, null, v0, v0, 0x4640e400
; GFX11-NEXT: v_rcp_f32_e32 v2, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v3, -v1, v2, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v2, v3, v2
; GFX11-NEXT: v_div_scale_f32 v3, vcc_lo, 0x4640e400, v0, 0x4640e400
@@ -6561,7 +6561,7 @@ define float @v_fdiv_f32_constlhs0_ieee_25ulp(float %x) #1 {
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: v_rcp_f32_e32 v1, v1
; GFX11-NEXT: v_sub_nc_u32_e32 v0, 14, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v1, 0x3f40e400, v1
; GFX11-NEXT: v_ldexp_f32 v0, v1, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -6682,7 +6682,7 @@ define float @v_fdiv_f32_constlhs0_dynamic(float %x) #2 {
; GFX11-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-NEXT: v_rcp_f32_e32 v2, v1
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v4, -v1, v2, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v2, v4, v2
; GFX11-NEXT: v_mul_f32_e32 v4, v3, v2
@@ -6758,7 +6758,7 @@ define float @v_fdiv_f32_constlhs0_dynamic_25ulp(float %x) #2 {
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: v_rcp_f32_e32 v1, v1
; GFX11-NEXT: v_sub_nc_u32_e32 v0, 14, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v1, 0x3f40e400, v1
; GFX11-NEXT: v_ldexp_f32 v0, v1, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -6873,7 +6873,7 @@ define float @v_fdiv_f32_constlhs0_daz(float %x) #0 {
; GFX11-NEXT: v_div_scale_f32 v3, vcc_lo, 0x4640e400, v0, 0x4640e400
; GFX11-NEXT: v_rcp_f32_e32 v2, v1
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v4, -v1, v2, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v2, v4, v2
; GFX11-NEXT: v_mul_f32_e32 v4, v3, v2
@@ -6925,7 +6925,7 @@ define float @v_fdiv_f32_constlhs0_daz_25ulp(float %x) #0 {
; GFX11-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x2f800000, s0
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX11-NEXT: v_rcp_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4640e400, v0
; GFX11-NEXT: v_mul_f32_e32 v0, v1, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -7024,7 +7024,7 @@ define float @v_fdiv_f32_ieee_nodenorm_x(float nofpclass(sub) %x, float %y) #1 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
; GFX11-NEXT: v_rcp_f32_e32 v3, v2
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v4, -v2, v3, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v3
; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
@@ -7111,7 +7111,7 @@ define float @v_fdiv_f32_ieee_25ulp_nodenorm_x(float nofpclass(sub) %x, float %y
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX11-NEXT: v_ldexp_f32 v0, v2, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -7228,7 +7228,7 @@ define float @v_fdiv_f32_dynamic_nodenorm_x(float nofpclass(sub) %x, float %y) #
; GFX11-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
@@ -7315,7 +7315,7 @@ define float @v_fdiv_f32_dynamic_25ulp_nodenorm_x(float nofpclass(sub) %x, float
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX11-NEXT: v_ldexp_f32 v0, v2, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -7426,7 +7426,7 @@ define float @v_fdiv_f32_daz_nodenorm_x(float nofpclass(sub) %x, float %y) #0 {
; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
; GFX11-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
@@ -7478,7 +7478,7 @@ define float @v_fdiv_f32_daz_25ulp_nodenorm_x(float nofpclass(sub) %x, float %y)
; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s0
; GFX11-NEXT: v_mul_f32_e32 v1, v1, v2
; GFX11-NEXT: v_rcp_f32_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX11-NEXT: v_mul_f32_e32 v0, v2, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -7577,7 +7577,7 @@ define float @v_fdiv_f32_ieee_nodenorm_y(float %x, float nofpclass(sub) %y) #1 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
; GFX11-NEXT: v_rcp_f32_e32 v3, v2
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v4, -v2, v3, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v3
; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
@@ -7664,7 +7664,7 @@ define float @v_fdiv_f32_ieee_25ulp_nodenorm_y(float %x, float nofpclass(sub) %y
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX11-NEXT: v_ldexp_f32 v0, v2, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -7781,7 +7781,7 @@ define float @v_fdiv_f32_dynamic_nodenorm_y(float %x, float nofpclass(sub) %y) #
; GFX11-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)
; GFX11-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
@@ -7868,7 +7868,7 @@ define float @v_fdiv_f32_dynamic_25ulp_nodenorm_y(float %x, float nofpclass(sub)
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2
; GFX11-NEXT: v_ldexp_f32 v0, v2, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -7979,7 +7979,7 @@ define float @v_fdiv_f32_daz_nodenorm_y(float %x, float nofpclass(sub) %y) #0 {
; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
; GFX11-NEXT: v_rcp_f32_e32 v3, v2
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
@@ -8031,7 +8031,7 @@ define float @v_fdiv_f32_daz_25ulp_nodenorm_y(float %x, float nofpclass(sub) %y)
; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s0
; GFX11-NEXT: v_mul_f32_e32 v1, v1, v2
; GFX11-NEXT: v_rcp_f32_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX11-NEXT: v_mul_f32_e32 v0, v2, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-wwm.ll b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-wwm.ll
index db32135939a5d..0290ffdf161cf 100644
--- a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-wwm.ll
+++ b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-wwm.ll
@@ -13,16 +13,16 @@ define amdgpu_gs i32 @main() {
; CHECK-NEXT: v_readfirstlane_b32 s1, v0
; CHECK-NEXT: s_mov_b32 exec_lo, s2
; CHECK-NEXT: s_or_b32 s0, s0, s1
-; CHECK-NEXT: s_wait_alu 0xfffe
+; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0)
; CHECK-NEXT: s_bitcmp1_b32 s0, 0
; CHECK-NEXT: s_cselect_b32 s0, -1, 0
-; CHECK-NEXT: s_wait_alu 0xfffe
+; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0)
; CHECK-NEXT: s_xor_b32 s0, s0, -1
-; CHECK-NEXT: s_wait_alu 0xfffe
+; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0)
; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; CHECK-NEXT: v_readfirstlane_b32 s0, v1
-; CHECK-NEXT: s_wait_alu 0xf1ff
+; CHECK-NEXT: s_wait_alu depctr_va_sdst(0)
; CHECK-NEXT: ; return to shader part epilog
bb:
%i = call i1 @llvm.amdgcn.readfirstlane.i1(i1 false)
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
index 841bbfc3d69e8..66d8b3f54d779 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
@@ -5710,7 +5710,7 @@ define double @flat_agent_atomic_fadd_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execz .LBB30_4
@@ -5728,9 +5728,9 @@ define double @flat_agent_atomic_fadd_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB30_2
; GFX12-NEXT: ; %bb.3: ; %Flow
@@ -5738,19 +5738,19 @@ define double @flat_agent_atomic_fadd_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: .LBB30_4: ; %Flow3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB30_6
; GFX12-NEXT: ; %bb.5: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_add_f64_e32 v[0:1], v[4:5], v[2:3]
; GFX12-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX12-NEXT: .LBB30_6: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -5907,7 +5907,7 @@ define double @flat_agent_atomic_fadd_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX10-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen offset:4
; GFX10-NEXT: .LBB30_6: ; %atomicrmw.phi
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: v_mov_b32_e32 v1, v5
@@ -6143,21 +6143,21 @@ define double @flat_agent_atomic_fadd_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, 0x7f8, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v5
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB31_3
; GFX12-NEXT: ; %bb.1: ; %Flow3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execnz .LBB31_6
; GFX12-NEXT: .LBB31_2: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -6175,9 +6175,9 @@ define double @flat_agent_atomic_fadd_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB31_4
; GFX12-NEXT: ; %bb.5: ; %Flow
@@ -6188,13 +6188,13 @@ define double @flat_agent_atomic_fadd_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execz .LBB31_2
; GFX12-NEXT: .LBB31_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_add_f64_e32 v[2:3], v[0:1], v[2:3]
; GFX12-NEXT: scratch_store_b64 v4, v[2:3], off
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -6361,7 +6361,7 @@ define double @flat_agent_atomic_fadd_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX10-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]
; GFX10-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -6604,21 +6604,21 @@ define double @flat_agent_atomic_fadd_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v5, null, -1, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v5
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB32_3
; GFX12-NEXT: ; %bb.1: ; %Flow3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execnz .LBB32_6
; GFX12-NEXT: .LBB32_2: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -6636,9 +6636,9 @@ define double @flat_agent_atomic_fadd_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB32_4
; GFX12-NEXT: ; %bb.5: ; %Flow
@@ -6649,13 +6649,13 @@ define double @flat_agent_atomic_fadd_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execz .LBB32_2
; GFX12-NEXT: .LBB32_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_add_f64_e32 v[2:3], v[0:1], v[2:3]
; GFX12-NEXT: scratch_store_b64 v4, v[2:3], off
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -6823,7 +6823,7 @@ define double @flat_agent_atomic_fadd_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX10-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]
; GFX10-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -7067,16 +7067,16 @@ define void @flat_agent_atomic_fadd_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB33_3
; GFX12-NEXT: ; %bb.1: ; %Flow3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execnz .LBB33_6
; GFX12-NEXT: .LBB33_2: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -7093,9 +7093,9 @@ define void @flat_agent_atomic_fadd_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB33_4
; GFX12-NEXT: ; %bb.5: ; %Flow
@@ -7106,13 +7106,13 @@ define void @flat_agent_atomic_fadd_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_cbranch_execz .LBB33_2
; GFX12-NEXT: .LBB33_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_add_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: scratch_store_b64 v4, v[0:1], off
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -7267,7 +7267,7 @@ define void @flat_agent_atomic_fadd_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX10-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
; GFX10-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -7496,20 +7496,20 @@ define void @flat_agent_atomic_fadd_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, 0x7f8, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB34_3
; GFX12-NEXT: ; %bb.1: ; %Flow3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execnz .LBB34_6
; GFX12-NEXT: .LBB34_2: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -7526,9 +7526,9 @@ define void @flat_agent_atomic_fadd_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB34_4
; GFX12-NEXT: ; %bb.5: ; %Flow
@@ -7539,13 +7539,13 @@ define void @flat_agent_atomic_fadd_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execz .LBB34_2
; GFX12-NEXT: .LBB34_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_add_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: scratch_store_b64 v4, v[0:1], off
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -7707,7 +7707,7 @@ define void @flat_agent_atomic_fadd_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX10-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
; GFX10-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -7945,20 +7945,20 @@ define void @flat_agent_atomic_fadd_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB35_3
; GFX12-NEXT: ; %bb.1: ; %Flow3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execnz .LBB35_6
; GFX12-NEXT: .LBB35_2: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -7975,9 +7975,9 @@ define void @flat_agent_atomic_fadd_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB35_4
; GFX12-NEXT: ; %bb.5: ; %Flow
@@ -7988,13 +7988,13 @@ define void @flat_agent_atomic_fadd_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execz .LBB35_2
; GFX12-NEXT: .LBB35_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_add_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: scratch_store_b64 v4, v[0:1], off
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -8157,7 +8157,7 @@ define void @flat_agent_atomic_fadd_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX10-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
; GFX10-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -8424,9 +8424,9 @@ define half @flat_agent_atomic_fadd_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB36_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8469,9 +8469,9 @@ define half @flat_agent_atomic_fadd_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB36_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8771,7 +8771,7 @@ define half @flat_agent_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -8797,9 +8797,9 @@ define half @flat_agent_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB37_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8816,7 +8816,7 @@ define half @flat_agent_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -8843,9 +8843,9 @@ define half @flat_agent_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB37_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9155,7 +9155,7 @@ define half @flat_agent_atomic_fadd_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -9181,9 +9181,9 @@ define half @flat_agent_atomic_fadd_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB38_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9200,7 +9200,7 @@ define half @flat_agent_atomic_fadd_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -9227,9 +9227,9 @@ define half @flat_agent_atomic_fadd_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB38_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9565,9 +9565,9 @@ define void @flat_agent_atomic_fadd_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB39_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9608,9 +9608,9 @@ define void @flat_agent_atomic_fadd_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB39_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9899,7 +9899,7 @@ define void @flat_agent_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -9925,9 +9925,9 @@ define void @flat_agent_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB40_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9943,7 +9943,7 @@ define void @flat_agent_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -9969,9 +9969,9 @@ define void @flat_agent_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB40_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10270,7 +10270,7 @@ define void @flat_agent_atomic_fadd_noret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -10296,9 +10296,9 @@ define void @flat_agent_atomic_fadd_noret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB41_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10314,7 +10314,7 @@ define void @flat_agent_atomic_fadd_noret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -10340,9 +10340,9 @@ define void @flat_agent_atomic_fadd_noret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB41_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10656,9 +10656,9 @@ define void @flat_agent_atomic_fadd_noret_f16__offset12b__align4_pos__amdgpu_no_
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB42_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10688,9 +10688,9 @@ define void @flat_agent_atomic_fadd_noret_f16__offset12b__align4_pos__amdgpu_no_
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB42_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10930,9 +10930,9 @@ define half @flat_agent_atomic_fadd_ret_f16__offset12b_pos__align4__amdgpu_no_fi
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB43_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10964,9 +10964,9 @@ define half @flat_agent_atomic_fadd_ret_f16__offset12b_pos__align4__amdgpu_no_fi
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB43_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11200,7 +11200,7 @@ define half @flat_system_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -11227,9 +11227,9 @@ define half @flat_system_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB44_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11246,7 +11246,7 @@ define half @flat_system_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -11274,9 +11274,9 @@ define half @flat_system_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB44_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11588,7 +11588,7 @@ define void @flat_system_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -11615,9 +11615,9 @@ define void @flat_system_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB45_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11633,7 +11633,7 @@ define void @flat_system_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -11660,9 +11660,9 @@ define void @flat_system_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB45_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11993,7 +11993,7 @@ define bfloat @flat_agent_atomic_fadd_ret_bf16__amdgpu_no_fine_grained_memory(pt
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -12005,9 +12005,9 @@ define bfloat @flat_agent_atomic_fadd_ret_bf16__amdgpu_no_fine_grained_memory(pt
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB46_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12047,7 +12047,7 @@ define bfloat @flat_agent_atomic_fadd_ret_bf16__amdgpu_no_fine_grained_memory(pt
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -12059,9 +12059,9 @@ define bfloat @flat_agent_atomic_fadd_ret_bf16__amdgpu_no_fine_grained_memory(pt
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB46_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12419,7 +12419,7 @@ define bfloat @flat_agent_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -12446,7 +12446,7 @@ define bfloat @flat_agent_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -12458,9 +12458,9 @@ define bfloat @flat_agent_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB47_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12477,7 +12477,7 @@ define bfloat @flat_agent_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -12503,7 +12503,7 @@ define bfloat @flat_agent_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -12515,9 +12515,9 @@ define bfloat @flat_agent_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB47_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12886,7 +12886,7 @@ define bfloat @flat_agent_atomic_fadd_ret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -12913,7 +12913,7 @@ define bfloat @flat_agent_atomic_fadd_ret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -12925,9 +12925,9 @@ define bfloat @flat_agent_atomic_fadd_ret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB48_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12944,7 +12944,7 @@ define bfloat @flat_agent_atomic_fadd_ret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -12970,7 +12970,7 @@ define bfloat @flat_agent_atomic_fadd_ret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -12982,9 +12982,9 @@ define bfloat @flat_agent_atomic_fadd_ret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB48_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13354,7 +13354,7 @@ define void @flat_agent_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -13379,7 +13379,7 @@ define void @flat_agent_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -13392,9 +13392,9 @@ define void @flat_agent_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB49_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13410,7 +13410,7 @@ define void @flat_agent_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -13434,7 +13434,7 @@ define void @flat_agent_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -13447,9 +13447,9 @@ define void @flat_agent_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB49_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13806,7 +13806,7 @@ define void @flat_agent_atomic_fadd_noret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -13831,7 +13831,7 @@ define void @flat_agent_atomic_fadd_noret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -13844,9 +13844,9 @@ define void @flat_agent_atomic_fadd_noret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB50_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13862,7 +13862,7 @@ define void @flat_agent_atomic_fadd_noret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -13886,7 +13886,7 @@ define void @flat_agent_atomic_fadd_noret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -13899,9 +13899,9 @@ define void @flat_agent_atomic_fadd_noret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB50_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14275,7 +14275,7 @@ define bfloat @flat_agent_atomic_fadd_ret_bf16__offset12b_pos__align4__amdgpu_no
; GFX12-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.h
@@ -14286,9 +14286,9 @@ define bfloat @flat_agent_atomic_fadd_ret_bf16__offset12b_pos__align4__amdgpu_no
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB51_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14319,7 +14319,7 @@ define bfloat @flat_agent_atomic_fadd_ret_bf16__offset12b_pos__align4__amdgpu_no
; GFX12-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -14330,9 +14330,9 @@ define bfloat @flat_agent_atomic_fadd_ret_bf16__offset12b_pos__align4__amdgpu_no
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB51_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14647,7 +14647,7 @@ define void @flat_agent_atomic_fadd_noret_bf16__offset12b__align4_pos__amdgpu_no
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.h
@@ -14658,9 +14658,9 @@ define void @flat_agent_atomic_fadd_noret_bf16__offset12b__align4_pos__amdgpu_no
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB52_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14689,7 +14689,7 @@ define void @flat_agent_atomic_fadd_noret_bf16__offset12b__align4_pos__amdgpu_no
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -14700,9 +14700,9 @@ define void @flat_agent_atomic_fadd_noret_bf16__offset12b__align4_pos__amdgpu_no
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB52_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15017,7 +15017,7 @@ define void @flat_agent_atomic_fadd_noret_bf16__amdgpu_no_fine_grained_memory(pt
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -15030,9 +15030,9 @@ define void @flat_agent_atomic_fadd_noret_bf16__amdgpu_no_fine_grained_memory(pt
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB53_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15069,7 +15069,7 @@ define void @flat_agent_atomic_fadd_noret_bf16__amdgpu_no_fine_grained_memory(pt
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -15082,9 +15082,9 @@ define void @flat_agent_atomic_fadd_noret_bf16__amdgpu_no_fine_grained_memory(pt
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB53_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15430,7 +15430,7 @@ define bfloat @flat_system_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -15457,7 +15457,7 @@ define bfloat @flat_system_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -15470,9 +15470,9 @@ define bfloat @flat_system_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB54_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15489,7 +15489,7 @@ define bfloat @flat_system_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -15515,7 +15515,7 @@ define bfloat @flat_system_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -15528,9 +15528,9 @@ define bfloat @flat_system_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB54_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15901,7 +15901,7 @@ define void @flat_system_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -15926,7 +15926,7 @@ define void @flat_system_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -15940,9 +15940,9 @@ define void @flat_system_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB55_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15958,7 +15958,7 @@ define void @flat_system_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -15982,7 +15982,7 @@ define void @flat_system_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -15996,9 +15996,9 @@ define void @flat_system_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB55_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
index 4509ab8425547..8aa1a35f3c608 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
@@ -2802,7 +2802,7 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execz .LBB18_4
@@ -2821,9 +2821,9 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB18_2
; GFX12-NEXT: ; %bb.3: ; %Flow
@@ -2831,12 +2831,12 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX12-NEXT: .LBB18_4: ; %Flow2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB18_6
; GFX12-NEXT: ; %bb.5: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[2:3], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -2845,7 +2845,7 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
; GFX12-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX12-NEXT: .LBB18_6: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -2957,7 +2957,7 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX10-NEXT: s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT: s_cbranch_execnz .LBB18_4
; GFX10-NEXT: .LBB18_2: ; %atomicrmw.phi
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
; GFX10-NEXT: .LBB18_3: ; %atomicrmw.global
@@ -2982,7 +2982,7 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX10-NEXT: v_max_f64 v[2:3], v[4:5], v[2:3]
; GFX10-NEXT: buffer_store_dword v2, v6, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen offset:4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -3190,21 +3190,21 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, 0x7f8, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v5
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB19_3
; GFX12-NEXT: ; %bb.1: ; %Flow2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execnz .LBB19_6
; GFX12-NEXT: .LBB19_2: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -3223,9 +3223,9 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB19_4
; GFX12-NEXT: ; %bb.5: ; %Flow
@@ -3236,7 +3236,7 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execz .LBB19_2
; GFX12-NEXT: .LBB19_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[0:1], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -3244,7 +3244,7 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[2:3]
; GFX12-NEXT: scratch_store_b64 v6, v[2:3], off
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -3360,7 +3360,7 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX10-NEXT: s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT: s_cbranch_execnz .LBB19_4
; GFX10-NEXT: .LBB19_2: ; %atomicrmw.phi
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
; GFX10-NEXT: .LBB19_3: ; %atomicrmw.global
@@ -3385,7 +3385,7 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX10-NEXT: v_max_f64 v[2:3], v[4:5], v[2:3]
; GFX10-NEXT: buffer_store_dword v2, v6, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen offset:4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -3602,21 +3602,21 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v5, null, -1, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v5
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB20_3
; GFX12-NEXT: ; %bb.1: ; %Flow2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execnz .LBB20_6
; GFX12-NEXT: .LBB20_2: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -3635,9 +3635,9 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB20_4
; GFX12-NEXT: ; %bb.5: ; %Flow
@@ -3648,7 +3648,7 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execz .LBB20_2
; GFX12-NEXT: .LBB20_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[0:1], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -3656,7 +3656,7 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[2:3]
; GFX12-NEXT: scratch_store_b64 v6, v[2:3], off
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -3773,7 +3773,7 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX10-NEXT: s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT: s_cbranch_execnz .LBB20_4
; GFX10-NEXT: .LBB20_2: ; %atomicrmw.phi
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
; GFX10-NEXT: .LBB20_3: ; %atomicrmw.global
@@ -3798,7 +3798,7 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX10-NEXT: v_max_f64 v[2:3], v[4:5], v[2:3]
; GFX10-NEXT: buffer_store_dword v2, v6, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen offset:4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -4016,16 +4016,16 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB21_3
; GFX12-NEXT: ; %bb.1: ; %Flow2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execnz .LBB21_6
; GFX12-NEXT: .LBB21_2: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4044,9 +4044,9 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB21_4
; GFX12-NEXT: ; %bb.5: ; %Flow
@@ -4057,7 +4057,7 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_cbranch_execz .LBB21_2
; GFX12-NEXT: .LBB21_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v2, -1, v0, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[0:1], v2, off
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -4065,7 +4065,7 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[6:7]
; GFX12-NEXT: scratch_store_b64 v2, v[0:1], off
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -4171,7 +4171,7 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX10-NEXT: s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT: s_cbranch_execnz .LBB21_4
; GFX10-NEXT: .LBB21_2: ; %atomicrmw.phi
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
; GFX10-NEXT: .LBB21_3: ; %atomicrmw.global
@@ -4197,7 +4197,7 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX10-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
; GFX10-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -4401,20 +4401,20 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
; GFX12-NEXT: v_add_co_u32 v6, vcc_lo, 0x7f8, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v7
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB22_3
; GFX12-NEXT: ; %bb.1: ; %Flow2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execnz .LBB22_6
; GFX12-NEXT: .LBB22_2: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4433,9 +4433,9 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB22_4
; GFX12-NEXT: ; %bb.5: ; %Flow
@@ -4446,7 +4446,7 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execz .LBB22_2
; GFX12-NEXT: .LBB22_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[0:1], v2, off
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -4454,7 +4454,7 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
; GFX12-NEXT: scratch_store_b64 v2, v[0:1], off
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -4567,7 +4567,7 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX10-NEXT: s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT: s_cbranch_execnz .LBB22_4
; GFX10-NEXT: .LBB22_2: ; %atomicrmw.phi
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
; GFX10-NEXT: .LBB22_3: ; %atomicrmw.global
@@ -4593,7 +4593,7 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX10-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
; GFX10-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -4806,20 +4806,20 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
; GFX12-NEXT: v_add_co_u32 v6, vcc_lo, 0xfffff800, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, -1, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v7
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB23_3
; GFX12-NEXT: ; %bb.1: ; %Flow2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execnz .LBB23_6
; GFX12-NEXT: .LBB23_2: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4838,9 +4838,9 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB23_4
; GFX12-NEXT: ; %bb.5: ; %Flow
@@ -4851,7 +4851,7 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execz .LBB23_2
; GFX12-NEXT: .LBB23_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[0:1], v2, off
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -4859,7 +4859,7 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
; GFX12-NEXT: scratch_store_b64 v2, v[0:1], off
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -4973,7 +4973,7 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX10-NEXT: s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT: s_cbranch_execnz .LBB23_4
; GFX10-NEXT: .LBB23_2: ; %atomicrmw.phi
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
; GFX10-NEXT: .LBB23_3: ; %atomicrmw.global
@@ -4999,7 +4999,7 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX10-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
; GFX10-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -5214,7 +5214,7 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execz .LBB24_4
@@ -5233,9 +5233,9 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB24_2
; GFX12-NEXT: ; %bb.3: ; %Flow
@@ -5243,12 +5243,12 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX12-NEXT: .LBB24_4: ; %Flow2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB24_6
; GFX12-NEXT: ; %bb.5: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[2:3], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -5257,7 +5257,7 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
; GFX12-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX12-NEXT: .LBB24_6: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -5402,7 +5402,7 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX10-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen offset:4
; GFX10-NEXT: .LBB24_6: ; %atomicrmw.phi
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: v_mov_b32_e32 v0, v2
; GFX10-NEXT: v_mov_b32_e32 v1, v3
@@ -5638,7 +5638,7 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execz .LBB25_4
@@ -5657,9 +5657,9 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB25_2
; GFX12-NEXT: ; %bb.3: ; %Flow
@@ -5667,12 +5667,12 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX12-NEXT: .LBB25_4: ; %Flow2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB25_6
; GFX12-NEXT: ; %bb.5: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[2:3], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -5681,7 +5681,7 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[4:5]
; GFX12-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX12-NEXT: .LBB25_6: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -5793,7 +5793,7 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX10-NEXT: s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT: s_cbranch_execnz .LBB25_4
; GFX10-NEXT: .LBB25_2: ; %atomicrmw.phi
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
; GFX10-NEXT: .LBB25_3: ; %atomicrmw.global
@@ -5818,7 +5818,7 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX10-NEXT: v_max_f64 v[2:3], v[4:5], v[2:3]
; GFX10-NEXT: buffer_store_dword v2, v6, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen offset:4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -6057,9 +6057,9 @@ define half @flat_agent_atomic_fmax_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB26_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6104,9 +6104,9 @@ define half @flat_agent_atomic_fmax_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB26_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6421,7 +6421,7 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
@@ -6452,9 +6452,9 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6471,7 +6471,7 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -6501,9 +6501,9 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6830,7 +6830,7 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
@@ -6861,9 +6861,9 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB28_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6880,7 +6880,7 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -6910,9 +6910,9 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB28_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7267,9 +7267,9 @@ define void @flat_agent_atomic_fmax_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB29_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7313,9 +7313,9 @@ define void @flat_agent_atomic_fmax_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB29_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7619,7 +7619,7 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
@@ -7649,9 +7649,9 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB30_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7667,7 +7667,7 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -7697,9 +7697,9 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB30_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8015,7 +8015,7 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
@@ -8045,9 +8045,9 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB31_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8063,7 +8063,7 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -8093,9 +8093,9 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB31_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8429,9 +8429,9 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_pos__align4__amdgpu_no_fi
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB32_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8465,9 +8465,9 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_pos__align4__amdgpu_no_fi
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB32_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8732,9 +8732,9 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b__align4_pos__amdgpu_no_
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB33_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8767,9 +8767,9 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b__align4_pos__amdgpu_no_
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB33_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9010,7 +9010,7 @@ define half @flat_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
@@ -9042,9 +9042,9 @@ define half @flat_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB34_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9061,7 +9061,7 @@ define half @flat_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -9092,9 +9092,9 @@ define half @flat_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB34_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9423,7 +9423,7 @@ define void @flat_system_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
@@ -9454,9 +9454,9 @@ define void @flat_system_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB35_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9472,7 +9472,7 @@ define void @flat_system_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -9503,9 +9503,9 @@ define void @flat_system_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB35_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9853,7 +9853,7 @@ define bfloat @flat_agent_atomic_fmax_ret_bf16__amdgpu_no_fine_grained_memory(pt
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -9865,9 +9865,9 @@ define bfloat @flat_agent_atomic_fmax_ret_bf16__amdgpu_no_fine_grained_memory(pt
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB36_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9907,7 +9907,7 @@ define bfloat @flat_agent_atomic_fmax_ret_bf16__amdgpu_no_fine_grained_memory(pt
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -9919,9 +9919,9 @@ define bfloat @flat_agent_atomic_fmax_ret_bf16__amdgpu_no_fine_grained_memory(pt
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB36_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10280,7 +10280,7 @@ define bfloat @flat_agent_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -10307,7 +10307,7 @@ define bfloat @flat_agent_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -10319,9 +10319,9 @@ define bfloat @flat_agent_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB37_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10338,7 +10338,7 @@ define bfloat @flat_agent_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -10364,7 +10364,7 @@ define bfloat @flat_agent_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -10376,9 +10376,9 @@ define bfloat @flat_agent_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB37_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10748,7 +10748,7 @@ define bfloat @flat_agent_atomic_fmax_ret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -10775,7 +10775,7 @@ define bfloat @flat_agent_atomic_fmax_ret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -10787,9 +10787,9 @@ define bfloat @flat_agent_atomic_fmax_ret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB38_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10806,7 +10806,7 @@ define bfloat @flat_agent_atomic_fmax_ret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -10832,7 +10832,7 @@ define bfloat @flat_agent_atomic_fmax_ret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -10844,9 +10844,9 @@ define bfloat @flat_agent_atomic_fmax_ret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB38_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11241,7 +11241,7 @@ define void @flat_agent_atomic_fmax_noret_bf16__amdgpu_no_fine_grained_memory(pt
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -11254,9 +11254,9 @@ define void @flat_agent_atomic_fmax_noret_bf16__amdgpu_no_fine_grained_memory(pt
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB39_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11293,7 +11293,7 @@ define void @flat_agent_atomic_fmax_noret_bf16__amdgpu_no_fine_grained_memory(pt
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -11306,9 +11306,9 @@ define void @flat_agent_atomic_fmax_noret_bf16__amdgpu_no_fine_grained_memory(pt
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB39_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11655,7 +11655,7 @@ define void @flat_agent_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -11680,7 +11680,7 @@ define void @flat_agent_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -11693,9 +11693,9 @@ define void @flat_agent_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB40_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11711,7 +11711,7 @@ define void @flat_agent_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -11735,7 +11735,7 @@ define void @flat_agent_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -11748,9 +11748,9 @@ define void @flat_agent_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB40_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12108,7 +12108,7 @@ define void @flat_agent_atomic_fmax_noret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -12133,7 +12133,7 @@ define void @flat_agent_atomic_fmax_noret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -12146,9 +12146,9 @@ define void @flat_agent_atomic_fmax_noret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB41_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12164,7 +12164,7 @@ define void @flat_agent_atomic_fmax_noret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -12188,7 +12188,7 @@ define void @flat_agent_atomic_fmax_noret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -12201,9 +12201,9 @@ define void @flat_agent_atomic_fmax_noret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB41_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12578,7 +12578,7 @@ define bfloat @flat_agent_atomic_fmax_ret_bf16__offset12b_pos__align4__amdgpu_no
; GFX12-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.h
@@ -12589,9 +12589,9 @@ define bfloat @flat_agent_atomic_fmax_ret_bf16__offset12b_pos__align4__amdgpu_no
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB42_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12622,7 +12622,7 @@ define bfloat @flat_agent_atomic_fmax_ret_bf16__offset12b_pos__align4__amdgpu_no
; GFX12-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -12633,9 +12633,9 @@ define bfloat @flat_agent_atomic_fmax_ret_bf16__offset12b_pos__align4__amdgpu_no
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB42_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12951,7 +12951,7 @@ define void @flat_agent_atomic_fmax_noret_bf16__offset12b__align4_pos__amdgpu_no
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.h
@@ -12962,9 +12962,9 @@ define void @flat_agent_atomic_fmax_noret_bf16__offset12b__align4_pos__amdgpu_no
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB43_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12993,7 +12993,7 @@ define void @flat_agent_atomic_fmax_noret_bf16__offset12b__align4_pos__amdgpu_no
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -13004,9 +13004,9 @@ define void @flat_agent_atomic_fmax_noret_bf16__offset12b__align4_pos__amdgpu_no
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB43_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13298,7 +13298,7 @@ define bfloat @flat_system_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -13325,7 +13325,7 @@ define bfloat @flat_system_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -13338,9 +13338,9 @@ define bfloat @flat_system_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB44_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13357,7 +13357,7 @@ define bfloat @flat_system_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -13383,7 +13383,7 @@ define bfloat @flat_system_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -13396,9 +13396,9 @@ define bfloat @flat_system_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB44_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13770,7 +13770,7 @@ define void @flat_system_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -13795,7 +13795,7 @@ define void @flat_system_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -13809,9 +13809,9 @@ define void @flat_system_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB45_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13827,7 +13827,7 @@ define void @flat_system_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -13851,7 +13851,7 @@ define void @flat_system_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -13865,9 +13865,9 @@ define void @flat_system_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB45_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14245,9 +14245,9 @@ define <2 x half> @flat_agent_atomic_fmax_ret_v2f16__amdgpu_no_fine_grained_memo
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB46_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14481,9 +14481,9 @@ define <2 x half> @flat_agent_atomic_fmax_ret_v2f16__offset12b_pos__amdgpu_no_fi
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB47_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14720,9 +14720,9 @@ define <2 x half> @flat_agent_atomic_fmax_ret_v2f16__offset12b_neg__amdgpu_no_fi
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB48_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14974,9 +14974,9 @@ define void @flat_agent_atomic_fmax_noret_v2f16__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB49_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15201,9 +15201,9 @@ define void @flat_agent_atomic_fmax_noret_v2f16__offset12b_pos__amdgpu_no_fine_g
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB50_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15435,9 +15435,9 @@ define void @flat_agent_atomic_fmax_noret_v2f16__offset12b_neg__amdgpu_no_fine_g
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB51_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15689,9 +15689,9 @@ define <2 x half> @flat_system_atomic_fmax_ret_v2f16__offset12b_pos__amdgpu_no_f
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB52_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15931,9 +15931,9 @@ define void @flat_system_atomic_fmax_noret_v2f16__offset12b_pos__amdgpu_no_fine_
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB53_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16179,10 +16179,10 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
@@ -16191,9 +16191,9 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB54_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16231,10 +16231,10 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
@@ -16243,9 +16243,9 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB54_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16626,10 +16626,10 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
@@ -16638,9 +16638,9 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB55_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16678,10 +16678,10 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
@@ -16690,9 +16690,9 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB55_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17076,10 +17076,10 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
@@ -17088,9 +17088,9 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB56_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17128,10 +17128,10 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
@@ -17140,9 +17140,9 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB56_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17539,11 +17539,11 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -17552,9 +17552,9 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB57_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17590,10 +17590,10 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
@@ -17603,9 +17603,9 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB57_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17971,11 +17971,11 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -17984,9 +17984,9 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB58_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18022,10 +18022,10 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
@@ -18035,9 +18035,9 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB58_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18410,11 +18410,11 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -18423,9 +18423,9 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB59_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18461,10 +18461,10 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
@@ -18474,9 +18474,9 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB59_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18874,10 +18874,10 @@ define <2 x bfloat> @flat_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
@@ -18887,9 +18887,9 @@ define <2 x bfloat> @flat_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB60_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18927,10 +18927,10 @@ define <2 x bfloat> @flat_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
@@ -18940,9 +18940,9 @@ define <2 x bfloat> @flat_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB60_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -19325,11 +19325,11 @@ define void @flat_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
@@ -19339,9 +19339,9 @@ define void @flat_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB61_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -19377,10 +19377,10 @@ define void @flat_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
@@ -19391,9 +19391,9 @@ define void @flat_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB61_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
index 62a3c7960c9f6..be3143da0a95c 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
@@ -2802,7 +2802,7 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execz .LBB18_4
@@ -2821,9 +2821,9 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB18_2
; GFX12-NEXT: ; %bb.3: ; %Flow
@@ -2831,12 +2831,12 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX12-NEXT: .LBB18_4: ; %Flow2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB18_6
; GFX12-NEXT: ; %bb.5: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[2:3], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -2845,7 +2845,7 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
; GFX12-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX12-NEXT: .LBB18_6: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -2957,7 +2957,7 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX10-NEXT: s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT: s_cbranch_execnz .LBB18_4
; GFX10-NEXT: .LBB18_2: ; %atomicrmw.phi
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
; GFX10-NEXT: .LBB18_3: ; %atomicrmw.global
@@ -2982,7 +2982,7 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX10-NEXT: v_min_f64 v[2:3], v[4:5], v[2:3]
; GFX10-NEXT: buffer_store_dword v2, v6, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen offset:4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -3190,21 +3190,21 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, 0x7f8, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v5
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB19_3
; GFX12-NEXT: ; %bb.1: ; %Flow2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execnz .LBB19_6
; GFX12-NEXT: .LBB19_2: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -3223,9 +3223,9 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB19_4
; GFX12-NEXT: ; %bb.5: ; %Flow
@@ -3236,7 +3236,7 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execz .LBB19_2
; GFX12-NEXT: .LBB19_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[0:1], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -3244,7 +3244,7 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[4:5], v[2:3]
; GFX12-NEXT: scratch_store_b64 v6, v[2:3], off
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -3360,7 +3360,7 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX10-NEXT: s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT: s_cbranch_execnz .LBB19_4
; GFX10-NEXT: .LBB19_2: ; %atomicrmw.phi
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
; GFX10-NEXT: .LBB19_3: ; %atomicrmw.global
@@ -3385,7 +3385,7 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX10-NEXT: v_min_f64 v[2:3], v[4:5], v[2:3]
; GFX10-NEXT: buffer_store_dword v2, v6, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen offset:4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -3602,21 +3602,21 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v5, null, -1, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v5
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB20_3
; GFX12-NEXT: ; %bb.1: ; %Flow2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execnz .LBB20_6
; GFX12-NEXT: .LBB20_2: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -3635,9 +3635,9 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB20_4
; GFX12-NEXT: ; %bb.5: ; %Flow
@@ -3648,7 +3648,7 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execz .LBB20_2
; GFX12-NEXT: .LBB20_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v4, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[0:1], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -3656,7 +3656,7 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[4:5], v[2:3]
; GFX12-NEXT: scratch_store_b64 v6, v[2:3], off
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -3773,7 +3773,7 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX10-NEXT: s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT: s_cbranch_execnz .LBB20_4
; GFX10-NEXT: .LBB20_2: ; %atomicrmw.phi
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
; GFX10-NEXT: .LBB20_3: ; %atomicrmw.global
@@ -3798,7 +3798,7 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX10-NEXT: v_min_f64 v[2:3], v[4:5], v[2:3]
; GFX10-NEXT: buffer_store_dword v2, v6, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen offset:4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -4016,16 +4016,16 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: v_max_num_f64_e32 v[6:7], v[2:3], v[2:3]
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB21_3
; GFX12-NEXT: ; %bb.1: ; %Flow2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execnz .LBB21_6
; GFX12-NEXT: .LBB21_2: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4044,9 +4044,9 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB21_4
; GFX12-NEXT: ; %bb.5: ; %Flow
@@ -4057,7 +4057,7 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_cbranch_execz .LBB21_2
; GFX12-NEXT: .LBB21_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v2, -1, v0, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[0:1], v2, off
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -4065,7 +4065,7 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[6:7]
; GFX12-NEXT: scratch_store_b64 v2, v[0:1], off
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -4171,7 +4171,7 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX10-NEXT: s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT: s_cbranch_execnz .LBB21_4
; GFX10-NEXT: .LBB21_2: ; %atomicrmw.phi
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
; GFX10-NEXT: .LBB21_3: ; %atomicrmw.global
@@ -4197,7 +4197,7 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr
; GFX10-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
; GFX10-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -4401,20 +4401,20 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
; GFX12-NEXT: v_add_co_u32 v6, vcc_lo, 0x7f8, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v7
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB22_3
; GFX12-NEXT: ; %bb.1: ; %Flow2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execnz .LBB22_6
; GFX12-NEXT: .LBB22_2: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4433,9 +4433,9 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB22_4
; GFX12-NEXT: ; %bb.5: ; %Flow
@@ -4446,7 +4446,7 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execz .LBB22_2
; GFX12-NEXT: .LBB22_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[0:1], v2, off
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -4454,7 +4454,7 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
; GFX12-NEXT: scratch_store_b64 v2, v[0:1], off
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -4567,7 +4567,7 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX10-NEXT: s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT: s_cbranch_execnz .LBB22_4
; GFX10-NEXT: .LBB22_2: ; %atomicrmw.phi
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
; GFX10-NEXT: .LBB22_3: ; %atomicrmw.global
@@ -4593,7 +4593,7 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_gra
; GFX10-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
; GFX10-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -4806,20 +4806,20 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_max_num_f64_e32 v[4:5], v[2:3], v[2:3]
; GFX12-NEXT: v_add_co_u32 v6, vcc_lo, 0xfffff800, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, -1, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v7
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB23_3
; GFX12-NEXT: ; %bb.1: ; %Flow2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execnz .LBB23_6
; GFX12-NEXT: .LBB23_2: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4838,9 +4838,9 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
; GFX12-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB23_4
; GFX12-NEXT: ; %bb.5: ; %Flow
@@ -4851,7 +4851,7 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_cbranch_execz .LBB23_2
; GFX12-NEXT: .LBB23_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v2, -1, v6, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[0:1], v2, off
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -4859,7 +4859,7 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
; GFX12-NEXT: scratch_store_b64 v2, v[0:1], off
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -4973,7 +4973,7 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX10-NEXT: s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT: s_cbranch_execnz .LBB23_4
; GFX10-NEXT: .LBB23_2: ; %atomicrmw.phi
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
; GFX10-NEXT: .LBB23_3: ; %atomicrmw.global
@@ -4999,7 +4999,7 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_gra
; GFX10-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
; GFX10-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -5214,7 +5214,7 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execz .LBB24_4
@@ -5233,9 +5233,9 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB24_2
; GFX12-NEXT: ; %bb.3: ; %Flow
@@ -5243,12 +5243,12 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX12-NEXT: .LBB24_4: ; %Flow2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB24_6
; GFX12-NEXT: ; %bb.5: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[2:3], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -5257,7 +5257,7 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
; GFX12-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX12-NEXT: .LBB24_6: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -5402,7 +5402,7 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory(ptr %ptr,
; GFX10-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen offset:4
; GFX10-NEXT: .LBB24_6: ; %atomicrmw.phi
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: v_mov_b32_e32 v0, v2
; GFX10-NEXT: v_mov_b32_e32 v1, v3
@@ -5638,7 +5638,7 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execz .LBB25_4
@@ -5657,9 +5657,9 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[8:9]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB25_2
; GFX12-NEXT: ; %bb.3: ; %Flow
@@ -5667,12 +5667,12 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX12-NEXT: .LBB25_4: ; %Flow2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB25_6
; GFX12-NEXT: ; %bb.5: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[2:3], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -5681,7 +5681,7 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
; GFX12-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX12-NEXT: .LBB25_6: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -5793,7 +5793,7 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX10-NEXT: s_andn2_saveexec_b32 s4, s4
; GFX10-NEXT: s_cbranch_execnz .LBB25_4
; GFX10-NEXT: .LBB25_2: ; %atomicrmw.phi
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
; GFX10-NEXT: .LBB25_3: ; %atomicrmw.global
@@ -5818,7 +5818,7 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__am
; GFX10-NEXT: v_min_f64 v[2:3], v[4:5], v[2:3]
; GFX10-NEXT: buffer_store_dword v2, v6, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen offset:4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -6057,9 +6057,9 @@ define half @flat_agent_atomic_fmin_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB26_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6104,9 +6104,9 @@ define half @flat_agent_atomic_fmin_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB26_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6421,7 +6421,7 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
@@ -6452,9 +6452,9 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6471,7 +6471,7 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -6501,9 +6501,9 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6830,7 +6830,7 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
@@ -6861,9 +6861,9 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB28_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6880,7 +6880,7 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -6910,9 +6910,9 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB28_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7267,9 +7267,9 @@ define void @flat_agent_atomic_fmin_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB29_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7313,9 +7313,9 @@ define void @flat_agent_atomic_fmin_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB29_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7619,7 +7619,7 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
@@ -7649,9 +7649,9 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB30_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7667,7 +7667,7 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -7697,9 +7697,9 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB30_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8015,7 +8015,7 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
@@ -8045,9 +8045,9 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB31_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8063,7 +8063,7 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -8093,9 +8093,9 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB31_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8429,9 +8429,9 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_pos__align4__amdgpu_no_fi
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB32_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8465,9 +8465,9 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_pos__align4__amdgpu_no_fi
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB32_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8732,9 +8732,9 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b__align4_pos__amdgpu_no_
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB33_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8767,9 +8767,9 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b__align4_pos__amdgpu_no_
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB33_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9010,7 +9010,7 @@ define half @flat_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
@@ -9042,9 +9042,9 @@ define half @flat_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB34_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9061,7 +9061,7 @@ define half @flat_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -9092,9 +9092,9 @@ define half @flat_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB34_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9423,7 +9423,7 @@ define void @flat_system_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
@@ -9454,9 +9454,9 @@ define void @flat_system_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB35_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9472,7 +9472,7 @@ define void @flat_system_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -9503,9 +9503,9 @@ define void @flat_system_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB35_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9853,7 +9853,7 @@ define bfloat @flat_agent_atomic_fmin_ret_bf16__amdgpu_no_fine_grained_memory(pt
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -9865,9 +9865,9 @@ define bfloat @flat_agent_atomic_fmin_ret_bf16__amdgpu_no_fine_grained_memory(pt
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB36_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9907,7 +9907,7 @@ define bfloat @flat_agent_atomic_fmin_ret_bf16__amdgpu_no_fine_grained_memory(pt
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -9919,9 +9919,9 @@ define bfloat @flat_agent_atomic_fmin_ret_bf16__amdgpu_no_fine_grained_memory(pt
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB36_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10280,7 +10280,7 @@ define bfloat @flat_agent_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -10307,7 +10307,7 @@ define bfloat @flat_agent_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -10319,9 +10319,9 @@ define bfloat @flat_agent_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB37_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10338,7 +10338,7 @@ define bfloat @flat_agent_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -10364,7 +10364,7 @@ define bfloat @flat_agent_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -10376,9 +10376,9 @@ define bfloat @flat_agent_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB37_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10748,7 +10748,7 @@ define bfloat @flat_agent_atomic_fmin_ret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -10775,7 +10775,7 @@ define bfloat @flat_agent_atomic_fmin_ret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -10787,9 +10787,9 @@ define bfloat @flat_agent_atomic_fmin_ret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB38_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10806,7 +10806,7 @@ define bfloat @flat_agent_atomic_fmin_ret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -10832,7 +10832,7 @@ define bfloat @flat_agent_atomic_fmin_ret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -10844,9 +10844,9 @@ define bfloat @flat_agent_atomic_fmin_ret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB38_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11241,7 +11241,7 @@ define void @flat_agent_atomic_fmin_noret_bf16__amdgpu_no_fine_grained_memory(pt
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -11254,9 +11254,9 @@ define void @flat_agent_atomic_fmin_noret_bf16__amdgpu_no_fine_grained_memory(pt
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB39_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11293,7 +11293,7 @@ define void @flat_agent_atomic_fmin_noret_bf16__amdgpu_no_fine_grained_memory(pt
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -11306,9 +11306,9 @@ define void @flat_agent_atomic_fmin_noret_bf16__amdgpu_no_fine_grained_memory(pt
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB39_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11655,7 +11655,7 @@ define void @flat_agent_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -11680,7 +11680,7 @@ define void @flat_agent_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -11693,9 +11693,9 @@ define void @flat_agent_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB40_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11711,7 +11711,7 @@ define void @flat_agent_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -11735,7 +11735,7 @@ define void @flat_agent_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -11748,9 +11748,9 @@ define void @flat_agent_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB40_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12108,7 +12108,7 @@ define void @flat_agent_atomic_fmin_noret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -12133,7 +12133,7 @@ define void @flat_agent_atomic_fmin_noret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -12146,9 +12146,9 @@ define void @flat_agent_atomic_fmin_noret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB41_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12164,7 +12164,7 @@ define void @flat_agent_atomic_fmin_noret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -12188,7 +12188,7 @@ define void @flat_agent_atomic_fmin_noret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -12201,9 +12201,9 @@ define void @flat_agent_atomic_fmin_noret_bf16__offset12b_neg__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB41_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12578,7 +12578,7 @@ define bfloat @flat_agent_atomic_fmin_ret_bf16__offset12b_pos__align4__amdgpu_no
; GFX12-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.h
@@ -12589,9 +12589,9 @@ define bfloat @flat_agent_atomic_fmin_ret_bf16__offset12b_pos__align4__amdgpu_no
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB42_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12622,7 +12622,7 @@ define bfloat @flat_agent_atomic_fmin_ret_bf16__offset12b_pos__align4__amdgpu_no
; GFX12-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -12633,9 +12633,9 @@ define bfloat @flat_agent_atomic_fmin_ret_bf16__offset12b_pos__align4__amdgpu_no
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB42_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12951,7 +12951,7 @@ define void @flat_agent_atomic_fmin_noret_bf16__offset12b__align4_pos__amdgpu_no
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.h
@@ -12962,9 +12962,9 @@ define void @flat_agent_atomic_fmin_noret_bf16__offset12b__align4_pos__amdgpu_no
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB43_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12993,7 +12993,7 @@ define void @flat_agent_atomic_fmin_noret_bf16__offset12b__align4_pos__amdgpu_no
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -13004,9 +13004,9 @@ define void @flat_agent_atomic_fmin_noret_bf16__offset12b__align4_pos__amdgpu_no
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB43_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13298,7 +13298,7 @@ define bfloat @flat_system_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -13325,7 +13325,7 @@ define bfloat @flat_system_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -13338,9 +13338,9 @@ define bfloat @flat_system_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB44_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13357,7 +13357,7 @@ define bfloat @flat_system_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -13383,7 +13383,7 @@ define bfloat @flat_system_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -13396,9 +13396,9 @@ define bfloat @flat_system_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB44_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13770,7 +13770,7 @@ define void @flat_system_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -13795,7 +13795,7 @@ define void @flat_system_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -13809,9 +13809,9 @@ define void @flat_system_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB45_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13827,7 +13827,7 @@ define void @flat_system_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -13851,7 +13851,7 @@ define void @flat_system_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -13865,9 +13865,9 @@ define void @flat_system_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB45_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14245,9 +14245,9 @@ define <2 x half> @flat_agent_atomic_fmin_ret_v2f16__amdgpu_no_fine_grained_memo
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB46_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14481,9 +14481,9 @@ define <2 x half> @flat_agent_atomic_fmin_ret_v2f16__offset12b_pos__amdgpu_no_fi
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB47_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14720,9 +14720,9 @@ define <2 x half> @flat_agent_atomic_fmin_ret_v2f16__offset12b_neg__amdgpu_no_fi
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB48_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14974,9 +14974,9 @@ define void @flat_agent_atomic_fmin_noret_v2f16__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB49_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15201,9 +15201,9 @@ define void @flat_agent_atomic_fmin_noret_v2f16__offset12b_pos__amdgpu_no_fine_g
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB50_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15435,9 +15435,9 @@ define void @flat_agent_atomic_fmin_noret_v2f16__offset12b_neg__amdgpu_no_fine_g
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB51_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15689,9 +15689,9 @@ define <2 x half> @flat_system_atomic_fmin_ret_v2f16__offset12b_pos__amdgpu_no_f
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB52_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15931,9 +15931,9 @@ define void @flat_system_atomic_fmin_noret_v2f16__offset12b_pos__amdgpu_no_fine_
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB53_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16179,10 +16179,10 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
@@ -16191,9 +16191,9 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB54_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16231,10 +16231,10 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
@@ -16243,9 +16243,9 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB54_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16626,10 +16626,10 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
@@ -16638,9 +16638,9 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB55_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16678,10 +16678,10 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
@@ -16690,9 +16690,9 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB55_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17076,10 +17076,10 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
@@ -17088,9 +17088,9 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB56_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17128,10 +17128,10 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
@@ -17140,9 +17140,9 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB56_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17539,11 +17539,11 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -17552,9 +17552,9 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB57_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17590,10 +17590,10 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
@@ -17603,9 +17603,9 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB57_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17971,11 +17971,11 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -17984,9 +17984,9 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB58_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18022,10 +18022,10 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
@@ -18035,9 +18035,9 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB58_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18410,11 +18410,11 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -18423,9 +18423,9 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB59_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18461,10 +18461,10 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
@@ -18474,9 +18474,9 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB59_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18874,10 +18874,10 @@ define <2 x bfloat> @flat_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
@@ -18887,9 +18887,9 @@ define <2 x bfloat> @flat_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB60_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18927,10 +18927,10 @@ define <2 x bfloat> @flat_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
@@ -18940,9 +18940,9 @@ define <2 x bfloat> @flat_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB60_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -19325,11 +19325,11 @@ define void @flat_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
@@ -19339,9 +19339,9 @@ define void @flat_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB61_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -19377,10 +19377,10 @@ define void @flat_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
@@ -19391,9 +19391,9 @@ define void @flat_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB61_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
index 1be5cee57d2c0..37fad11cd5039 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
@@ -35,9 +35,9 @@ define float @flat_agent_atomic_fsub_ret_f32(ptr %ptr, float %val) #0 {
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB0_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -231,9 +231,9 @@ define float @flat_agent_atomic_fsub_ret_f32__offset12b_pos(ptr %ptr, float %val
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB1_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -431,9 +431,9 @@ define float @flat_agent_atomic_fsub_ret_f32__offset12b_neg(ptr %ptr, float %val
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB2_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -645,9 +645,9 @@ define void @flat_agent_atomic_fsub_noret_f32(ptr %ptr, float %val) #0 {
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB3_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -831,9 +831,9 @@ define void @flat_agent_atomic_fsub_noret_f32__offset12b_pos(ptr %ptr, float %va
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB4_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1024,9 +1024,9 @@ define void @flat_agent_atomic_fsub_noret_f32__offset12b_neg(ptr %ptr, float %va
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB5_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1238,9 +1238,9 @@ define float @flat_system_atomic_fsub_ret_f32__offset12b_pos(ptr %ptr, float %va
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB6_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1440,9 +1440,9 @@ define void @flat_system_atomic_fsub_noret_f32__offset12b_pos(ptr %ptr, float %v
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB7_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1640,9 +1640,9 @@ define float @flat_agent_atomic_fsub_ret_f32__ftz(ptr %ptr, float %val) #1 {
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB8_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1836,9 +1836,9 @@ define float @flat_agent_atomic_fsub_ret_f32__offset12b_pos__ftz(ptr %ptr, float
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB9_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2036,9 +2036,9 @@ define float @flat_agent_atomic_fsub_ret_f32__offset12b_neg__ftz(ptr %ptr, float
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB10_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2250,9 +2250,9 @@ define void @flat_agent_atomic_fsub_noret_f32__ftz(ptr %ptr, float %val) #1 {
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB11_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2436,9 +2436,9 @@ define void @flat_agent_atomic_fsub_noret_f32__offset12b_pos__ftz(ptr %ptr, floa
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB12_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2629,9 +2629,9 @@ define void @flat_agent_atomic_fsub_noret_f32__offset12b_neg__ftz(ptr %ptr, floa
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB13_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2843,9 +2843,9 @@ define float @flat_system_atomic_fsub_ret_f32__offset12b_pos__ftz(ptr %ptr, floa
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB14_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3045,9 +3045,9 @@ define void @flat_system_atomic_fsub_noret_f32__offset12b_pos__ftz(ptr %ptr, flo
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB15_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3235,7 +3235,7 @@ define double @flat_agent_atomic_fsub_ret_f64(ptr %ptr, double %val) #0 {
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execz .LBB16_4
@@ -3253,9 +3253,9 @@ define double @flat_agent_atomic_fsub_ret_f64(ptr %ptr, double %val) #0 {
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB16_2
; GFX12-NEXT: ; %bb.3: ; %Flow
@@ -3263,19 +3263,19 @@ define double @flat_agent_atomic_fsub_ret_f64(ptr %ptr, double %val) #0 {
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: .LBB16_4: ; %Flow3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execz .LBB16_6
; GFX12-NEXT: ; %bb.5: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, -1, v0, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_add_f64_e64 v[0:1], v[4:5], -v[2:3]
; GFX12-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX12-NEXT: .LBB16_6: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -3420,7 +3420,7 @@ define double @flat_agent_atomic_fsub_ret_f64(ptr %ptr, double %val) #0 {
; GFX10-NEXT: buffer_store_dword v0, v6, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen offset:4
; GFX10-NEXT: .LBB16_6: ; %atomicrmw.phi
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: v_mov_b32_e32 v1, v5
@@ -3645,21 +3645,21 @@ define double @flat_agent_atomic_fsub_ret_f64__offset12b_pos(ptr %ptr, double %v
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, 0x7f8, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v5
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB17_3
; GFX12-NEXT: ; %bb.1: ; %Flow3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execnz .LBB17_6
; GFX12-NEXT: .LBB17_2: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -3677,9 +3677,9 @@ define double @flat_agent_atomic_fsub_ret_f64__offset12b_pos(ptr %ptr, double %v
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB17_4
; GFX12-NEXT: ; %bb.5: ; %Flow
@@ -3690,13 +3690,13 @@ define double @flat_agent_atomic_fsub_ret_f64__offset12b_pos(ptr %ptr, double %v
; GFX12-NEXT: s_cbranch_execz .LBB17_2
; GFX12-NEXT: .LBB17_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_add_f64_e64 v[2:3], v[0:1], -v[2:3]
; GFX12-NEXT: scratch_store_b64 v4, v[2:3], off
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -3855,7 +3855,7 @@ define double @flat_agent_atomic_fsub_ret_f64__offset12b_pos(ptr %ptr, double %v
; GFX10-NEXT: v_add_f64 v[2:3], v[0:1], -v[2:3]
; GFX10-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -4091,21 +4091,21 @@ define double @flat_agent_atomic_fsub_ret_f64__offset12b_neg(ptr %ptr, double %v
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v5, null, -1, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v5
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB18_3
; GFX12-NEXT: ; %bb.1: ; %Flow3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execnz .LBB18_6
; GFX12-NEXT: .LBB18_2: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4123,9 +4123,9 @@ define double @flat_agent_atomic_fsub_ret_f64__offset12b_neg(ptr %ptr, double %v
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB18_4
; GFX12-NEXT: ; %bb.5: ; %Flow
@@ -4136,13 +4136,13 @@ define double @flat_agent_atomic_fsub_ret_f64__offset12b_neg(ptr %ptr, double %v
; GFX12-NEXT: s_cbranch_execz .LBB18_2
; GFX12-NEXT: .LBB18_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_add_f64_e64 v[2:3], v[0:1], -v[2:3]
; GFX12-NEXT: scratch_store_b64 v4, v[2:3], off
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -4302,7 +4302,7 @@ define double @flat_agent_atomic_fsub_ret_f64__offset12b_neg(ptr %ptr, double %v
; GFX10-NEXT: v_add_f64 v[2:3], v[0:1], -v[2:3]
; GFX10-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -4539,16 +4539,16 @@ define void @flat_agent_atomic_fsub_noret_f64(ptr %ptr, double %val) #0 {
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB19_3
; GFX12-NEXT: ; %bb.1: ; %Flow3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execnz .LBB19_6
; GFX12-NEXT: .LBB19_2: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4565,9 +4565,9 @@ define void @flat_agent_atomic_fsub_noret_f64(ptr %ptr, double %val) #0 {
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB19_4
; GFX12-NEXT: ; %bb.5: ; %Flow
@@ -4578,13 +4578,13 @@ define void @flat_agent_atomic_fsub_noret_f64(ptr %ptr, double %val) #0 {
; GFX12-NEXT: s_cbranch_execz .LBB19_2
; GFX12-NEXT: .LBB19_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_add_f64_e64 v[0:1], v[0:1], -v[2:3]
; GFX12-NEXT: scratch_store_b64 v4, v[0:1], off
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -4732,7 +4732,7 @@ define void @flat_agent_atomic_fsub_noret_f64(ptr %ptr, double %val) #0 {
; GFX10-NEXT: v_add_f64 v[0:1], v[0:1], -v[2:3]
; GFX10-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -4955,20 +4955,20 @@ define void @flat_agent_atomic_fsub_noret_f64__offset12b_pos(ptr %ptr, double %v
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, 0x7f8, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB20_3
; GFX12-NEXT: ; %bb.1: ; %Flow3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execnz .LBB20_6
; GFX12-NEXT: .LBB20_2: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -4985,9 +4985,9 @@ define void @flat_agent_atomic_fsub_noret_f64__offset12b_pos(ptr %ptr, double %v
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB20_4
; GFX12-NEXT: ; %bb.5: ; %Flow
@@ -4998,13 +4998,13 @@ define void @flat_agent_atomic_fsub_noret_f64__offset12b_pos(ptr %ptr, double %v
; GFX12-NEXT: s_cbranch_execz .LBB20_2
; GFX12-NEXT: .LBB20_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_add_f64_e64 v[0:1], v[0:1], -v[2:3]
; GFX12-NEXT: scratch_store_b64 v4, v[0:1], off
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -5159,7 +5159,7 @@ define void @flat_agent_atomic_fsub_noret_f64__offset12b_pos(ptr %ptr, double %v
; GFX10-NEXT: v_add_f64 v[0:1], v[0:1], -v[2:3]
; GFX10-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -5391,20 +5391,20 @@ define void @flat_agent_atomic_fsub_noret_f64__offset12b_neg(ptr %ptr, double %v
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX12-NEXT: s_mov_b32 s0, exec_lo
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cmpx_ne_u32_e64 s1, v1
; GFX12-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB21_3
; GFX12-NEXT: ; %bb.1: ; %Flow3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX12-NEXT: s_cbranch_execnz .LBB21_6
; GFX12-NEXT: .LBB21_2: ; %atomicrmw.phi
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -5421,9 +5421,9 @@ define void @flat_agent_atomic_fsub_noret_f64__offset12b_neg(ptr %ptr, double %v
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_cbranch_execnz .LBB21_4
; GFX12-NEXT: ; %bb.5: ; %Flow
@@ -5434,13 +5434,13 @@ define void @flat_agent_atomic_fsub_noret_f64__offset12b_neg(ptr %ptr, double %v
; GFX12-NEXT: s_cbranch_execz .LBB21_2
; GFX12-NEXT: .LBB21_6: ; %atomicrmw.private
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc_lo
; GFX12-NEXT: scratch_load_b64 v[0:1], v4, off
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_add_f64_e64 v[0:1], v[0:1], -v[2:3]
; GFX12-NEXT: scratch_store_b64 v4, v[0:1], off
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -5596,7 +5596,7 @@ define void @flat_agent_atomic_fsub_noret_f64__offset12b_neg(ptr %ptr, double %v
; GFX10-NEXT: v_add_f64 v[0:1], v[0:1], -v[2:3]
; GFX10-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
; GFX10-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen offset:4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -5857,9 +5857,9 @@ define half @flat_agent_atomic_fsub_ret_f16(ptr %ptr, half %val) #0 {
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB22_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5902,9 +5902,9 @@ define half @flat_agent_atomic_fsub_ret_f16(ptr %ptr, half %val) #0 {
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB22_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6204,7 +6204,7 @@ define half @flat_agent_atomic_fsub_ret_f16__offset12b_pos(ptr %ptr, half %val)
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -6230,9 +6230,9 @@ define half @flat_agent_atomic_fsub_ret_f16__offset12b_pos(ptr %ptr, half %val)
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB23_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6249,7 +6249,7 @@ define half @flat_agent_atomic_fsub_ret_f16__offset12b_pos(ptr %ptr, half %val)
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -6276,9 +6276,9 @@ define half @flat_agent_atomic_fsub_ret_f16__offset12b_pos(ptr %ptr, half %val)
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB23_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6588,7 +6588,7 @@ define half @flat_agent_atomic_fsub_ret_f16__offset12b_neg(ptr %ptr, half %val)
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -6614,9 +6614,9 @@ define half @flat_agent_atomic_fsub_ret_f16__offset12b_neg(ptr %ptr, half %val)
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB24_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6633,7 +6633,7 @@ define half @flat_agent_atomic_fsub_ret_f16__offset12b_neg(ptr %ptr, half %val)
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -6660,9 +6660,9 @@ define half @flat_agent_atomic_fsub_ret_f16__offset12b_neg(ptr %ptr, half %val)
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB24_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6998,9 +6998,9 @@ define void @flat_agent_atomic_fsub_noret_f16(ptr %ptr, half %val) #0 {
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB25_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7041,9 +7041,9 @@ define void @flat_agent_atomic_fsub_noret_f16(ptr %ptr, half %val) #0 {
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB25_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7332,7 +7332,7 @@ define void @flat_agent_atomic_fsub_noret_f16__offset12b_pos(ptr %ptr, half %val
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -7358,9 +7358,9 @@ define void @flat_agent_atomic_fsub_noret_f16__offset12b_pos(ptr %ptr, half %val
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB26_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7376,7 +7376,7 @@ define void @flat_agent_atomic_fsub_noret_f16__offset12b_pos(ptr %ptr, half %val
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -7402,9 +7402,9 @@ define void @flat_agent_atomic_fsub_noret_f16__offset12b_pos(ptr %ptr, half %val
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB26_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7703,7 +7703,7 @@ define void @flat_agent_atomic_fsub_noret_f16__offset12b_neg(ptr %ptr, half %val
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -7729,9 +7729,9 @@ define void @flat_agent_atomic_fsub_noret_f16__offset12b_neg(ptr %ptr, half %val
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7747,7 +7747,7 @@ define void @flat_agent_atomic_fsub_noret_f16__offset12b_neg(ptr %ptr, half %val
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -7773,9 +7773,9 @@ define void @flat_agent_atomic_fsub_noret_f16__offset12b_neg(ptr %ptr, half %val
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8089,9 +8089,9 @@ define half @flat_agent_atomic_fsub_ret_f16__offset12b_pos__align4(ptr %ptr, hal
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB28_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8123,9 +8123,9 @@ define half @flat_agent_atomic_fsub_ret_f16__offset12b_pos__align4(ptr %ptr, hal
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB28_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8373,9 +8373,9 @@ define void @flat_agent_atomic_fsub_noret_f16__offset12b__align4_pos(ptr %ptr, h
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB29_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8405,9 +8405,9 @@ define void @flat_agent_atomic_fsub_noret_f16__offset12b__align4_pos(ptr %ptr, h
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB29_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8633,7 +8633,7 @@ define half @flat_system_atomic_fsub_ret_f16__offset12b_pos(ptr %ptr, half %val)
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -8660,9 +8660,9 @@ define half @flat_system_atomic_fsub_ret_f16__offset12b_pos(ptr %ptr, half %val)
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB30_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8679,7 +8679,7 @@ define half @flat_system_atomic_fsub_ret_f16__offset12b_pos(ptr %ptr, half %val)
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -8707,9 +8707,9 @@ define half @flat_system_atomic_fsub_ret_f16__offset12b_pos(ptr %ptr, half %val)
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB30_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9021,7 +9021,7 @@ define void @flat_system_atomic_fsub_noret_f16__offset12b_pos(ptr %ptr, half %va
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -9048,9 +9048,9 @@ define void @flat_system_atomic_fsub_noret_f16__offset12b_pos(ptr %ptr, half %va
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB31_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9066,7 +9066,7 @@ define void @flat_system_atomic_fsub_noret_f16__offset12b_pos(ptr %ptr, half %va
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -9093,9 +9093,9 @@ define void @flat_system_atomic_fsub_noret_f16__offset12b_pos(ptr %ptr, half %va
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB31_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9426,7 +9426,7 @@ define bfloat @flat_agent_atomic_fsub_ret_bf16(ptr %ptr, bfloat %val) #0 {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -9438,9 +9438,9 @@ define bfloat @flat_agent_atomic_fsub_ret_bf16(ptr %ptr, bfloat %val) #0 {
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB32_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9480,7 +9480,7 @@ define bfloat @flat_agent_atomic_fsub_ret_bf16(ptr %ptr, bfloat %val) #0 {
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -9492,9 +9492,9 @@ define bfloat @flat_agent_atomic_fsub_ret_bf16(ptr %ptr, bfloat %val) #0 {
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB32_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9852,7 +9852,7 @@ define bfloat @flat_agent_atomic_fsub_ret_bf16__offset12b_pos(ptr %ptr, bfloat %
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -9879,7 +9879,7 @@ define bfloat @flat_agent_atomic_fsub_ret_bf16__offset12b_pos(ptr %ptr, bfloat %
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -9891,9 +9891,9 @@ define bfloat @flat_agent_atomic_fsub_ret_bf16__offset12b_pos(ptr %ptr, bfloat %
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB33_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9910,7 +9910,7 @@ define bfloat @flat_agent_atomic_fsub_ret_bf16__offset12b_pos(ptr %ptr, bfloat %
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -9936,7 +9936,7 @@ define bfloat @flat_agent_atomic_fsub_ret_bf16__offset12b_pos(ptr %ptr, bfloat %
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -9948,9 +9948,9 @@ define bfloat @flat_agent_atomic_fsub_ret_bf16__offset12b_pos(ptr %ptr, bfloat %
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB33_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10319,7 +10319,7 @@ define bfloat @flat_agent_atomic_fsub_ret_bf16__offset12b_neg(ptr %ptr, bfloat %
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -10346,7 +10346,7 @@ define bfloat @flat_agent_atomic_fsub_ret_bf16__offset12b_neg(ptr %ptr, bfloat %
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -10358,9 +10358,9 @@ define bfloat @flat_agent_atomic_fsub_ret_bf16__offset12b_neg(ptr %ptr, bfloat %
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB34_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10377,7 +10377,7 @@ define bfloat @flat_agent_atomic_fsub_ret_bf16__offset12b_neg(ptr %ptr, bfloat %
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -10403,7 +10403,7 @@ define bfloat @flat_agent_atomic_fsub_ret_bf16__offset12b_neg(ptr %ptr, bfloat %
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -10415,9 +10415,9 @@ define bfloat @flat_agent_atomic_fsub_ret_bf16__offset12b_neg(ptr %ptr, bfloat %
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB34_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10811,7 +10811,7 @@ define void @flat_agent_atomic_fsub_noret_bf16(ptr %ptr, bfloat %val) #0 {
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -10824,9 +10824,9 @@ define void @flat_agent_atomic_fsub_noret_bf16(ptr %ptr, bfloat %val) #0 {
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB35_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10863,7 +10863,7 @@ define void @flat_agent_atomic_fsub_noret_bf16(ptr %ptr, bfloat %val) #0 {
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -10876,9 +10876,9 @@ define void @flat_agent_atomic_fsub_noret_bf16(ptr %ptr, bfloat %val) #0 {
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB35_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11224,7 +11224,7 @@ define void @flat_agent_atomic_fsub_noret_bf16__offset12b_pos(ptr %ptr, bfloat %
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -11249,7 +11249,7 @@ define void @flat_agent_atomic_fsub_noret_bf16__offset12b_pos(ptr %ptr, bfloat %
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -11262,9 +11262,9 @@ define void @flat_agent_atomic_fsub_noret_bf16__offset12b_pos(ptr %ptr, bfloat %
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB36_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11280,7 +11280,7 @@ define void @flat_agent_atomic_fsub_noret_bf16__offset12b_pos(ptr %ptr, bfloat %
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -11304,7 +11304,7 @@ define void @flat_agent_atomic_fsub_noret_bf16__offset12b_pos(ptr %ptr, bfloat %
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -11317,9 +11317,9 @@ define void @flat_agent_atomic_fsub_noret_bf16__offset12b_pos(ptr %ptr, bfloat %
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB36_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11676,7 +11676,7 @@ define void @flat_agent_atomic_fsub_noret_bf16__offset12b_neg(ptr %ptr, bfloat %
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -11701,7 +11701,7 @@ define void @flat_agent_atomic_fsub_noret_bf16__offset12b_neg(ptr %ptr, bfloat %
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -11714,9 +11714,9 @@ define void @flat_agent_atomic_fsub_noret_bf16__offset12b_neg(ptr %ptr, bfloat %
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB37_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11732,7 +11732,7 @@ define void @flat_agent_atomic_fsub_noret_bf16__offset12b_neg(ptr %ptr, bfloat %
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -11756,7 +11756,7 @@ define void @flat_agent_atomic_fsub_noret_bf16__offset12b_neg(ptr %ptr, bfloat %
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -11769,9 +11769,9 @@ define void @flat_agent_atomic_fsub_noret_bf16__offset12b_neg(ptr %ptr, bfloat %
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB37_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12145,7 +12145,7 @@ define bfloat @flat_agent_atomic_fsub_ret_bf16__offset12b_pos__align4(ptr %ptr,
; GFX12-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.h
@@ -12156,9 +12156,9 @@ define bfloat @flat_agent_atomic_fsub_ret_bf16__offset12b_pos__align4(ptr %ptr,
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB38_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12189,7 +12189,7 @@ define bfloat @flat_agent_atomic_fsub_ret_bf16__offset12b_pos__align4(ptr %ptr,
; GFX12-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -12200,9 +12200,9 @@ define bfloat @flat_agent_atomic_fsub_ret_bf16__offset12b_pos__align4(ptr %ptr,
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB38_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12517,7 +12517,7 @@ define void @flat_agent_atomic_fsub_noret_bf16__offset12b__align4_pos(ptr %ptr,
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.h
@@ -12528,9 +12528,9 @@ define void @flat_agent_atomic_fsub_noret_bf16__offset12b__align4_pos(ptr %ptr,
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB39_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12559,7 +12559,7 @@ define void @flat_agent_atomic_fsub_noret_bf16__offset12b__align4_pos(ptr %ptr,
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -12570,9 +12570,9 @@ define void @flat_agent_atomic_fsub_noret_bf16__offset12b__align4_pos(ptr %ptr,
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB39_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12863,7 +12863,7 @@ define bfloat @flat_system_atomic_fsub_ret_bf16__offset12b_pos(ptr %ptr, bfloat
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -12890,7 +12890,7 @@ define bfloat @flat_system_atomic_fsub_ret_bf16__offset12b_pos(ptr %ptr, bfloat
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -12903,9 +12903,9 @@ define bfloat @flat_system_atomic_fsub_ret_bf16__offset12b_pos(ptr %ptr, bfloat
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB40_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12922,7 +12922,7 @@ define bfloat @flat_system_atomic_fsub_ret_bf16__offset12b_pos(ptr %ptr, bfloat
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -12948,7 +12948,7 @@ define bfloat @flat_system_atomic_fsub_ret_bf16__offset12b_pos(ptr %ptr, bfloat
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -12961,9 +12961,9 @@ define bfloat @flat_system_atomic_fsub_ret_bf16__offset12b_pos(ptr %ptr, bfloat
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB40_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13334,7 +13334,7 @@ define void @flat_system_atomic_fsub_noret_bf16__offset12b_pos(ptr %ptr, bfloat
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -13359,7 +13359,7 @@ define void @flat_system_atomic_fsub_noret_bf16__offset12b_pos(ptr %ptr, bfloat
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -13373,9 +13373,9 @@ define void @flat_system_atomic_fsub_noret_bf16__offset12b_pos(ptr %ptr, bfloat
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB41_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13391,7 +13391,7 @@ define void @flat_system_atomic_fsub_noret_bf16__offset12b_pos(ptr %ptr, bfloat
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -13415,7 +13415,7 @@ define void @flat_system_atomic_fsub_noret_bf16__offset12b_pos(ptr %ptr, bfloat
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -13429,9 +13429,9 @@ define void @flat_system_atomic_fsub_noret_bf16__offset12b_pos(ptr %ptr, bfloat
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB41_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13806,9 +13806,9 @@ define <2 x half> @flat_agent_atomic_fsub_ret_v2f16(ptr %ptr, <2 x half> %val) #
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB42_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14025,9 +14025,9 @@ define <2 x half> @flat_agent_atomic_fsub_ret_v2f16__offset12b_pos(ptr %ptr, <2
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB43_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14247,9 +14247,9 @@ define <2 x half> @flat_agent_atomic_fsub_ret_v2f16__offset12b_neg(ptr %ptr, <2
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB44_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14483,9 +14483,9 @@ define void @flat_agent_atomic_fsub_noret_v2f16(ptr %ptr, <2 x half> %val) #0 {
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB45_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14691,9 +14691,9 @@ define void @flat_agent_atomic_fsub_noret_v2f16__offset12b_pos(ptr %ptr, <2 x ha
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB46_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14906,9 +14906,9 @@ define void @flat_agent_atomic_fsub_noret_v2f16__offset12b_neg(ptr %ptr, <2 x ha
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB47_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15142,9 +15142,9 @@ define <2 x half> @flat_system_atomic_fsub_ret_v2f16__offset12b_pos(ptr %ptr, <2
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB48_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15366,9 +15366,9 @@ define void @flat_system_atomic_fsub_noret_v2f16__offset12b_pos(ptr %ptr, <2 x h
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB49_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15598,10 +15598,10 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16(ptr %ptr, <2 x bfloat> %v
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
@@ -15610,9 +15610,9 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16(ptr %ptr, <2 x bfloat> %v
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB50_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15650,10 +15650,10 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16(ptr %ptr, <2 x bfloat> %v
; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
@@ -15662,9 +15662,9 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16(ptr %ptr, <2 x bfloat> %v
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB50_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16045,10 +16045,10 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr,
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
@@ -16057,9 +16057,9 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr,
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB51_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16097,10 +16097,10 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr,
; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
@@ -16109,9 +16109,9 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr,
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB51_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16495,10 +16495,10 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16__offset12b_neg(ptr %ptr,
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
@@ -16507,9 +16507,9 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16__offset12b_neg(ptr %ptr,
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB52_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16547,10 +16547,10 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16__offset12b_neg(ptr %ptr,
; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
@@ -16559,9 +16559,9 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16__offset12b_neg(ptr %ptr,
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB52_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16958,11 +16958,11 @@ define void @flat_agent_atomic_fsub_noret_v2bf16(ptr %ptr, <2 x bfloat> %val) #0
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -16971,9 +16971,9 @@ define void @flat_agent_atomic_fsub_noret_v2bf16(ptr %ptr, <2 x bfloat> %val) #0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB53_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17009,10 +17009,10 @@ define void @flat_agent_atomic_fsub_noret_v2bf16(ptr %ptr, <2 x bfloat> %val) #0
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
@@ -17022,9 +17022,9 @@ define void @flat_agent_atomic_fsub_noret_v2bf16(ptr %ptr, <2 x bfloat> %val) #0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB53_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17390,11 +17390,11 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x b
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -17403,9 +17403,9 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x b
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB54_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17441,10 +17441,10 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x b
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
@@ -17454,9 +17454,9 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x b
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB54_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17829,11 +17829,11 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr %ptr, <2 x b
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -17842,9 +17842,9 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr %ptr, <2 x b
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB55_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17880,10 +17880,10 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr %ptr, <2 x b
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
@@ -17893,9 +17893,9 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr %ptr, <2 x b
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB55_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18293,10 +18293,10 @@ define <2 x bfloat> @flat_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr,
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
@@ -18306,9 +18306,9 @@ define <2 x bfloat> @flat_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr,
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB56_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18346,10 +18346,10 @@ define <2 x bfloat> @flat_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr,
; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
@@ -18359,9 +18359,9 @@ define <2 x bfloat> @flat_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr,
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB56_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18744,11 +18744,11 @@ define void @flat_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
@@ -18758,9 +18758,9 @@ define void @flat_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB57_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18796,10 +18796,10 @@ define void @flat_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
@@ -18810,9 +18810,9 @@ define void @flat_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB57_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch.ll b/llvm/test/CodeGen/AMDGPU/flat-scratch.ll
index 870b679a84d11..b2e9831d6c84f 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-scratch.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-scratch.ll
@@ -269,11 +269,11 @@ define void @zero_init_foo() {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_mov_b32 s0, 0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 s1, s0
; GFX12-NEXT: s_mov_b32 s2, s0
; GFX12-NEXT: s_mov_b32 s3, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX12-NEXT: s_clause 0x3
@@ -359,11 +359,11 @@ define void @zero_init_foo() {
; GFX12-PAL-NEXT: s_wait_bvhcnt 0x0
; GFX12-PAL-NEXT: s_wait_kmcnt 0x0
; GFX12-PAL-NEXT: s_mov_b32 s0, 0
-; GFX12-PAL-NEXT: s_wait_alu 0xfffe
+; GFX12-PAL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-PAL-NEXT: s_mov_b32 s1, s0
; GFX12-PAL-NEXT: s_mov_b32 s2, s0
; GFX12-PAL-NEXT: s_mov_b32 s3, s0
-; GFX12-PAL-NEXT: s_wait_alu 0xfffe
+; GFX12-PAL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-PAL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-PAL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX12-PAL-NEXT: s_clause 0x3
@@ -1358,11 +1358,11 @@ define void @zero_init_small_offset_foo() {
; GFX12-NEXT: scratch_load_b32 v0, off, s32 scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_mov_b32 s0, 0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 s1, s0
; GFX12-NEXT: s_mov_b32 s2, s0
; GFX12-NEXT: s_mov_b32 s3, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX12-NEXT: s_clause 0x3
@@ -1458,11 +1458,11 @@ define void @zero_init_small_offset_foo() {
; GFX12-PAL-NEXT: scratch_load_b32 v0, off, s32 scope:SCOPE_SYS
; GFX12-PAL-NEXT: s_wait_loadcnt 0x0
; GFX12-PAL-NEXT: s_mov_b32 s0, 0
-; GFX12-PAL-NEXT: s_wait_alu 0xfffe
+; GFX12-PAL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-PAL-NEXT: s_mov_b32 s1, s0
; GFX12-PAL-NEXT: s_mov_b32 s2, s0
; GFX12-PAL-NEXT: s_mov_b32 s3, s0
-; GFX12-PAL-NEXT: s_wait_alu 0xfffe
+; GFX12-PAL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-PAL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-PAL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX12-PAL-NEXT: s_clause 0x3
@@ -2613,11 +2613,11 @@ define void @zero_init_large_offset_foo() {
; GFX12-NEXT: scratch_load_b32 v0, off, s32 scope:SCOPE_SYS
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_mov_b32 s0, 0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 s1, s0
; GFX12-NEXT: s_mov_b32 s2, s0
; GFX12-NEXT: s_mov_b32 s3, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX12-NEXT: s_clause 0x3
@@ -2688,13 +2688,13 @@ define void @zero_init_large_offset_foo() {
; GFX1010-PAL-NEXT: v_mov_b32_e32 v3, s3
; GFX1010-PAL-NEXT: s_add_i32 s0, s32, 0x4004
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0
-; GFX1010-PAL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010-PAL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010-PAL-NEXT: s_add_i32 s0, s32, 0x4004
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:16
-; GFX1010-PAL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010-PAL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010-PAL-NEXT: s_add_i32 s0, s32, 0x4004
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:32
-; GFX1010-PAL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010-PAL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010-PAL-NEXT: s_add_i32 s0, s32, 0x4004
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:48
; GFX1010-PAL-NEXT: s_setpc_b64 s[30:31]
@@ -2754,11 +2754,11 @@ define void @zero_init_large_offset_foo() {
; GFX12-PAL-NEXT: scratch_load_b32 v0, off, s32 scope:SCOPE_SYS
; GFX12-PAL-NEXT: s_wait_loadcnt 0x0
; GFX12-PAL-NEXT: s_mov_b32 s0, 0
-; GFX12-PAL-NEXT: s_wait_alu 0xfffe
+; GFX12-PAL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-PAL-NEXT: s_mov_b32 s1, s0
; GFX12-PAL-NEXT: s_mov_b32 s2, s0
; GFX12-PAL-NEXT: s_mov_b32 s3, s0
-; GFX12-PAL-NEXT: s_wait_alu 0xfffe
+; GFX12-PAL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-PAL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-PAL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX12-PAL-NEXT: s_clause 0x3
@@ -5062,7 +5062,7 @@ define amdgpu_ps void @large_offset() {
; GFX1010-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1010-PAL-NEXT: scratch_load_dwordx4 v[0:3], off, s1 glc dlc
; GFX1010-PAL-NEXT: s_waitcnt vmcnt(0)
-; GFX1010-PAL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010-PAL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010-PAL-NEXT: s_mov_b32 s1, 16
; GFX1010-PAL-NEXT: ;;#ASMSTART
; GFX1010-PAL-NEXT: ; use s1
diff --git a/llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll b/llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
index 6dfe4594a248c..25fbdbc83b2b9 100644
--- a/llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
@@ -14111,7 +14111,7 @@ define amdgpu_kernel void @atomic_inc_i64_offset(ptr %out, i64 %in) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v1, vcc_lo
; GFX12-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v0, 0, v2
; GFX12-NEXT: scratch_store_b64 off, v[0:1], s0
; GFX12-NEXT: s_endpgm
@@ -14261,7 +14261,7 @@ define amdgpu_kernel void @atomic_inc_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v1, vcc_lo
; GFX12-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_dual_cndmask_b32 v3, 0, v3 :: v_dual_cndmask_b32 v2, 0, v2
; GFX12-NEXT: scratch_store_b64 off, v[2:3], s0
; GFX12-NEXT: .LBB108_4: ; %atomicrmw.end
@@ -14425,7 +14425,7 @@ define amdgpu_kernel void @atomic_inc_i64_incr64_offset(ptr %out, i64 %in, i64 %
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v1, vcc_lo
; GFX12-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v0, 0, v2
; GFX12-NEXT: scratch_store_b64 off, v[0:1], s0
; GFX12-NEXT: s_endpgm
@@ -14581,7 +14581,7 @@ define amdgpu_kernel void @atomic_inc_i64_ret_incr64_offset(ptr %out, ptr %out2,
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v1, vcc_lo
; GFX12-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_dual_cndmask_b32 v3, 0, v3 :: v_dual_cndmask_b32 v2, 0, v2
; GFX12-NEXT: scratch_store_b64 off, v[2:3], s0
; GFX12-NEXT: .LBB110_4: ; %atomicrmw.end
@@ -14728,7 +14728,7 @@ define amdgpu_kernel void @atomic_inc_i64(ptr %out, i64 %in) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v1, vcc_lo
; GFX12-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v0, 0, v2
; GFX12-NEXT: scratch_store_b64 off, v[0:1], s0
; GFX12-NEXT: s_endpgm
@@ -14872,7 +14872,7 @@ define amdgpu_kernel void @atomic_inc_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v1, vcc_lo
; GFX12-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_dual_cndmask_b32 v3, 0, v3 :: v_dual_cndmask_b32 v2, 0, v2
; GFX12-NEXT: scratch_store_b64 off, v[2:3], s0
; GFX12-NEXT: .LBB112_4: ; %atomicrmw.end
@@ -15030,7 +15030,7 @@ define amdgpu_kernel void @atomic_inc_i64_incr64(ptr %out, i64 %in, i64 %index)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v1, vcc_lo
; GFX12-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v0, 0, v2
; GFX12-NEXT: scratch_store_b64 off, v[0:1], s0
; GFX12-NEXT: s_endpgm
@@ -15180,7 +15180,7 @@ define amdgpu_kernel void @atomic_inc_i64_ret_incr64(ptr %out, ptr %out2, i64 %i
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v1, vcc_lo
; GFX12-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_dual_cndmask_b32 v3, 0, v3 :: v_dual_cndmask_b32 v2, 0, v2
; GFX12-NEXT: scratch_store_b64 off, v[2:3], s0
; GFX12-NEXT: .LBB114_4: ; %atomicrmw.end
@@ -15336,10 +15336,10 @@ define amdgpu_kernel void @atomic_dec_i64_offset(ptr %out, i64 %in) {
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: v_cmp_lt_u64_e64 s0, s[2:3], v[0:1]
; GFX12-NEXT: v_add_co_u32 v0, s1, v0, -1
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, s1
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v1, v1, s3, s0
; GFX12-NEXT: v_cndmask_b32_e64 v0, v0, s2, s0
; GFX12-NEXT: scratch_store_b64 off, v[0:1], s4
@@ -15497,10 +15497,10 @@ define amdgpu_kernel void @atomic_dec_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: v_cmp_lt_u64_e64 s0, s[4:5], v[0:1]
; GFX12-NEXT: v_add_co_u32 v2, s1, v0, -1
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, -1, v1, s1
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v3, v3, s5, s0
; GFX12-NEXT: v_cndmask_b32_e64 v2, v2, s4, s0
; GFX12-NEXT: scratch_store_b64 off, v[2:3], s6
@@ -15670,10 +15670,10 @@ define amdgpu_kernel void @atomic_dec_i64_decr64_offset(ptr %out, i64 %in, i64 %
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: v_cmp_lt_u64_e64 s0, s[2:3], v[0:1]
; GFX12-NEXT: v_add_co_u32 v0, s1, v0, -1
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, s1
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v1, v1, s3, s0
; GFX12-NEXT: v_cndmask_b32_e64 v0, v0, s2, s0
; GFX12-NEXT: scratch_store_b64 off, v[0:1], s4
@@ -15837,10 +15837,10 @@ define amdgpu_kernel void @atomic_dec_i64_ret_decr64_offset(ptr %out, ptr %out2,
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: v_cmp_lt_u64_e64 s0, s[4:5], v[0:1]
; GFX12-NEXT: v_add_co_u32 v2, s1, v0, -1
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, -1, v1, s1
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v3, v3, s5, s0
; GFX12-NEXT: v_cndmask_b32_e64 v2, v2, s4, s0
; GFX12-NEXT: scratch_store_b64 off, v[2:3], s6
@@ -15993,10 +15993,10 @@ define amdgpu_kernel void @atomic_dec_i64(ptr %out, i64 %in) {
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: v_cmp_lt_u64_e64 s0, s[2:3], v[0:1]
; GFX12-NEXT: v_add_co_u32 v0, s1, v0, -1
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, s1
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v1, v1, s3, s0
; GFX12-NEXT: v_cndmask_b32_e64 v0, v0, s2, s0
; GFX12-NEXT: scratch_store_b64 off, v[0:1], s4
@@ -16148,10 +16148,10 @@ define amdgpu_kernel void @atomic_dec_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: v_cmp_lt_u64_e64 s0, s[4:5], v[0:1]
; GFX12-NEXT: v_add_co_u32 v2, s1, v0, -1
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, -1, v1, s1
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v3, v3, s5, s0
; GFX12-NEXT: v_cndmask_b32_e64 v2, v2, s4, s0
; GFX12-NEXT: scratch_store_b64 off, v[2:3], s6
@@ -16315,10 +16315,10 @@ define amdgpu_kernel void @atomic_dec_i64_decr64(ptr %out, i64 %in, i64 %index)
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: v_cmp_lt_u64_e64 s0, s[2:3], v[0:1]
; GFX12-NEXT: v_add_co_u32 v0, s1, v0, -1
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, s1
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v1, v1, s3, s0
; GFX12-NEXT: v_cndmask_b32_e64 v0, v0, s2, s0
; GFX12-NEXT: scratch_store_b64 off, v[0:1], s4
@@ -16476,10 +16476,10 @@ define amdgpu_kernel void @atomic_dec_i64_ret_decr64(ptr %out, ptr %out2, i64 %i
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
; GFX12-NEXT: v_cmp_lt_u64_e64 s0, s[4:5], v[0:1]
; GFX12-NEXT: v_add_co_u32 v2, s1, v0, -1
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, -1, v1, s1
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v3, v3, s5, s0
; GFX12-NEXT: v_cndmask_b32_e64 v2, v2, s4, s0
; GFX12-NEXT: scratch_store_b64 off, v[2:3], s6
diff --git a/llvm/test/CodeGen/AMDGPU/fma.f16.ll b/llvm/test/CodeGen/AMDGPU/fma.f16.ll
index fe46ac110cedd..bbd493f668847 100644
--- a/llvm/test/CodeGen/AMDGPU/fma.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fma.f16.ll
@@ -480,7 +480,7 @@ define i32 @test_D139469_f16(half %arg) {
; GFX12-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v1.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v0.l
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -498,7 +498,7 @@ define i32 @test_D139469_f16(half %arg) {
; GFX12-SDAG-FAKE16-NEXT: v_min_num_f16_e32 v0, v2, v1
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -517,7 +517,7 @@ define i32 @test_D139469_f16(half %arg) {
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-GISEL-TRUE16-NEXT: v_cmp_gt_f16_e64 s0, 0, v0.h
; GFX12-GISEL-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-GISEL-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -536,7 +536,7 @@ define i32 @test_D139469_f16(half %arg) {
; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-GISEL-FAKE16-NEXT: v_cmp_gt_f16_e64 s0, 0, v1
; GFX12-GISEL-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-GISEL-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX12-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
bb:
@@ -696,16 +696,16 @@ define <2 x i32> @test_D139469_v2f16(<2 x half> %arg) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_movk_i32 s0, 0x211e
; GFX12-SDAG-TRUE16-NEXT: v_pk_mul_f16 v1, 0x291e, v0 op_sel_hi:[0,1]
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: v_pk_fma_f16 v0, 0x291e, v0, s0 op_sel_hi:[0,1,0]
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v1, v1, v0
; GFX12-SDAG-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v1.l
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v1.h
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -718,17 +718,17 @@ define <2 x i32> @test_D139469_v2f16(<2 x half> %arg) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x211e
; GFX12-SDAG-FAKE16-NEXT: v_pk_mul_f16 v1, 0x291e, v0 op_sel_hi:[0,1]
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-FAKE16-NEXT: v_pk_fma_f16 v0, 0x291e, v0, s0 op_sel_hi:[0,1,0]
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_pk_min_num_f16 v0, v1, v0
; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX12-SDAG-FAKE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-SDAG-FAKE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v1
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -750,10 +750,10 @@ define <2 x i32> @test_D139469_v2f16(<2 x half> %arg) {
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-GISEL-TRUE16-NEXT: v_cmp_gt_f16_e64 s2, 0, v0.h
; GFX12-GISEL-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-GISEL-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX12-GISEL-TRUE16-NEXT: s_or_b32 s0, s1, s2
-; GFX12-GISEL-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -777,10 +777,10 @@ define <2 x i32> @test_D139469_v2f16(<2 x half> %arg) {
; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-GISEL-FAKE16-NEXT: v_cmp_gt_f16_e64 s2, 0, v3
; GFX12-GISEL-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-GISEL-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX12-GISEL-FAKE16-NEXT: s_or_b32 s0, s1, s2
-; GFX12-GISEL-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
; GFX12-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
bb:
diff --git a/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll b/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
index 87843522fe0ab..35150f2d43942 100644
--- a/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
@@ -816,7 +816,7 @@ define amdgpu_ps i32 @s_max3_f32_maximumnum_maximumnum__s_s_s(float inreg %a, fl
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_max3_num_f32 v0, s0, s1, v0
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: ; return to shader part epilog
%tmp0 = call float @llvm.maximumnum.f32(float %a, float %b)
%max3 = call float @llvm.maximumnum.f32(float %tmp0, float %c)
@@ -1977,51 +1977,51 @@ define bfloat @v_max3_bf16_maximumnum_maximumnum__v_v_v_0(bfloat %a, bfloat %b,
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.h, v1.l
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, v0.l, v0.h, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.h
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.h, v0.h, v1.h, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v1, v3
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.h, v1.h, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3.h
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v1.h, s0
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v3.h, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.h, v0.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v1, v1
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.h, v0.l, v0.h, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.h, v3.h, v0.l, vcc_lo
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, v0.l, v3.h, s0
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.h
; GFX12-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v1
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.h, v3.h, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.h
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v3.h, s0
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.h, v0.l
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v1.h, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2035,54 +2035,54 @@ define bfloat @v_max3_bf16_maximumnum_maximumnum__v_v_v_0(bfloat %a, bfloat %b,
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
; GFX12-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v4
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v0, v3, v0 :: v_dual_lshlrev_b32 v3, 16, v2
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0
; GFX12-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v0, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_lshlrev_b32 v3, 16, v2
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -2664,22 +2664,22 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.l
; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v5.h, v0.h, v1.h, vcc_lo
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.h, v1.h, v5.h, s0
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v5.h
; GFX12-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v3
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.h, v5.h, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v5.l
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, v5.h, s0
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v4.h, v0.l, v1.l, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
@@ -2687,36 +2687,36 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v4.h
; GFX12-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v4, v5
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v5.h
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.h, v4.h, s0
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.h
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.l, v4.h, s1
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v3.h, s0
; GFX12-SDAG-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.h, s2
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.h, v0.l
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.h, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5
; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v5.h, v3.l, v2.h, s0
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.h, v2.h, v5.h, s1
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v5.h
; GFX12-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v5, v3
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.h, v5.h, s0
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, v5.h, s1
@@ -2727,7 +2727,7 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.h, v0.l
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v5.h, v0.l, v2.l, s0
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, v2.l, v5.h, s1
@@ -2735,21 +2735,21 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v5, v1
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v1.h
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.h, v5.h, s0
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.h
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.l, v5.h, s1
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.h, v0.l
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v3.h, s0
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v1.h, s2
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v5
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, v0.h, vcc_lo
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2765,21 +2765,21 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v3, v5, v4, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
; GFX12-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v3, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
@@ -2787,79 +2787,79 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v6
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v5, v4, v3, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v8
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v6, v1, v0, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v4 :: v_dual_lshlrev_b32 v4, 16, v6
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4
; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v0, v6, v0 :: v_dual_lshlrev_b32 v3, 16, v1
; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
; GFX12-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX12-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v0 :: v_dual_lshlrev_b32 v3, 16, v1
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
; GFX12-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v5
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v3, v4, v1 :: v_dual_lshlrev_b32 v6, 16, v0
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v5, v2, v0 :: v_dual_lshlrev_b32 v6, 16, v3
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
diff --git a/llvm/test/CodeGen/AMDGPU/fmaximum.ll b/llvm/test/CodeGen/AMDGPU/fmaximum.ll
index 62ec010107d8f..0283b5ff5d439 100644
--- a/llvm/test/CodeGen/AMDGPU/fmaximum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmaximum.ll
@@ -515,7 +515,7 @@ define amdgpu_ps <3 x half> @test_fmaximum_v3f16_ss(<3 x half> inreg %a, <3 x ha
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: v_pk_maximum_f16 v0, s0, s2
; GFX12-GISEL-NEXT: s_maximum_f16 s0, s1, s3
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, s0
; GFX12-GISEL-NEXT: ; return to shader part epilog
diff --git a/llvm/test/CodeGen/AMDGPU/fmaximum3.ll b/llvm/test/CodeGen/AMDGPU/fmaximum3.ll
index 069a47ec97bfe..91f95859ed3db 100644
--- a/llvm/test/CodeGen/AMDGPU/fmaximum3.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmaximum3.ll
@@ -81,7 +81,7 @@ define amdgpu_ps i32 @s_fmaximum3_f32(float inreg %a, float inreg %b, float inre
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_maximum3_f32 v0, s0, s1, v0
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: ; return to shader part epilog
;
; GFX942-LABEL: s_fmaximum3_f32:
@@ -599,7 +599,7 @@ define float @v_fmaximum3_f32_const1_const2(float %a) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_mov_b32 s0, 0x41000000
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_maximum3_f32 v0, v0, s0, 0x41800000
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -1341,7 +1341,7 @@ define amdgpu_ps i32 @s_fmaximum3_f16(half inreg %a, half inreg %b, half inreg %
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: ; return to shader part epilog
;
; GFX12-FAKE16-LABEL: s_fmaximum3_f16:
@@ -1352,7 +1352,7 @@ define amdgpu_ps i32 @s_fmaximum3_f16(half inreg %a, half inreg %b, half inreg %
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: ; return to shader part epilog
;
; GFX942-LABEL: s_fmaximum3_f16:
@@ -2031,7 +2031,7 @@ define half @v_fmaximum3_f16_const1_const2(half %a) {
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_movk_i32 s0, 0x4800
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_maximum3_f16 v0, v0, s0, 0x4c00
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3224,7 +3224,7 @@ define amdgpu_ps <2 x i32> @s_fmaximum3_f64(double inreg %a, double inreg %b, do
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT: v_readfirstlane_b32 s1, v1
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_fmaximum3_f64:
diff --git a/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll b/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
index 7b2d793973d08..16553afd7c700 100644
--- a/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
@@ -816,7 +816,7 @@ define amdgpu_ps i32 @s_min3_f32_minimumnum_minimumnum__s_s_s(float inreg %a, fl
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_min3_num_f32 v0, s0, s1, v0
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: ; return to shader part epilog
%tmp0 = call float @llvm.minimumnum.f32(float %a, float %b)
%min3 = call float @llvm.minimumnum.f32(float %tmp0, float %c)
@@ -1979,51 +1979,51 @@ define bfloat @v_min3_bf16_minimumnum_minimumnum__v_v_v_0(bfloat %a, bfloat %b,
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.h, v1.l
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, v0.l, v0.h, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.h
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.h, v0.h, v1.h, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v1, v3
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.h, v1.h, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3.h
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v1.h, s0
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v3.h, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.h, v0.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v1, v1
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.h, v0.l, v0.h, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.h, v3.h, v0.l, vcc_lo
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, v0.l, v3.h, s0
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.h
; GFX12-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v3, v1
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.h, v3.h, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.h
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v3.h, s0
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.h, v0.l
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v1.h, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2037,54 +2037,54 @@ define bfloat @v_min3_bf16_minimumnum_minimumnum__v_v_v_0(bfloat %a, bfloat %b,
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
; GFX12-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v3, v4
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v0, v3, v0 :: v_dual_lshlrev_b32 v3, 16, v2
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0
; GFX12-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v0, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_lshlrev_b32 v3, 16, v2
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -2669,22 +2669,22 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.l
; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v5.h, v0.h, v1.h, vcc_lo
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.h, v1.h, v5.h, s0
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v5.h
; GFX12-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v3
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.h, v5.h, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v5.l
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, v5.h, s0
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v4.h, v0.l, v1.l, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
@@ -2692,36 +2692,36 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v4.h
; GFX12-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v4, v5
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v5.h
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.h, v4.h, s0
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.h
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.l, v4.h, s1
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v3.h, s0
; GFX12-SDAG-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.h, s2
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.h, v0.l
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.h, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5
; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v5.h, v3.l, v2.h, s0
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.h, v2.h, v5.h, s1
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v5.h
; GFX12-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v5, v3
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.h, v5.h, s0
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, v5.h, s1
@@ -2732,7 +2732,7 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.h, v0.l
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v5.h, v0.l, v2.l, s0
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, v2.l, v5.h, s1
@@ -2740,21 +2740,21 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v5, v1
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v1.h
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.h, v5.h, s0
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.h
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.l, v5.h, s1
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.h, v0.l
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v3.h, s0
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v1.h, s2
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v5
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, v0.h, vcc_lo
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2770,21 +2770,21 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v3, v5, v4, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
; GFX12-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v3, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
@@ -2792,79 +2792,79 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v6
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v5, v4, v3, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v7, v8
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v6, v1, v0, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v4 :: v_dual_lshlrev_b32 v4, 16, v6
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4
; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v0, v6, v0 :: v_dual_lshlrev_b32 v3, 16, v1
; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
; GFX12-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX12-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v0 :: v_dual_lshlrev_b32 v3, 16, v1
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
; GFX12-SDAG-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v3, v5
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v3, v4, v1 :: v_dual_lshlrev_b32 v6, 16, v0
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v7
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v5, v2, v0 :: v_dual_lshlrev_b32 v6, 16, v3
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
diff --git a/llvm/test/CodeGen/AMDGPU/fminimum.ll b/llvm/test/CodeGen/AMDGPU/fminimum.ll
index 474ac7ce887f0..4cccc768d3c50 100644
--- a/llvm/test/CodeGen/AMDGPU/fminimum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fminimum.ll
@@ -515,7 +515,7 @@ define amdgpu_ps <3 x half> @test_fminimum_v3f16_ss(<3 x half> inreg %a, <3 x ha
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: v_pk_minimum_f16 v0, s0, s2
; GFX12-GISEL-NEXT: s_minimum_f16 s0, s1, s3
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, s0
; GFX12-GISEL-NEXT: ; return to shader part epilog
diff --git a/llvm/test/CodeGen/AMDGPU/fminimum3.ll b/llvm/test/CodeGen/AMDGPU/fminimum3.ll
index d8746b58b16b7..55fc7747bf81d 100644
--- a/llvm/test/CodeGen/AMDGPU/fminimum3.ll
+++ b/llvm/test/CodeGen/AMDGPU/fminimum3.ll
@@ -81,7 +81,7 @@ define amdgpu_ps i32 @s_fminimum3_f32(float inreg %a, float inreg %b, float inre
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_minimum3_f32 v0, s0, s1, v0
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: ; return to shader part epilog
;
; GFX942-LABEL: s_fminimum3_f32:
@@ -599,7 +599,7 @@ define float @v_fminimum3_f32_const1_const2(float %a) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_mov_b32 s0, 0x41000000
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_minimum3_f32 v0, v0, s0, 0x41800000
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -1341,7 +1341,7 @@ define amdgpu_ps i32 @s_fminimum3_f16(half inreg %a, half inreg %b, half inreg %
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: ; return to shader part epilog
;
; GFX12-FAKE16-LABEL: s_fminimum3_f16:
@@ -1352,7 +1352,7 @@ define amdgpu_ps i32 @s_fminimum3_f16(half inreg %a, half inreg %b, half inreg %
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: ; return to shader part epilog
;
; GFX942-LABEL: s_fminimum3_f16:
@@ -2031,7 +2031,7 @@ define half @v_fminimum3_f16_const1_const2(half %a) {
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_movk_i32 s0, 0x4800
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_minimum3_f16 v0, v0, s0, 0x4c00
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3224,7 +3224,7 @@ define amdgpu_ps <2 x i32> @s_fminimum3_f64(double inreg %a, double inreg %b, do
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT: v_readfirstlane_b32 s1, v1
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_fminimum3_f64:
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
index b14e8c44ffcce..04300bf0e26ac 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
@@ -627,7 +627,7 @@ define amdgpu_ps half @fneg_fadd_0_safe_f16(half inreg %tmp2, half inreg %tmp6,
; GFX11-LABEL: fneg_fadd_0_safe_f16:
; GFX11: ; %bb.0: ; %.entry
; GFX11-NEXT: v_rcp_f16_e32 v0, s1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f16_e32 v0, 0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_f16_e32 v0, 0, v0
@@ -682,7 +682,7 @@ define amdgpu_ps half @fneg_fadd_0_nsz_f16(half inreg %tmp2, half inreg %tmp6, <
; GFX11-LABEL: fneg_fadd_0_nsz_f16:
; GFX11: ; %bb.0: ; %.entry
; GFX11-NEXT: v_rcp_f16_e32 v0, s1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f16_e32 v0, 0x8000, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cmp_nlt_f16_e64 s1, -v0, s0
diff --git a/llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll b/llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
index 43d8271de2a43..af753812b4c0c 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
+++ b/llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
@@ -90,11 +90,11 @@ define i32 @flat_offset_maybe_oob(ptr %p, i32 %i) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_lshlrev_b64_e32 v[2:3], 2, v[2:3]
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, 12
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-NEXT: flat_load_b32 v0, v[0:1]
@@ -279,7 +279,7 @@ define i32 @flat_offset_inbounds(ptr %p, i32 %i) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_lshlrev_b64_e32 v[2:3], 2, v[2:3]
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
; GFX12-NEXT: flat_load_b32 v0, v[0:1] offset:12
@@ -375,11 +375,11 @@ define void @flat_offset_inbounds_wide(ptr %p, ptr %pout, i32 %i) {
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_lshlrev_b64_e32 v[4:5], 2, v[4:5]
; GFX12-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v5, vcc_lo
; GFX12-SDAG-NEXT: v_add_co_u32 v4, vcc_lo, v0, 28
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v1, vcc_lo
; GFX12-SDAG-NEXT: s_clause 0x1
@@ -467,7 +467,7 @@ define void @flat_offset_inbounds_wide(ptr %p, ptr %pout, i32 %i) {
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_lshlrev_b64_e32 v[4:5], 2, v[4:5]
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v5, vcc_lo
; GFX12-GISEL-NEXT: s_clause 0x1
@@ -723,11 +723,11 @@ define void @flat_offset_inbounds_very_wide(ptr %p, ptr %pout, i32 %i) {
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_lshlrev_b64_e32 v[4:5], 2, v[4:5]
; GFX12-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v5, vcc_lo
; GFX12-SDAG-NEXT: v_add_co_u32 v36, vcc_lo, v0, 28
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v37, null, 0, v1, vcc_lo
; GFX12-SDAG-NEXT: s_clause 0x7
@@ -742,10 +742,10 @@ define void @flat_offset_inbounds_very_wide(ptr %p, ptr %pout, i32 %i) {
; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-NEXT: flat_load_b128 v[35:38], v[36:37] offset:48
; GFX12-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, v2, 48
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo
; GFX12-SDAG-NEXT: v_add_co_u32 v48, vcc_lo, 0x88, v2
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v49, null, 0, v3, vcc_lo
; GFX12-SDAG-NEXT: s_clause 0x7
; GFX12-SDAG-NEXT: flat_store_b128 v[0:1], v[4:7] offset:48
@@ -908,7 +908,7 @@ define void @flat_offset_inbounds_very_wide(ptr %p, ptr %pout, i32 %i) {
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_lshlrev_b64_e32 v[4:5], 2, v[4:5]
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v5, vcc_lo
; GFX12-GISEL-NEXT: s_clause 0x8
diff --git a/llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll b/llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
index fe95d4561d0cd..bd9807477c1c0 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
@@ -1366,7 +1366,7 @@ define float @fdiv_pow_shl_cnt_fail_maybe_z(i64 %cnt) nounwind {
; GFX11-NEXT: v_div_scale_f32 v1, null, v0, v0, 0xc1100000
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f32_e32 v2, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v3, -v1, v2, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v2, v3, v2
; GFX11-NEXT: v_div_scale_f32 v3, vcc_lo, 0xc1100000, v0, 0xc1100000
@@ -1470,7 +1470,7 @@ define float @fdiv_pow_shl_cnt_fail_neg_int(i64 %cnt) nounwind {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_div_scale_f32 v1, null, v0, v0, 0xc1100000
; GFX11-NEXT: v_rcp_f32_e32 v2, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v3, -v1, v2, 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fmac_f32_e32 v2, v3, v2
@@ -1575,7 +1575,7 @@ define half @fdiv_pow_shl_cnt_fail_out_of_bounds(i32 %cnt) nounwind {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v1.l
; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v2, 0x46000000, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fma_mix_f32 v3, -v1, v2, s0 op_sel_hi:[1,0,0]
@@ -1602,7 +1602,7 @@ define half @fdiv_pow_shl_cnt_fail_out_of_bounds(i32 %cnt) nounwind {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v0
; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_mul_f32_e32 v2, 0x46000000, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_fma_mix_f32 v3, -v0, v2, s0 op_sel_hi:[1,0,0]
@@ -1742,7 +1742,7 @@ define half @fdiv_pow_shl_cnt_fail_out_of_bound2(i16 %cnt) nounwind {
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v1.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v0, v0
; GFX11-TRUE16-NEXT: v_fma_mix_f32 v3, -v1, v2, s0 op_sel_hi:[1,0,0]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1768,7 +1768,7 @@ define half @fdiv_pow_shl_cnt_fail_out_of_bound2(i16 %cnt) nounwind {
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, v1, v1
; GFX11-FAKE16-NEXT: v_fma_mix_f32 v3, -v0, v2, s0 op_sel_hi:[1,0,0]
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1871,7 +1871,7 @@ define float @fdiv_pow_shl_cnt32_out_of_bounds2(i32 %cnt) nounwind {
; GFX11-NEXT: v_div_scale_f32 v1, null, v0, v0, 0x10fffff8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f32_e32 v2, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v3, -v1, v2, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v2, v3, v2
; GFX11-NEXT: v_div_scale_f32 v3, vcc_lo, 0x10fffff8, v0, 0x10fffff8
diff --git a/llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll b/llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
index db938d672f61f..f3dd4cbeda16d 100644
--- a/llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
+++ b/llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
@@ -347,7 +347,7 @@ define amdgpu_kernel void @raw_buffer_atomic_min_rtn_f32_off4_slc(<4 x i32> inre
; G_GFX10-NEXT: v_mov_b32_e32 v0, s6
; G_GFX10-NEXT: v_mov_b32_e32 v1, s7
; G_GFX10-NEXT: buffer_atomic_fmin v0, v1, s[0:3], 4 offen glc slc
-; G_GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; G_GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; G_GFX10-NEXT: s_load_dword s0, s[4:5], 0x3c
; G_GFX10-NEXT: s_waitcnt lgkmcnt(0)
; G_GFX10-NEXT: v_mov_b32_e32 v1, s0
diff --git a/llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll b/llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
index ca7e2e9614bc8..fd4046a70687d 100644
--- a/llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
+++ b/llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
@@ -314,7 +314,7 @@ define amdgpu_kernel void @raw_ptr_buffer_atomic_min_rtn_f32_off4_slc(ptr addrsp
; G_GFX10-NEXT: v_mov_b32_e32 v0, s6
; G_GFX10-NEXT: v_mov_b32_e32 v1, s7
; G_GFX10-NEXT: buffer_atomic_fmin v0, v1, s[0:3], 4 offen glc slc
-; G_GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; G_GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; G_GFX10-NEXT: s_load_dword s0, s[4:5], 0x3c
; G_GFX10-NEXT: s_waitcnt lgkmcnt(0)
; G_GFX10-NEXT: v_mov_b32_e32 v1, s0
diff --git a/llvm/test/CodeGen/AMDGPU/fpow.ll b/llvm/test/CodeGen/AMDGPU/fpow.ll
index 6d383951be9c1..11e74facb7a71 100644
--- a/llvm/test/CodeGen/AMDGPU/fpow.ll
+++ b/llvm/test/CodeGen/AMDGPU/fpow.ll
@@ -52,7 +52,7 @@ define float @v_pow_f32(float %x, float %y) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_log_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
@@ -122,7 +122,7 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_log_f32_e32 v0, v0
; GFX11-NEXT: v_log_f32_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_dual_mul_dx9_zero_f32 v0, v2, v0 :: v_dual_mul_dx9_zero_f32 v1, v3, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
@@ -196,10 +196,10 @@ define half @v_pow_f16(half %x, half %y) {
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -210,10 +210,10 @@ define half @v_pow_f16(half %x, half %y) {
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: v_exp_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%pow = call half @llvm.pow.f16(half %x, half %y)
@@ -322,13 +322,13 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v2, v2
; GFX11-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v3, v2
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v1, v2
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v0
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v1
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -348,13 +348,13 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v3
; GFX11-FAKE16-NEXT: v_log_f32_e32 v2, v2
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v3, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_exp_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: v_exp_f32_e32 v1, v2
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -470,13 +470,13 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v2, v2
; GFX11-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v3, v2
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v1, v2
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v0
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v1
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -496,13 +496,13 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v3
; GFX11-FAKE16-NEXT: v_log_f32_e32 v2, v2
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v3, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_exp_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: v_exp_f32_e32 v1, v2
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -619,13 +619,13 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v2, v2
; GFX11-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v3, v2
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v1, v2
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v0
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v1
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -645,13 +645,13 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v3, -v3
; GFX11-FAKE16-NEXT: v_log_f32_e32 v2, v2
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v3, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_exp_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: v_exp_f32_e32 v1, v2
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -772,13 +772,13 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v2, v2
; GFX11-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v3, v2
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v1, v2
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v0
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v1
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -798,13 +798,13 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v3, -v3
; GFX11-FAKE16-NEXT: v_log_f32_e32 v2, v2
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v3, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_exp_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: v_exp_f32_e32 v1, v2
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -867,7 +867,7 @@ define float @v_pow_f32_fabs_lhs(float %x, float %y) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_log_f32_e64 v0, |v0|
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
@@ -922,7 +922,7 @@ define float @v_pow_f32_fabs_rhs(float %x, float %y) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_log_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, |v1|, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
@@ -977,7 +977,7 @@ define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_log_f32_e64 v0, |v0|
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, |v1|, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
@@ -1027,7 +1027,7 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX11-LABEL: v_pow_f32_sgpr_vgpr:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_log_f32_e32 v1, s0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
@@ -1075,7 +1075,7 @@ define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) {
; GFX11-LABEL: v_pow_f32_vgpr_sgpr:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_log_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, s0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
@@ -1123,7 +1123,7 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX11-LABEL: v_pow_f32_sgpr_sgpr:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_log_f32_e32 v0, s0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, s1, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
diff --git a/llvm/test/CodeGen/AMDGPU/fract-match.ll b/llvm/test/CodeGen/AMDGPU/fract-match.ll
index d97ea042b50fc..f00657da440f0 100644
--- a/llvm/test/CodeGen/AMDGPU/fract-match.ll
+++ b/llvm/test/CodeGen/AMDGPU/fract-match.ll
@@ -117,7 +117,7 @@ define float @safe_math_fract_f32(float %x, ptr addrspace(1) writeonly captures(
; GFX12-NEXT: v_fract_f32_e32 v3, v0
; GFX12-NEXT: v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX12-NEXT: v_floor_f32_e32 v4, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc_lo
; GFX12-NEXT: global_store_b32 v[1:2], v4, off
@@ -229,7 +229,7 @@ define float @safe_math_fract_f32_swap(float %x, ptr addrspace(1) writeonly capt
; GFX12-NEXT: v_fract_f32_e32 v3, v0
; GFX12-NEXT: v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX12-NEXT: v_floor_f32_e32 v4, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc_lo
; GFX12-NEXT: global_store_b32 v[1:2], v4, off
@@ -420,7 +420,7 @@ define float @no_nan_check_math_fract_f32(float %x, ptr addrspace(1) writeonly c
; GFX12-NEXT: v_sub_f32_e32 v4, v0, v3
; GFX12-NEXT: global_store_b32 v[1:2], v3, off
; GFX12-NEXT: v_min_num_f32_e32 v4, 0x3f7fffff, v4
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -1539,7 +1539,7 @@ define float @wrong_commuted_nan_select_f32(float %x) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_sub_f32_e32 v1, v0, v1
; GFX12-NEXT: v_min_num_f32_e32 v1, 0x3f7fffff, v1
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -2293,11 +2293,11 @@ define <2 x float> @safe_math_fract_v2f32(<2 x float> %x, ptr addrspace(1) write
; GFX12-NEXT: v_fract_f32_e32 v7, v1
; GFX12-NEXT: v_floor_f32_e32 v4, v0
; GFX12-NEXT: v_floor_f32_e32 v5, v1
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v0, v6, 0, s0
; GFX12-NEXT: v_cmp_class_f32_e64 s0, v1, 0x204
; GFX12-NEXT: global_store_b64 v[2:3], v[4:5], off
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v1, v7, 0, s0
; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -2423,7 +2423,7 @@ define double @safe_math_fract_f64(double %x, ptr addrspace(1) writeonly capture
; GFX12-NEXT: v_fract_f64_e32 v[4:5], v[0:1]
; GFX12-NEXT: v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[0:1]|
; GFX12-NEXT: v_floor_f64_e32 v[6:7], v[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-NEXT: v_dual_cndmask_b32 v0, 0, v4 :: v_dual_cndmask_b32 v1, 0, v5
; GFX12-NEXT: global_store_b64 v[2:3], v[6:7], off
@@ -2571,7 +2571,7 @@ define half @safe_math_fract_f16(half %x, ptr addrspace(1) writeonly captures(no
; GFX12-TRUE16-NEXT: v_fract_f16_e32 v0.h, v0.l
; GFX12-TRUE16-NEXT: v_cmp_neq_f16_e64 s0, 0x7c00, |v0.l|
; GFX12-TRUE16-NEXT: v_floor_f16_e32 v3.l, v0.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, 0, v0.h, s0
; GFX12-TRUE16-NEXT: global_store_b16 v[1:2], v3, off
@@ -2587,7 +2587,7 @@ define half @safe_math_fract_f16(half %x, ptr addrspace(1) writeonly captures(no
; GFX12-FAKE16-NEXT: v_fract_f16_e32 v3, v0
; GFX12-FAKE16-NEXT: v_cmp_neq_f16_e64 vcc_lo, 0x7c00, |v0|
; GFX12-FAKE16-NEXT: v_floor_f16_e32 v4, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc_lo
; GFX12-FAKE16-NEXT: global_store_b16 v[1:2], v4, off
@@ -2790,7 +2790,7 @@ define <2 x half> @safe_math_fract_v2f16(<2 x half> %x, ptr addrspace(1) writeon
; GFX12-TRUE16-NEXT: v_cmp_class_f16_e64 s1, v0.l, 0x204
; GFX12-TRUE16-NEXT: v_floor_f16_e32 v0.h, v0.h
; GFX12-TRUE16-NEXT: v_floor_f16_e32 v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s0
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, 0, s1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -2813,12 +2813,12 @@ define <2 x half> @safe_math_fract_v2f16(<2 x half> %x, ptr addrspace(1) writeon
; GFX12-FAKE16-NEXT: v_fract_f16_e32 v4, v3
; GFX12-FAKE16-NEXT: v_cmp_class_f16_e64 s0, v3, 0x204
; GFX12-FAKE16-NEXT: v_floor_f16_e32 v7, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v4, 0, s0
; GFX12-FAKE16-NEXT: v_cmp_class_f16_e64 s0, v0, 0x204
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_pack_b32_f16 v4, v5, v7
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, v6, 0, s0
; GFX12-FAKE16-NEXT: global_store_b32 v[1:2], v4, off
; GFX12-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v3
@@ -2980,7 +2980,7 @@ define <2 x double> @safe_math_fract_v2f64(<2 x double> %x, ptr addrspace(1) wri
; GFX12-NEXT: v_cmp_class_f64_e64 s1, v[2:3], 0x204
; GFX12-NEXT: v_floor_f64_e32 v[8:9], v[2:3]
; GFX12-NEXT: v_floor_f64_e32 v[6:7], v[0:1]
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v0, v10, 0, s0
; GFX12-NEXT: v_cndmask_b32_e64 v1, v11, 0, s0
; GFX12-NEXT: v_cndmask_b32_e64 v2, v12, 0, s1
@@ -3097,7 +3097,7 @@ define float @safe_math_fract_f32_minimum(float %x, ptr addrspace(1) writeonly c
; GFX12-NEXT: v_fract_f32_e32 v3, v0
; GFX12-NEXT: v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX12-NEXT: v_floor_f32_e32 v4, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc_lo
; GFX12-NEXT: global_store_b32 v[1:2], v4, off
@@ -3212,7 +3212,7 @@ define float @safe_math_fract_f32_minimum_swap(float %x, ptr addrspace(1) writeo
; GFX12-NEXT: v_fract_f32_e32 v3, v0
; GFX12-NEXT: v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX12-NEXT: v_floor_f32_e32 v4, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc_lo
; GFX12-NEXT: global_store_b32 v[1:2], v4, off
@@ -3324,7 +3324,7 @@ define float @safe_math_fract_f32_minimumnum(float %x, ptr addrspace(1) writeonl
; GFX12-NEXT: v_fract_f32_e32 v3, v0
; GFX12-NEXT: v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX12-NEXT: v_floor_f32_e32 v4, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc_lo
; GFX12-NEXT: global_store_b32 v[1:2], v4, off
@@ -3436,7 +3436,7 @@ define float @safe_math_fract_f32_minimumnum_swap(float %x, ptr addrspace(1) wri
; GFX12-NEXT: v_fract_f32_e32 v3, v0
; GFX12-NEXT: v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX12-NEXT: v_floor_f32_e32 v4, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc_lo
; GFX12-NEXT: global_store_b32 v[1:2], v4, off
diff --git a/llvm/test/CodeGen/AMDGPU/freeze-binary.ll b/llvm/test/CodeGen/AMDGPU/freeze-binary.ll
index 93e1e4bcc0236..20085f1453595 100644
--- a/llvm/test/CodeGen/AMDGPU/freeze-binary.ll
+++ b/llvm/test/CodeGen/AMDGPU/freeze-binary.ll
@@ -152,7 +152,7 @@ define <8 x float> @freeze_frem_vec(<8 x float> %input) nounwind {
; CHECK-NEXT: v_trunc_f32_e32 v12, v0
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; CHECK-NEXT: v_sub_f32_e32 v0, v0, v12
-; CHECK-NEXT: s_waitcnt_depctr 0xfff
+; CHECK-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; CHECK-NEXT: v_fma_f32 v17, -v11, v13, 1.0
; CHECK-NEXT: v_fmac_f32_e32 v13, v17, v13
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -177,7 +177,7 @@ define <8 x float> @freeze_frem_vec(<8 x float> %input) nounwind {
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; CHECK-NEXT: v_fma_f32 v15, -v8, v19, v14
; CHECK-NEXT: v_fmac_f32_e32 v19, v15, v10
-; CHECK-NEXT: s_waitcnt_depctr 0xfff
+; CHECK-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; CHECK-NEXT: v_fma_f32 v15, -v16, v18, 1.0
; CHECK-NEXT: v_mul_f32_e32 v9, 0x3e800000, v3
; CHECK-NEXT: v_fma_f32 v8, -v8, v19, v14
diff --git a/llvm/test/CodeGen/AMDGPU/frem.ll b/llvm/test/CodeGen/AMDGPU/frem.ll
index d8cbdb11a911f..11954ab7e5a2c 100644
--- a/llvm/test/CodeGen/AMDGPU/frem.ll
+++ b/llvm/test/CodeGen/AMDGPU/frem.ll
@@ -568,7 +568,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
; GFX11-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
@@ -682,7 +682,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
; GFX11-FAKE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX11-FAKE16-NEXT: s_denorm_mode 15
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v8, v9, v8
@@ -1063,15 +1063,15 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB0_7
; GFX1200-TRUE16-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; GFX1200-TRUE16-NEXT: s_sub_co_i32 s0, s1, s0
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s0, s0, 11
; GFX1200-TRUE16-NEXT: .LBB0_5: ; %frem.loop_body
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v7, v4
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s0, s0, -11
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s0, 11
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v7, v5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1081,7 +1081,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-TRUE16-NEXT: v_fma_f32 v4, v4, v3, v7
; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1200-TRUE16-NEXT: v_add_f32_e32 v6, v4, v3
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
@@ -1102,7 +1102,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1200-TRUE16-NEXT: v_add_f32_e32 v3, v4, v3
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
@@ -1116,7 +1116,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_cmp_nle_f16_e64 s0, 0x7c00, v0.l
; GFX1200-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v2.l, s0
; GFX1200-TRUE16-NEXT: global_store_b16 v3, v0, s[8:9]
; GFX1200-TRUE16-NEXT: s_endpgm
@@ -1182,7 +1182,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v9, v10, v8
; GFX1200-FAKE16-NEXT: v_fma_f32 v5, -v7, v9, v5
; GFX1200-FAKE16-NEXT: s_denorm_mode 12
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
@@ -1190,15 +1190,15 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB0_7
; GFX1200-FAKE16-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; GFX1200-FAKE16-NEXT: s_sub_co_i32 s0, s1, s0
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s0, s0, 11
; GFX1200-FAKE16-NEXT: .LBB0_5: ; %frem.loop_body
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v7, v4
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s0, s0, -11
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_cmp_gt_i32 s0, 11
; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v4, v7, v5
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1208,7 +1208,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-FAKE16-NEXT: v_fma_f32 v4, v4, v3, v7
; GFX1200-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1200-FAKE16-NEXT: v_add_f32_e32 v6, v4, v3
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v4, v4, 11
@@ -1229,7 +1229,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1200-FAKE16-NEXT: v_add_f32_e32 v3, v4, v3
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v3, v2
@@ -1242,7 +1242,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-FAKE16-NEXT: v_cmp_nle_f16_e64 s0, 0x7c00, v0
; GFX1200-FAKE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
; GFX1200-FAKE16-NEXT: global_store_b16 v3, v0, s[8:9]
; GFX1200-FAKE16-NEXT: s_endpgm
@@ -1444,7 +1444,7 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v3.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v4, v4
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v0, v0, v4
; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v0, v2 op_sel_hi:[1,0,1]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1480,7 +1480,7 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v4, v4
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_mul_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1]
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1845,7 +1845,7 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v3.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v4, v4
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v0, v0, v4
; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v0, v2 op_sel_hi:[1,0,1]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1881,7 +1881,7 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v4, v4
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_mul_f32_e32 v3, v3, v4
; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1]
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -2568,7 +2568,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-NEXT: v_add_nc_u32_e32 v6, v6, v5
; GFX11-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v9, -v7, v8, 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fmac_f32_e32 v8, v9, v8
@@ -2801,7 +2801,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: v_fmac_f32_e32 v10, v11, v9
; GFX1200-NEXT: v_fma_f32 v6, -v8, v10, v6
; GFX1200-NEXT: s_denorm_mode 12
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_div_fmas_f32 v6, v6, v9, v10
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v7
@@ -2826,7 +2826,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1200-NEXT: v_add_f32_e32 v7, v5, v4
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v5, v5, 12
@@ -2847,7 +2847,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1200-NEXT: v_add_f32_e32 v4, v5, v4
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v3, v4, v3
@@ -2857,7 +2857,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: v_cmp_nle_f32_e64 s0, 0x7f800000, v1
; GFX1200-NEXT: v_mov_b32_e32 v2, 0
; GFX1200-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v3, vcc_lo
; GFX1200-NEXT: global_store_b32 v2, v0, s[8:9]
; GFX1200-NEXT: s_endpgm
@@ -3049,7 +3049,7 @@ define amdgpu_kernel void @fast_frem_f32(ptr addrspace(1) %out, ptr addrspace(1)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f32_e32 v5, v4
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v6, -v4, v5, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -3327,7 +3327,7 @@ define amdgpu_kernel void @unsafe_frem_f32(ptr addrspace(1) %out, ptr addrspace(
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f32_e32 v5, v4
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v6, -v4, v5, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -3985,7 +3985,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_rcp_f64_e32 v[10:11], v[8:9]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
@@ -4208,7 +4208,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_mul_f64_e32 v[16:17], v[14:15], v[10:11]
; GFX1200-NEXT: v_fma_f64 v[8:9], -v[8:9], v[16:17], v[14:15]
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[16:17]
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v13
@@ -4231,7 +4231,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: v_fma_f64 v[6:7], -v[6:7], v[4:5], v[10:11]
; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX1200-NEXT: v_add_f64_e32 v[13:14], v[6:7], v[4:5]
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_dual_cndmask_b32 v7, v7, v14 :: v_dual_cndmask_b32 v6, v6, v13
; GFX1200-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
@@ -4250,7 +4250,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: v_fma_f64 v[6:7], -v[8:9], v[4:5], v[6:7]
; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX1200-NEXT: v_add_f64_e32 v[4:5], v[6:7], v[4:5]
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_dual_cndmask_b32 v5, v7, v5 :: v_dual_cndmask_b32 v4, v6, v4
; GFX1200-NEXT: v_ldexp_f64 v[4:5], v[4:5], v12
@@ -4260,7 +4260,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0, v[2:3]
; GFX1200-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
; GFX1200-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_dual_mov_b32 v6, 0 :: v_dual_cndmask_b32 v1, 0x7ff80000, v5
; GFX1200-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
; GFX1200-NEXT: global_store_b64 v6, v[0:1], s[0:1]
@@ -4459,7 +4459,7 @@ define amdgpu_kernel void @fast_frem_f64(ptr addrspace(1) %out, ptr addrspace(1)
; GFX11-NEXT: v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f64_e32 v[6:7], v[4:5]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX11-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4737,7 +4737,7 @@ define amdgpu_kernel void @unsafe_frem_f64(ptr addrspace(1) %out, ptr addrspace(
; GFX11-NEXT: v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f64_e32 v[6:7], v[4:5]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
; GFX11-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -5813,7 +5813,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
; GFX11-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
@@ -5911,7 +5911,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v9, v8
; GFX11-TRUE16-NEXT: v_div_scale_f32 v8, vcc_lo, 1.0, v6, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_fma_f32 v12, -v10, v11, 1.0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v11, v12, v11
@@ -6029,7 +6029,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
; GFX11-FAKE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX11-FAKE16-NEXT: s_denorm_mode 15
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v8, v9, v8
@@ -6124,7 +6124,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v9, v8
; GFX11-FAKE16-NEXT: v_div_scale_f32 v8, vcc_lo, 1.0, v6, 1.0
; GFX11-FAKE16-NEXT: s_denorm_mode 15
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_fma_f32 v12, -v10, v11, 1.0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v11, v12, v11
@@ -6734,15 +6734,15 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB9_7
; GFX1200-TRUE16-NEXT: ; %bb.4: ; %frem.loop_body27.preheader
; GFX1200-TRUE16-NEXT: s_sub_co_i32 s5, s6, s5
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s5, s5, 11
; GFX1200-TRUE16-NEXT: .LBB9_5: ; %frem.loop_body27
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v5, v2
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s5, s5, -11
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s5, 11
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -6752,7 +6752,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_fma_f32 v2, v2, v1, v5
; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-TRUE16-NEXT: v_add_f32_e32 v4, v2, v1
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
@@ -6773,7 +6773,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-TRUE16-NEXT: v_add_f32_e32 v1, v2, v1
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v1, v0
@@ -6784,13 +6784,13 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: .LBB9_8:
; GFX1200-TRUE16-NEXT: s_lshr_b32 s6, s4, 16
; GFX1200-TRUE16-NEXT: s_lshr_b32 s5, s3, 16
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_and_b32 s4, s6, 0x7fff
; GFX1200-TRUE16-NEXT: s_and_b32 s7, s5, 0x7fff
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s8, s4
; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s7, s7
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s8, s7
; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB9_10
@@ -6836,7 +6836,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
; GFX1200-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
@@ -6844,15 +6844,15 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB9_15
; GFX1200-TRUE16-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; GFX1200-TRUE16-NEXT: s_sub_co_i32 s7, s8, s7
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s7, s7, 11
; GFX1200-TRUE16-NEXT: .LBB9_13: ; %frem.loop_body
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s7, s7, -11
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s7, 11
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v6, v4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -6862,7 +6862,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_fma_f32 v3, v3, v2, v6
; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1200-TRUE16-NEXT: v_add_f32_e32 v5, v3, v2
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
@@ -6883,7 +6883,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1200-TRUE16-NEXT: v_add_f32_e32 v2, v3, v2
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v2, v1
@@ -6904,9 +6904,9 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX1200-TRUE16-NEXT: s_cmp_nge_f16 s4, 0x7c00
; GFX1200-TRUE16-NEXT: s_cselect_b32 s3, -1, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_and_b32 s2, s3, s2
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v1.l, s2
; GFX1200-TRUE16-NEXT: global_store_b32 v2, v0, s[0:1]
; GFX1200-TRUE16-NEXT: s_endpgm
@@ -6972,7 +6972,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v7, v8, v6
; GFX1200-FAKE16-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX1200-FAKE16-NEXT: s_denorm_mode 12
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
@@ -6980,15 +6980,15 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB9_7
; GFX1200-FAKE16-NEXT: ; %bb.4: ; %frem.loop_body27.preheader
; GFX1200-FAKE16-NEXT: s_sub_co_i32 s5, s6, s5
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s5, s5, 11
; GFX1200-FAKE16-NEXT: .LBB9_5: ; %frem.loop_body27
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v5, v2
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s5, s5, -11
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_cmp_gt_i32 s5, 11
; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v2, v5, v3
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -6998,7 +6998,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_fma_f32 v2, v2, v1, v5
; GFX1200-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-FAKE16-NEXT: v_add_f32_e32 v4, v2, v1
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v2, 11
@@ -7019,7 +7019,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-FAKE16-NEXT: v_add_f32_e32 v1, v2, v1
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v0, v1, v0
@@ -7029,13 +7029,13 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: .LBB9_8:
; GFX1200-FAKE16-NEXT: s_lshr_b32 s6, s4, 16
; GFX1200-FAKE16-NEXT: s_lshr_b32 s5, s3, 16
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_and_b32 s4, s6, 0x7fff
; GFX1200-FAKE16-NEXT: s_and_b32 s7, s5, 0x7fff
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s8, s4
; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s7, s7
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-FAKE16-NEXT: s_cmp_ngt_f32 s8, s7
; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB9_10
@@ -7043,7 +7043,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s8, s7
; GFX1200-FAKE16-NEXT: v_bfi_b32 v1, 0x7fff, 0, s6
; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v1, s6, v1, vcc_lo
; GFX1200-FAKE16-NEXT: s_cbranch_execz .LBB9_11
@@ -7080,7 +7080,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v8, v9, v7
; GFX1200-FAKE16-NEXT: v_fma_f32 v4, -v6, v8, v4
; GFX1200-FAKE16-NEXT: s_denorm_mode 12
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
@@ -7088,15 +7088,15 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB9_15
; GFX1200-FAKE16-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; GFX1200-FAKE16-NEXT: s_sub_co_i32 s7, s8, s7
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s7, s7, 11
; GFX1200-FAKE16-NEXT: .LBB9_13: ; %frem.loop_body
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s7, s7, -11
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_cmp_gt_i32 s7, 11
; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v3, v6, v4
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -7106,7 +7106,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_fma_f32 v3, v3, v2, v6
; GFX1200-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1200-FAKE16-NEXT: v_add_f32_e32 v5, v3, v2
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v3, 11
@@ -7127,7 +7127,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1200-FAKE16-NEXT: v_add_f32_e32 v2, v3, v2
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v1, v2, v1
@@ -7142,7 +7142,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s3
; GFX1200-FAKE16-NEXT: s_cmp_lg_f16 s5, 0
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo
; GFX1200-FAKE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX1200-FAKE16-NEXT: s_cmp_nge_f16 s4, 0x7c00
@@ -7150,7 +7150,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX1200-FAKE16-NEXT: s_cselect_b32 s3, -1, 0
; GFX1200-FAKE16-NEXT: s_and_b32 vcc_lo, s3, s2
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v1, 0x7e00, v1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
@@ -8986,7 +8986,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v7
; GFX11-TRUE16-NEXT: v_div_scale_f32 v7, vcc_lo, 1.0, v5, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_fma_f32 v11, -v9, v10, 1.0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v10, v11, v10
@@ -9084,7 +9084,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v11, v10
; GFX11-TRUE16-NEXT: v_div_scale_f32 v10, vcc_lo, 1.0, v8, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_fma_f32 v14, -v12, v13, 1.0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v13, v14, v13
@@ -9179,7 +9179,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, v12, v11
; GFX11-TRUE16-NEXT: v_div_scale_f32 v11, vcc_lo, 1.0, v9, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_fma_f32 v15, -v13, v14, 1.0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v14, v15, v14
@@ -9277,7 +9277,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, v15, v14
; GFX11-TRUE16-NEXT: v_div_scale_f32 v14, vcc_lo, 1.0, v12, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_fma_f32 v18, -v16, v17, 1.0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v17, v18, v17
@@ -9403,7 +9403,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v7
; GFX11-FAKE16-NEXT: v_div_scale_f32 v7, vcc_lo, 1.0, v5, 1.0
; GFX11-FAKE16-NEXT: s_denorm_mode 15
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_fma_f32 v11, -v9, v10, 1.0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v10, v11, v10
@@ -9498,7 +9498,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v11, v10
; GFX11-FAKE16-NEXT: v_div_scale_f32 v10, vcc_lo, 1.0, v8, 1.0
; GFX11-FAKE16-NEXT: s_denorm_mode 15
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_fma_f32 v14, -v12, v13, 1.0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v13, v14, v13
@@ -9590,7 +9590,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v12, v11
; GFX11-FAKE16-NEXT: v_div_scale_f32 v11, vcc_lo, 1.0, v9, 1.0
; GFX11-FAKE16-NEXT: s_denorm_mode 15
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_fma_f32 v15, -v13, v14, 1.0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v14, v15, v14
@@ -9685,7 +9685,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v15, v14
; GFX11-FAKE16-NEXT: v_div_scale_f32 v14, vcc_lo, 1.0, v12, 1.0
; GFX11-FAKE16-NEXT: s_denorm_mode 15
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_fma_f32 v18, -v16, v17, 1.0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v17, v18, v17
@@ -10742,15 +10742,15 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_7
; GFX1200-TRUE16-NEXT: ; %bb.4: ; %frem.loop_body93.preheader
; GFX1200-TRUE16-NEXT: s_sub_co_i32 s6, s8, s6
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s6, s6, 11
; GFX1200-TRUE16-NEXT: .LBB10_5: ; %frem.loop_body93
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v5, v2
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s6, s6, -11
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s6, 11
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -10760,7 +10760,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_fma_f32 v2, v2, v1, v5
; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-TRUE16-NEXT: v_add_f32_e32 v4, v2, v1
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
@@ -10781,7 +10781,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-TRUE16-NEXT: v_add_f32_e32 v1, v2, v1
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v1, v0
@@ -10792,13 +10792,13 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: .LBB10_8:
; GFX1200-TRUE16-NEXT: s_lshr_b32 s8, s5, 16
; GFX1200-TRUE16-NEXT: s_lshr_b32 s6, s4, 16
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_and_b32 s5, s8, 0x7fff
; GFX1200-TRUE16-NEXT: s_and_b32 s9, s6, 0x7fff
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s10, s5
; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s9, s9
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s10, s9
; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_10
@@ -10844,7 +10844,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
; GFX1200-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
@@ -10852,15 +10852,15 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_15
; GFX1200-TRUE16-NEXT: ; %bb.12: ; %frem.loop_body60.preheader
; GFX1200-TRUE16-NEXT: s_sub_co_i32 s9, s10, s9
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s9, s9, 11
; GFX1200-TRUE16-NEXT: .LBB10_13: ; %frem.loop_body60
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s9, s9, -11
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s9, 11
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v6, v4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -10870,7 +10870,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_fma_f32 v3, v3, v2, v6
; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1200-TRUE16-NEXT: v_add_f32_e32 v5, v3, v2
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
@@ -10891,7 +10891,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1200-TRUE16-NEXT: v_add_f32_e32 v2, v3, v2
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v2, v1
@@ -10902,10 +10902,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: .LBB10_16:
; GFX1200-TRUE16-NEXT: s_and_b32 s8, s7, 0x7fff
; GFX1200-TRUE16-NEXT: s_and_b32 s9, s2, 0x7fff
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s10, s8
; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s9, s9
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s10, s9
; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_18
@@ -10916,7 +10916,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_bfi_b32 v2, 0x7fff, v3, v2
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: v_cndmask_b16 v2.l, s7, v2.l, s11
; GFX1200-TRUE16-NEXT: s_cbranch_execz .LBB10_19
; GFX1200-TRUE16-NEXT: s_branch .LBB10_24
@@ -10952,7 +10952,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
; GFX1200-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
@@ -10960,15 +10960,15 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_23
; GFX1200-TRUE16-NEXT: ; %bb.20: ; %frem.loop_body27.preheader
; GFX1200-TRUE16-NEXT: s_sub_co_i32 s9, s10, s9
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s9, s9, 11
; GFX1200-TRUE16-NEXT: .LBB10_21: ; %frem.loop_body27
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v7, v4
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s9, s9, -11
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s9, 11
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v7, v5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -10978,7 +10978,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_fma_f32 v4, v4, v3, v7
; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1200-TRUE16-NEXT: v_add_f32_e32 v6, v4, v3
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
@@ -10999,7 +10999,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1200-TRUE16-NEXT: v_add_f32_e32 v3, v4, v3
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
@@ -11010,13 +11010,13 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: .LBB10_24:
; GFX1200-TRUE16-NEXT: s_lshr_b32 s10, s7, 16
; GFX1200-TRUE16-NEXT: s_lshr_b32 s9, s2, 16
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_and_b32 s7, s10, 0x7fff
; GFX1200-TRUE16-NEXT: s_and_b32 s11, s9, 0x7fff
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s12, s7
; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s11, s11
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s12, s11
; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_26
@@ -11062,7 +11062,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v10, v11, v9
; GFX1200-TRUE16-NEXT: v_fma_f32 v6, -v8, v10, v6
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v6, v6, v9, v10
; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v7
@@ -11070,15 +11070,15 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_31
; GFX1200-TRUE16-NEXT: ; %bb.28: ; %frem.loop_body.preheader
; GFX1200-TRUE16-NEXT: s_sub_co_i32 s11, s12, s11
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s11, s11, 11
; GFX1200-TRUE16-NEXT: .LBB10_29: ; %frem.loop_body
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v8, v5
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s11, s11, -11
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s11, 11
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v5, v8, v6
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -11088,7 +11088,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_fma_f32 v5, v5, v4, v8
; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1200-TRUE16-NEXT: v_add_f32_e32 v7, v5, v4
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v5, v5, 11
@@ -11109,7 +11109,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1200-TRUE16-NEXT: v_add_f32_e32 v4, v5, v4
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v4, v3
@@ -11122,33 +11122,33 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_cselect_b32 s4, -1, 0
; GFX1200-TRUE16-NEXT: s_cmp_nge_f16 s3, 0x7c00
; GFX1200-TRUE16-NEXT: s_cselect_b32 s3, -1, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_and_b32 s3, s3, s4
; GFX1200-TRUE16-NEXT: s_cmp_lg_f16 s6, 0
; GFX1200-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, s3
; GFX1200-TRUE16-NEXT: s_cselect_b32 s3, -1, 0
; GFX1200-TRUE16-NEXT: s_cmp_nge_f16 s5, 0x7c00
; GFX1200-TRUE16-NEXT: s_cselect_b32 s4, -1, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_and_b32 s3, s4, s3
; GFX1200-TRUE16-NEXT: s_cmp_lg_f16 s2, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v1.l, s3
; GFX1200-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX1200-TRUE16-NEXT: s_cmp_nge_f16 s8, 0x7c00
; GFX1200-TRUE16-NEXT: s_cselect_b32 s3, -1, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_and_b32 s2, s3, s2
; GFX1200-TRUE16-NEXT: s_cmp_lg_f16 s9, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v2.l, s2
; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v2, 0
; GFX1200-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX1200-TRUE16-NEXT: s_cmp_nge_f16 s7, 0x7c00
; GFX1200-TRUE16-NEXT: s_cselect_b32 s3, -1, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_and_b32 s2, s3, s2
-; GFX1200-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v3.l, s2
; GFX1200-TRUE16-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1200-TRUE16-NEXT: s_endpgm
@@ -11216,7 +11216,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v7, v8, v6
; GFX1200-FAKE16-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX1200-FAKE16-NEXT: s_denorm_mode 12
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
@@ -11224,15 +11224,15 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_7
; GFX1200-FAKE16-NEXT: ; %bb.4: ; %frem.loop_body93.preheader
; GFX1200-FAKE16-NEXT: s_sub_co_i32 s6, s8, s6
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s6, s6, 11
; GFX1200-FAKE16-NEXT: .LBB10_5: ; %frem.loop_body93
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v5, v2
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s6, s6, -11
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_cmp_gt_i32 s6, 11
; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v2, v5, v3
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -11242,7 +11242,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_fma_f32 v2, v2, v1, v5
; GFX1200-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-FAKE16-NEXT: v_add_f32_e32 v4, v2, v1
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v2, 11
@@ -11263,7 +11263,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-FAKE16-NEXT: v_add_f32_e32 v1, v2, v1
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v0, v1, v0
@@ -11273,13 +11273,13 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: .LBB10_8:
; GFX1200-FAKE16-NEXT: s_lshr_b32 s8, s5, 16
; GFX1200-FAKE16-NEXT: s_lshr_b32 s6, s4, 16
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_and_b32 s5, s8, 0x7fff
; GFX1200-FAKE16-NEXT: s_and_b32 s9, s6, 0x7fff
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s10, s5
; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s9, s9
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-FAKE16-NEXT: s_cmp_ngt_f32 s10, s9
; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_10
@@ -11287,7 +11287,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s10, s9
; GFX1200-FAKE16-NEXT: v_bfi_b32 v1, 0x7fff, 0, s8
; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v1, s8, v1, vcc_lo
; GFX1200-FAKE16-NEXT: s_cbranch_execz .LBB10_11
@@ -11324,7 +11324,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v8, v9, v7
; GFX1200-FAKE16-NEXT: v_fma_f32 v4, -v6, v8, v4
; GFX1200-FAKE16-NEXT: s_denorm_mode 12
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
@@ -11332,15 +11332,15 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_15
; GFX1200-FAKE16-NEXT: ; %bb.12: ; %frem.loop_body60.preheader
; GFX1200-FAKE16-NEXT: s_sub_co_i32 s9, s10, s9
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s9, s9, 11
; GFX1200-FAKE16-NEXT: .LBB10_13: ; %frem.loop_body60
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s9, s9, -11
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_cmp_gt_i32 s9, 11
; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v3, v6, v4
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -11350,7 +11350,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_fma_f32 v3, v3, v2, v6
; GFX1200-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1200-FAKE16-NEXT: v_add_f32_e32 v5, v3, v2
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v3, 11
@@ -11371,7 +11371,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1200-FAKE16-NEXT: v_add_f32_e32 v2, v3, v2
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v1, v2, v1
@@ -11381,10 +11381,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: .LBB10_16:
; GFX1200-FAKE16-NEXT: s_and_b32 s8, s7, 0x7fff
; GFX1200-FAKE16-NEXT: s_and_b32 s9, s2, 0x7fff
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s10, s8
; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s9, s9
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-FAKE16-NEXT: s_cmp_ngt_f32 s10, s9
; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_18
@@ -11392,7 +11392,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s10, s9
; GFX1200-FAKE16-NEXT: v_bfi_b32 v2, 0x7fff, 0, s7
; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v2, s7, v2, vcc_lo
; GFX1200-FAKE16-NEXT: s_cbranch_execz .LBB10_19
@@ -11429,7 +11429,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v9, v10, v8
; GFX1200-FAKE16-NEXT: v_fma_f32 v5, -v7, v9, v5
; GFX1200-FAKE16-NEXT: s_denorm_mode 12
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
@@ -11437,15 +11437,15 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_23
; GFX1200-FAKE16-NEXT: ; %bb.20: ; %frem.loop_body27.preheader
; GFX1200-FAKE16-NEXT: s_sub_co_i32 s9, s10, s9
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s9, s9, 11
; GFX1200-FAKE16-NEXT: .LBB10_21: ; %frem.loop_body27
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v7, v4
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s9, s9, -11
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_cmp_gt_i32 s9, 11
; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v4, v7, v5
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -11455,7 +11455,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_fma_f32 v4, v4, v3, v7
; GFX1200-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1200-FAKE16-NEXT: v_add_f32_e32 v6, v4, v3
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v4, v4, 11
@@ -11476,7 +11476,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1200-FAKE16-NEXT: v_add_f32_e32 v3, v4, v3
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v3, v2
@@ -11486,13 +11486,13 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: .LBB10_24:
; GFX1200-FAKE16-NEXT: s_lshr_b32 s10, s7, 16
; GFX1200-FAKE16-NEXT: s_lshr_b32 s9, s2, 16
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_and_b32 s7, s10, 0x7fff
; GFX1200-FAKE16-NEXT: s_and_b32 s11, s9, 0x7fff
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s12, s7
; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s11, s11
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-FAKE16-NEXT: s_cmp_ngt_f32 s12, s11
; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_26
@@ -11500,7 +11500,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s12, s11
; GFX1200-FAKE16-NEXT: v_bfi_b32 v3, 0x7fff, 0, s10
; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v3, s10, v3, vcc_lo
; GFX1200-FAKE16-NEXT: s_cbranch_execz .LBB10_27
@@ -11537,7 +11537,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v10, v11, v9
; GFX1200-FAKE16-NEXT: v_fma_f32 v6, -v8, v10, v6
; GFX1200-FAKE16-NEXT: s_denorm_mode 12
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v6, v6, v9, v10
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v7
@@ -11545,15 +11545,15 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_31
; GFX1200-FAKE16-NEXT: ; %bb.28: ; %frem.loop_body.preheader
; GFX1200-FAKE16-NEXT: s_sub_co_i32 s11, s12, s11
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s11, s11, 11
; GFX1200-FAKE16-NEXT: .LBB10_29: ; %frem.loop_body
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v8, v5
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s11, s11, -11
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_cmp_gt_i32 s11, 11
; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v5, v8, v6
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -11563,7 +11563,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_fma_f32 v5, v5, v4, v8
; GFX1200-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1200-FAKE16-NEXT: v_add_f32_e32 v7, v5, v4
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v5, v5, 11
@@ -11584,7 +11584,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1200-FAKE16-NEXT: v_add_f32_e32 v4, v5, v4
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v4, v3
@@ -11596,20 +11596,20 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_cselect_b32 s4, -1, 0
; GFX1200-FAKE16-NEXT: s_cmp_nge_f16 s3, 0x7c00
; GFX1200-FAKE16-NEXT: s_cselect_b32 s3, -1, 0
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_and_b32 vcc_lo, s3, s4
; GFX1200-FAKE16-NEXT: s_cmp_lg_f16 s6, 0
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo
; GFX1200-FAKE16-NEXT: s_cselect_b32 s3, -1, 0
; GFX1200-FAKE16-NEXT: s_cmp_nge_f16 s5, 0x7c00
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX1200-FAKE16-NEXT: s_cselect_b32 s4, -1, 0
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_and_b32 vcc_lo, s4, s3
; GFX1200-FAKE16-NEXT: s_cmp_lg_f16 s2, 0
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v4, 0x7e00, v1, vcc_lo
; GFX1200-FAKE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX1200-FAKE16-NEXT: s_cmp_nge_f16 s8, 0x7c00
@@ -11618,7 +11618,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_cselect_b32 s3, -1, 0
; GFX1200-FAKE16-NEXT: s_and_b32 vcc_lo, s3, s2
; GFX1200-FAKE16-NEXT: s_cmp_lg_f16 s9, 0
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: v_dual_cndmask_b32 v1, 0x7e00, v2 :: v_dual_mov_b32 v2, 0
; GFX1200-FAKE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX1200-FAKE16-NEXT: s_cmp_nge_f16 s7, 0x7c00
@@ -11626,7 +11626,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX1200-FAKE16-NEXT: s_cselect_b32 s3, -1, 0
; GFX1200-FAKE16-NEXT: s_and_b32 vcc_lo, s3, s2
-; GFX1200-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v3, 0x7e00, v3, vcc_lo
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v1
@@ -12526,7 +12526,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_add_nc_u32_e32 v8, v8, v7
; GFX11-NEXT: v_div_scale_f32 v7, vcc_lo, 1.0, v5, 1.0
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v11, -v9, v10, 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fmac_f32_e32 v10, v11, v10
@@ -12615,7 +12615,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_add_nc_u32_e32 v9, v9, v8
; GFX11-NEXT: v_div_scale_f32 v8, vcc_lo, 1.0, v6, 1.0
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v12, -v10, v11, 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fmac_f32_e32 v11, v12, v11
@@ -12963,7 +12963,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_fmac_f32_e32 v7, v8, v6
; GFX1200-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX1200-NEXT: s_denorm_mode 12
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v4
@@ -12971,15 +12971,15 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_cbranch_vccnz .LBB11_7
; GFX1200-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
; GFX1200-NEXT: s_sub_co_i32 s7, s7, s8
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s7, s7, 12
; GFX1200-NEXT: .LBB11_5: ; %frem.loop_body23
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v5, v2
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s7, s7, -12
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cmp_gt_i32 s7, 12
; GFX1200-NEXT: v_mul_f32_e32 v2, v5, v3
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -12989,7 +12989,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_fma_f32 v2, v2, v1, v5
; GFX1200-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-NEXT: v_add_f32_e32 v4, v2, v1
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1200-NEXT: v_ldexp_f32 v2, v2, 12
@@ -13010,7 +13010,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-NEXT: v_add_f32_e32 v1, v2, v1
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v0, v1, v0
@@ -13018,14 +13018,14 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: .LBB11_8:
; GFX1200-NEXT: s_and_b32 s6, s5, 0x7fffffff
; GFX1200-NEXT: s_and_b32 s8, s2, 0x7fffffff
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cmp_ngt_f32 s6, s8
; GFX1200-NEXT: s_cbranch_scc0 .LBB11_10
; GFX1200-NEXT: ; %bb.9: ; %frem.else
; GFX1200-NEXT: s_cmp_eq_f32 s6, s8
; GFX1200-NEXT: v_bfi_b32 v1, 0x7fffffff, 0, s5
; GFX1200-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v1, s5, v1, vcc_lo
; GFX1200-NEXT: s_cbranch_execz .LBB11_11
@@ -13062,7 +13062,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_fmac_f32_e32 v8, v9, v7
; GFX1200-NEXT: v_fma_f32 v4, -v6, v8, v4
; GFX1200-NEXT: s_denorm_mode 12
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v5
@@ -13070,15 +13070,15 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_cbranch_vccnz .LBB11_15
; GFX1200-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; GFX1200-NEXT: s_sub_co_i32 s7, s7, s8
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s7, s7, 12
; GFX1200-NEXT: .LBB11_13: ; %frem.loop_body
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v6, v3
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s7, s7, -12
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cmp_gt_i32 s7, 12
; GFX1200-NEXT: v_mul_f32_e32 v3, v6, v4
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -13088,7 +13088,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_fma_f32 v3, v3, v2, v6
; GFX1200-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1200-NEXT: v_add_f32_e32 v5, v3, v2
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1200-NEXT: v_ldexp_f32 v3, v3, 12
@@ -13109,7 +13109,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1200-NEXT: v_add_f32_e32 v2, v3, v2
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v1, v2, v1
@@ -13119,17 +13119,17 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_cselect_b32 s4, -1, 0
; GFX1200-NEXT: s_cmp_nge_f32 s3, 0x7f800000
; GFX1200-NEXT: s_cselect_b32 s3, -1, 0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_b32 vcc_lo, s3, s4
; GFX1200-NEXT: s_cmp_lg_f32 s2, 0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
; GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GFX1200-NEXT: s_cmp_nge_f32 s6, 0x7f800000
; GFX1200-NEXT: s_cselect_b32 s3, -1, 0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_b32 vcc_lo, s3, s2
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v1, 0x7fc00000, v1
; GFX1200-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1200-NEXT: s_endpgm
@@ -14775,7 +14775,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_add_nc_u32_e32 v12, v12, v11
; GFX11-NEXT: v_div_scale_f32 v11, vcc_lo, 1.0, v9, 1.0
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v15, -v13, v14, 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fmac_f32_e32 v14, v15, v14
@@ -14864,7 +14864,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_add_nc_u32_e32 v13, v13, v12
; GFX11-NEXT: v_div_scale_f32 v12, vcc_lo, 1.0, v10, 1.0
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v16, -v14, v15, 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fmac_f32_e32 v15, v16, v15
@@ -14953,7 +14953,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_add_nc_u32_e32 v14, v14, v13
; GFX11-NEXT: v_div_scale_f32 v13, vcc_lo, 1.0, v11, 1.0
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v17, -v15, v16, 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fmac_f32_e32 v16, v17, v16
@@ -15042,7 +15042,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_add_nc_u32_e32 v15, v15, v14
; GFX11-NEXT: v_div_scale_f32 v14, vcc_lo, 1.0, v12, 1.0
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v18, -v16, v17, 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fmac_f32_e32 v17, v18, v17
@@ -15610,7 +15610,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_fmac_f32_e32 v7, v8, v6
; GFX1200-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX1200-NEXT: s_denorm_mode 12
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v4
@@ -15635,7 +15635,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-NEXT: v_add_f32_e32 v4, v2, v1
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v2, v2, 12
@@ -15656,7 +15656,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
; GFX1200-NEXT: v_add_f32_e32 v1, v2, v1
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v0, v1, v0
@@ -15664,14 +15664,14 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: .LBB12_8:
; GFX1200-NEXT: s_and_b32 s8, s10, 0x7fffffff
; GFX1200-NEXT: s_and_b32 s12, s4, 0x7fffffff
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cmp_ngt_f32 s8, s12
; GFX1200-NEXT: s_cbranch_scc0 .LBB12_10
; GFX1200-NEXT: ; %bb.9: ; %frem.else47
; GFX1200-NEXT: s_cmp_eq_f32 s8, s12
; GFX1200-NEXT: v_bfi_b32 v1, 0x7fffffff, 0, s10
; GFX1200-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v1, s10, v1, vcc_lo
; GFX1200-NEXT: s_cbranch_execz .LBB12_11
@@ -15708,7 +15708,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_fmac_f32_e32 v8, v9, v7
; GFX1200-NEXT: v_fma_f32 v4, -v6, v8, v4
; GFX1200-NEXT: s_denorm_mode 12
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v5
@@ -15716,15 +15716,15 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_cbranch_vccnz .LBB12_15
; GFX1200-NEXT: ; %bb.12: ; %frem.loop_body54.preheader
; GFX1200-NEXT: s_sub_co_i32 s11, s11, s12
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s11, s11, 12
; GFX1200-NEXT: .LBB12_13: ; %frem.loop_body54
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v6, v3
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s11, s11, -12
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cmp_gt_i32 s11, 12
; GFX1200-NEXT: v_mul_f32_e32 v3, v6, v4
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -15734,7 +15734,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_fma_f32 v3, v3, v2, v6
; GFX1200-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1200-NEXT: v_add_f32_e32 v5, v3, v2
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1200-NEXT: v_ldexp_f32 v3, v3, 12
@@ -15755,7 +15755,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
; GFX1200-NEXT: v_add_f32_e32 v2, v3, v2
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v1, v2, v1
@@ -15763,14 +15763,14 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: .LBB12_16:
; GFX1200-NEXT: s_and_b32 s10, s9, 0x7fffffff
; GFX1200-NEXT: s_and_b32 s12, s3, 0x7fffffff
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cmp_ngt_f32 s10, s12
; GFX1200-NEXT: s_cbranch_scc0 .LBB12_18
; GFX1200-NEXT: ; %bb.17: ; %frem.else16
; GFX1200-NEXT: s_cmp_eq_f32 s10, s12
; GFX1200-NEXT: v_bfi_b32 v2, 0x7fffffff, 0, s9
; GFX1200-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v2, s9, v2, vcc_lo
; GFX1200-NEXT: s_cbranch_execz .LBB12_19
@@ -15807,7 +15807,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_fmac_f32_e32 v9, v10, v8
; GFX1200-NEXT: v_fma_f32 v5, -v7, v9, v5
; GFX1200-NEXT: s_denorm_mode 12
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v6
@@ -15815,15 +15815,15 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_cbranch_vccnz .LBB12_23
; GFX1200-NEXT: ; %bb.20: ; %frem.loop_body23.preheader
; GFX1200-NEXT: s_sub_co_i32 s11, s11, s12
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s11, s11, 12
; GFX1200-NEXT: .LBB12_21: ; %frem.loop_body23
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v7, v4
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s11, s11, -12
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cmp_gt_i32 s11, 12
; GFX1200-NEXT: v_mul_f32_e32 v4, v7, v5
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -15833,7 +15833,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_fma_f32 v4, v4, v3, v7
; GFX1200-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1200-NEXT: v_add_f32_e32 v6, v4, v3
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1200-NEXT: v_ldexp_f32 v4, v4, 12
@@ -15854,7 +15854,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
; GFX1200-NEXT: v_add_f32_e32 v3, v4, v3
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v2, v3, v2
@@ -15862,14 +15862,14 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: .LBB12_24:
; GFX1200-NEXT: s_and_b32 s9, s7, 0x7fffffff
; GFX1200-NEXT: s_and_b32 s12, s2, 0x7fffffff
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cmp_ngt_f32 s9, s12
; GFX1200-NEXT: s_cbranch_scc0 .LBB12_26
; GFX1200-NEXT: ; %bb.25: ; %frem.else
; GFX1200-NEXT: s_cmp_eq_f32 s9, s12
; GFX1200-NEXT: v_bfi_b32 v3, 0x7fffffff, 0, s7
; GFX1200-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v3, s7, v3, vcc_lo
; GFX1200-NEXT: s_cbranch_execz .LBB12_27
@@ -15906,7 +15906,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_fmac_f32_e32 v10, v11, v9
; GFX1200-NEXT: v_fma_f32 v6, -v8, v10, v6
; GFX1200-NEXT: s_denorm_mode 12
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_div_fmas_f32 v6, v6, v9, v10
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v7
@@ -15914,15 +15914,15 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_cbranch_vccnz .LBB12_31
; GFX1200-NEXT: ; %bb.28: ; %frem.loop_body.preheader
; GFX1200-NEXT: s_sub_co_i32 s11, s11, s12
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s11, s11, 12
; GFX1200-NEXT: .LBB12_29: ; %frem.loop_body
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v8, v5
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s11, s11, -12
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cmp_gt_i32 s11, 12
; GFX1200-NEXT: v_mul_f32_e32 v5, v8, v6
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -15932,7 +15932,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_fma_f32 v5, v5, v4, v8
; GFX1200-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1200-NEXT: v_add_f32_e32 v7, v5, v4
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1200-NEXT: v_ldexp_f32 v5, v5, 12
@@ -15953,7 +15953,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
; GFX1200-NEXT: v_add_f32_e32 v4, v5, v4
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v3, v4, v3
@@ -15964,33 +15964,33 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_cselect_b32 s6, -1, 0
; GFX1200-NEXT: s_cmp_nge_f32 s5, 0x7f800000
; GFX1200-NEXT: s_cselect_b32 s5, -1, 0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_b32 vcc_lo, s5, s6
; GFX1200-NEXT: s_cmp_lg_f32 s4, 0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
; GFX1200-NEXT: s_cselect_b32 s4, -1, 0
; GFX1200-NEXT: s_cmp_nge_f32 s8, 0x7f800000
; GFX1200-NEXT: s_cselect_b32 s5, -1, 0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_b32 vcc_lo, s5, s4
; GFX1200-NEXT: s_cmp_lg_f32 s3, 0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v1, 0x7fc00000, v1, vcc_lo
; GFX1200-NEXT: s_cselect_b32 s3, -1, 0
; GFX1200-NEXT: s_cmp_nge_f32 s10, 0x7f800000
; GFX1200-NEXT: s_cselect_b32 s4, -1, 0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_b32 vcc_lo, s4, s3
; GFX1200-NEXT: s_cmp_lg_f32 s2, 0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo
; GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GFX1200-NEXT: s_cmp_nge_f32 s9, 0x7f800000
; GFX1200-NEXT: s_cselect_b32 s3, -1, 0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_b32 vcc_lo, s3, s2
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v3, 0x7fc00000, v3, vcc_lo
; GFX1200-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX1200-NEXT: s_endpgm
@@ -16986,7 +16986,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_div_scale_f64 v[12:13], null, v[8:9], v[8:9], 1.0
; GFX11-NEXT: v_rcp_f64_e32 v[14:15], v[12:13]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
@@ -17074,7 +17074,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_div_scale_f64 v[14:15], null, v[10:11], v[10:11], 1.0
; GFX11-NEXT: v_rcp_f64_e32 v[16:17], v[14:15]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
@@ -17396,7 +17396,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_mul_f64_e32 v[20:21], v[18:19], v[14:15]
; GFX1200-NEXT: v_fma_f64 v[12:13], -v[12:13], v[20:21], v[18:19]
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[20:21]
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v17
@@ -17419,7 +17419,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_fma_f64 v[10:11], -v[10:11], v[8:9], v[14:15]
; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
; GFX1200-NEXT: v_add_f64_e32 v[17:18], v[10:11], v[8:9]
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_dual_cndmask_b32 v11, v11, v18 :: v_dual_cndmask_b32 v10, v10, v17
; GFX1200-NEXT: v_ldexp_f64 v[10:11], v[10:11], 26
@@ -17438,7 +17438,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_fma_f64 v[10:11], -v[12:13], v[8:9], v[10:11]
; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
; GFX1200-NEXT: v_add_f64_e32 v[8:9], v[10:11], v[8:9]
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_dual_cndmask_b32 v9, v11, v9 :: v_dual_cndmask_b32 v8, v10, v8
; GFX1200-NEXT: v_ldexp_f64 v[8:9], v[8:9], v16
@@ -17447,12 +17447,12 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: .LBB13_8:
; GFX1200-NEXT: v_cmp_ngt_f64_e64 s2, |v[2:3]|, |v[6:7]|
; GFX1200-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cbranch_vccz .LBB13_10
; GFX1200-NEXT: ; %bb.9: ; %frem.else
; GFX1200-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
; GFX1200-NEXT: v_and_b32_e32 v10, 0x80000000, v3
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc_lo
; GFX1200-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc_lo
@@ -17487,7 +17487,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_mul_f64_e32 v[22:23], v[20:21], v[16:17]
; GFX1200-NEXT: v_fma_f64 v[14:15], -v[14:15], v[22:23], v[20:21]
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_div_fmas_f64 v[14:15], v[14:15], v[16:17], v[22:23]
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v19
@@ -17495,15 +17495,15 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_cbranch_vccnz .LBB13_15
; GFX1200-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; GFX1200-NEXT: s_sub_co_i32 s2, s2, s3
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s2, s2, 26
; GFX1200-NEXT: .LBB13_13: ; %frem.loop_body
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_dual_mov_b32 v17, v13 :: v_dual_mov_b32 v16, v12
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_sub_co_i32 s2, s2, 26
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cmp_gt_i32 s2, 26
; GFX1200-NEXT: v_mul_f64_e32 v[12:13], v[16:17], v[14:15]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -17512,7 +17512,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
; GFX1200-NEXT: v_add_f64_e32 v[19:20], v[12:13], v[10:11]
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_dual_cndmask_b32 v13, v13, v20 :: v_dual_cndmask_b32 v12, v12, v19
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
@@ -17531,7 +17531,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_fma_f64 v[12:13], -v[14:15], v[10:11], v[12:13]
; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
; GFX1200-NEXT: v_add_f64_e32 v[10:11], v[12:13], v[10:11]
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_dual_cndmask_b32 v11, v13, v11 :: v_dual_cndmask_b32 v10, v12, v10
; GFX1200-NEXT: v_ldexp_f64 v[10:11], v[10:11], v18
@@ -17543,12 +17543,12 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_mov_b32_e32 v4, 0
; GFX1200-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
; GFX1200-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[2:3]|
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v9, vcc_lo
; GFX1200-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc_lo
; GFX1200-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0, v[6:7]
; GFX1200-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v3, 0x7ff80000, v11, vcc_lo
; GFX1200-NEXT: v_cndmask_b32_e32 v2, 0, v10, vcc_lo
; GFX1200-NEXT: global_store_b128 v4, v[0:3], s[0:1]
@@ -17728,7 +17728,7 @@ define amdgpu_kernel void @frem_v2f64_const_zero_num(ptr addrspace(1) %out, ptr
; GFX1200-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, v0
; GFX1200-NEXT: s_and_b32 s3, vcc_lo, exec_lo
; GFX1200-NEXT: s_cselect_b32 s3, 0x7ff80000, 0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_mov_b32_e32 v3, s3
; GFX1200-NEXT: global_store_b128 v0, v[0:3], s[0:1]
; GFX1200-NEXT: s_endpgm
@@ -18716,7 +18716,7 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX1200-NEXT: v_add_f64_e32 v[8:9], 1.0, v[4:5]
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_dual_cndmask_b32 v5, v5, v9 :: v_dual_cndmask_b32 v4, v4, v8
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
@@ -18734,19 +18734,19 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX1200-NEXT: v_add_f64_e32 v[6:7], 1.0, v[4:5]
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v5, v5, v7
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
; GFX1200-NEXT: .LBB15_8:
; GFX1200-NEXT: v_cmp_ngt_f64_e64 s2, |v[2:3]|, 1.0
; GFX1200-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cbranch_vccz .LBB15_10
; GFX1200-NEXT: ; %bb.9: ; %frem.else
; GFX1200-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, 1.0
; GFX1200-NEXT: v_and_b32_e32 v6, 0x80000000, v3
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_cndmask_b32_e32 v7, v3, v6, vcc_lo
; GFX1200-NEXT: v_cndmask_b32_e64 v6, v2, 0, vcc_lo
@@ -18770,16 +18770,16 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_sub_co_i32 s2, s2, 26
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cmp_gt_i32 s2, 26
; GFX1200-NEXT: v_rndne_f64_e32 v[6:7], v[8:9]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_add_f64_e64 v[6:7], v[8:9], -v[6:7]
; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX1200-NEXT: v_add_f64_e32 v[10:11], 1.0, v[6:7]
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_dual_cndmask_b32 v7, v7, v11 :: v_dual_cndmask_b32 v6, v6, v10
; GFX1200-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
@@ -18797,17 +18797,17 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX1200-NEXT: v_add_f64_e32 v[8:9], 1.0, v[6:7]
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_dual_cndmask_b32 v6, v6, v8 :: v_dual_cndmask_b32 v7, v7, v9
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, v3
; GFX1200-NEXT: .LBB15_16: ; %Flow49
; GFX1200-NEXT: v_cmp_nle_f64_e64 vcc_lo, 0x7ff00000, |v[0:1]|
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
; GFX1200-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
; GFX1200-NEXT: v_cmp_nle_f64_e64 vcc_lo, 0x7ff00000, |v[2:3]|
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_cndmask_b32 v3, 0x7ff80000, v7
; GFX1200-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc_lo
; GFX1200-NEXT: global_store_b128 v4, v[0:3], s[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll b/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
index 234eaa8af7edf..2bcc5df70d94d 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
+++ b/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
@@ -159,7 +159,7 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v0, 1
@@ -176,7 +176,7 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -218,7 +218,7 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1
@@ -235,7 +235,7 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -282,7 +282,7 @@ define amdgpu_gfx void @test_call_external_void_func_i1_signext(i32) #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -301,7 +301,7 @@ define amdgpu_gfx void @test_call_external_void_func_i1_signext(i32) #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -344,7 +344,7 @@ define amdgpu_gfx void @test_call_external_void_func_i1_signext(i32) #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: global_load_ubyte v0, v[0:1], off glc dlc
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -363,7 +363,7 @@ define amdgpu_gfx void @test_call_external_void_func_i1_signext(i32) #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -411,7 +411,7 @@ define amdgpu_gfx void @test_call_external_void_func_i1_zeroext(i32) #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -430,7 +430,7 @@ define amdgpu_gfx void @test_call_external_void_func_i1_zeroext(i32) #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -473,7 +473,7 @@ define amdgpu_gfx void @test_call_external_void_func_i1_zeroext(i32) #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: global_load_ubyte v0, v[0:1], off glc dlc
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -492,7 +492,7 @@ define amdgpu_gfx void @test_call_external_void_func_i1_zeroext(i32) #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -537,7 +537,7 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm(i32) #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v0, 0x7b
@@ -553,7 +553,7 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm(i32) #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -622,7 +622,7 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm(i32) #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x7b
@@ -638,7 +638,7 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm(i32) #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -683,7 +683,7 @@ define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: global_load_sbyte v0, v[0:1], off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -700,7 +700,7 @@ define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -771,7 +771,7 @@ define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: global_load_sbyte v0, v[0:1], off glc dlc
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -788,7 +788,7 @@ define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -834,7 +834,7 @@ define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -851,7 +851,7 @@ define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -922,7 +922,7 @@ define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: global_load_ubyte v0, v[0:1], off glc dlc
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -939,7 +939,7 @@ define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -984,7 +984,7 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v0, 0x7b
@@ -1000,7 +1000,7 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -1069,7 +1069,7 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x7b
@@ -1085,7 +1085,7 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -1130,7 +1130,7 @@ define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: global_load_ushort v0, v[0:1], off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -1147,7 +1147,7 @@ define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -1218,7 +1218,7 @@ define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: global_load_ushort v0, v[0:1], off glc dlc
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -1235,7 +1235,7 @@ define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -1281,7 +1281,7 @@ define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: global_load_ushort v0, v[0:1], off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -1298,7 +1298,7 @@ define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -1369,7 +1369,7 @@ define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: global_load_ushort v0, v[0:1], off glc dlc
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -1386,7 +1386,7 @@ define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -1431,7 +1431,7 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm(i32) #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v0, 42
@@ -1447,7 +1447,7 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm(i32) #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -1488,7 +1488,7 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm(i32) #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 42
@@ -1504,7 +1504,7 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm(i32) #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -1549,7 +1549,7 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v0, 0x7b
@@ -1566,7 +1566,7 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -1607,7 +1607,7 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x7b
@@ -1624,7 +1624,7 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -1670,7 +1670,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0
@@ -1688,7 +1688,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -1731,7 +1731,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
@@ -1749,7 +1749,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -1797,7 +1797,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v0, 1
@@ -1816,7 +1816,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -1858,7 +1858,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1
@@ -1877,7 +1877,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -1925,7 +1925,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0
@@ -1945,7 +1945,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -1988,7 +1988,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
@@ -2008,7 +2008,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -2061,7 +2061,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0
@@ -2083,7 +2083,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -2127,7 +2127,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
@@ -2149,7 +2149,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -2195,7 +2195,7 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v0, 0x4400
@@ -2211,7 +2211,7 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -2280,7 +2280,7 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x4400
@@ -2296,7 +2296,7 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -2340,7 +2340,7 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v0, 4.0
@@ -2356,7 +2356,7 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -2397,7 +2397,7 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 4.0
@@ -2413,7 +2413,7 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -2458,7 +2458,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v0, 1.0
@@ -2475,7 +2475,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -2516,7 +2516,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1.0
@@ -2533,7 +2533,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -2579,7 +2579,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v0, 1.0
@@ -2597,7 +2597,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -2639,7 +2639,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1.0
@@ -2657,7 +2657,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -2705,7 +2705,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v0, 1.0
@@ -2725,7 +2725,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -2768,7 +2768,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1.0
@@ -2788,7 +2788,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -2833,7 +2833,7 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v0, 0
@@ -2850,7 +2850,7 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -2891,7 +2891,7 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
@@ -2908,7 +2908,7 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -2955,7 +2955,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v0, 0
@@ -2974,7 +2974,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -3016,7 +3016,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
@@ -3035,7 +3035,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -3084,7 +3084,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v0, 0
@@ -3105,7 +3105,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -3148,7 +3148,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
@@ -3169,7 +3169,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -3218,7 +3218,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0
@@ -3239,7 +3239,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -3318,7 +3318,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
@@ -3339,7 +3339,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -3389,7 +3389,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0
@@ -3410,7 +3410,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -3455,7 +3455,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
@@ -3476,7 +3476,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -3527,7 +3527,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0
@@ -3549,7 +3549,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -3595,7 +3595,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
@@ -3617,7 +3617,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -3670,7 +3670,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0
@@ -3694,7 +3694,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -3742,7 +3742,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
@@ -3766,7 +3766,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -3822,7 +3822,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0
@@ -3849,7 +3849,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -3899,7 +3899,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
@@ -3926,7 +3926,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -4014,7 +4014,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v4, 16
@@ -4074,7 +4074,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -4153,7 +4153,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 16
@@ -4213,7 +4213,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -4267,7 +4267,7 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
@@ -4282,7 +4282,7 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 {
; GFX10-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: global_store_byte v[40:41], v0, off
-; GFX10-NEXT: s_clause 0x1
+; GFX10-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4
; GFX10-NEXT: v_readlane_b32 s31, v42, 1
@@ -4291,7 +4291,7 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v42, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -4305,7 +4305,7 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-TRUE16-NEXT: s_clause 0x1
+; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0
@@ -4319,7 +4319,7 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 {
; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-TRUE16-NEXT: global_store_b8 v[40:41], v0, off
-; GFX11-TRUE16-NEXT: s_clause 0x1
+; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s33
; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1
@@ -4341,7 +4341,7 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-FAKE16-NEXT: s_clause 0x1
+; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0
@@ -4355,7 +4355,7 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 {
; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-FAKE16-NEXT: global_store_b8 v[40:41], v0, off
-; GFX11-FAKE16-NEXT: s_clause 0x1
+; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s33
; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1
@@ -4376,7 +4376,7 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill
@@ -4391,7 +4391,7 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: global_store_byte v[40:41], v0, off
-; GFX10-SCRATCH-NEXT: s_clause 0x1
+; GFX10-SCRATCH-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 offset:4
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1
@@ -4400,7 +4400,7 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v42, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v42, off, s33 offset:8 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -4460,7 +4460,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
@@ -4484,12 +4484,12 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v42, 2
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: global_store_short v[40:41], v0, off
-; GFX10-NEXT: s_clause 0x1
+; GFX10-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -4503,7 +4503,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-TRUE16-NEXT: s_clause 0x1
+; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0
@@ -4529,7 +4529,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v42, 2
; GFX11-TRUE16-NEXT: global_store_b16 v[40:41], v0, off
-; GFX11-TRUE16-NEXT: s_clause 0x1
+; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s33
; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -4547,7 +4547,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-FAKE16-NEXT: s_clause 0x1
+; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0
@@ -4572,7 +4572,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v42, 2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: global_store_b16 v[40:41], v0, off
-; GFX11-FAKE16-NEXT: s_clause 0x1
+; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s33
; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -4589,7 +4589,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill
@@ -4613,12 +4613,12 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v42, 2
; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-SCRATCH-NEXT: global_store_short v[40:41], v0, off
-; GFX10-SCRATCH-NEXT: s_clause 0x1
+; GFX10-SCRATCH-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 offset:4
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v42, off, s33 offset:8 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -4681,7 +4681,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
@@ -4708,12 +4708,12 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v42, 2
; GFX10-NEXT: global_store_byte v[3:4], v2, off
; GFX10-NEXT: global_store_short v[40:41], v0, off
-; GFX10-NEXT: s_clause 0x1
+; GFX10-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -4727,7 +4727,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-TRUE16-NEXT: s_clause 0x1
+; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0
@@ -4753,7 +4753,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: global_store_b8 v[3:4], v2, off
; GFX11-TRUE16-NEXT: global_store_b16 v[40:41], v0, off
-; GFX11-TRUE16-NEXT: s_clause 0x1
+; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s33
; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0
@@ -4774,7 +4774,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-FAKE16-NEXT: s_clause 0x1
+; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0
@@ -4803,7 +4803,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: global_store_b8 v[0:1], v2, off
; GFX11-FAKE16-NEXT: global_store_b16 v[40:41], v3, off
-; GFX11-FAKE16-NEXT: s_clause 0x1
+; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s33
; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -4820,7 +4820,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill
@@ -4847,12 +4847,12 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v42, 2
; GFX10-SCRATCH-NEXT: global_store_byte v[3:4], v2, off
; GFX10-SCRATCH-NEXT: global_store_short v[40:41], v0, off
-; GFX10-SCRATCH-NEXT: s_clause 0x1
+; GFX10-SCRATCH-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 offset:4
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v42, off, s33 offset:8 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -4916,7 +4916,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
@@ -4944,12 +4944,12 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v42, 2
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX10-NEXT: global_store_dword v[40:41], v0, off
-; GFX10-NEXT: s_clause 0x1
+; GFX10-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -4963,7 +4963,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-TRUE16-NEXT: s_clause 0x1
+; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0
@@ -4992,7 +4992,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
; GFX11-TRUE16-NEXT: global_store_b32 v[40:41], v0, off
-; GFX11-TRUE16-NEXT: s_clause 0x1
+; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s33
; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v42, 2
@@ -5011,7 +5011,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-FAKE16-NEXT: s_clause 0x1
+; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0
@@ -5045,7 +5045,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: global_store_b32 v[40:41], v0, off
-; GFX11-FAKE16-NEXT: s_clause 0x1
+; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s33
; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -5062,7 +5062,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill
@@ -5090,12 +5090,12 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v42, 2
; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX10-SCRATCH-NEXT: global_store_dword v[40:41], v0, off
-; GFX10-SCRATCH-NEXT: s_clause 0x1
+; GFX10-SCRATCH-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 offset:4
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v42, off, s33 offset:8 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -5164,7 +5164,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
@@ -5197,12 +5197,12 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX10-NEXT: v_or_b32_sdwa v2, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX10-NEXT: global_store_byte v[0:1], v4, off
; GFX10-NEXT: global_store_dword v[40:41], v2, off
-; GFX10-NEXT: s_clause 0x1
+; GFX10-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -5216,7 +5216,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-TRUE16-NEXT: s_clause 0x1
+; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0
@@ -5247,7 +5247,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: global_store_b8 v[2:3], v4, off
; GFX11-TRUE16-NEXT: global_store_b32 v[40:41], v0, off
-; GFX11-TRUE16-NEXT: s_clause 0x1
+; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s33
; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1
@@ -5269,7 +5269,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-FAKE16-NEXT: s_clause 0x1
+; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0
@@ -5308,7 +5308,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: global_store_b8 v[0:1], v4, off
; GFX11-FAKE16-NEXT: global_store_b32 v[40:41], v2, off
-; GFX11-FAKE16-NEXT: s_clause 0x1
+; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s33
; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -5325,7 +5325,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill
@@ -5358,12 +5358,12 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v2, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX10-SCRATCH-NEXT: global_store_byte v[0:1], v4, off
; GFX10-SCRATCH-NEXT: global_store_dword v[40:41], v2, off
-; GFX10-SCRATCH-NEXT: s_clause 0x1
+; GFX10-SCRATCH-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 offset:4
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v42, off, s33 offset:8 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -5437,7 +5437,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
@@ -5475,12 +5475,12 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v42, 2
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX10-NEXT: global_store_dwordx2 v[40:41], v[0:1], off
-; GFX10-NEXT: s_clause 0x1
+; GFX10-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -5494,7 +5494,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-TRUE16-NEXT: s_clause 0x1
+; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0
@@ -5530,7 +5530,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_or_b16 v3.l, v0.l, v1.l
; GFX11-TRUE16-NEXT: global_store_b64 v[40:41], v[3:4], off
-; GFX11-TRUE16-NEXT: s_clause 0x1
+; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s33
; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1
@@ -5552,7 +5552,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-FAKE16-NEXT: s_clause 0x1
+; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0
@@ -5598,7 +5598,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v4
; GFX11-FAKE16-NEXT: global_store_b64 v[40:41], v[0:1], off
-; GFX11-FAKE16-NEXT: s_clause 0x1
+; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s33
; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -5615,7 +5615,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill
@@ -5653,12 +5653,12 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v42, 2
; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX10-SCRATCH-NEXT: global_store_dwordx2 v[40:41], v[0:1], off
-; GFX10-SCRATCH-NEXT: s_clause 0x1
+; GFX10-SCRATCH-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 offset:4
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v42, off, s33 offset:8 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -5799,7 +5799,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
@@ -5899,7 +5899,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX10-NEXT: v_or_b32_sdwa v3, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX10-NEXT: global_store_dwordx4 v[42:43], v[7:10], off
; GFX10-NEXT: global_store_dwordx4 v[40:41], v[3:6], off
-; GFX10-NEXT: s_clause 0x3
+; GFX10-NEXT: s_clause 0x3 ; 16-byte Folded Reload
; GFX10-NEXT: buffer_load_dword v43, off, s[0:3], s33
; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:4
; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:8
@@ -5910,7 +5910,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v44, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v44, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -5924,7 +5924,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s33 offset:16 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-TRUE16-NEXT: s_clause 0x3
+; GFX11-TRUE16-NEXT: s_clause 0x3 ; 16-byte Folded Spill
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:12
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33 offset:8
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:4
@@ -6027,7 +6027,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: global_store_b128 v[42:43], v[0:3], off
; GFX11-TRUE16-NEXT: global_store_b128 v[40:41], v[9:12], off
-; GFX11-TRUE16-NEXT: s_clause 0x3
+; GFX11-TRUE16-NEXT: s_clause 0x3 ; 16-byte Folded Reload
; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s33
; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s33 offset:4
; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s33 offset:8
@@ -6051,7 +6051,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s33 offset:16 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-FAKE16-NEXT: s_clause 0x3
+; GFX11-FAKE16-NEXT: s_clause 0x3 ; 16-byte Folded Spill
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:12
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33 offset:8
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:4
@@ -6178,7 +6178,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: global_store_b128 v[42:43], v[7:10], off
; GFX11-FAKE16-NEXT: global_store_b128 v[40:41], v[3:6], off
-; GFX11-FAKE16-NEXT: s_clause 0x3
+; GFX11-FAKE16-NEXT: s_clause 0x3 ; 16-byte Folded Reload
; GFX11-FAKE16-NEXT: scratch_load_b32 v43, off, s33
; GFX11-FAKE16-NEXT: scratch_load_b32 v42, off, s33 offset:4
; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s33 offset:8
@@ -6201,7 +6201,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v44, s33 offset:16 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:12 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 offset:8 ; 4-byte Folded Spill
@@ -6301,7 +6301,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v3, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX10-SCRATCH-NEXT: global_store_dwordx4 v[42:43], v[7:10], off
; GFX10-SCRATCH-NEXT: global_store_dwordx4 v[40:41], v[3:6], off
-; GFX10-SCRATCH-NEXT: s_clause 0x3
+; GFX10-SCRATCH-NEXT: s_clause 0x3 ; 16-byte Folded Reload
; GFX10-SCRATCH-NEXT: scratch_load_dword v43, off, s33
; GFX10-SCRATCH-NEXT: scratch_load_dword v42, off, s33 offset:4
; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33 offset:8
@@ -6312,7 +6312,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v44, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v44, off, s33 offset:16 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -6360,7 +6360,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: global_load_dword v0, v[0:1], off
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
@@ -6376,7 +6376,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -6417,7 +6417,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: global_load_dword v0, v[0:1], off
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
@@ -6433,7 +6433,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -6478,7 +6478,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
@@ -6494,7 +6494,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -6535,7 +6535,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
@@ -6551,7 +6551,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -6596,7 +6596,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
@@ -6612,7 +6612,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -6653,7 +6653,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
@@ -6669,7 +6669,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -6715,7 +6715,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v0, 0x20001
@@ -6732,7 +6732,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -6773,7 +6773,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x20001
@@ -6790,7 +6790,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -6835,7 +6835,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v0, 0x40003c00
@@ -6852,7 +6852,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -6894,7 +6894,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x40003c00
@@ -6911,7 +6911,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -6955,7 +6955,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
@@ -6971,7 +6971,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -7012,7 +7012,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
@@ -7028,7 +7028,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -7074,7 +7074,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v0, 0x20001
@@ -7091,7 +7091,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -7133,7 +7133,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x20001
@@ -7150,7 +7150,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -7194,7 +7194,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: global_load_dword v0, v[0:1], off
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
@@ -7210,7 +7210,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -7251,7 +7251,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: global_load_dword v0, v[0:1], off
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
@@ -7267,7 +7267,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -7312,7 +7312,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
@@ -7328,7 +7328,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -7369,7 +7369,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
@@ -7385,7 +7385,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -7431,7 +7431,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v0, 1
@@ -7448,7 +7448,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -7489,7 +7489,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1
@@ -7506,7 +7506,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -7552,7 +7552,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm(i32) #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v0, 3
@@ -7570,7 +7570,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm(i32) #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -7612,7 +7612,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm(i32) #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 3
@@ -7630,7 +7630,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm(i32) #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -7677,7 +7677,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32(i32) #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v0, 3
@@ -7696,7 +7696,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32(i32) #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -7738,7 +7738,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32(i32) #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 3
@@ -7757,7 +7757,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32(i32) #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -7801,7 +7801,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
@@ -7817,7 +7817,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -7858,7 +7858,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
@@ -7874,7 +7874,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -7922,7 +7922,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v0, 1
@@ -7941,7 +7941,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -7983,7 +7983,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1
@@ -8002,7 +8002,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -8050,7 +8050,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v0, 1
@@ -8070,7 +8070,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -8113,7 +8113,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1
@@ -8133,7 +8133,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -8181,7 +8181,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
@@ -8202,7 +8202,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -8248,7 +8248,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
@@ -8269,7 +8269,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -8322,7 +8322,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v0, 1
@@ -8345,7 +8345,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -8389,7 +8389,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1
@@ -8412,7 +8412,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -8462,7 +8462,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
@@ -8485,7 +8485,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -8533,7 +8533,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
@@ -8556,7 +8556,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -8613,7 +8613,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
@@ -8640,7 +8640,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -8692,7 +8692,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
@@ -8719,7 +8719,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -8779,7 +8779,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
@@ -8809,7 +8809,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -8863,7 +8863,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
@@ -8893,7 +8893,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -8948,7 +8948,7 @@ define amdgpu_gfx void @test_call_external_i32_func_i32_imm(ptr addrspace(1) %ou
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v42, s34, 2
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
@@ -8964,7 +8964,7 @@ define amdgpu_gfx void @test_call_external_i32_func_i32_imm(ptr addrspace(1) %ou
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: global_store_dword v[40:41], v0, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: s_clause 0x1
+; GFX10-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4
; GFX10-NEXT: v_readlane_b32 s31, v42, 1
@@ -8973,7 +8973,7 @@ define amdgpu_gfx void @test_call_external_i32_func_i32_imm(ptr addrspace(1) %ou
; GFX10-NEXT: v_readlane_b32 s34, v42, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -8988,7 +8988,7 @@ define amdgpu_gfx void @test_call_external_i32_func_i32_imm(ptr addrspace(1) %ou
; GFX11-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v42, s0, 2
-; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_clause 0x1 ; 8-byte Folded Spill
; GFX11-NEXT: scratch_store_b32 off, v40, s33 offset:4
; GFX11-NEXT: scratch_store_b32 off, v41, s33
; GFX11-NEXT: v_dual_mov_b32 v41, v1 :: v_dual_mov_b32 v40, v0
@@ -9001,7 +9001,7 @@ define amdgpu_gfx void @test_call_external_i32_func_i32_imm(ptr addrspace(1) %ou
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: global_store_b32 v[40:41], v0, off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX11-NEXT: scratch_load_b32 v41, off, s33
; GFX11-NEXT: scratch_load_b32 v40, off, s33 offset:4
; GFX11-NEXT: v_readlane_b32 s31, v42, 1
@@ -9022,7 +9022,7 @@ define amdgpu_gfx void @test_call_external_i32_func_i32_imm(ptr addrspace(1) %ou
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill
@@ -9038,7 +9038,7 @@ define amdgpu_gfx void @test_call_external_i32_func_i32_imm(ptr addrspace(1) %ou
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: global_store_dword v[40:41], v0, off
; GFX10-SCRATCH-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-SCRATCH-NEXT: s_clause 0x1
+; GFX10-SCRATCH-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 offset:4
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1
@@ -9047,7 +9047,7 @@ define amdgpu_gfx void @test_call_external_i32_func_i32_imm(ptr addrspace(1) %ou
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v42, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v42, off, s33 offset:8 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -9096,7 +9096,7 @@ define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
@@ -9117,7 +9117,7 @@ define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -9196,7 +9196,7 @@ define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
@@ -9217,7 +9217,7 @@ define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -9267,7 +9267,7 @@ define amdgpu_gfx void @test_call_external_void_func_byval_struct_i8_i32() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v0, 3
@@ -9287,7 +9287,7 @@ define amdgpu_gfx void @test_call_external_void_func_byval_struct_i8_i32() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -9365,7 +9365,7 @@ define amdgpu_gfx void @test_call_external_void_func_byval_struct_i8_i32() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:8 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 3
@@ -9385,7 +9385,7 @@ define amdgpu_gfx void @test_call_external_void_func_byval_struct_i8_i32() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 offset:8 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -9447,7 +9447,7 @@ define amdgpu_gfx void @test_call_external_void_func_sret_struct_i8_i32_byval_st
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_mov_b32_e32 v0, 3
; GFX10-NEXT: v_mov_b32_e32 v1, 8
@@ -9477,7 +9477,7 @@ define amdgpu_gfx void @test_call_external_void_func_sret_struct_i8_i32_byval_st
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -9571,7 +9571,7 @@ define amdgpu_gfx void @test_call_external_void_func_sret_struct_i8_i32_byval_st
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:16 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 3
@@ -9601,7 +9601,7 @@ define amdgpu_gfx void @test_call_external_void_func_sret_struct_i8_i32_byval_st
; GFX10-SCRATCH-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 offset:16 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -9680,7 +9680,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16i8() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
@@ -9690,7 +9690,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16i8() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_load_dwordx4 v[0:3], v0, s[34:35]
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v16i8 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v16i8 at abs32@lo
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -9719,7 +9719,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16i8() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -9779,7 +9779,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16i8() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
@@ -9789,7 +9789,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16i8() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1]
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v16i8 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v16i8 at abs32@lo
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -9818,7 +9818,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16i8() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -9896,7 +9896,7 @@ define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s4, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s4
; GFX10-NEXT: s_clause 0x2
; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s33 offset:16
@@ -9945,7 +9945,7 @@ define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 {
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: s_or_saveexec_b32 s4, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s4
; GFX10-NEXT: s_mov_b32 s33, s6
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -10015,7 +10015,7 @@ define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s0, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:24 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s0
; GFX10-SCRATCH-NEXT: s_clause 0x1
; GFX10-SCRATCH-NEXT: scratch_load_dwordx2 v[32:33], off, s33 offset:16
@@ -10061,7 +10061,7 @@ define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s0, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 offset:24 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s0
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s4
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -10109,7 +10109,7 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v0, 1
@@ -10126,7 +10126,7 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -10168,7 +10168,7 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1
@@ -10185,7 +10185,7 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -10231,7 +10231,7 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm_inreg(i32) #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 3
; GFX10-NEXT: s_mov_b32 s35, external_void_func_i8_inreg at abs32@hi
@@ -10249,7 +10249,7 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm_inreg(i32) #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 3
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -10292,7 +10292,7 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm_inreg(i32) #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i8_inreg at abs32@hi
@@ -10310,7 +10310,7 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm_inreg(i32) #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 3
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -10356,7 +10356,7 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 3
; GFX10-NEXT: s_mov_b32 s35, external_void_func_i16_inreg at abs32@hi
@@ -10374,7 +10374,7 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 3
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -10417,7 +10417,7 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i16_inreg at abs32@hi
@@ -10435,7 +10435,7 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 3
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -10481,7 +10481,7 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm_inreg(i32) #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 3
; GFX10-NEXT: s_mov_b32 s35, external_void_func_i32_inreg at abs32@hi
@@ -10499,7 +10499,7 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm_inreg(i32) #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 3
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -10542,7 +10542,7 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm_inreg(i32) #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i32_inreg at abs32@hi
@@ -10560,7 +10560,7 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm_inreg(i32) #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 3
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -10609,7 +10609,7 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 4
; GFX10-NEXT: s_mov_b32 s35, external_void_func_i64_inreg at abs32@hi
@@ -10630,7 +10630,7 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 4
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -10676,7 +10676,7 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i64_inreg at abs32@hi
@@ -10697,7 +10697,7 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 4
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -10750,7 +10750,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 6
; GFX10-NEXT: s_mov_b64 s[34:35], 0
@@ -10775,7 +10775,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 6
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -10825,7 +10825,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 6
; GFX10-SCRATCH-NEXT: s_mov_b64 s[0:1], 0
@@ -10850,7 +10850,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 6
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -10906,7 +10906,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 6
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i64_inreg at abs32@hi
@@ -10933,7 +10933,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 6
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -10985,7 +10985,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 6
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i64_inreg at abs32@hi
@@ -11012,7 +11012,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 6
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -11071,7 +11071,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 8
; GFX10-NEXT: s_mov_b64 s[34:35], 0
@@ -11102,7 +11102,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 8
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -11158,7 +11158,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 8
; GFX10-SCRATCH-NEXT: s_mov_b64 s[0:1], 0
@@ -11189,7 +11189,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 8
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -11257,7 +11257,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 10
; GFX10-NEXT: s_mov_b64 s[34:35], 0
@@ -11294,7 +11294,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 10
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -11356,7 +11356,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 10
; GFX10-SCRATCH-NEXT: s_mov_b64 s[0:1], 0
@@ -11393,7 +11393,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 10
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -11441,7 +11441,7 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 3
; GFX10-NEXT: s_mov_b32 s35, external_void_func_f16_inreg at abs32@hi
@@ -11459,7 +11459,7 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 3
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -11502,7 +11502,7 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f16_inreg at abs32@hi
@@ -11520,7 +11520,7 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 3
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -11566,7 +11566,7 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 3
; GFX10-NEXT: s_mov_b32 s35, external_void_func_f32_inreg at abs32@hi
@@ -11584,7 +11584,7 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 3
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -11627,7 +11627,7 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f32_inreg at abs32@hi
@@ -11645,7 +11645,7 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 3
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -11694,7 +11694,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 4
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2f32_inreg at abs32@hi
@@ -11715,7 +11715,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 4
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -11761,7 +11761,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2f32_inreg at abs32@hi
@@ -11782,7 +11782,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 4
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -11834,7 +11834,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 5
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f32_inreg at abs32@hi
@@ -11858,7 +11858,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 5
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -11907,7 +11907,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 5
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f32_inreg at abs32@hi
@@ -11931,7 +11931,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 5
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -11989,7 +11989,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 7
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v5f32_inreg at abs32@hi
@@ -12019,7 +12019,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 7
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -12074,7 +12074,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 7
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v5f32_inreg at abs32@hi
@@ -12104,7 +12104,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 7
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -12153,7 +12153,7 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 4
; GFX10-NEXT: s_mov_b32 s35, external_void_func_f64_inreg at abs32@hi
@@ -12174,7 +12174,7 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 4
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -12220,7 +12220,7 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f64_inreg at abs32@hi
@@ -12241,7 +12241,7 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 4
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -12296,7 +12296,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 6
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2f64_inreg at abs32@hi
@@ -12323,7 +12323,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 6
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -12375,7 +12375,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 6
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2f64_inreg at abs32@hi
@@ -12402,7 +12402,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 6
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -12463,7 +12463,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 8
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f64_inreg at abs32@hi
@@ -12496,7 +12496,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 8
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -12554,7 +12554,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 8
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f64_inreg at abs32@hi
@@ -12587,7 +12587,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 8
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -12633,7 +12633,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 3
; GFX10-NEXT: s_addk_i32 s32, 0x200
@@ -12651,7 +12651,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 3
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -12694,7 +12694,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
@@ -12712,7 +12712,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 3
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -12761,7 +12761,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 4
; GFX10-NEXT: s_addk_i32 s32, 0x200
@@ -12781,7 +12781,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 4
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -12826,7 +12826,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
@@ -12846,7 +12846,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 4
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -12895,7 +12895,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 4
; GFX10-NEXT: s_addk_i32 s32, 0x200
@@ -12915,7 +12915,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 4
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -12960,7 +12960,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
@@ -12980,7 +12980,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 4
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -13030,7 +13030,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 4
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i16_inreg at abs32@hi
@@ -13051,7 +13051,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 4
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -13097,7 +13097,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i16_inreg at abs32@hi
@@ -13118,7 +13118,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 4
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -13167,7 +13167,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 4
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f16_inreg at abs32@hi
@@ -13188,7 +13188,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 4
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -13234,7 +13234,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f16_inreg at abs32@hi
@@ -13255,7 +13255,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 4
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -13303,7 +13303,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 4
; GFX10-NEXT: s_addk_i32 s32, 0x200
@@ -13323,7 +13323,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 4
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -13368,7 +13368,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
@@ -13388,7 +13388,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 4
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -13438,7 +13438,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 4
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i16_inreg at abs32@hi
@@ -13459,7 +13459,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 4
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -13505,7 +13505,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i16_inreg at abs32@hi
@@ -13526,7 +13526,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 4
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -13572,7 +13572,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 3
; GFX10-NEXT: s_addk_i32 s32, 0x200
@@ -13590,7 +13590,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 3
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -13633,7 +13633,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
@@ -13651,7 +13651,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 3
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -13700,7 +13700,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 4
; GFX10-NEXT: s_addk_i32 s32, 0x200
@@ -13720,7 +13720,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 4
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -13765,7 +13765,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
@@ -13785,7 +13785,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 4
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -13835,7 +13835,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 4
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i32_inreg at abs32@hi
@@ -13856,7 +13856,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 4
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -13902,7 +13902,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i32_inreg at abs32@hi
@@ -13923,7 +13923,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 4
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -13975,7 +13975,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm_inreg(i32) #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 5
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i32_inreg at abs32@hi
@@ -13999,7 +13999,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm_inreg(i32) #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 5
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -14048,7 +14048,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm_inreg(i32) #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 5
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i32_inreg at abs32@hi
@@ -14072,7 +14072,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm_inreg(i32) #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 5
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -14127,7 +14127,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32_inreg(i32) #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 6
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i32_i32_inreg at abs32@hi
@@ -14154,7 +14154,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32_inreg(i32) #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 6
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -14206,7 +14206,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32_inreg(i32) #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 6
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i32_i32_inreg at abs32@hi
@@ -14233,7 +14233,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32_inreg(i32) #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 6
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -14285,7 +14285,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 6
; GFX10-NEXT: s_addk_i32 s32, 0x200
@@ -14309,7 +14309,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 6
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -14358,7 +14358,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 6
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
@@ -14382,7 +14382,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 6
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -14438,7 +14438,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 6
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i32_inreg at abs32@hi
@@ -14465,7 +14465,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 6
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -14517,7 +14517,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 6
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i32_inreg at abs32@hi
@@ -14544,7 +14544,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 6
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -14602,7 +14602,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 7
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v5i32_inreg at abs32@hi
@@ -14632,7 +14632,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 7
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -14687,7 +14687,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 7
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v5i32_inreg at abs32@hi
@@ -14717,7 +14717,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 7
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -14779,7 +14779,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 10
; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
@@ -14813,7 +14813,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 10
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -14872,7 +14872,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 10
; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
@@ -14906,7 +14906,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 10
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -14975,7 +14975,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 10
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8i32_inreg at abs32@hi
@@ -15014,7 +15014,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 10
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -15078,7 +15078,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 10
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8i32_inreg at abs32@hi
@@ -15117,7 +15117,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 10
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -15195,7 +15195,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 18
; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
@@ -15245,7 +15245,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 18
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -15320,7 +15320,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 18
; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
@@ -15370,7 +15370,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 18
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -15494,7 +15494,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 28
; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
@@ -15589,7 +15589,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 28
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -15704,7 +15704,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 28
; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
@@ -15796,7 +15796,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 28
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -15925,7 +15925,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 28
; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
@@ -16025,7 +16025,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 28
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -16144,7 +16144,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 28
; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
@@ -16242,7 +16242,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 28
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -16294,7 +16294,7 @@ define amdgpu_gfx void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, d
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s33
@@ -16316,7 +16316,7 @@ define amdgpu_gfx void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, d
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -16358,7 +16358,7 @@ define amdgpu_gfx void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, d
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:8 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: scratch_load_dwordx2 v[32:33], off, s33
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
@@ -16376,7 +16376,7 @@ define amdgpu_gfx void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, d
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 offset:8 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -16460,7 +16460,7 @@ define amdgpu_gfx void @stack_12xv3i32() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v0, 12
@@ -16515,7 +16515,7 @@ define amdgpu_gfx void @stack_12xv3i32() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -16574,7 +16574,7 @@ define amdgpu_gfx void @stack_12xv3i32() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 12
@@ -16626,7 +16626,7 @@ define amdgpu_gfx void @stack_12xv3i32() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -16730,7 +16730,7 @@ define amdgpu_gfx void @stack_8xv5i32() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_mov_b32_e32 v0, 8
; GFX10-NEXT: v_mov_b32_e32 v1, 9
@@ -16793,7 +16793,7 @@ define amdgpu_gfx void @stack_8xv5i32() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -16856,7 +16856,7 @@ define amdgpu_gfx void @stack_8xv5i32() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 8
@@ -16914,7 +16914,7 @@ define amdgpu_gfx void @stack_8xv5i32() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -17014,7 +17014,7 @@ define amdgpu_gfx void @stack_8xv5f32() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_mov_b32_e32 v0, 0x41000000
; GFX10-NEXT: v_mov_b32_e32 v1, 0x41100000
@@ -17077,7 +17077,7 @@ define amdgpu_gfx void @stack_8xv5f32() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -17145,7 +17145,7 @@ define amdgpu_gfx void @stack_8xv5f32() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x41000000
@@ -17203,7 +17203,7 @@ define amdgpu_gfx void @stack_8xv5f32() #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -17255,7 +17255,7 @@ define amdgpu_gfx void @test_call_external_void_func_bf16(i16 %arg) #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_bf16 at abs32@hi
@@ -17270,7 +17270,7 @@ define amdgpu_gfx void @test_call_external_void_func_bf16(i16 %arg) #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -17310,7 +17310,7 @@ define amdgpu_gfx void @test_call_external_void_func_bf16(i16 %arg) #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_bf16 at abs32@hi
@@ -17325,7 +17325,7 @@ define amdgpu_gfx void @test_call_external_void_func_bf16(i16 %arg) #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -17369,7 +17369,7 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16(i16 %arg) #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v1bf16 at abs32@hi
@@ -17384,7 +17384,7 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16(i16 %arg) #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -17424,7 +17424,7 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16(i16 %arg) #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v1bf16 at abs32@hi
@@ -17439,7 +17439,7 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16(i16 %arg) #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -17483,7 +17483,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16(i32 %arg) #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2bf16 at abs32@hi
@@ -17498,7 +17498,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16(i32 %arg) #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -17538,7 +17538,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16(i32 %arg) #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2bf16 at abs32@hi
@@ -17553,7 +17553,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16(i32 %arg) #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -17597,7 +17597,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16(<3 x i16> %arg) #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3bf16 at abs32@hi
@@ -17612,7 +17612,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16(<3 x i16> %arg) #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -17652,7 +17652,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16(<3 x i16> %arg) #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3bf16 at abs32@hi
@@ -17667,7 +17667,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16(<3 x i16> %arg) #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -17711,7 +17711,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16(<4 x i16> %arg) #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4bf16 at abs32@hi
@@ -17726,7 +17726,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16(<4 x i16> %arg) #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -17766,7 +17766,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16(<4 x i16> %arg) #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4bf16 at abs32@hi
@@ -17781,7 +17781,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16(<4 x i16> %arg) #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -17825,7 +17825,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16(<8 x i16> %arg) #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8bf16 at abs32@hi
@@ -17840,7 +17840,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16(<8 x i16> %arg) #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -17880,7 +17880,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16(<8 x i16> %arg) #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8bf16 at abs32@hi
@@ -17895,7 +17895,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16(<8 x i16> %arg) #0 {
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -17939,7 +17939,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16(<16 x i16> %arg) #0
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v16bf16 at abs32@hi
@@ -17954,7 +17954,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16(<16 x i16> %arg) #0
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -17994,7 +17994,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16(<16 x i16> %arg) #0
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v16bf16 at abs32@hi
@@ -18009,7 +18009,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16(<16 x i16> %arg) #0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -18053,7 +18053,7 @@ define amdgpu_gfx void @test_call_external_void_func_bf16_inreg(i16 inreg %arg)
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_bf16 at abs32@hi
@@ -18068,7 +18068,7 @@ define amdgpu_gfx void @test_call_external_void_func_bf16_inreg(i16 inreg %arg)
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -18108,7 +18108,7 @@ define amdgpu_gfx void @test_call_external_void_func_bf16_inreg(i16 inreg %arg)
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_bf16 at abs32@hi
@@ -18123,7 +18123,7 @@ define amdgpu_gfx void @test_call_external_void_func_bf16_inreg(i16 inreg %arg)
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -18167,7 +18167,7 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16_inreg(i16 inreg %arg
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v1bf16 at abs32@hi
@@ -18182,7 +18182,7 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16_inreg(i16 inreg %arg
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -18222,7 +18222,7 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16_inreg(i16 inreg %arg
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v1bf16 at abs32@hi
@@ -18237,7 +18237,7 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16_inreg(i16 inreg %arg
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -18281,7 +18281,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16_inreg(i32 inreg %arg
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2bf16 at abs32@hi
@@ -18296,7 +18296,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16_inreg(i32 inreg %arg
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -18336,7 +18336,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16_inreg(i32 inreg %arg
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2bf16 at abs32@hi
@@ -18351,7 +18351,7 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16_inreg(i32 inreg %arg
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -18395,7 +18395,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16_inreg(<3 x i16> inre
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3bf16 at abs32@hi
@@ -18410,7 +18410,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16_inreg(<3 x i16> inre
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -18450,7 +18450,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16_inreg(<3 x i16> inre
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3bf16 at abs32@hi
@@ -18465,7 +18465,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16_inreg(<3 x i16> inre
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -18509,7 +18509,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16_inreg(<4 x i16> inre
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4bf16 at abs32@hi
@@ -18524,7 +18524,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16_inreg(<4 x i16> inre
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -18564,7 +18564,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16_inreg(<4 x i16> inre
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4bf16 at abs32@hi
@@ -18579,7 +18579,7 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16_inreg(<4 x i16> inre
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -18623,7 +18623,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16_inreg(<8 x i16> inre
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8bf16 at abs32@hi
@@ -18638,7 +18638,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16_inreg(<8 x i16> inre
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -18678,7 +18678,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16_inreg(<8 x i16> inre
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8bf16 at abs32@hi
@@ -18693,7 +18693,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16_inreg(<8 x i16> inre
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -18737,7 +18737,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16_inreg(<16 x i16> in
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v16bf16 at abs32@hi
@@ -18752,7 +18752,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16_inreg(<16 x i16> in
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -18792,7 +18792,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16_inreg(<16 x i16> in
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s32
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v16bf16 at abs32@hi
@@ -18807,7 +18807,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16_inreg(<16 x i16> in
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: s_mov_b32 s33, s0
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll b/llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
index 124de7e00f020..0005e8a2619b2 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
+++ b/llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
@@ -46,7 +46,7 @@ define amdgpu_gfx void @test_call_external_void_func_void_clobber_s30_s31_call_e
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 4
; GFX10-NEXT: s_addk_i32 s32, 0x200
@@ -68,7 +68,7 @@ define amdgpu_gfx void @test_call_external_void_func_void_clobber_s30_s31_call_e
; GFX10-NEXT: v_readlane_b32 s34, v40, 4
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -145,7 +145,7 @@ define amdgpu_gfx void @void_func_void_clobber_s28_s29() #1 {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_xor_saveexec_b32 s34, -1
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s34
; GFX10-NEXT: v_writelane_b32 v0, s28, 0
; GFX10-NEXT: v_writelane_b32 v0, s29, 1
@@ -163,7 +163,7 @@ define amdgpu_gfx void @void_func_void_clobber_s28_s29() #1 {
; GFX10-NEXT: v_readlane_b32 s28, v0, 0
; GFX10-NEXT: s_xor_saveexec_b32 s34, -1
; GFX10-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -243,7 +243,7 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_s31(ptr addrspace(1)
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 3
; GFX10-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
@@ -268,7 +268,7 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_s31(ptr addrspace(1)
; GFX10-NEXT: v_readlane_b32 s34, v40, 3
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -359,7 +359,7 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_v31(ptr addrspace(1)
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v41, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
@@ -384,7 +384,7 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_v31(ptr addrspace(1)
; GFX10-NEXT: v_readlane_b32 s34, v41, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -477,7 +477,7 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_s33(ptr addrspace(1)
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 3
; GFX10-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
@@ -502,7 +502,7 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_s33(ptr addrspace(1)
; GFX10-NEXT: v_readlane_b32 s34, v40, 3
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -594,7 +594,7 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_s34(ptr addrspace(1)
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 3
; GFX10-NEXT: ;;#ASMSTART
@@ -619,7 +619,7 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_s34(ptr addrspace(1)
; GFX10-NEXT: v_readlane_b32 s34, v40, 3
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -709,7 +709,7 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_v40(ptr addrspace(1)
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v41, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
@@ -732,7 +732,7 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_v40(ptr addrspace(1)
; GFX10-NEXT: v_readlane_b32 s34, v41, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -867,7 +867,7 @@ define amdgpu_gfx void @test_call_void_func_void_clobber_s33() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_mov_b32 s35, void_func_void_clobber_s33 at abs32@hi
@@ -882,7 +882,7 @@ define amdgpu_gfx void @test_call_void_func_void_clobber_s33() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -952,7 +952,7 @@ define amdgpu_gfx void @test_call_void_func_void_clobber_s34() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_mov_b32 s35, void_func_void_clobber_s34 at abs32@hi
@@ -967,7 +967,7 @@ define amdgpu_gfx void @test_call_void_func_void_clobber_s34() #0 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -1046,7 +1046,7 @@ define amdgpu_gfx void @callee_saved_sgpr_kernel() #1 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 3
; GFX10-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
@@ -1070,7 +1070,7 @@ define amdgpu_gfx void @callee_saved_sgpr_kernel() #1 {
; GFX10-NEXT: v_readlane_b32 s34, v40, 3
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -1169,7 +1169,7 @@ define amdgpu_gfx void @callee_saved_sgpr_vgpr_kernel() #1 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v41, s34, 3
; GFX10-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
@@ -1202,7 +1202,7 @@ define amdgpu_gfx void @callee_saved_sgpr_vgpr_kernel() #1 {
; GFX10-NEXT: v_readlane_b32 s34, v41, 3
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: s_mov_b32 s33, s34
; GFX10-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll b/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
index 20666560a7ec7..c06011c259f9b 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
+++ b/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
@@ -51,7 +51,7 @@ define amdgpu_gfx void @call_i1() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_xor_saveexec_b32 s34, -1
; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s34
; GFX10-NEXT: v_writelane_b32 v1, s30, 0
; GFX10-NEXT: s_mov_b32 s35, return_i1 at abs32@hi
@@ -64,7 +64,7 @@ define amdgpu_gfx void @call_i1() #0 {
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: s_xor_saveexec_b32 s34, -1
; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s34
; GFX10-NEXT: s_mov_b32 s33, s36
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -153,7 +153,7 @@ define amdgpu_gfx void @call_i16() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_xor_saveexec_b32 s34, -1
; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s34
; GFX10-NEXT: v_writelane_b32 v1, s30, 0
; GFX10-NEXT: s_mov_b32 s35, return_i16 at abs32@hi
@@ -166,7 +166,7 @@ define amdgpu_gfx void @call_i16() #0 {
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: s_xor_saveexec_b32 s34, -1
; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s34
; GFX10-NEXT: s_mov_b32 s33, s36
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -249,7 +249,7 @@ define amdgpu_gfx void @call_2xi16() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_xor_saveexec_b32 s34, -1
; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s34
; GFX10-NEXT: v_writelane_b32 v1, s30, 0
; GFX10-NEXT: s_mov_b32 s35, return_2xi16 at abs32@hi
@@ -262,7 +262,7 @@ define amdgpu_gfx void @call_2xi16() #0 {
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: s_xor_saveexec_b32 s34, -1
; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s34
; GFX10-NEXT: s_mov_b32 s33, s36
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -353,7 +353,7 @@ define amdgpu_gfx void @call_3xi16() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_xor_saveexec_b32 s34, -1
; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s34
; GFX10-NEXT: v_writelane_b32 v2, s30, 0
; GFX10-NEXT: s_mov_b32 s35, return_3xi16 at abs32@hi
@@ -366,7 +366,7 @@ define amdgpu_gfx void @call_3xi16() #0 {
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: s_xor_saveexec_b32 s34, -1
; GFX10-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s34
; GFX10-NEXT: s_mov_b32 s33, s36
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -767,7 +767,7 @@ define amdgpu_gfx void @call_100xi32() #0 {
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_xor_saveexec_b32 s34, -1
; GFX10-NEXT: buffer_store_dword v100, off, s[0:3], s33 offset:128 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s34
; GFX10-NEXT: v_writelane_b32 v100, s30, 0
; GFX10-NEXT: s_mov_b32 s35, return_100xi32 at abs32@hi
@@ -845,7 +845,7 @@ define amdgpu_gfx void @call_100xi32() #0 {
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: s_xor_saveexec_b32 s34, -1
; GFX10-NEXT: buffer_load_dword v100, off, s[0:3], s33 offset:128 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s34
; GFX10-NEXT: s_mov_b32 s33, s36
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -2170,7 +2170,7 @@ define amdgpu_gfx void @call_512xi32() #0 {
; GFX10-NEXT: s_and_b32 s33, s33, 0xffff0000
; GFX10-NEXT: s_xor_saveexec_b32 s36, -1
; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:2048 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s36
; GFX10-NEXT: v_writelane_b32 v2, s30, 0
; GFX10-NEXT: v_lshrrev_b32_e64 v0, 5, s33
@@ -2187,7 +2187,7 @@ define amdgpu_gfx void @call_512xi32() #0 {
; GFX10-NEXT: s_mov_b32 s34, s38
; GFX10-NEXT: s_xor_saveexec_b32 s36, -1
; GFX10-NEXT: buffer_load_dword v2, off, s[0:3], s33 offset:2048 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s36
; GFX10-NEXT: s_mov_b32 s33, s35
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -2908,7 +2908,7 @@ define amdgpu_gfx void @call_72xi32() #1 {
; GFX10-NEXT: s_and_b32 s33, s33, 0xffffc000
; GFX10-NEXT: s_or_saveexec_b32 s36, -1
; GFX10-NEXT: buffer_store_dword v63, off, s[0:3], s33 offset:1568 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s36
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_mov_b32 s38, s34
@@ -3173,7 +3173,7 @@ define amdgpu_gfx void @call_72xi32() #1 {
; GFX10-NEXT: s_mov_b32 s34, s38
; GFX10-NEXT: s_or_saveexec_b32 s36, -1
; GFX10-NEXT: buffer_load_dword v63, off, s[0:3], s33 offset:1568 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s36
; GFX10-NEXT: s_mov_b32 s33, s35
; GFX10-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
index d88973da77bf9..21e5994819997 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
@@ -7438,9 +7438,9 @@ define double @global_agent_atomic_fadd_ret_f64__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB38_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7672,9 +7672,9 @@ define double @global_agent_atomic_fadd_ret_f64__offset12b_pos__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB39_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7907,9 +7907,9 @@ define double @global_agent_atomic_fadd_ret_f64__offset12b_neg__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB40_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8145,9 +8145,9 @@ define void @global_agent_atomic_fadd_noret_f64__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB41_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8361,9 +8361,9 @@ define void @global_agent_atomic_fadd_noret_f64__offset12b_pos__amdgpu_no_fine_g
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB42_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8580,9 +8580,9 @@ define void @global_agent_atomic_fadd_noret_f64__offset12b_neg__amdgpu_no_fine_g
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB43_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8899,9 +8899,9 @@ define half @global_agent_atomic_fadd_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB44_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8944,9 +8944,9 @@ define half @global_agent_atomic_fadd_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB44_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9382,7 +9382,7 @@ define half @global_agent_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -9408,9 +9408,9 @@ define half @global_agent_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB45_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9427,7 +9427,7 @@ define half @global_agent_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -9454,9 +9454,9 @@ define half @global_agent_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB45_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9905,7 +9905,7 @@ define half @global_agent_atomic_fadd_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -9931,9 +9931,9 @@ define half @global_agent_atomic_fadd_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB46_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9950,7 +9950,7 @@ define half @global_agent_atomic_fadd_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -9977,9 +9977,9 @@ define half @global_agent_atomic_fadd_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB46_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10449,9 +10449,9 @@ define void @global_agent_atomic_fadd_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB47_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10492,9 +10492,9 @@ define void @global_agent_atomic_fadd_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB47_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10914,7 +10914,7 @@ define void @global_agent_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -10940,9 +10940,9 @@ define void @global_agent_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB48_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10958,7 +10958,7 @@ define void @global_agent_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -10984,9 +10984,9 @@ define void @global_agent_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB48_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11419,7 +11419,7 @@ define void @global_agent_atomic_fadd_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -11445,9 +11445,9 @@ define void @global_agent_atomic_fadd_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB49_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11463,7 +11463,7 @@ define void @global_agent_atomic_fadd_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -11489,9 +11489,9 @@ define void @global_agent_atomic_fadd_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB49_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11918,9 +11918,9 @@ define half @global_agent_atomic_fadd_ret_f16__offset12b_pos__align4__amdgpu_no_
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB50_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11952,9 +11952,9 @@ define half @global_agent_atomic_fadd_ret_f16__offset12b_pos__align4__amdgpu_no_
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB50_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12301,9 +12301,9 @@ define void @global_agent_atomic_fadd_noret_f16__offset12b__align4_pos__amdgpu_n
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB51_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12333,9 +12333,9 @@ define void @global_agent_atomic_fadd_noret_f16__offset12b__align4_pos__amdgpu_n
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB51_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12683,7 +12683,7 @@ define half @global_system_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -12710,9 +12710,9 @@ define half @global_system_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB52_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12729,7 +12729,7 @@ define half @global_system_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -12757,9 +12757,9 @@ define half @global_system_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB52_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13205,7 +13205,7 @@ define void @global_system_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -13232,9 +13232,9 @@ define void @global_system_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB53_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13250,7 +13250,7 @@ define void @global_system_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -13277,9 +13277,9 @@ define void @global_system_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB53_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13755,7 +13755,7 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__amdgpu_no_fine_grained_memory(
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -13767,9 +13767,9 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__amdgpu_no_fine_grained_memory(
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB54_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13809,7 +13809,7 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__amdgpu_no_fine_grained_memory(
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -13821,9 +13821,9 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__amdgpu_no_fine_grained_memory(
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB54_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14326,7 +14326,7 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -14353,7 +14353,7 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -14365,9 +14365,9 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB55_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14384,7 +14384,7 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -14410,7 +14410,7 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -14422,9 +14422,9 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB55_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14943,7 +14943,7 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -14970,7 +14970,7 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -14982,9 +14982,9 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB56_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15001,7 +15001,7 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -15027,7 +15027,7 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -15039,9 +15039,9 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB56_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15578,7 +15578,7 @@ define void @global_agent_atomic_fadd_noret_bf16__amdgpu_no_fine_grained_memory(
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -15591,9 +15591,9 @@ define void @global_agent_atomic_fadd_noret_bf16__amdgpu_no_fine_grained_memory(
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB57_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15630,7 +15630,7 @@ define void @global_agent_atomic_fadd_noret_bf16__amdgpu_no_fine_grained_memory(
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -15643,9 +15643,9 @@ define void @global_agent_atomic_fadd_noret_bf16__amdgpu_no_fine_grained_memory(
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB57_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16131,7 +16131,7 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -16156,7 +16156,7 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -16169,9 +16169,9 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB58_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16187,7 +16187,7 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -16211,7 +16211,7 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -16224,9 +16224,9 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB58_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16728,7 +16728,7 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -16753,7 +16753,7 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -16766,9 +16766,9 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB59_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16784,7 +16784,7 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -16808,7 +16808,7 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -16821,9 +16821,9 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB59_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17322,7 +17322,7 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_pos__align4__amdgpu_
; GFX12-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.h
@@ -17333,9 +17333,9 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_pos__align4__amdgpu_
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB60_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17366,7 +17366,7 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_pos__align4__amdgpu_
; GFX12-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -17377,9 +17377,9 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_pos__align4__amdgpu_
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB60_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17804,7 +17804,7 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b__align4_pos__amdgpu_
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.h
@@ -17815,9 +17815,9 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b__align4_pos__amdgpu_
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB61_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17846,7 +17846,7 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b__align4_pos__amdgpu_
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -17857,9 +17857,9 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b__align4_pos__amdgpu_
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB61_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18283,7 +18283,7 @@ define bfloat @global_system_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -18310,7 +18310,7 @@ define bfloat @global_system_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -18323,9 +18323,9 @@ define bfloat @global_system_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB62_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18342,7 +18342,7 @@ define bfloat @global_system_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -18368,7 +18368,7 @@ define bfloat @global_system_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -18381,9 +18381,9 @@ define bfloat @global_system_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB62_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18898,7 +18898,7 @@ define void @global_system_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -18923,7 +18923,7 @@ define void @global_system_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -18937,9 +18937,9 @@ define void @global_system_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB63_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18955,7 +18955,7 @@ define void @global_system_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -18979,7 +18979,7 @@ define void @global_system_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -18993,9 +18993,9 @@ define void @global_system_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB63_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
index dec3dd79f60d1..dbd48d2a7cf8f 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
@@ -3025,9 +3025,9 @@ define double @global_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB18_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3198,9 +3198,9 @@ define double @global_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB19_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3372,9 +3372,9 @@ define double @global_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB20_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3546,9 +3546,9 @@ define void @global_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB21_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3709,9 +3709,9 @@ define void @global_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_g
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB22_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3875,9 +3875,9 @@ define void @global_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_g
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB23_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4041,9 +4041,9 @@ define double @global_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory(ptr add
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB24_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4289,9 +4289,9 @@ define double @global_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB25_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4480,9 +4480,9 @@ define half @global_agent_atomic_fmax_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB26_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4527,9 +4527,9 @@ define half @global_agent_atomic_fmax_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB26_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4894,7 +4894,7 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
@@ -4925,9 +4925,9 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4944,7 +4944,7 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -4974,9 +4974,9 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5355,7 +5355,7 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
@@ -5386,9 +5386,9 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB28_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5405,7 +5405,7 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -5435,9 +5435,9 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB28_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5844,9 +5844,9 @@ define void @global_agent_atomic_fmax_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB29_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5890,9 +5890,9 @@ define void @global_agent_atomic_fmax_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB29_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6245,7 +6245,7 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
@@ -6275,9 +6275,9 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB30_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6293,7 +6293,7 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -6323,9 +6323,9 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB30_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6691,7 +6691,7 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
@@ -6721,9 +6721,9 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB31_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6739,7 +6739,7 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -6769,9 +6769,9 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB31_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7155,9 +7155,9 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_pos__align4__amdgpu_no_
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB32_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7191,9 +7191,9 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_pos__align4__amdgpu_no_
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB32_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7497,9 +7497,9 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b__align4_pos__amdgpu_n
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB33_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7532,9 +7532,9 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b__align4_pos__amdgpu_n
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB33_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7812,7 +7812,7 @@ define half @global_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
@@ -7844,9 +7844,9 @@ define half @global_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB34_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7863,7 +7863,7 @@ define half @global_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -7894,9 +7894,9 @@ define half @global_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB34_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8277,7 +8277,7 @@ define void @global_system_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
@@ -8308,9 +8308,9 @@ define void @global_system_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB35_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8326,7 +8326,7 @@ define void @global_system_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -8357,9 +8357,9 @@ define void @global_system_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB35_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8757,7 +8757,7 @@ define bfloat @global_agent_atomic_fmax_ret_bf16__amdgpu_no_fine_grained_memory(
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -8769,9 +8769,9 @@ define bfloat @global_agent_atomic_fmax_ret_bf16__amdgpu_no_fine_grained_memory(
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB36_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8811,7 +8811,7 @@ define bfloat @global_agent_atomic_fmax_ret_bf16__amdgpu_no_fine_grained_memory(
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -8823,9 +8823,9 @@ define bfloat @global_agent_atomic_fmax_ret_bf16__amdgpu_no_fine_grained_memory(
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB36_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9235,7 +9235,7 @@ define bfloat @global_agent_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -9262,7 +9262,7 @@ define bfloat @global_agent_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -9274,9 +9274,9 @@ define bfloat @global_agent_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB37_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9293,7 +9293,7 @@ define bfloat @global_agent_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -9319,7 +9319,7 @@ define bfloat @global_agent_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -9331,9 +9331,9 @@ define bfloat @global_agent_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB37_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9756,7 +9756,7 @@ define bfloat @global_agent_atomic_fmax_ret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -9783,7 +9783,7 @@ define bfloat @global_agent_atomic_fmax_ret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -9795,9 +9795,9 @@ define bfloat @global_agent_atomic_fmax_ret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB38_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9814,7 +9814,7 @@ define bfloat @global_agent_atomic_fmax_ret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -9840,7 +9840,7 @@ define bfloat @global_agent_atomic_fmax_ret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -9852,9 +9852,9 @@ define bfloat @global_agent_atomic_fmax_ret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB38_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10302,7 +10302,7 @@ define void @global_agent_atomic_fmax_noret_bf16__amdgpu_no_fine_grained_memory(
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -10315,9 +10315,9 @@ define void @global_agent_atomic_fmax_noret_bf16__amdgpu_no_fine_grained_memory(
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB39_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10354,7 +10354,7 @@ define void @global_agent_atomic_fmax_noret_bf16__amdgpu_no_fine_grained_memory(
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -10367,9 +10367,9 @@ define void @global_agent_atomic_fmax_noret_bf16__amdgpu_no_fine_grained_memory(
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB39_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10766,7 +10766,7 @@ define void @global_agent_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -10791,7 +10791,7 @@ define void @global_agent_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -10804,9 +10804,9 @@ define void @global_agent_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB40_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10822,7 +10822,7 @@ define void @global_agent_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -10846,7 +10846,7 @@ define void @global_agent_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -10859,9 +10859,9 @@ define void @global_agent_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB40_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11270,7 +11270,7 @@ define void @global_agent_atomic_fmax_noret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -11295,7 +11295,7 @@ define void @global_agent_atomic_fmax_noret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -11308,9 +11308,9 @@ define void @global_agent_atomic_fmax_noret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB41_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11326,7 +11326,7 @@ define void @global_agent_atomic_fmax_noret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -11350,7 +11350,7 @@ define void @global_agent_atomic_fmax_noret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -11363,9 +11363,9 @@ define void @global_agent_atomic_fmax_noret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB41_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11791,7 +11791,7 @@ define bfloat @global_agent_atomic_fmax_ret_bf16__offset12b_pos__align4__amdgpu_
; GFX12-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.h
@@ -11802,9 +11802,9 @@ define bfloat @global_agent_atomic_fmax_ret_bf16__offset12b_pos__align4__amdgpu_
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB42_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11835,7 +11835,7 @@ define bfloat @global_agent_atomic_fmax_ret_bf16__offset12b_pos__align4__amdgpu_
; GFX12-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -11846,9 +11846,9 @@ define bfloat @global_agent_atomic_fmax_ret_bf16__offset12b_pos__align4__amdgpu_
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB42_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12204,7 +12204,7 @@ define void @global_agent_atomic_fmax_noret_bf16__offset12b__align4_pos__amdgpu_
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.h
@@ -12215,9 +12215,9 @@ define void @global_agent_atomic_fmax_noret_bf16__offset12b__align4_pos__amdgpu_
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB43_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12246,7 +12246,7 @@ define void @global_agent_atomic_fmax_noret_bf16__offset12b__align4_pos__amdgpu_
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -12257,9 +12257,9 @@ define void @global_agent_atomic_fmax_noret_bf16__offset12b__align4_pos__amdgpu_
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB43_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12589,7 +12589,7 @@ define bfloat @global_system_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -12616,7 +12616,7 @@ define bfloat @global_system_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -12629,9 +12629,9 @@ define bfloat @global_system_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB44_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12648,7 +12648,7 @@ define bfloat @global_system_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -12674,7 +12674,7 @@ define bfloat @global_system_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -12687,9 +12687,9 @@ define bfloat @global_system_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB44_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13114,7 +13114,7 @@ define void @global_system_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -13139,7 +13139,7 @@ define void @global_system_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -13153,9 +13153,9 @@ define void @global_system_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB45_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13171,7 +13171,7 @@ define void @global_system_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -13195,7 +13195,7 @@ define void @global_system_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -13209,9 +13209,9 @@ define void @global_system_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB45_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13640,9 +13640,9 @@ define <2 x half> @global_agent_atomic_fmax_ret_v2f16__amdgpu_no_fine_grained_me
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB46_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13933,9 +13933,9 @@ define <2 x half> @global_agent_atomic_fmax_ret_v2f16__offset12b_pos__amdgpu_no_
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB47_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14228,9 +14228,9 @@ define <2 x half> @global_agent_atomic_fmax_ret_v2f16__offset12b_neg__amdgpu_no_
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB48_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14527,9 +14527,9 @@ define void @global_agent_atomic_fmax_noret_v2f16__amdgpu_no_fine_grained_memory
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB49_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14809,9 +14809,9 @@ define void @global_agent_atomic_fmax_noret_v2f16__offset12b_pos__amdgpu_no_fine
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB50_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15094,9 +15094,9 @@ define void @global_agent_atomic_fmax_noret_v2f16__offset12b_neg__amdgpu_no_fine
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB51_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15388,9 +15388,9 @@ define <2 x half> @global_system_atomic_fmax_ret_v2f16__offset12b_pos__amdgpu_no
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB52_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15686,9 +15686,9 @@ define void @global_system_atomic_fmax_noret_v2f16__offset12b_pos__amdgpu_no_fin
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB53_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15985,10 +15985,10 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
@@ -15997,9 +15997,9 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB54_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16037,10 +16037,10 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained
; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
@@ -16049,9 +16049,9 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB54_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16485,10 +16485,10 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
@@ -16497,9 +16497,9 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB55_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16537,10 +16537,10 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_
; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
@@ -16549,9 +16549,9 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB55_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16987,10 +16987,10 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_neg__amdgpu_
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
@@ -16999,9 +16999,9 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_neg__amdgpu_
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB56_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17039,10 +17039,10 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_neg__amdgpu_
; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
@@ -17051,9 +17051,9 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_neg__amdgpu_
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB56_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17490,11 +17490,11 @@ define void @global_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -17503,9 +17503,9 @@ define void @global_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB57_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17541,10 +17541,10 @@ define void @global_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
@@ -17554,9 +17554,9 @@ define void @global_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB57_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17973,11 +17973,11 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -17986,9 +17986,9 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB58_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18024,10 +18024,10 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
@@ -18037,9 +18037,9 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB58_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18459,11 +18459,11 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -18472,9 +18472,9 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB59_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18510,10 +18510,10 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
@@ -18523,9 +18523,9 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB59_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18956,10 +18956,10 @@ define <2 x bfloat> @global_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
@@ -18969,9 +18969,9 @@ define <2 x bfloat> @global_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB60_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -19009,10 +19009,10 @@ define <2 x bfloat> @global_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu
; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
@@ -19022,9 +19022,9 @@ define <2 x bfloat> @global_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB60_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -19459,11 +19459,11 @@ define void @global_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
@@ -19473,9 +19473,9 @@ define void @global_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB61_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -19511,10 +19511,10 @@ define void @global_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
@@ -19525,9 +19525,9 @@ define void @global_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB61_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
index ce087737b852a..7930ad8a15404 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
@@ -3025,9 +3025,9 @@ define double @global_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB18_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3198,9 +3198,9 @@ define double @global_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB19_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3372,9 +3372,9 @@ define double @global_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_g
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB20_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3546,9 +3546,9 @@ define void @global_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(p
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB21_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3709,9 +3709,9 @@ define void @global_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_g
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB22_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3875,9 +3875,9 @@ define void @global_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_g
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
; GFX12-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB23_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4041,9 +4041,9 @@ define double @global_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory(ptr add
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB24_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4289,9 +4289,9 @@ define double @global_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB25_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4480,9 +4480,9 @@ define half @global_agent_atomic_fmin_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB26_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4527,9 +4527,9 @@ define half @global_agent_atomic_fmin_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB26_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4894,7 +4894,7 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
@@ -4925,9 +4925,9 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4944,7 +4944,7 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -4974,9 +4974,9 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5355,7 +5355,7 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
@@ -5386,9 +5386,9 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB28_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5405,7 +5405,7 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -5435,9 +5435,9 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB28_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5844,9 +5844,9 @@ define void @global_agent_atomic_fmin_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB29_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5890,9 +5890,9 @@ define void @global_agent_atomic_fmin_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB29_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6245,7 +6245,7 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
@@ -6275,9 +6275,9 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB30_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6293,7 +6293,7 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -6323,9 +6323,9 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB30_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6691,7 +6691,7 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
@@ -6721,9 +6721,9 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB31_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6739,7 +6739,7 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -6769,9 +6769,9 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB31_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7155,9 +7155,9 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_pos__align4__amdgpu_no_
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB32_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7191,9 +7191,9 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_pos__align4__amdgpu_no_
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB32_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7497,9 +7497,9 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b__align4_pos__amdgpu_n
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB33_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7532,9 +7532,9 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b__align4_pos__amdgpu_n
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB33_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7812,7 +7812,7 @@ define half @global_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
@@ -7844,9 +7844,9 @@ define half @global_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB34_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7863,7 +7863,7 @@ define half @global_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -7894,9 +7894,9 @@ define half @global_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB34_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8277,7 +8277,7 @@ define void @global_system_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, -4, v0
@@ -8308,9 +8308,9 @@ define void @global_system_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB35_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8326,7 +8326,7 @@ define void @global_system_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v6, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -8357,9 +8357,9 @@ define void @global_system_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB35_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8757,7 +8757,7 @@ define bfloat @global_agent_atomic_fmin_ret_bf16__amdgpu_no_fine_grained_memory(
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -8769,9 +8769,9 @@ define bfloat @global_agent_atomic_fmin_ret_bf16__amdgpu_no_fine_grained_memory(
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB36_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8811,7 +8811,7 @@ define bfloat @global_agent_atomic_fmin_ret_bf16__amdgpu_no_fine_grained_memory(
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -8823,9 +8823,9 @@ define bfloat @global_agent_atomic_fmin_ret_bf16__amdgpu_no_fine_grained_memory(
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB36_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9235,7 +9235,7 @@ define bfloat @global_agent_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -9262,7 +9262,7 @@ define bfloat @global_agent_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -9274,9 +9274,9 @@ define bfloat @global_agent_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB37_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9293,7 +9293,7 @@ define bfloat @global_agent_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -9319,7 +9319,7 @@ define bfloat @global_agent_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -9331,9 +9331,9 @@ define bfloat @global_agent_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB37_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9756,7 +9756,7 @@ define bfloat @global_agent_atomic_fmin_ret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -9783,7 +9783,7 @@ define bfloat @global_agent_atomic_fmin_ret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -9795,9 +9795,9 @@ define bfloat @global_agent_atomic_fmin_ret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB38_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9814,7 +9814,7 @@ define bfloat @global_agent_atomic_fmin_ret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -9840,7 +9840,7 @@ define bfloat @global_agent_atomic_fmin_ret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -9852,9 +9852,9 @@ define bfloat @global_agent_atomic_fmin_ret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB38_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10302,7 +10302,7 @@ define void @global_agent_atomic_fmin_noret_bf16__amdgpu_no_fine_grained_memory(
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -10315,9 +10315,9 @@ define void @global_agent_atomic_fmin_noret_bf16__amdgpu_no_fine_grained_memory(
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB39_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10354,7 +10354,7 @@ define void @global_agent_atomic_fmin_noret_bf16__amdgpu_no_fine_grained_memory(
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -10367,9 +10367,9 @@ define void @global_agent_atomic_fmin_noret_bf16__amdgpu_no_fine_grained_memory(
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB39_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10766,7 +10766,7 @@ define void @global_agent_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -10791,7 +10791,7 @@ define void @global_agent_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -10804,9 +10804,9 @@ define void @global_agent_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB40_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10822,7 +10822,7 @@ define void @global_agent_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -10846,7 +10846,7 @@ define void @global_agent_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -10859,9 +10859,9 @@ define void @global_agent_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB40_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11270,7 +11270,7 @@ define void @global_agent_atomic_fmin_noret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -11295,7 +11295,7 @@ define void @global_agent_atomic_fmin_noret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -11308,9 +11308,9 @@ define void @global_agent_atomic_fmin_noret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB41_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11326,7 +11326,7 @@ define void @global_agent_atomic_fmin_noret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -11350,7 +11350,7 @@ define void @global_agent_atomic_fmin_noret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -11363,9 +11363,9 @@ define void @global_agent_atomic_fmin_noret_bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB41_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11791,7 +11791,7 @@ define bfloat @global_agent_atomic_fmin_ret_bf16__offset12b_pos__align4__amdgpu_
; GFX12-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.h
@@ -11802,9 +11802,9 @@ define bfloat @global_agent_atomic_fmin_ret_bf16__offset12b_pos__align4__amdgpu_
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB42_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11835,7 +11835,7 @@ define bfloat @global_agent_atomic_fmin_ret_bf16__offset12b_pos__align4__amdgpu_
; GFX12-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -11846,9 +11846,9 @@ define bfloat @global_agent_atomic_fmin_ret_bf16__offset12b_pos__align4__amdgpu_
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB42_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12204,7 +12204,7 @@ define void @global_agent_atomic_fmin_noret_bf16__offset12b__align4_pos__amdgpu_
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.h
@@ -12215,9 +12215,9 @@ define void @global_agent_atomic_fmin_noret_bf16__offset12b__align4_pos__amdgpu_
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB43_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12246,7 +12246,7 @@ define void @global_agent_atomic_fmin_noret_bf16__offset12b__align4_pos__amdgpu_
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -12257,9 +12257,9 @@ define void @global_agent_atomic_fmin_noret_bf16__offset12b__align4_pos__amdgpu_
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB43_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12589,7 +12589,7 @@ define bfloat @global_system_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -12616,7 +12616,7 @@ define bfloat @global_system_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -12629,9 +12629,9 @@ define bfloat @global_system_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB44_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12648,7 +12648,7 @@ define bfloat @global_system_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -12674,7 +12674,7 @@ define bfloat @global_system_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -12687,9 +12687,9 @@ define bfloat @global_system_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB44_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13114,7 +13114,7 @@ define void @global_system_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -13139,7 +13139,7 @@ define void @global_system_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -13153,9 +13153,9 @@ define void @global_system_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB45_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13171,7 +13171,7 @@ define void @global_system_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -13195,7 +13195,7 @@ define void @global_system_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -13209,9 +13209,9 @@ define void @global_system_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB45_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13640,9 +13640,9 @@ define <2 x half> @global_agent_atomic_fmin_ret_v2f16__amdgpu_no_fine_grained_me
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB46_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13933,9 +13933,9 @@ define <2 x half> @global_agent_atomic_fmin_ret_v2f16__offset12b_pos__amdgpu_no_
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB47_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14228,9 +14228,9 @@ define <2 x half> @global_agent_atomic_fmin_ret_v2f16__offset12b_neg__amdgpu_no_
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB48_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14527,9 +14527,9 @@ define void @global_agent_atomic_fmin_noret_v2f16__amdgpu_no_fine_grained_memory
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB49_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14809,9 +14809,9 @@ define void @global_agent_atomic_fmin_noret_v2f16__offset12b_pos__amdgpu_no_fine
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB50_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15094,9 +15094,9 @@ define void @global_agent_atomic_fmin_noret_v2f16__offset12b_neg__amdgpu_no_fine
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB51_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15388,9 +15388,9 @@ define <2 x half> @global_system_atomic_fmin_ret_v2f16__offset12b_pos__amdgpu_no
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB52_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15686,9 +15686,9 @@ define void @global_system_atomic_fmin_noret_v2f16__offset12b_pos__amdgpu_no_fin
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB53_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15985,10 +15985,10 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
@@ -15997,9 +15997,9 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB54_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16037,10 +16037,10 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained
; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
@@ -16049,9 +16049,9 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB54_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16485,10 +16485,10 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
@@ -16497,9 +16497,9 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB55_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16537,10 +16537,10 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_
; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
@@ -16549,9 +16549,9 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB55_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16987,10 +16987,10 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_neg__amdgpu_
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
@@ -16999,9 +16999,9 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_neg__amdgpu_
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB56_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17039,10 +17039,10 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_neg__amdgpu_
; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
@@ -17051,9 +17051,9 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_neg__amdgpu_
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB56_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17490,11 +17490,11 @@ define void @global_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -17503,9 +17503,9 @@ define void @global_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB57_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17541,10 +17541,10 @@ define void @global_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
@@ -17554,9 +17554,9 @@ define void @global_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB57_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17973,11 +17973,11 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -17986,9 +17986,9 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB58_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18024,10 +18024,10 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
@@ -18037,9 +18037,9 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB58_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18459,11 +18459,11 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -18472,9 +18472,9 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB59_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18510,10 +18510,10 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
@@ -18523,9 +18523,9 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB59_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18956,10 +18956,10 @@ define <2 x bfloat> @global_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
@@ -18969,9 +18969,9 @@ define <2 x bfloat> @global_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB60_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -19009,10 +19009,10 @@ define <2 x bfloat> @global_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu
; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
@@ -19022,9 +19022,9 @@ define <2 x bfloat> @global_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB60_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -19459,11 +19459,11 @@ define void @global_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
@@ -19473,9 +19473,9 @@ define void @global_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB61_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -19511,10 +19511,10 @@ define void @global_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
@@ -19525,9 +19525,9 @@ define void @global_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB61_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
index f72296b68bea2..b79d0df960a0f 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
@@ -36,9 +36,9 @@ define float @global_agent_atomic_fsub_ret_f32(ptr addrspace(1) %ptr, float %val
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB0_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -268,9 +268,9 @@ define float @global_agent_atomic_fsub_ret_f32__offset12b_pos(ptr addrspace(1) %
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB1_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -502,9 +502,9 @@ define float @global_agent_atomic_fsub_ret_f32__offset12b_neg(ptr addrspace(1) %
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB2_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -745,9 +745,9 @@ define void @global_agent_atomic_fsub_noret_f32(ptr addrspace(1) %ptr, float %va
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB3_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -966,9 +966,9 @@ define void @global_agent_atomic_fsub_noret_f32__offset12b_pos(ptr addrspace(1)
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB4_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1190,9 +1190,9 @@ define void @global_agent_atomic_fsub_noret_f32__offset12b_neg(ptr addrspace(1)
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB5_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1424,9 +1424,9 @@ define float @global_system_atomic_fsub_ret_f32__offset12b_pos(ptr addrspace(1)
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB6_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1660,9 +1660,9 @@ define void @global_system_atomic_fsub_noret_f32__offset12b_pos(ptr addrspace(1)
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB7_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1891,9 +1891,9 @@ define float @global_agent_atomic_fsub_ret_f32__ftz(ptr addrspace(1) %ptr, float
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB8_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2123,9 +2123,9 @@ define float @global_agent_atomic_fsub_ret_f32__offset12b_pos__ftz(ptr addrspace
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB9_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2357,9 +2357,9 @@ define float @global_agent_atomic_fsub_ret_f32__offset12b_neg__ftz(ptr addrspace
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB10_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2600,9 +2600,9 @@ define void @global_agent_atomic_fsub_noret_f32__ftz(ptr addrspace(1) %ptr, floa
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB11_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2821,9 +2821,9 @@ define void @global_agent_atomic_fsub_noret_f32__offset12b_pos__ftz(ptr addrspac
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB12_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3045,9 +3045,9 @@ define void @global_agent_atomic_fsub_noret_f32__offset12b_neg__ftz(ptr addrspac
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB13_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3279,9 +3279,9 @@ define float @global_system_atomic_fsub_ret_f32__offset12b_pos__ftz(ptr addrspac
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB14_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3515,9 +3515,9 @@ define void @global_system_atomic_fsub_noret_f32__offset12b_pos__ftz(ptr addrspa
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB15_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3746,9 +3746,9 @@ define double @global_agent_atomic_fsub_ret_f64(ptr addrspace(1) %ptr, double %v
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB16_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3998,9 +3998,9 @@ define double @global_agent_atomic_fsub_ret_f64__offset12b_pos(ptr addrspace(1)
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB17_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4251,9 +4251,9 @@ define double @global_agent_atomic_fsub_ret_f64__offset12b_neg(ptr addrspace(1)
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB18_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4507,9 +4507,9 @@ define void @global_agent_atomic_fsub_noret_f64(ptr addrspace(1) %ptr, double %v
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB19_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4737,9 +4737,9 @@ define void @global_agent_atomic_fsub_noret_f64__offset12b_pos(ptr addrspace(1)
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB20_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4970,9 +4970,9 @@ define void @global_agent_atomic_fsub_noret_f64__offset12b_neg(ptr addrspace(1)
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
; GFX12-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB21_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5229,9 +5229,9 @@ define half @global_agent_atomic_fsub_ret_f16(ptr addrspace(1) %ptr, half %val)
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB22_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5274,9 +5274,9 @@ define half @global_agent_atomic_fsub_ret_f16(ptr addrspace(1) %ptr, half %val)
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB22_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5626,7 +5626,7 @@ define half @global_agent_atomic_fsub_ret_f16__offset12b_pos(ptr addrspace(1) %p
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -5652,9 +5652,9 @@ define half @global_agent_atomic_fsub_ret_f16__offset12b_pos(ptr addrspace(1) %p
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB23_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5671,7 +5671,7 @@ define half @global_agent_atomic_fsub_ret_f16__offset12b_pos(ptr addrspace(1) %p
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -5698,9 +5698,9 @@ define half @global_agent_atomic_fsub_ret_f16__offset12b_pos(ptr addrspace(1) %p
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB23_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6062,7 +6062,7 @@ define half @global_agent_atomic_fsub_ret_f16__offset12b_neg(ptr addrspace(1) %p
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -6088,9 +6088,9 @@ define half @global_agent_atomic_fsub_ret_f16__offset12b_neg(ptr addrspace(1) %p
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB24_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6107,7 +6107,7 @@ define half @global_agent_atomic_fsub_ret_f16__offset12b_neg(ptr addrspace(1) %p
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -6134,9 +6134,9 @@ define half @global_agent_atomic_fsub_ret_f16__offset12b_neg(ptr addrspace(1) %p
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB24_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6524,9 +6524,9 @@ define void @global_agent_atomic_fsub_noret_f16(ptr addrspace(1) %ptr, half %val
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB25_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6567,9 +6567,9 @@ define void @global_agent_atomic_fsub_noret_f16(ptr addrspace(1) %ptr, half %val
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB25_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6907,7 +6907,7 @@ define void @global_agent_atomic_fsub_noret_f16__offset12b_pos(ptr addrspace(1)
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -6933,9 +6933,9 @@ define void @global_agent_atomic_fsub_noret_f16__offset12b_pos(ptr addrspace(1)
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB26_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6951,7 +6951,7 @@ define void @global_agent_atomic_fsub_noret_f16__offset12b_pos(ptr addrspace(1)
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -6977,9 +6977,9 @@ define void @global_agent_atomic_fsub_noret_f16__offset12b_pos(ptr addrspace(1)
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB26_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7328,7 +7328,7 @@ define void @global_agent_atomic_fsub_noret_f16__offset12b_neg(ptr addrspace(1)
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -7354,9 +7354,9 @@ define void @global_agent_atomic_fsub_noret_f16__offset12b_neg(ptr addrspace(1)
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7372,7 +7372,7 @@ define void @global_agent_atomic_fsub_noret_f16__offset12b_neg(ptr addrspace(1)
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -7398,9 +7398,9 @@ define void @global_agent_atomic_fsub_noret_f16__offset12b_neg(ptr addrspace(1)
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7764,9 +7764,9 @@ define half @global_agent_atomic_fsub_ret_f16__offset12b_pos__align4(ptr addrspa
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB28_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7798,9 +7798,9 @@ define half @global_agent_atomic_fsub_ret_f16__offset12b_pos__align4(ptr addrspa
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB28_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8087,9 +8087,9 @@ define void @global_agent_atomic_fsub_noret_f16__offset12b__align4_pos(ptr addrs
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB29_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8119,9 +8119,9 @@ define void @global_agent_atomic_fsub_noret_f16__offset12b__align4_pos(ptr addrs
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB29_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8384,7 +8384,7 @@ define half @global_system_atomic_fsub_ret_f16__offset12b_pos(ptr addrspace(1) %
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -8411,9 +8411,9 @@ define half @global_system_atomic_fsub_ret_f16__offset12b_pos(ptr addrspace(1) %
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB30_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8430,7 +8430,7 @@ define half @global_system_atomic_fsub_ret_f16__offset12b_pos(ptr addrspace(1) %
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -8458,9 +8458,9 @@ define half @global_system_atomic_fsub_ret_f16__offset12b_pos(ptr addrspace(1) %
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB30_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8824,7 +8824,7 @@ define void @global_system_atomic_fsub_noret_f16__offset12b_pos(ptr addrspace(1)
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -8851,9 +8851,9 @@ define void @global_system_atomic_fsub_noret_f16__offset12b_pos(ptr addrspace(1)
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB31_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8869,7 +8869,7 @@ define void @global_system_atomic_fsub_noret_f16__offset12b_pos(ptr addrspace(1)
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -8896,9 +8896,9 @@ define void @global_system_atomic_fsub_noret_f16__offset12b_pos(ptr addrspace(1)
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB31_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9279,7 +9279,7 @@ define bfloat @global_agent_atomic_fsub_ret_bf16(ptr addrspace(1) %ptr, bfloat %
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -9291,9 +9291,9 @@ define bfloat @global_agent_atomic_fsub_ret_bf16(ptr addrspace(1) %ptr, bfloat %
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB32_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9333,7 +9333,7 @@ define bfloat @global_agent_atomic_fsub_ret_bf16(ptr addrspace(1) %ptr, bfloat %
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -9345,9 +9345,9 @@ define bfloat @global_agent_atomic_fsub_ret_bf16(ptr addrspace(1) %ptr, bfloat %
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB32_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9755,7 +9755,7 @@ define bfloat @global_agent_atomic_fsub_ret_bf16__offset12b_pos(ptr addrspace(1)
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -9782,7 +9782,7 @@ define bfloat @global_agent_atomic_fsub_ret_bf16__offset12b_pos(ptr addrspace(1)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -9794,9 +9794,9 @@ define bfloat @global_agent_atomic_fsub_ret_bf16__offset12b_pos(ptr addrspace(1)
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB33_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9813,7 +9813,7 @@ define bfloat @global_agent_atomic_fsub_ret_bf16__offset12b_pos(ptr addrspace(1)
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -9839,7 +9839,7 @@ define bfloat @global_agent_atomic_fsub_ret_bf16__offset12b_pos(ptr addrspace(1)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -9851,9 +9851,9 @@ define bfloat @global_agent_atomic_fsub_ret_bf16__offset12b_pos(ptr addrspace(1)
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB33_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10274,7 +10274,7 @@ define bfloat @global_agent_atomic_fsub_ret_bf16__offset12b_neg(ptr addrspace(1)
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -10301,7 +10301,7 @@ define bfloat @global_agent_atomic_fsub_ret_bf16__offset12b_neg(ptr addrspace(1)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -10313,9 +10313,9 @@ define bfloat @global_agent_atomic_fsub_ret_bf16__offset12b_neg(ptr addrspace(1)
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB34_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10332,7 +10332,7 @@ define bfloat @global_agent_atomic_fsub_ret_bf16__offset12b_neg(ptr addrspace(1)
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -10358,7 +10358,7 @@ define bfloat @global_agent_atomic_fsub_ret_bf16__offset12b_neg(ptr addrspace(1)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -10370,9 +10370,9 @@ define bfloat @global_agent_atomic_fsub_ret_bf16__offset12b_neg(ptr addrspace(1)
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB34_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10818,7 +10818,7 @@ define void @global_agent_atomic_fsub_noret_bf16(ptr addrspace(1) %ptr, bfloat %
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -10831,9 +10831,9 @@ define void @global_agent_atomic_fsub_noret_bf16(ptr addrspace(1) %ptr, bfloat %
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB35_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -10870,7 +10870,7 @@ define void @global_agent_atomic_fsub_noret_bf16(ptr addrspace(1) %ptr, bfloat %
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -10883,9 +10883,9 @@ define void @global_agent_atomic_fsub_noret_bf16(ptr addrspace(1) %ptr, bfloat %
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB35_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11280,7 +11280,7 @@ define void @global_agent_atomic_fsub_noret_bf16__offset12b_pos(ptr addrspace(1)
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -11305,7 +11305,7 @@ define void @global_agent_atomic_fsub_noret_bf16__offset12b_pos(ptr addrspace(1)
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -11318,9 +11318,9 @@ define void @global_agent_atomic_fsub_noret_bf16__offset12b_pos(ptr addrspace(1)
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB36_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11336,7 +11336,7 @@ define void @global_agent_atomic_fsub_noret_bf16__offset12b_pos(ptr addrspace(1)
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -11360,7 +11360,7 @@ define void @global_agent_atomic_fsub_noret_bf16__offset12b_pos(ptr addrspace(1)
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -11373,9 +11373,9 @@ define void @global_agent_atomic_fsub_noret_bf16__offset12b_pos(ptr addrspace(1)
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB36_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11782,7 +11782,7 @@ define void @global_agent_atomic_fsub_noret_bf16__offset12b_neg(ptr addrspace(1)
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0xfffff800, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -11807,7 +11807,7 @@ define void @global_agent_atomic_fsub_noret_bf16__offset12b_neg(ptr addrspace(1)
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -11820,9 +11820,9 @@ define void @global_agent_atomic_fsub_noret_bf16__offset12b_neg(ptr addrspace(1)
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB37_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -11838,7 +11838,7 @@ define void @global_agent_atomic_fsub_noret_bf16__offset12b_neg(ptr addrspace(1)
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0xfffff800, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -11862,7 +11862,7 @@ define void @global_agent_atomic_fsub_noret_bf16__offset12b_neg(ptr addrspace(1)
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -11875,9 +11875,9 @@ define void @global_agent_atomic_fsub_noret_bf16__offset12b_neg(ptr addrspace(1)
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB37_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12301,7 +12301,7 @@ define bfloat @global_agent_atomic_fsub_ret_bf16__offset12b_pos__align4(ptr addr
; GFX12-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.h
@@ -12312,9 +12312,9 @@ define bfloat @global_agent_atomic_fsub_ret_bf16__offset12b_pos__align4(ptr addr
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB38_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12345,7 +12345,7 @@ define bfloat @global_agent_atomic_fsub_ret_bf16__offset12b_pos__align4(ptr addr
; GFX12-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -12356,9 +12356,9 @@ define bfloat @global_agent_atomic_fsub_ret_bf16__offset12b_pos__align4(ptr addr
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB38_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12712,7 +12712,7 @@ define void @global_agent_atomic_fsub_noret_bf16__offset12b__align4_pos(ptr addr
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.h
@@ -12723,9 +12723,9 @@ define void @global_agent_atomic_fsub_noret_bf16__offset12b__align4_pos(ptr addr
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB39_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -12754,7 +12754,7 @@ define void @global_agent_atomic_fsub_noret_bf16__offset12b__align4_pos(ptr addr
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -12765,9 +12765,9 @@ define void @global_agent_atomic_fsub_noret_bf16__offset12b__align4_pos(ptr addr
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB39_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13095,7 +13095,7 @@ define bfloat @global_system_atomic_fsub_ret_bf16__offset12b_pos(ptr addrspace(1
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -13122,7 +13122,7 @@ define bfloat @global_system_atomic_fsub_ret_bf16__offset12b_pos(ptr addrspace(1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
@@ -13135,9 +13135,9 @@ define bfloat @global_system_atomic_fsub_ret_bf16__offset12b_pos(ptr addrspace(1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB40_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13154,7 +13154,7 @@ define bfloat @global_system_atomic_fsub_ret_bf16__offset12b_pos(ptr addrspace(1
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -13180,7 +13180,7 @@ define bfloat @global_system_atomic_fsub_ret_bf16__offset12b_pos(ptr addrspace(1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
@@ -13193,9 +13193,9 @@ define bfloat @global_system_atomic_fsub_ret_bf16__offset12b_pos(ptr addrspace(1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB40_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13618,7 +13618,7 @@ define void @global_system_atomic_fsub_noret_bf16__offset12b_pos(ptr addrspace(1
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, 0x7fe, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, -4, v3
@@ -13643,7 +13643,7 @@ define void @global_system_atomic_fsub_noret_bf16__offset12b_pos(ptr addrspace(1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h
@@ -13657,9 +13657,9 @@ define void @global_system_atomic_fsub_noret_bf16__offset12b_pos(ptr addrspace(1
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB41_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -13675,7 +13675,7 @@ define void @global_system_atomic_fsub_noret_bf16__offset12b_pos(ptr addrspace(1
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, 0x7fe, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
@@ -13699,7 +13699,7 @@ define void @global_system_atomic_fsub_noret_bf16__offset12b_pos(ptr addrspace(1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -13713,9 +13713,9 @@ define void @global_system_atomic_fsub_noret_bf16__offset12b_pos(ptr addrspace(1
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB41_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14140,9 +14140,9 @@ define <2 x half> @global_agent_atomic_fsub_ret_v2f16(ptr addrspace(1) %ptr, <2
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB42_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14416,9 +14416,9 @@ define <2 x half> @global_agent_atomic_fsub_ret_v2f16__offset12b_pos(ptr addrspa
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB43_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14694,9 +14694,9 @@ define <2 x half> @global_agent_atomic_fsub_ret_v2f16__offset12b_neg(ptr addrspa
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB44_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -14975,9 +14975,9 @@ define void @global_agent_atomic_fsub_noret_v2f16(ptr addrspace(1) %ptr, <2 x ha
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB45_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15238,9 +15238,9 @@ define void @global_agent_atomic_fsub_noret_v2f16__offset12b_pos(ptr addrspace(1
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB46_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15504,9 +15504,9 @@ define void @global_agent_atomic_fsub_noret_v2f16__offset12b_neg(ptr addrspace(1
; GFX12-NEXT: global_inv scope:SCOPE_DEV
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB47_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -15780,9 +15780,9 @@ define <2 x half> @global_system_atomic_fsub_ret_v2f16__offset12b_pos(ptr addrsp
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB48_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16060,9 +16060,9 @@ define void @global_system_atomic_fsub_noret_v2f16__offset12b_pos(ptr addrspace(
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
; GFX12-NEXT: v_mov_b32_e32 v4, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB49_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16343,10 +16343,10 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16(ptr addrspace(1) %ptr,
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
@@ -16355,9 +16355,9 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16(ptr addrspace(1) %ptr,
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB50_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16395,10 +16395,10 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16(ptr addrspace(1) %ptr,
; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
@@ -16407,9 +16407,9 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16(ptr addrspace(1) %ptr,
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB50_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16843,10 +16843,10 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr addr
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
@@ -16855,9 +16855,9 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr addr
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB51_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -16895,10 +16895,10 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr addr
; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
@@ -16907,9 +16907,9 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr addr
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB51_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17345,10 +17345,10 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_neg(ptr addr
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
@@ -17357,9 +17357,9 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_neg(ptr addr
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB52_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17397,10 +17397,10 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_neg(ptr addr
; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
@@ -17409,9 +17409,9 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_neg(ptr addr
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB52_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17848,11 +17848,11 @@ define void @global_agent_atomic_fsub_noret_v2bf16(ptr addrspace(1) %ptr, <2 x b
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -17861,9 +17861,9 @@ define void @global_agent_atomic_fsub_noret_v2bf16(ptr addrspace(1) %ptr, <2 x b
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB53_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -17899,10 +17899,10 @@ define void @global_agent_atomic_fsub_noret_v2bf16(ptr addrspace(1) %ptr, <2 x b
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
@@ -17912,9 +17912,9 @@ define void @global_agent_atomic_fsub_noret_v2bf16(ptr addrspace(1) %ptr, <2 x b
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB53_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18331,11 +18331,11 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace(
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -18344,9 +18344,9 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace(
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB54_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18382,10 +18382,10 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace(
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
@@ -18395,9 +18395,9 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace(
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB54_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18817,11 +18817,11 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr addrspace(
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -18830,9 +18830,9 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr addrspace(
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB55_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -18868,10 +18868,10 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr addrspace(
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
@@ -18881,9 +18881,9 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr addrspace(
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_DEV
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB55_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -19314,10 +19314,10 @@ define <2 x bfloat> @global_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr add
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
@@ -19327,9 +19327,9 @@ define <2 x bfloat> @global_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr add
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB56_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -19367,10 +19367,10 @@ define <2 x bfloat> @global_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr add
; GFX12-FAKE16-NEXT: v_bfe_u32 v7, v3, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v5, v3, 0x7060302
@@ -19380,9 +19380,9 @@ define <2 x bfloat> @global_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr add
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB56_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -19817,11 +19817,11 @@ define void @global_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
@@ -19831,9 +19831,9 @@ define void @global_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB57_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -19869,10 +19869,10 @@ define void @global_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v7, v9, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x7060302
@@ -19883,9 +19883,9 @@ define void @global_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SYS
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB57_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
diff --git a/llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll b/llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll
index 65832f8db2b00..6fd1285c0a345 100644
--- a/llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll
@@ -67,7 +67,7 @@ define amdgpu_ps float @global_max_saddr_i32_rtn(ptr addrspace(1) inreg %sbase,
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB0_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -107,9 +107,9 @@ define amdgpu_ps float @global_max_saddr_i32_rtn(ptr addrspace(1) inreg %sbase,
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc, v0, v5
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB0_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -180,7 +180,7 @@ define amdgpu_ps float @global_max_saddr_i32_rtn_neg128(ptr addrspace(1) inreg %
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB1_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -220,9 +220,9 @@ define amdgpu_ps float @global_max_saddr_i32_rtn_neg128(ptr addrspace(1) inreg %
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc, v0, v5
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB1_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -289,7 +289,7 @@ define amdgpu_ps void @global_max_saddr_i32_nortn(ptr addrspace(1) inreg %sbase,
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB2_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -325,9 +325,9 @@ define amdgpu_ps void @global_max_saddr_i32_nortn(ptr addrspace(1) inreg %sbase,
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc, v0, v5
; GFX12-NEXT: v_mov_b32_e32 v5, v0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB2_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -390,7 +390,7 @@ define amdgpu_ps void @global_max_saddr_i32_nortn_neg128(ptr addrspace(1) inreg
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB3_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -426,9 +426,9 @@ define amdgpu_ps void @global_max_saddr_i32_nortn_neg128(ptr addrspace(1) inreg
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc, v0, v5
; GFX12-NEXT: v_mov_b32_e32 v5, v0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB3_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -504,7 +504,7 @@ define amdgpu_ps <2 x float> @global_max_saddr_i64_rtn(ptr addrspace(1) inreg %s
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v6, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB4_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -519,7 +519,7 @@ define amdgpu_ps <2 x float> @global_max_saddr_i64_rtn(ptr addrspace(1) inreg %s
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[9:10]
-; GFX11-NEXT: s_waitcnt_depctr 0xfffd
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX11-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_b64 exec, exec, s[0:1]
@@ -544,7 +544,7 @@ define amdgpu_ps <2 x float> @global_max_saddr_i64_rtn(ptr addrspace(1) inreg %s
; GFX12-NEXT: v_mov_b32_e32 v9, v3
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_cmp_gt_i64_e32 vcc, v[9:10], v[1:2]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v8, v2, v10, vcc
; GFX12-NEXT: v_cndmask_b32_e32 v7, v1, v9, vcc
; GFX12-NEXT: global_wb scope:SCOPE_SYS
@@ -553,9 +553,9 @@ define amdgpu_ps <2 x float> @global_max_saddr_i64_rtn(ptr addrspace(1) inreg %s
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[9:10]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB4_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -635,7 +635,7 @@ define amdgpu_ps <2 x float> @global_max_saddr_i64_rtn_neg128(ptr addrspace(1) i
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v6, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB5_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -650,7 +650,7 @@ define amdgpu_ps <2 x float> @global_max_saddr_i64_rtn_neg128(ptr addrspace(1) i
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[9:10]
-; GFX11-NEXT: s_waitcnt_depctr 0xfffd
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX11-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_b64 exec, exec, s[0:1]
@@ -675,7 +675,7 @@ define amdgpu_ps <2 x float> @global_max_saddr_i64_rtn_neg128(ptr addrspace(1) i
; GFX12-NEXT: v_mov_b32_e32 v9, v3
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_cmp_gt_i64_e32 vcc, v[9:10], v[1:2]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v8, v2, v10, vcc
; GFX12-NEXT: v_cndmask_b32_e32 v7, v1, v9, vcc
; GFX12-NEXT: global_wb scope:SCOPE_SYS
@@ -684,9 +684,9 @@ define amdgpu_ps <2 x float> @global_max_saddr_i64_rtn_neg128(ptr addrspace(1) i
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[9:10]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB5_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -761,7 +761,7 @@ define amdgpu_ps void @global_max_saddr_i64_nortn(ptr addrspace(1) inreg %sbase,
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v8, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB6_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -773,7 +773,7 @@ define amdgpu_ps void @global_max_saddr_i64_nortn(ptr addrspace(1) inreg %sbase,
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[5:6]
-; GFX11-NEXT: s_waitcnt_depctr 0xfffd
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX11-NEXT: v_mov_b32_e32 v6, v4
; GFX11-NEXT: v_mov_b32_e32 v5, v3
; GFX11-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
@@ -794,7 +794,7 @@ define amdgpu_ps void @global_max_saddr_i64_nortn(ptr addrspace(1) inreg %sbase,
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_cmp_gt_i64_e32 vcc, v[5:6], v[1:2]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX12-NEXT: v_cndmask_b32_e32 v3, v1, v5, vcc
; GFX12-NEXT: global_wb scope:SCOPE_SYS
@@ -805,9 +805,9 @@ define amdgpu_ps void @global_max_saddr_i64_nortn(ptr addrspace(1) inreg %sbase,
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[5:6]
; GFX12-NEXT: v_mov_b32_e32 v6, v4
; GFX12-NEXT: v_mov_b32_e32 v5, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB6_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -876,7 +876,7 @@ define amdgpu_ps void @global_max_saddr_i64_nortn_neg128(ptr addrspace(1) inreg
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v8, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB7_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -888,7 +888,7 @@ define amdgpu_ps void @global_max_saddr_i64_nortn_neg128(ptr addrspace(1) inreg
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[5:6]
-; GFX11-NEXT: s_waitcnt_depctr 0xfffd
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX11-NEXT: v_mov_b32_e32 v6, v4
; GFX11-NEXT: v_mov_b32_e32 v5, v3
; GFX11-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
@@ -909,7 +909,7 @@ define amdgpu_ps void @global_max_saddr_i64_nortn_neg128(ptr addrspace(1) inreg
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_cmp_gt_i64_e32 vcc, v[5:6], v[1:2]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX12-NEXT: v_cndmask_b32_e32 v3, v1, v5, vcc
; GFX12-NEXT: global_wb scope:SCOPE_SYS
@@ -920,9 +920,9 @@ define amdgpu_ps void @global_max_saddr_i64_nortn_neg128(ptr addrspace(1) inreg
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[5:6]
; GFX12-NEXT: v_mov_b32_e32 v6, v4
; GFX12-NEXT: v_mov_b32_e32 v5, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB7_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -995,7 +995,7 @@ define amdgpu_ps float @global_min_saddr_i32_rtn(ptr addrspace(1) inreg %sbase,
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB8_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -1035,9 +1035,9 @@ define amdgpu_ps float @global_min_saddr_i32_rtn(ptr addrspace(1) inreg %sbase,
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc, v0, v5
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB8_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1108,7 +1108,7 @@ define amdgpu_ps float @global_min_saddr_i32_rtn_neg128(ptr addrspace(1) inreg %
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB9_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -1148,9 +1148,9 @@ define amdgpu_ps float @global_min_saddr_i32_rtn_neg128(ptr addrspace(1) inreg %
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc, v0, v5
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB9_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1217,7 +1217,7 @@ define amdgpu_ps void @global_min_saddr_i32_nortn(ptr addrspace(1) inreg %sbase,
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB10_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -1253,9 +1253,9 @@ define amdgpu_ps void @global_min_saddr_i32_nortn(ptr addrspace(1) inreg %sbase,
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc, v0, v5
; GFX12-NEXT: v_mov_b32_e32 v5, v0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB10_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1318,7 +1318,7 @@ define amdgpu_ps void @global_min_saddr_i32_nortn_neg128(ptr addrspace(1) inreg
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB11_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -1354,9 +1354,9 @@ define amdgpu_ps void @global_min_saddr_i32_nortn_neg128(ptr addrspace(1) inreg
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc, v0, v5
; GFX12-NEXT: v_mov_b32_e32 v5, v0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB11_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1432,7 +1432,7 @@ define amdgpu_ps <2 x float> @global_min_saddr_i64_rtn(ptr addrspace(1) inreg %s
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v6, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB12_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -1447,7 +1447,7 @@ define amdgpu_ps <2 x float> @global_min_saddr_i64_rtn(ptr addrspace(1) inreg %s
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[9:10]
-; GFX11-NEXT: s_waitcnt_depctr 0xfffd
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX11-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_b64 exec, exec, s[0:1]
@@ -1472,7 +1472,7 @@ define amdgpu_ps <2 x float> @global_min_saddr_i64_rtn(ptr addrspace(1) inreg %s
; GFX12-NEXT: v_mov_b32_e32 v9, v3
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_cmp_le_i64_e32 vcc, v[9:10], v[1:2]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v8, v2, v10, vcc
; GFX12-NEXT: v_cndmask_b32_e32 v7, v1, v9, vcc
; GFX12-NEXT: global_wb scope:SCOPE_SYS
@@ -1481,9 +1481,9 @@ define amdgpu_ps <2 x float> @global_min_saddr_i64_rtn(ptr addrspace(1) inreg %s
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[9:10]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB12_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1563,7 +1563,7 @@ define amdgpu_ps <2 x float> @global_min_saddr_i64_rtn_neg128(ptr addrspace(1) i
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v6, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB13_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -1578,7 +1578,7 @@ define amdgpu_ps <2 x float> @global_min_saddr_i64_rtn_neg128(ptr addrspace(1) i
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[9:10]
-; GFX11-NEXT: s_waitcnt_depctr 0xfffd
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX11-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_b64 exec, exec, s[0:1]
@@ -1603,7 +1603,7 @@ define amdgpu_ps <2 x float> @global_min_saddr_i64_rtn_neg128(ptr addrspace(1) i
; GFX12-NEXT: v_mov_b32_e32 v9, v3
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_cmp_le_i64_e32 vcc, v[9:10], v[1:2]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v8, v2, v10, vcc
; GFX12-NEXT: v_cndmask_b32_e32 v7, v1, v9, vcc
; GFX12-NEXT: global_wb scope:SCOPE_SYS
@@ -1612,9 +1612,9 @@ define amdgpu_ps <2 x float> @global_min_saddr_i64_rtn_neg128(ptr addrspace(1) i
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[9:10]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB13_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1689,7 +1689,7 @@ define amdgpu_ps void @global_min_saddr_i64_nortn(ptr addrspace(1) inreg %sbase,
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v8, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB14_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -1701,7 +1701,7 @@ define amdgpu_ps void @global_min_saddr_i64_nortn(ptr addrspace(1) inreg %sbase,
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[5:6]
-; GFX11-NEXT: s_waitcnt_depctr 0xfffd
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX11-NEXT: v_mov_b32_e32 v6, v4
; GFX11-NEXT: v_mov_b32_e32 v5, v3
; GFX11-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
@@ -1722,7 +1722,7 @@ define amdgpu_ps void @global_min_saddr_i64_nortn(ptr addrspace(1) inreg %sbase,
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_cmp_le_i64_e32 vcc, v[5:6], v[1:2]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX12-NEXT: v_cndmask_b32_e32 v3, v1, v5, vcc
; GFX12-NEXT: global_wb scope:SCOPE_SYS
@@ -1733,9 +1733,9 @@ define amdgpu_ps void @global_min_saddr_i64_nortn(ptr addrspace(1) inreg %sbase,
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[5:6]
; GFX12-NEXT: v_mov_b32_e32 v6, v4
; GFX12-NEXT: v_mov_b32_e32 v5, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB14_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1804,7 +1804,7 @@ define amdgpu_ps void @global_min_saddr_i64_nortn_neg128(ptr addrspace(1) inreg
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v8, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB15_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -1816,7 +1816,7 @@ define amdgpu_ps void @global_min_saddr_i64_nortn_neg128(ptr addrspace(1) inreg
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[5:6]
-; GFX11-NEXT: s_waitcnt_depctr 0xfffd
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX11-NEXT: v_mov_b32_e32 v6, v4
; GFX11-NEXT: v_mov_b32_e32 v5, v3
; GFX11-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
@@ -1837,7 +1837,7 @@ define amdgpu_ps void @global_min_saddr_i64_nortn_neg128(ptr addrspace(1) inreg
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_cmp_le_i64_e32 vcc, v[5:6], v[1:2]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX12-NEXT: v_cndmask_b32_e32 v3, v1, v5, vcc
; GFX12-NEXT: global_wb scope:SCOPE_SYS
@@ -1848,9 +1848,9 @@ define amdgpu_ps void @global_min_saddr_i64_nortn_neg128(ptr addrspace(1) inreg
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[5:6]
; GFX12-NEXT: v_mov_b32_e32 v6, v4
; GFX12-NEXT: v_mov_b32_e32 v5, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB15_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1923,7 +1923,7 @@ define amdgpu_ps float @global_umax_saddr_i32_rtn(ptr addrspace(1) inreg %sbase,
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB16_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -1963,9 +1963,9 @@ define amdgpu_ps float @global_umax_saddr_i32_rtn(ptr addrspace(1) inreg %sbase,
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc, v0, v5
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB16_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2036,7 +2036,7 @@ define amdgpu_ps float @global_umax_saddr_i32_rtn_neg128(ptr addrspace(1) inreg
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB17_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -2076,9 +2076,9 @@ define amdgpu_ps float @global_umax_saddr_i32_rtn_neg128(ptr addrspace(1) inreg
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc, v0, v5
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB17_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2145,7 +2145,7 @@ define amdgpu_ps void @global_umax_saddr_i32_nortn(ptr addrspace(1) inreg %sbase
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB18_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -2181,9 +2181,9 @@ define amdgpu_ps void @global_umax_saddr_i32_nortn(ptr addrspace(1) inreg %sbase
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc, v0, v5
; GFX12-NEXT: v_mov_b32_e32 v5, v0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB18_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2246,7 +2246,7 @@ define amdgpu_ps void @global_umax_saddr_i32_nortn_neg128(ptr addrspace(1) inreg
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB19_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -2282,9 +2282,9 @@ define amdgpu_ps void @global_umax_saddr_i32_nortn_neg128(ptr addrspace(1) inreg
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc, v0, v5
; GFX12-NEXT: v_mov_b32_e32 v5, v0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB19_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2360,7 +2360,7 @@ define amdgpu_ps <2 x float> @global_umax_saddr_i64_rtn(ptr addrspace(1) inreg %
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v6, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB20_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -2375,7 +2375,7 @@ define amdgpu_ps <2 x float> @global_umax_saddr_i64_rtn(ptr addrspace(1) inreg %
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[9:10]
-; GFX11-NEXT: s_waitcnt_depctr 0xfffd
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX11-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_b64 exec, exec, s[0:1]
@@ -2400,7 +2400,7 @@ define amdgpu_ps <2 x float> @global_umax_saddr_i64_rtn(ptr addrspace(1) inreg %
; GFX12-NEXT: v_mov_b32_e32 v9, v3
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_cmp_gt_u64_e32 vcc, v[9:10], v[1:2]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v8, v2, v10, vcc
; GFX12-NEXT: v_cndmask_b32_e32 v7, v1, v9, vcc
; GFX12-NEXT: global_wb scope:SCOPE_SYS
@@ -2409,9 +2409,9 @@ define amdgpu_ps <2 x float> @global_umax_saddr_i64_rtn(ptr addrspace(1) inreg %
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[9:10]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB20_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2491,7 +2491,7 @@ define amdgpu_ps <2 x float> @global_umax_saddr_i64_rtn_neg128(ptr addrspace(1)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v6, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB21_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -2506,7 +2506,7 @@ define amdgpu_ps <2 x float> @global_umax_saddr_i64_rtn_neg128(ptr addrspace(1)
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[9:10]
-; GFX11-NEXT: s_waitcnt_depctr 0xfffd
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX11-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_b64 exec, exec, s[0:1]
@@ -2531,7 +2531,7 @@ define amdgpu_ps <2 x float> @global_umax_saddr_i64_rtn_neg128(ptr addrspace(1)
; GFX12-NEXT: v_mov_b32_e32 v9, v3
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_cmp_gt_u64_e32 vcc, v[9:10], v[1:2]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v8, v2, v10, vcc
; GFX12-NEXT: v_cndmask_b32_e32 v7, v1, v9, vcc
; GFX12-NEXT: global_wb scope:SCOPE_SYS
@@ -2540,9 +2540,9 @@ define amdgpu_ps <2 x float> @global_umax_saddr_i64_rtn_neg128(ptr addrspace(1)
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[9:10]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB21_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2617,7 +2617,7 @@ define amdgpu_ps void @global_umax_saddr_i64_nortn(ptr addrspace(1) inreg %sbase
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v8, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB22_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -2629,7 +2629,7 @@ define amdgpu_ps void @global_umax_saddr_i64_nortn(ptr addrspace(1) inreg %sbase
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[5:6]
-; GFX11-NEXT: s_waitcnt_depctr 0xfffd
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX11-NEXT: v_mov_b32_e32 v6, v4
; GFX11-NEXT: v_mov_b32_e32 v5, v3
; GFX11-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
@@ -2650,7 +2650,7 @@ define amdgpu_ps void @global_umax_saddr_i64_nortn(ptr addrspace(1) inreg %sbase
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_cmp_gt_u64_e32 vcc, v[5:6], v[1:2]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX12-NEXT: v_cndmask_b32_e32 v3, v1, v5, vcc
; GFX12-NEXT: global_wb scope:SCOPE_SYS
@@ -2661,9 +2661,9 @@ define amdgpu_ps void @global_umax_saddr_i64_nortn(ptr addrspace(1) inreg %sbase
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[5:6]
; GFX12-NEXT: v_mov_b32_e32 v6, v4
; GFX12-NEXT: v_mov_b32_e32 v5, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB22_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2732,7 +2732,7 @@ define amdgpu_ps void @global_umax_saddr_i64_nortn_neg128(ptr addrspace(1) inreg
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v8, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB23_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -2744,7 +2744,7 @@ define amdgpu_ps void @global_umax_saddr_i64_nortn_neg128(ptr addrspace(1) inreg
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[5:6]
-; GFX11-NEXT: s_waitcnt_depctr 0xfffd
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX11-NEXT: v_mov_b32_e32 v6, v4
; GFX11-NEXT: v_mov_b32_e32 v5, v3
; GFX11-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
@@ -2765,7 +2765,7 @@ define amdgpu_ps void @global_umax_saddr_i64_nortn_neg128(ptr addrspace(1) inreg
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_cmp_gt_u64_e32 vcc, v[5:6], v[1:2]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX12-NEXT: v_cndmask_b32_e32 v3, v1, v5, vcc
; GFX12-NEXT: global_wb scope:SCOPE_SYS
@@ -2776,9 +2776,9 @@ define amdgpu_ps void @global_umax_saddr_i64_nortn_neg128(ptr addrspace(1) inreg
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[5:6]
; GFX12-NEXT: v_mov_b32_e32 v6, v4
; GFX12-NEXT: v_mov_b32_e32 v5, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB23_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2851,7 +2851,7 @@ define amdgpu_ps float @global_umin_saddr_i32_rtn(ptr addrspace(1) inreg %sbase,
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB24_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -2891,9 +2891,9 @@ define amdgpu_ps float @global_umin_saddr_i32_rtn(ptr addrspace(1) inreg %sbase,
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc, v0, v5
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB24_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2964,7 +2964,7 @@ define amdgpu_ps float @global_umin_saddr_i32_rtn_neg128(ptr addrspace(1) inreg
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB25_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -3004,9 +3004,9 @@ define amdgpu_ps float @global_umin_saddr_i32_rtn_neg128(ptr addrspace(1) inreg
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc, v0, v5
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB25_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3073,7 +3073,7 @@ define amdgpu_ps void @global_umin_saddr_i32_nortn(ptr addrspace(1) inreg %sbase
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB26_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -3109,9 +3109,9 @@ define amdgpu_ps void @global_umin_saddr_i32_nortn(ptr addrspace(1) inreg %sbase
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc, v0, v5
; GFX12-NEXT: v_mov_b32_e32 v5, v0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB26_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3174,7 +3174,7 @@ define amdgpu_ps void @global_umin_saddr_i32_nortn_neg128(ptr addrspace(1) inreg
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -3210,9 +3210,9 @@ define amdgpu_ps void @global_umin_saddr_i32_nortn_neg128(ptr addrspace(1) inreg
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc, v0, v5
; GFX12-NEXT: v_mov_b32_e32 v5, v0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3288,7 +3288,7 @@ define amdgpu_ps <2 x float> @global_umin_saddr_i64_rtn(ptr addrspace(1) inreg %
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v6, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB28_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -3303,7 +3303,7 @@ define amdgpu_ps <2 x float> @global_umin_saddr_i64_rtn(ptr addrspace(1) inreg %
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[9:10]
-; GFX11-NEXT: s_waitcnt_depctr 0xfffd
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX11-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_b64 exec, exec, s[0:1]
@@ -3328,7 +3328,7 @@ define amdgpu_ps <2 x float> @global_umin_saddr_i64_rtn(ptr addrspace(1) inreg %
; GFX12-NEXT: v_mov_b32_e32 v9, v3
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_cmp_le_u64_e32 vcc, v[9:10], v[1:2]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v8, v2, v10, vcc
; GFX12-NEXT: v_cndmask_b32_e32 v7, v1, v9, vcc
; GFX12-NEXT: global_wb scope:SCOPE_SYS
@@ -3337,9 +3337,9 @@ define amdgpu_ps <2 x float> @global_umin_saddr_i64_rtn(ptr addrspace(1) inreg %
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[9:10]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB28_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3419,7 +3419,7 @@ define amdgpu_ps <2 x float> @global_umin_saddr_i64_rtn_neg128(ptr addrspace(1)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v6, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB29_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -3434,7 +3434,7 @@ define amdgpu_ps <2 x float> @global_umin_saddr_i64_rtn_neg128(ptr addrspace(1)
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[9:10]
-; GFX11-NEXT: s_waitcnt_depctr 0xfffd
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX11-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_b64 exec, exec, s[0:1]
@@ -3459,7 +3459,7 @@ define amdgpu_ps <2 x float> @global_umin_saddr_i64_rtn_neg128(ptr addrspace(1)
; GFX12-NEXT: v_mov_b32_e32 v9, v3
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_cmp_le_u64_e32 vcc, v[9:10], v[1:2]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v8, v2, v10, vcc
; GFX12-NEXT: v_cndmask_b32_e32 v7, v1, v9, vcc
; GFX12-NEXT: global_wb scope:SCOPE_SYS
@@ -3468,9 +3468,9 @@ define amdgpu_ps <2 x float> @global_umin_saddr_i64_rtn_neg128(ptr addrspace(1)
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[9:10]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB29_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3545,7 +3545,7 @@ define amdgpu_ps void @global_umin_saddr_i64_nortn(ptr addrspace(1) inreg %sbase
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v8, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB30_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -3557,7 +3557,7 @@ define amdgpu_ps void @global_umin_saddr_i64_nortn(ptr addrspace(1) inreg %sbase
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[5:6]
-; GFX11-NEXT: s_waitcnt_depctr 0xfffd
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX11-NEXT: v_mov_b32_e32 v6, v4
; GFX11-NEXT: v_mov_b32_e32 v5, v3
; GFX11-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
@@ -3578,7 +3578,7 @@ define amdgpu_ps void @global_umin_saddr_i64_nortn(ptr addrspace(1) inreg %sbase
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_cmp_le_u64_e32 vcc, v[5:6], v[1:2]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX12-NEXT: v_cndmask_b32_e32 v3, v1, v5, vcc
; GFX12-NEXT: global_wb scope:SCOPE_SYS
@@ -3589,9 +3589,9 @@ define amdgpu_ps void @global_umin_saddr_i64_nortn(ptr addrspace(1) inreg %sbase
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[5:6]
; GFX12-NEXT: v_mov_b32_e32 v6, v4
; GFX12-NEXT: v_mov_b32_e32 v5, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB30_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3660,7 +3660,7 @@ define amdgpu_ps void @global_umin_saddr_i64_nortn_neg128(ptr addrspace(1) inreg
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v8, null, s3, 0, s[0:1]
; GFX11-NEXT: s_mov_b64 s[0:1], 0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffe
+; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX11-NEXT: .LBB31_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
@@ -3672,7 +3672,7 @@ define amdgpu_ps void @global_umin_saddr_i64_nortn_neg128(ptr addrspace(1) inreg
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
; GFX11-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[5:6]
-; GFX11-NEXT: s_waitcnt_depctr 0xfffd
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX11-NEXT: v_mov_b32_e32 v6, v4
; GFX11-NEXT: v_mov_b32_e32 v5, v3
; GFX11-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
@@ -3693,7 +3693,7 @@ define amdgpu_ps void @global_umin_saddr_i64_nortn_neg128(ptr addrspace(1) inreg
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_cmp_le_u64_e32 vcc, v[5:6], v[1:2]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX12-NEXT: v_cndmask_b32_e32 v3, v1, v5, vcc
; GFX12-NEXT: global_wb scope:SCOPE_SYS
@@ -3704,9 +3704,9 @@ define amdgpu_ps void @global_umin_saddr_i64_nortn_neg128(ptr addrspace(1) inreg
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[5:6]
; GFX12-NEXT: v_mov_b32_e32 v6, v4
; GFX12-NEXT: v_mov_b32_e32 v5, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b64 exec, exec, s[0:1]
; GFX12-NEXT: s_cbranch_execnz .LBB31_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
diff --git a/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll b/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
index 9ebf6ae88a517..890ebddf36801 100644
--- a/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
@@ -4743,7 +4743,7 @@ define amdgpu_ps void @global_addr_64bit_lsr_iv(ptr addrspace(1) inreg %arg) {
; GFX10-NEXT: s_mov_b64 s[0:1], 0
; GFX10-NEXT: .LBB132_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_add_u32 s4, s2, s0
; GFX10-NEXT: s_addc_u32 s5, s3, s1
; GFX10-NEXT: s_add_u32 s0, s0, 4
@@ -4800,10 +4800,10 @@ define amdgpu_ps void @global_addr_64bit_lsr_iv(ptr addrspace(1) inreg %arg) {
; GFX12-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-GISEL-NEXT: v_add_co_u32 v4, vcc, v0, v2
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v1, v3, vcc
; GFX12-GISEL-NEXT: v_add_co_u32 v2, vcc, v2, 4
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc
; GFX12-GISEL-NEXT: global_load_b32 v4, v[4:5], off scope:SCOPE_SYS
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
@@ -4856,7 +4856,7 @@ define amdgpu_ps void @global_addr_64bit_lsr_iv_multiload(ptr addrspace(1) inreg
; GFX10-NEXT: s_mov_b64 s[0:1], 0
; GFX10-NEXT: .LBB133_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_add_u32 s4, s2, s0
; GFX10-NEXT: s_addc_u32 s5, s3, s1
; GFX10-NEXT: s_add_u32 s0, s0, 4
@@ -4920,10 +4920,10 @@ define amdgpu_ps void @global_addr_64bit_lsr_iv_multiload(ptr addrspace(1) inreg
; GFX12-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-GISEL-NEXT: v_add_co_u32 v4, vcc, v0, v2
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v1, v3, vcc
; GFX12-GISEL-NEXT: v_add_co_u32 v2, vcc, v2, 4
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc
; GFX12-GISEL-NEXT: global_load_b32 v6, v[4:5], off scope:SCOPE_SYS
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
index 483880bd9f4b0..daa053ceea161 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
@@ -194,7 +194,7 @@ define amdgpu_kernel void @atomic_add_i64_addr64_offset(ptr addrspace(1) %out, i
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: s_lshl_b64 s[2:3], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GFX12-NEXT: global_atomic_add_u64 v2, v[0:1], s[0:1] offset:32 scope:SCOPE_DEV
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -275,7 +275,7 @@ define amdgpu_kernel void @atomic_add_i64_ret_addr64_offset(ptr addrspace(1) %ou
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5]
; GFX12-NEXT: global_atomic_add_u64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -480,7 +480,7 @@ define amdgpu_kernel void @atomic_add_i64_addr64(ptr addrspace(1) %out, i64 %in,
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: s_lshl_b64 s[2:3], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GFX12-NEXT: global_atomic_add_u64 v2, v[0:1], s[0:1] scope:SCOPE_DEV
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -558,7 +558,7 @@ define amdgpu_kernel void @atomic_add_i64_ret_addr64(ptr addrspace(1) %out, ptr
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5]
; GFX12-NEXT: global_atomic_add_u64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -762,7 +762,7 @@ define amdgpu_kernel void @atomic_and_i64_addr64_offset(ptr addrspace(1) %out, i
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: s_lshl_b64 s[2:3], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GFX12-NEXT: global_atomic_and_b64 v2, v[0:1], s[0:1] offset:32 scope:SCOPE_DEV
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -843,7 +843,7 @@ define amdgpu_kernel void @atomic_and_i64_ret_addr64_offset(ptr addrspace(1) %ou
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5]
; GFX12-NEXT: global_atomic_and_b64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -1048,7 +1048,7 @@ define amdgpu_kernel void @atomic_and_i64_addr64(ptr addrspace(1) %out, i64 %in,
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: s_lshl_b64 s[2:3], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GFX12-NEXT: global_atomic_and_b64 v2, v[0:1], s[0:1] scope:SCOPE_DEV
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -1126,7 +1126,7 @@ define amdgpu_kernel void @atomic_and_i64_ret_addr64(ptr addrspace(1) %out, ptr
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5]
; GFX12-NEXT: global_atomic_and_b64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -1330,7 +1330,7 @@ define amdgpu_kernel void @atomic_sub_i64_addr64_offset(ptr addrspace(1) %out, i
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: s_lshl_b64 s[2:3], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GFX12-NEXT: global_atomic_sub_u64 v2, v[0:1], s[0:1] offset:32 scope:SCOPE_DEV
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -1411,7 +1411,7 @@ define amdgpu_kernel void @atomic_sub_i64_ret_addr64_offset(ptr addrspace(1) %ou
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5]
; GFX12-NEXT: global_atomic_sub_u64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -1616,7 +1616,7 @@ define amdgpu_kernel void @atomic_sub_i64_addr64(ptr addrspace(1) %out, i64 %in,
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: s_lshl_b64 s[2:3], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GFX12-NEXT: global_atomic_sub_u64 v2, v[0:1], s[0:1] scope:SCOPE_DEV
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -1694,7 +1694,7 @@ define amdgpu_kernel void @atomic_sub_i64_ret_addr64(ptr addrspace(1) %out, ptr
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5]
; GFX12-NEXT: global_atomic_sub_u64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -1883,7 +1883,7 @@ define amdgpu_kernel void @atomic_max_i64_addr64_offset(ptr addrspace(1) %out, i
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: s_lshl_b64 s[2:3], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GFX12-NEXT: global_atomic_max_i64 v2, v[0:1], s[0:1] offset:32 scope:SCOPE_SE
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -1961,7 +1961,7 @@ define amdgpu_kernel void @atomic_max_i64_ret_addr64_offset(ptr addrspace(1) %ou
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5]
; GFX12-NEXT: global_atomic_max_i64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN scope:SCOPE_SE
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -2151,7 +2151,7 @@ define amdgpu_kernel void @atomic_max_i64_addr64(ptr addrspace(1) %out, i64 %in,
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: s_lshl_b64 s[2:3], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GFX12-NEXT: global_atomic_max_i64 v2, v[0:1], s[0:1] scope:SCOPE_SE
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -2226,7 +2226,7 @@ define amdgpu_kernel void @atomic_max_i64_ret_addr64(ptr addrspace(1) %out, ptr
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5]
; GFX12-NEXT: global_atomic_max_i64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_SE
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -2415,7 +2415,7 @@ define amdgpu_kernel void @atomic_umax_i64_addr64_offset(ptr addrspace(1) %out,
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: s_lshl_b64 s[2:3], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GFX12-NEXT: global_atomic_max_u64 v2, v[0:1], s[0:1] offset:32 scope:SCOPE_SE
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -2493,7 +2493,7 @@ define amdgpu_kernel void @atomic_umax_i64_ret_addr64_offset(ptr addrspace(1) %o
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5]
; GFX12-NEXT: global_atomic_max_u64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN scope:SCOPE_SE
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -2683,7 +2683,7 @@ define amdgpu_kernel void @atomic_umax_i64_addr64(ptr addrspace(1) %out, i64 %in
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: s_lshl_b64 s[2:3], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GFX12-NEXT: global_atomic_max_u64 v2, v[0:1], s[0:1] scope:SCOPE_SE
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -2758,7 +2758,7 @@ define amdgpu_kernel void @atomic_umax_i64_ret_addr64(ptr addrspace(1) %out, ptr
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5]
; GFX12-NEXT: global_atomic_max_u64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_SE
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -2947,7 +2947,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64_offset(ptr addrspace(1) %out, i
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: s_lshl_b64 s[2:3], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GFX12-NEXT: global_atomic_min_i64 v2, v[0:1], s[0:1] offset:32 scope:SCOPE_SE
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -3025,7 +3025,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(ptr addrspace(1) %ou
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5]
; GFX12-NEXT: global_atomic_min_i64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN scope:SCOPE_SE
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -3215,7 +3215,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64(ptr addrspace(1) %out, i64 %in,
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: s_lshl_b64 s[2:3], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GFX12-NEXT: global_atomic_min_i64 v2, v[0:1], s[0:1] scope:SCOPE_SE
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -3290,7 +3290,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64(ptr addrspace(1) %out, ptr
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5]
; GFX12-NEXT: global_atomic_min_i64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_SE
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -3479,7 +3479,7 @@ define amdgpu_kernel void @atomic_umin_i64_addr64_offset(ptr addrspace(1) %out,
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: s_lshl_b64 s[2:3], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GFX12-NEXT: global_atomic_min_u64 v2, v[0:1], s[0:1] offset:32 scope:SCOPE_SE
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -3557,7 +3557,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret_addr64_offset(ptr addrspace(1) %o
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5]
; GFX12-NEXT: global_atomic_min_u64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN scope:SCOPE_SE
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -3747,7 +3747,7 @@ define amdgpu_kernel void @atomic_umin_i64_addr64(ptr addrspace(1) %out, i64 %in
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: s_lshl_b64 s[2:3], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GFX12-NEXT: global_atomic_min_u64 v2, v[0:1], s[0:1] scope:SCOPE_SE
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -3822,7 +3822,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret_addr64(ptr addrspace(1) %out, ptr
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5]
; GFX12-NEXT: global_atomic_min_u64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_SE
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -4026,7 +4026,7 @@ define amdgpu_kernel void @atomic_or_i64_addr64_offset(ptr addrspace(1) %out, i6
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: s_lshl_b64 s[2:3], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GFX12-NEXT: global_atomic_or_b64 v2, v[0:1], s[0:1] offset:32 scope:SCOPE_DEV
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -4107,7 +4107,7 @@ define amdgpu_kernel void @atomic_or_i64_ret_addr64_offset(ptr addrspace(1) %out
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5]
; GFX12-NEXT: global_atomic_or_b64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -4312,7 +4312,7 @@ define amdgpu_kernel void @atomic_or_i64_addr64(ptr addrspace(1) %out, i64 %in,
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: s_lshl_b64 s[2:3], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GFX12-NEXT: global_atomic_or_b64 v2, v[0:1], s[0:1] scope:SCOPE_DEV
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -4390,7 +4390,7 @@ define amdgpu_kernel void @atomic_or_i64_ret_addr64(ptr addrspace(1) %out, ptr a
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5]
; GFX12-NEXT: global_atomic_or_b64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -4704,7 +4704,7 @@ define amdgpu_kernel void @atomic_xchg_i64_addr64_offset(ptr addrspace(1) %out,
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: s_lshl_b64 s[2:3], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GFX12-NEXT: global_atomic_swap_b64 v2, v[0:1], s[0:1] offset:32 scope:SCOPE_DEV
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -4785,7 +4785,7 @@ define amdgpu_kernel void @atomic_xchg_i64_ret_addr64_offset(ptr addrspace(1) %o
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5]
; GFX12-NEXT: global_atomic_swap_b64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -4990,7 +4990,7 @@ define amdgpu_kernel void @atomic_xchg_i64_addr64(ptr addrspace(1) %out, i64 %in
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: s_lshl_b64 s[2:3], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GFX12-NEXT: global_atomic_swap_b64 v2, v[0:1], s[0:1] scope:SCOPE_DEV
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -5068,7 +5068,7 @@ define amdgpu_kernel void @atomic_xchg_i64_ret_addr64(ptr addrspace(1) %out, ptr
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5]
; GFX12-NEXT: global_atomic_swap_b64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -5272,7 +5272,7 @@ define amdgpu_kernel void @atomic_xor_i64_addr64_offset(ptr addrspace(1) %out, i
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: s_lshl_b64 s[2:3], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GFX12-NEXT: global_atomic_xor_b64 v2, v[0:1], s[0:1] offset:32 scope:SCOPE_DEV
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -5353,7 +5353,7 @@ define amdgpu_kernel void @atomic_xor_i64_ret_addr64_offset(ptr addrspace(1) %ou
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5]
; GFX12-NEXT: global_atomic_xor_b64 v[0:1], v2, v[0:1], s[0:1] offset:32 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -5558,7 +5558,7 @@ define amdgpu_kernel void @atomic_xor_i64_addr64(ptr addrspace(1) %out, i64 %in,
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: s_lshl_b64 s[2:3], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GFX12-NEXT: global_atomic_xor_b64 v2, v[0:1], s[0:1] scope:SCOPE_DEV
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -5636,7 +5636,7 @@ define amdgpu_kernel void @atomic_xor_i64_ret_addr64(ptr addrspace(1) %out, ptr
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: s_lshl_b64 s[4:5], s[6:7], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5]
; GFX12-NEXT: global_atomic_xor_b64 v[0:1], v2, v[0:1], s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -5935,7 +5935,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_addr64_offset(ptr addrspace(1) %ou
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v3, s7
; GFX12-NEXT: v_mov_b32_e32 v2, s6
; GFX12-NEXT: s_lshl_b64 s[2:3], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GFX12-NEXT: global_atomic_cmpswap_b64 v4, v[0:3], s[0:1] offset:32 scope:SCOPE_DEV
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -6028,7 +6028,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64_offset(ptr addrspace(1)
; GFX12-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v3, s1
; GFX12-NEXT: v_mov_b32_e32 v2, s0
; GFX12-NEXT: s_lshl_b64 s[0:1], s[14:15], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[8:9], s[0:1]
; GFX12-NEXT: global_atomic_cmpswap_b64 v[0:1], v4, v[0:3], s[0:1] offset:32 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -6252,7 +6252,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_addr64(ptr addrspace(1) %out, i64
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v3, s7
; GFX12-NEXT: v_mov_b32_e32 v2, s6
; GFX12-NEXT: s_lshl_b64 s[2:3], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GFX12-NEXT: global_atomic_cmpswap_b64 v4, v[0:3], s[0:1] scope:SCOPE_DEV
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -6342,7 +6342,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64(ptr addrspace(1) %out,
; GFX12-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v3, s1
; GFX12-NEXT: v_mov_b32_e32 v2, s0
; GFX12-NEXT: s_lshl_b64 s[0:1], s[14:15], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[8:9], s[0:1]
; GFX12-NEXT: global_atomic_cmpswap_b64 v[0:1], v4, v[0:3], s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-NEXT: s_wait_loadcnt 0x0
@@ -6945,7 +6945,7 @@ define amdgpu_kernel void @atomic_store_i64_addr64_offset(i64 %in, ptr addrspace
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-NEXT: s_lshl_b64 s[0:1], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1]
; GFX12-NEXT: global_wb scope:SCOPE_SYS
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -7013,7 +7013,7 @@ define amdgpu_kernel void @atomic_store_i64_addr64(i64 %in, ptr addrspace(1) %ou
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-NEXT: s_lshl_b64 s[0:1], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1]
; GFX12-NEXT: global_wb scope:SCOPE_SYS
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -7082,7 +7082,7 @@ define amdgpu_kernel void @atomic_store_f64_addr64_offset(double %in, ptr addrsp
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-NEXT: s_lshl_b64 s[0:1], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1]
; GFX12-NEXT: global_wb scope:SCOPE_SYS
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -7285,7 +7285,7 @@ define amdgpu_kernel void @atomic_inc_i64_incr64_offset(ptr addrspace(1) %out, i
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: s_lshl_b64 s[2:3], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GFX12-NEXT: global_atomic_inc_u64 v2, v[0:1], s[0:1] offset:32 scope:SCOPE_DEV
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -7488,7 +7488,7 @@ define amdgpu_kernel void @atomic_dec_i64_decr64_offset(ptr addrspace(1) %out, i
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: s_lshl_b64 s[2:3], s[4:5], 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; GFX12-NEXT: global_atomic_dec_u64 v2, v[0:1], s[0:1] offset:32 scope:SCOPE_DEV
; GFX12-NEXT: s_wait_storecnt 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
index 31f277f73099b..a6a886dc321ce 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
@@ -1051,7 +1051,7 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_add_f32_e32 v1, v1, v2
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -2264,7 +2264,7 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_one_as_scope
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_add_f32_e32 v1, v1, v2
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -3537,7 +3537,7 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_add_f32_e32 v1, v1, v2
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -4306,7 +4306,7 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_agent_scope_
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_add_f32_e32 v1, v1, v2
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -5604,7 +5604,7 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_div_value_default_scop
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_add_f32_e32 v1, v1, v2
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -6936,7 +6936,7 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
@@ -8363,7 +8363,7 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_one_a
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
@@ -9790,7 +9790,7 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
@@ -10699,7 +10699,7 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_agent
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
@@ -12126,7 +12126,7 @@ define amdgpu_kernel void @global_atomic_fadd_double_uni_address_div_value_defau
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
index ff4b658606390..e62d6c593215b 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
@@ -963,7 +963,7 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_agent_scope_
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_max_f32_e32 v1, v1, v2
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -1996,7 +1996,7 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_one_as_scope
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_max_f32_e32 v1, v1, v2
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -3029,7 +3029,7 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_div_value_default_scop
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_max_f32_e32 v1, v1, v2
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -4252,7 +4252,7 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_agent
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
@@ -5516,7 +5516,7 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_one_a
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
@@ -6780,7 +6780,7 @@ define amdgpu_kernel void @global_atomic_fmax_double_uni_address_div_value_defau
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
index 15d4b9a84f3f8..1c14ff65dcbb6 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
@@ -963,7 +963,7 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_agent_scope_
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_min_f32_e32 v1, v1, v2
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -1996,7 +1996,7 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_one_as_scope
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_min_f32_e32 v1, v1, v2
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -3029,7 +3029,7 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_div_value_default_scop
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_min_f32_e32 v1, v1, v2
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -4252,7 +4252,7 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_agent
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
@@ -5516,7 +5516,7 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_one_a
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
@@ -6780,7 +6780,7 @@ define amdgpu_kernel void @global_atomic_fmin_double_uni_address_div_value_defau
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
index 1f2d70c931e73..b97c3cdf32d12 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
@@ -1137,7 +1137,7 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_add_f32_e32 v1, v1, v2
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -2462,7 +2462,7 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_one_as_scope
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_add_f32_e32 v1, v1, v2
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -3787,7 +3787,7 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_add_f32_e32 v1, v1, v2
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -4608,7 +4608,7 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_agent_scope_
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_add_f32_e32 v1, v1, v2
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -5932,7 +5932,7 @@ define amdgpu_kernel void @global_atomic_fsub_uni_address_div_value_default_scop
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: s_or_saveexec_b64 s[0:1], -1
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_add_f32_e32 v1, v1, v2
; GFX1164-DPP-NEXT: s_mov_b64 exec, s[0:1]
; GFX1164-DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -7264,7 +7264,7 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
@@ -8690,7 +8690,7 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_one_a
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
@@ -10117,7 +10117,7 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
@@ -11026,7 +11026,7 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_agent
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
@@ -12452,7 +12452,7 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_defau
; GFX1164-DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
; GFX1164-DPP-NEXT: v_mov_b32_e32 v10, 0
; GFX1164-DPP-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164-DPP-NEXT: s_waitcnt_depctr 0xfffe
+; GFX1164-DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; GFX1164-DPP-NEXT: v_mbcnt_hi_u32_b32 v6, exec_hi, v0
; GFX1164-DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1164-DPP-NEXT: v_mov_b32_e32 v0, v2
diff --git a/llvm/test/CodeGen/AMDGPU/hazards-gfx1250.mir b/llvm/test/CodeGen/AMDGPU/hazards-gfx1250.mir
index 170478539d8a9..0aea3afccc406 100644
--- a/llvm/test/CodeGen/AMDGPU/hazards-gfx1250.mir
+++ b/llvm/test/CodeGen/AMDGPU/hazards-gfx1250.mir
@@ -26,7 +26,7 @@ body: |
; GCN: liveins: $vgpr0
; GCN-NEXT: {{ $}}
; GCN-NEXT: $sgpr102 = S_MOV_B32 0
- ; GCN-NEXT: S_WAITCNT_DEPCTR 61950
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 61854
; GCN-NEXT: $vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_lo, $vgpr0, implicit $exec
$sgpr102 = S_MOV_B32 0
$vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_lo, $vgpr0, implicit $exec
@@ -42,7 +42,7 @@ body: |
; GCN: liveins: $vgpr0
; GCN-NEXT: {{ $}}
; GCN-NEXT: $sgpr103 = S_MOV_B32 0
- ; GCN-NEXT: S_WAITCNT_DEPCTR 61950
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 61854
; GCN-NEXT: $vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_hi, $vgpr0, implicit $exec
$sgpr103 = S_MOV_B32 0
$vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_hi, $vgpr0, implicit $exec
@@ -55,7 +55,7 @@ body: |
bb.0:
; GCN-LABEL: name: write_s102_read_flat_scr_base
; GCN: $sgpr102 = S_MOV_B32 0
- ; GCN-NEXT: S_WAITCNT_DEPCTR 61950
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 61854
; GCN-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $src_flat_scratch_base
$sgpr102 = S_MOV_B32 0
$sgpr0_sgpr1 = S_MOV_B64 $src_flat_scratch_base
@@ -68,7 +68,7 @@ body: |
bb.0:
; GCN-LABEL: name: write_s103_read_flat_scr_base
; GCN: $sgpr103 = S_MOV_B32 0
- ; GCN-NEXT: S_WAITCNT_DEPCTR 61950
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 61854
; GCN-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $src_flat_scratch_base
$sgpr103 = S_MOV_B32 0
$sgpr0_sgpr1 = S_MOV_B64 $src_flat_scratch_base
@@ -81,7 +81,7 @@ body: |
bb.0:
; GCN-LABEL: name: write_s102_s103_read_flat_scr_base
; GCN: $sgpr102_sgpr103 = S_MOV_B64 0
- ; GCN-NEXT: S_WAITCNT_DEPCTR 61950
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 61854
; GCN-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $src_flat_scratch_base
$sgpr102_sgpr103 = S_MOV_B64 0
$sgpr0_sgpr1 = S_MOV_B64 $src_flat_scratch_base
@@ -97,7 +97,7 @@ body: |
; GCN: liveins: $vgpr0
; GCN-NEXT: {{ $}}
; GCN-NEXT: $sgpr102 = S_MOV_B32 0
- ; GCN-NEXT: S_WAITCNT_DEPCTR 61950
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 61854
; GCN-NEXT: $sgpr1 = S_GETREG_B32 20, implicit $mode
$sgpr102 = S_MOV_B32 0
$sgpr1 = S_GETREG_B32 20, implicit $mode
@@ -113,7 +113,7 @@ body: |
; GCN: liveins: $vgpr0
; GCN-NEXT: {{ $}}
; GCN-NEXT: $sgpr103 = S_MOV_B32 0
- ; GCN-NEXT: S_WAITCNT_DEPCTR 61950
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 61854
; GCN-NEXT: $sgpr1 = S_GETREG_B32 21, implicit $mode
$sgpr103 = S_MOV_B32 0
$sgpr1 = S_GETREG_B32 21, implicit $mode
@@ -126,7 +126,7 @@ body: |
bb.0:
; GCN-LABEL: name: write_s102_s103_getreg_flat_scr_base_hi
; GCN: $sgpr102_sgpr103 = S_MOV_B64 0
- ; GCN-NEXT: S_WAITCNT_DEPCTR 61950
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 61854
; GCN-NEXT: $sgpr1 = S_GETREG_B32 21, implicit $mode
$sgpr102_sgpr103 = S_MOV_B64 0
$sgpr1 = S_GETREG_B32 21, implicit $mode
@@ -154,7 +154,7 @@ body: |
; GCN-NEXT: $sgpr6 = S_MOV_B32 0
; GCN-NEXT: $sgpr7 = S_MOV_B32 0
; GCN-NEXT: $sgpr8_sgpr9 = S_LOAD_DWORDX2_IMM renamable $sgpr4_sgpr5, 0, 0
- ; GCN-NEXT: S_WAITCNT_DEPCTR 61950
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 61854
; GCN-NEXT: $vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_lo, $vgpr0, implicit $exec
$sgpr102 = S_MOV_B32 0
$sgpr0 = S_MOV_B32 0
@@ -241,7 +241,7 @@ body: |
; GCN-NEXT: $sgpr6 = S_MOV_B32 0
; GCN-NEXT: $sgpr7 = S_MOV_B32 0
; GCN-NEXT: $sgpr8_sgpr9 = S_LOAD_DWORDX2_IMM renamable $sgpr4_sgpr5, 0, 0
- ; GCN-NEXT: S_WAITCNT_DEPCTR 61950
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 61854
; GCN-NEXT: $vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_hi, $vgpr0, implicit $exec
$sgpr103 = S_MOV_B32 0
$sgpr0 = S_MOV_B32 0
@@ -371,7 +371,7 @@ body: |
; GCN-NEXT: $sgpr102 = S_MOV_B32 0
; GCN-NEXT: S_WAITCNT_DEPCTR 61951
; GCN-NEXT: S_NOP 0
- ; GCN-NEXT: S_WAITCNT_DEPCTR 61950
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 61854
; GCN-NEXT: $vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_lo, $vgpr0, implicit $exec
$sgpr102 = S_MOV_B32 0
S_WAITCNT_DEPCTR 61951
@@ -391,7 +391,7 @@ body: |
; GCN-NEXT: $sgpr102 = S_MOV_B32 0
; GCN-NEXT: S_WAITCNT_DEPCTR 65534
; GCN-NEXT: S_NOP 0
- ; GCN-NEXT: S_WAITCNT_DEPCTR 61950
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 61854
; GCN-NEXT: $vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_lo, $vgpr0, implicit $exec
$sgpr102 = S_MOV_B32 0
S_WAITCNT_DEPCTR 65534
@@ -410,7 +410,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: $sgpr102 = S_MOV_B32 0
; GCN-NEXT: $sgpr103 = S_MOV_B32 0
- ; GCN-NEXT: S_WAITCNT_DEPCTR 61950
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 61854
; GCN-NEXT: $vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_lo, $vgpr0, implicit $exec
; GCN-NEXT: $vgpr1 = V_ADD_U32_e32 $src_flat_scratch_base_hi, $vgpr0, implicit $exec
$sgpr102 = S_MOV_B32 0
@@ -459,7 +459,7 @@ body: |
; GCN-NEXT: bb.2:
; GCN-NEXT: liveins: $vgpr0
; GCN-NEXT: {{ $}}
- ; GCN-NEXT: S_WAITCNT_DEPCTR 61950
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 61854
; GCN-NEXT: $vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_lo, $vgpr0, implicit $exec
bb.0:
liveins: $vgpr0, $sgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll b/llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
index 492bd1b508bc6..86dbb16948ebe 100644
--- a/llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
@@ -77,14 +77,14 @@ define bfloat @v_uitofp_i1_to_bf16(i1 %num) {
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 1, v0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
@@ -100,14 +100,14 @@ define bfloat @v_uitofp_i1_to_bf16(i1 %num) {
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
@@ -179,7 +179,7 @@ define amdgpu_ps i32 @s_uitofp_i1_to_bf16(i1 inreg %num) {
; GFX12-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: ; return to shader part epilog
%op = uitofp i1 %num to bfloat
%b16 = bitcast bfloat %op to i16
@@ -292,12 +292,12 @@ define <2 x bfloat> @v_uitofp_v2i1_to_v2bf16(<2 x i1> %num) {
; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
@@ -306,10 +306,10 @@ define <2 x bfloat> @v_uitofp_v2i1_to_v2bf16(<2 x i1> %num) {
; GFX12-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX12-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
@@ -325,7 +325,7 @@ define <2 x bfloat> @v_uitofp_v2i1_to_v2bf16(<2 x i1> %num) {
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
@@ -333,17 +333,17 @@ define <2 x bfloat> @v_uitofp_v2i1_to_v2bf16(<2 x i1> %num) {
; GFX12-FAKE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-FAKE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
@@ -438,7 +438,7 @@ define amdgpu_ps <2 x i32> @s_uitofp_v2i1_to_v2bf16(<2 x i1> inreg %num) {
; GFX12-NEXT: s_cmp_eq_u32 s1, 1
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s0
; GFX12-NEXT: s_cselect_b32 s0, -1, 0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX12-NEXT: v_bfe_u32 v2, v0, 16, 1
@@ -456,13 +456,13 @@ define amdgpu_ps <2 x i32> @s_uitofp_v2i1_to_v2bf16(<2 x i1> inreg %num) {
; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX12-NEXT: v_readfirstlane_b32 s1, v1
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: ; return to shader part epilog
%op = uitofp <2 x i1> %num to <2 x bfloat>
%b16 = bitcast <2 x bfloat> %op to <2 x i16>
@@ -611,35 +611,35 @@ define <3 x bfloat> @v_uitofp_v3i1_to_v3bf16(<3 x i1> %num) {
; GFX12-TRUE16-NEXT: v_and_b16 v1.l, 1, v1.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
; GFX12-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v1.l
; GFX12-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX12-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -655,12 +655,12 @@ define <3 x bfloat> @v_uitofp_v3i1_to_v3bf16(<3 x i1> %num) {
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
@@ -671,21 +671,21 @@ define <3 x bfloat> @v_uitofp_v3i1_to_v3bf16(<3 x i1> %num) {
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-FAKE16-NEXT: v_bfe_u32 v5, v1, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v1, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_alignbit_b32 v1, s0, v2, 16
@@ -810,11 +810,11 @@ define amdgpu_ps <3 x i32> @s_uitofp_v3i1_to_v3bf16(<3 x i1> inreg %num) {
; GFX12-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s0
; GFX12-NEXT: s_cselect_b32 s1, -1, 0
; GFX12-NEXT: s_cmp_eq_u32 s2, 1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s1
; GFX12-NEXT: s_cselect_b32 s0, -1, 0
; GFX12-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s0
; GFX12-NEXT: v_or_b32_e32 v6, 0x400000, v1
; GFX12-NEXT: v_bfe_u32 v3, v0, 16, 1
@@ -832,20 +832,20 @@ define amdgpu_ps <3 x i32> @s_uitofp_v3i1_to_v3bf16(<3 x i1> inreg %num) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
; GFX12-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-NEXT: v_readfirstlane_b32 s1, v0
; GFX12-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc_lo
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_readfirstlane_b32 s0, v1
; GFX12-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_readfirstlane_b32 s2, v2
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: ; return to shader part epilog
%op = uitofp <3 x i1> %num to <3 x bfloat>
%b16 = bitcast <3 x bfloat> %op to <3 x i16>
@@ -1026,44 +1026,44 @@ define <4 x bfloat> @v_uitofp_v4i1_to_v4bf16(<4 x i1> %num) {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v2.l
; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v9, v0, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v7.h
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1079,12 +1079,12 @@ define <4 x bfloat> @v_uitofp_v4i1_to_v4bf16(<4 x i1> %num) {
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 1, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
@@ -1096,31 +1096,31 @@ define <4 x bfloat> @v_uitofp_v4i1_to_v4bf16(<4 x i1> %num) {
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; GFX12-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX12-FAKE16-NEXT: v_bfe_u32 v8, v1, 16, 1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v8, v1, 0x7fff
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v5, v9, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x7060302
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -1275,14 +1275,14 @@ define amdgpu_ps <4 x i32> @s_uitofp_v4i1_to_v4bf16(<4 x i1> inreg %num) {
; GFX12-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, s0
; GFX12-NEXT: s_cselect_b32 s1, -1, 0
; GFX12-NEXT: s_cmp_eq_u32 s2, 1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s1
; GFX12-NEXT: s_cselect_b32 s2, -1, 0
; GFX12-NEXT: s_cmp_eq_u32 s3, 1
; GFX12-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s2
; GFX12-NEXT: s_cselect_b32 s3, -1, 0
; GFX12-NEXT: v_bfe_u32 v7, v4, 16, 1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s3
; GFX12-NEXT: v_bfe_u32 v6, v3, 16, 1
; GFX12-NEXT: v_bfe_u32 v5, v1, 16, 1
@@ -1304,15 +1304,15 @@ define amdgpu_ps <4 x i32> @s_uitofp_v4i1_to_v4bf16(<4 x i1> inreg %num) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
; GFX12-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v3, v6, v11, vcc_lo
; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-NEXT: v_readfirstlane_b32 s2, v1
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v4, v7, v10, vcc_lo
; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
; GFX12-NEXT: v_lshrrev_b32_e32 v2, 16, v3
; GFX12-NEXT: v_lshrrev_b32_e32 v3, 16, v4
@@ -1322,7 +1322,7 @@ define amdgpu_ps <4 x i32> @s_uitofp_v4i1_to_v4bf16(<4 x i1> inreg %num) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-NEXT: v_readfirstlane_b32 s1, v3
; GFX12-NEXT: v_readfirstlane_b32 s3, v0
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: ; return to shader part epilog
%op = uitofp <4 x i1> %num to <4 x bfloat>
%b16 = bitcast <4 x bfloat> %op to <4 x i16>
@@ -1401,14 +1401,14 @@ define bfloat @v_sitofp_i1_to_bf16(i1 %num) {
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 1, v0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
@@ -1424,14 +1424,14 @@ define bfloat @v_sitofp_i1_to_bf16(i1 %num) {
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
@@ -1503,7 +1503,7 @@ define amdgpu_ps i32 @s_sitofp_i1_to_bf16(i1 inreg %num) {
; GFX12-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: ; return to shader part epilog
%op = sitofp i1 %num to bfloat
%b16 = bitcast bfloat %op to i16
@@ -1616,12 +1616,12 @@ define <2 x bfloat> @v_sitofp_v2i1_to_v2bf16(<2 x i1> %num) {
; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
@@ -1630,10 +1630,10 @@ define <2 x bfloat> @v_sitofp_v2i1_to_v2bf16(<2 x i1> %num) {
; GFX12-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX12-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
@@ -1649,7 +1649,7 @@ define <2 x bfloat> @v_sitofp_v2i1_to_v2bf16(<2 x i1> %num) {
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
@@ -1657,17 +1657,17 @@ define <2 x bfloat> @v_sitofp_v2i1_to_v2bf16(<2 x i1> %num) {
; GFX12-FAKE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-FAKE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
@@ -1763,7 +1763,7 @@ define amdgpu_ps <2 x i32> @s_sitofp_v2i1_to_v2bf16(<2 x i1> inreg %num) {
; GFX12-NEXT: s_cmp_eq_u32 s0, 1
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, s1
; GFX12-NEXT: s_cselect_b32 s0, -1, 0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, s0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-NEXT: v_bfe_u32 v3, v0, 16, 1
@@ -1780,7 +1780,7 @@ define amdgpu_ps <2 x i32> @s_sitofp_v2i1_to_v2bf16(<2 x i1> inreg %num) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
; GFX12-NEXT: v_ashrrev_i32_e32 v1, 16, v1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -1788,7 +1788,7 @@ define amdgpu_ps <2 x i32> @s_sitofp_v2i1_to_v2bf16(<2 x i1> inreg %num) {
; GFX12-NEXT: v_readfirstlane_b32 s0, v1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT: v_readfirstlane_b32 s1, v0
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: ; return to shader part epilog
%op = sitofp <2 x i1> %num to <2 x bfloat>
%b16 = bitcast <2 x bfloat> %op to <2 x i16>
@@ -1937,35 +1937,35 @@ define <3 x bfloat> @v_sitofp_v3i1_to_v3bf16(<3 x i1> %num) {
; GFX12-TRUE16-NEXT: v_and_b16 v1.l, 1, v1.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, -1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
; GFX12-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v1.l
; GFX12-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX12-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1981,12 +1981,12 @@ define <3 x bfloat> @v_sitofp_v3i1_to_v3bf16(<3 x i1> %num) {
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, -1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
@@ -1997,21 +1997,21 @@ define <3 x bfloat> @v_sitofp_v3i1_to_v3bf16(<3 x i1> %num) {
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 1, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-FAKE16-NEXT: v_bfe_u32 v5, v1, 16, 1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v1, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_alignbit_b32 v1, s0, v2, 16
@@ -2141,7 +2141,7 @@ define amdgpu_ps <3 x i32> @s_sitofp_v3i1_to_v3bf16(<3 x i1> inreg %num) {
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, s1
; GFX12-NEXT: s_cselect_b32 s0, -1, 0
; GFX12-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, s0
; GFX12-NEXT: v_or_b32_e32 v6, 0x400000, v2
; GFX12-NEXT: v_bfe_u32 v3, v0, 16, 1
@@ -2161,20 +2161,20 @@ define amdgpu_ps <3 x i32> @s_sitofp_v3i1_to_v3bf16(<3 x i1> inreg %num) {
; GFX12-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc_lo
; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-NEXT: v_ashrrev_i32_e32 v0, 16, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v1, v4, v8, vcc_lo
; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-NEXT: v_readfirstlane_b32 s1, v0
; GFX12-NEXT: v_ashrrev_i32_e32 v1, 16, v1
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc_lo
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_readfirstlane_b32 s0, v1
; GFX12-NEXT: v_ashrrev_i32_e32 v2, 16, v2
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_readfirstlane_b32 s2, v2
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: ; return to shader part epilog
%op = sitofp <3 x i1> %num to <3 x bfloat>
%b16 = bitcast <3 x bfloat> %op to <3 x i16>
@@ -2355,44 +2355,44 @@ define <4 x bfloat> @v_sitofp_v4i1_to_v4bf16(<4 x i1> %num) {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, -1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v2.l
; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, -1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v9, v0, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v7.h
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -2408,12 +2408,12 @@ define <4 x bfloat> @v_sitofp_v4i1_to_v4bf16(<4 x i1> %num) {
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 1, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, -1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, -1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
@@ -2425,31 +2425,31 @@ define <4 x bfloat> @v_sitofp_v4i1_to_v4bf16(<4 x i1> %num) {
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; GFX12-FAKE16-NEXT: v_bfe_u32 v6, v0, 16, 1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX12-FAKE16-NEXT: v_bfe_u32 v8, v1, 16, 1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v8, v1, 0x7fff
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v5, v9, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x7060302
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -2608,14 +2608,14 @@ define amdgpu_ps <4 x i32> @s_sitofp_v4i1_to_v4bf16(<4 x i1> inreg %num) {
; GFX12-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, s3
; GFX12-NEXT: s_cselect_b32 s2, -1, 0
; GFX12-NEXT: s_cmp_eq_u32 s1, 1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v4, 0, -1.0, s2
; GFX12-NEXT: s_cselect_b32 s1, -1, 0
; GFX12-NEXT: s_cmp_eq_u32 s0, 1
; GFX12-NEXT: v_cndmask_b32_e64 v3, 0, -1.0, s1
; GFX12-NEXT: s_cselect_b32 s0, -1, 0
; GFX12-NEXT: v_bfe_u32 v7, v4, 16, 1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, s0
; GFX12-NEXT: v_bfe_u32 v5, v1, 16, 1
; GFX12-NEXT: v_bfe_u32 v6, v3, 16, 1
@@ -2639,26 +2639,26 @@ define amdgpu_ps <4 x i32> @s_sitofp_v4i1_to_v4bf16(<4 x i1> inreg %num) {
; GFX12-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX12-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX12-NEXT: v_ashrrev_i32_e32 v0, 16, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
; GFX12-NEXT: v_ashrrev_i32_e32 v2, 16, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v3, v7, v6, vcc_lo
; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-NEXT: v_readfirstlane_b32 s1, v2
; GFX12-NEXT: v_ashrrev_i32_e32 v3, 16, v3
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v1, v5, v9, vcc_lo
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_readfirstlane_b32 s2, v3
; GFX12-NEXT: v_ashrrev_i32_e32 v1, 16, v1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_readfirstlane_b32 s3, v1
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: ; return to shader part epilog
%op = sitofp <4 x i1> %num to <4 x bfloat>
%b16 = bitcast <4 x bfloat> %op to <4 x i16>
diff --git a/llvm/test/CodeGen/AMDGPU/idiv-licm.ll b/llvm/test/CodeGen/AMDGPU/idiv-licm.ll
index 835818fb2fd15..b018fd3545374 100644
--- a/llvm/test/CodeGen/AMDGPU/idiv-licm.ll
+++ b/llvm/test/CodeGen/AMDGPU/idiv-licm.ll
@@ -71,7 +71,7 @@ define amdgpu_kernel void @udiv32_invariant_denom(ptr addrspace(1) nocapture %ar
; GFX10-NEXT: s_mov_b64 s[4:5], 0
; GFX10-NEXT: .LBB0_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_not_b32 s10, s5
; GFX10-NEXT: s_mul_i32 s9, s6, s5
; GFX10-NEXT: s_mul_i32 s10, s6, s10
@@ -109,7 +109,7 @@ define amdgpu_kernel void @udiv32_invariant_denom(ptr addrspace(1) nocapture %ar
; GFX11-NEXT: s_sub_i32 s2, 0, s6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
@@ -233,7 +233,7 @@ define amdgpu_kernel void @urem32_invariant_denom(ptr addrspace(1) nocapture %ar
; GFX10-NEXT: .LBB1_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: s_not_b32 s9, s5
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mul_i32 s10, s6, s5
; GFX10-NEXT: s_mul_i32 s9, s6, s9
; GFX10-NEXT: s_sub_i32 s10, s7, s10
@@ -268,7 +268,7 @@ define amdgpu_kernel void @urem32_invariant_denom(ptr addrspace(1) nocapture %ar
; GFX11-NEXT: s_sub_i32 s2, 0, s6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
@@ -405,7 +405,7 @@ define amdgpu_kernel void @sdiv32_invariant_denom(ptr addrspace(1) nocapture %ar
; GFX10-NEXT: s_sub_i32 s6, s6, s3
; GFX10-NEXT: v_mov_b32_e32 v1, s6
; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_add_u32 s0, s0, 4
; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_cmpk_eq_i32 s4, 0x400
@@ -425,7 +425,7 @@ define amdgpu_kernel void @sdiv32_invariant_denom(ptr addrspace(1) nocapture %ar
; GFX11-NEXT: s_sub_i32 s4, 0, s2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
@@ -552,7 +552,7 @@ define amdgpu_kernel void @srem32_invariant_denom(ptr addrspace(1) nocapture %ar
; GFX10-NEXT: v_mov_b32_e32 v1, s5
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_add_u32 s0, s0, 4
; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_cmpk_eq_i32 s3, 0x400
@@ -570,7 +570,7 @@ define amdgpu_kernel void @srem32_invariant_denom(ptr addrspace(1) nocapture %ar
; GFX11-NEXT: s_sub_i32 s3, 0, s2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
@@ -704,7 +704,7 @@ define amdgpu_kernel void @udiv16_invariant_denom(ptr addrspace(1) nocapture %ar
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mov_b32_e32 v4, s3
; GFX11-NEXT: s_and_b32 s3, s2, 0xffff
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v3, v2, v1
; GFX11-NEXT: s_cmpk_eq_i32 s3, 0x400
; GFX11-NEXT: v_trunc_f32_e32 v3, v3
@@ -818,7 +818,7 @@ define amdgpu_kernel void @urem16_invariant_denom(ptr addrspace(1) nocapture %ar
; GFX11-NEXT: s_add_i32 s3, s3, 1
; GFX11-NEXT: v_cvt_f32_u32_e32 v2, s4
; GFX11-NEXT: s_lshl_b32 s5, s4, 1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v3, v2, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_trunc_f32_e32 v3, v3
@@ -949,7 +949,7 @@ define amdgpu_kernel void @sdiv16_invariant_denom(ptr addrspace(1) nocapture %ar
; GFX11-NEXT: s_ashr_i32 s4, s4, 30
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_or_b32 s4, s4, 1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v3, v2, v1
; GFX11-NEXT: v_trunc_f32_e32 v3, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1084,7 +1084,7 @@ define amdgpu_kernel void @srem16_invariant_denom(ptr addrspace(1) nocapture %ar
; GFX11-NEXT: s_ashr_i32 s5, s5, 30
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_or_b32 s5, s5, 1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v3, v2, v1
; GFX11-NEXT: v_trunc_f32_e32 v3, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
diff --git a/llvm/test/CodeGen/AMDGPU/idot2.ll b/llvm/test/CodeGen/AMDGPU/idot2.ll
index d3a31f7133ab9..bf65657ff841c 100644
--- a/llvm/test/CodeGen/AMDGPU/idot2.ll
+++ b/llvm/test/CodeGen/AMDGPU/idot2.ll
@@ -110,7 +110,7 @@ define amdgpu_kernel void @udot2(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -252,7 +252,7 @@ define amdgpu_kernel void @udot2_MulMul(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v0, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0
@@ -390,7 +390,7 @@ define amdgpu_kernel void @idot2(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -529,7 +529,7 @@ define amdgpu_kernel void @idot2_MixedTypedMul(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mul_i32_i24_sdwa v0, sext(v2), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0
@@ -672,7 +672,7 @@ define amdgpu_kernel void @udot2_alt_AddOperands(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -811,7 +811,7 @@ define amdgpu_kernel void @idot2_MixedExt(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mul_i32_i24_sdwa v0, v2, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0
@@ -951,7 +951,7 @@ define amdgpu_kernel void @notudot2_SameVec(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v0, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0
@@ -1092,7 +1092,7 @@ define amdgpu_kernel void @udot2_v4i16(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1232,7 +1232,7 @@ define amdgpu_kernel void @udot2_v4i16_Hi(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1] offset:4
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3] offset:4
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1372,7 +1372,7 @@ define amdgpu_kernel void @notudot2_v4i16_Even(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dwordx2 v[0:1], v4, s[0:1]
; GFX10-DL-NEXT: global_load_dwordx2 v[2:3], v4, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0
@@ -1515,7 +1515,7 @@ define amdgpu_kernel void @notudot2_v4i16_Middle(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dwordx2 v[0:1], v4, s[0:1]
; GFX10-DL-NEXT: global_load_dwordx2 v[2:3], v4, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
@@ -1657,7 +1657,7 @@ define amdgpu_kernel void @notudot2_DiffIndex(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v0, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_0
@@ -1805,7 +1805,7 @@ define amdgpu_kernel void @udot2_MultipleUses_add1(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v0, 16, v1
@@ -1958,7 +1958,7 @@ define amdgpu_kernel void @idot2_MultipleUses_add1(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_ashrrev_i32_e32 v0, 16, v1
@@ -2115,7 +2115,7 @@ define amdgpu_kernel void @udot2_MultipleUses_mul1(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_and_b32_e32 v0, 0xffff, v1
@@ -2274,7 +2274,7 @@ define amdgpu_kernel void @idot2_MultipleUses_mul1(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_bfe_i32 v0, v1, 0, 16
@@ -2431,7 +2431,7 @@ define amdgpu_kernel void @udot2_MultipleUses_mul2(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v0, 16, v1
@@ -2588,7 +2588,7 @@ define amdgpu_kernel void @idot2_MultipleUses_mul2(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_ashrrev_i32_e32 v0, 16, v1
@@ -2885,7 +2885,7 @@ define amdgpu_kernel void @notsdot2_sext8(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_ushort v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_ushort v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_perm_b32 v0, v1, v1, 0xc0c0001
diff --git a/llvm/test/CodeGen/AMDGPU/idot4s.ll b/llvm/test/CodeGen/AMDGPU/idot4s.ll
index c96538b557cf6..1a22fa805a5a7 100644
--- a/llvm/test/CodeGen/AMDGPU/idot4s.ll
+++ b/llvm/test/CodeGen/AMDGPU/idot4s.ll
@@ -125,7 +125,7 @@ define amdgpu_kernel void @idot4_acc32(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0
@@ -706,7 +706,7 @@ define amdgpu_kernel void @idot4_multiuse_mul1(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_bfe_i32 v0, v1, 0, 8
@@ -908,7 +908,7 @@ define amdgpu_kernel void @idot4_acc32_vecMul(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0
@@ -1378,7 +1378,7 @@ define amdgpu_kernel void @idot4_acc32_2ele(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[2:3]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[0:1]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_perm_b32 v0, v1, v1, 0xc0c0100
@@ -1558,7 +1558,7 @@ define amdgpu_kernel void @idot4_acc32_3ele(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[2:3]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[0:1]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_perm_b32 v0, v1, v1, 0xc020100
@@ -1745,7 +1745,7 @@ define amdgpu_kernel void @idot4_acc32_3ele_permuted(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[2:3]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[0:1]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_perm_b32 v0, v1, v1, 0xc020003
@@ -2526,7 +2526,7 @@ define amdgpu_kernel void @idot4_bad_source(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x44
; GFX10-DL-NEXT: s_sext_i32_i16 s3, s6
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
@@ -2728,7 +2728,7 @@ define amdgpu_kernel void @idot4_commutative(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[2:3]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[0:1]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_perm_b32 v0, v1, v1, 0xc020100
diff --git a/llvm/test/CodeGen/AMDGPU/idot4u.ll b/llvm/test/CodeGen/AMDGPU/idot4u.ll
index f80d50b56f550..61d09fda44528 100644
--- a/llvm/test/CodeGen/AMDGPU/idot4u.ll
+++ b/llvm/test/CodeGen/AMDGPU/idot4u.ll
@@ -124,7 +124,7 @@ define amdgpu_kernel void @udot4_acc32(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1213,7 +1213,7 @@ define amdgpu_kernel void @udot4_multiuse_mul1(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_and_b32_e32 v0, 0xff, v1
@@ -1421,7 +1421,7 @@ define amdgpu_kernel void @udot4_multiuse_add1(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mul_u32_u24_sdwa v0, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
@@ -2193,7 +2193,7 @@ define amdgpu_kernel void @udot4_acc32_vecMul(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -2925,7 +2925,7 @@ define amdgpu_kernel void @idot4_acc32_2ele(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[2:3]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[0:1]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_perm_b32 v0, v1, v1, 0xc0c0100
@@ -3103,7 +3103,7 @@ define amdgpu_kernel void @idot4_acc32_3ele(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[2:3]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[0:1]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_perm_b32 v0, v1, v1, 0xc020100
@@ -3288,7 +3288,7 @@ define amdgpu_kernel void @idot4_acc32_3ele_permuted(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[2:3]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[0:1]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_perm_b32 v0, v1, v1, 0xc020003
@@ -4070,7 +4070,7 @@ define amdgpu_kernel void @udot4_bad_source(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x44
; GFX10-DL-NEXT: s_and_b32 s3, s6, 0xffff
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
@@ -4271,7 +4271,7 @@ define amdgpu_kernel void @udot4_commutative(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[2:3]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[0:1]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_perm_b32 v0, v1, v1, 0xc020100
@@ -4942,7 +4942,7 @@ define amdgpu_kernel void @udot4_acc32_multi(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1]
; GFX10-DL-NEXT: global_load_dword v3, v2, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_perm_b32 v2, v1, v0, 0x6040200
@@ -6252,7 +6252,7 @@ define amdgpu_kernel void @idot4_acc32_anyext(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_perm_b32 v0, v2, v1, 0xc0c0500
diff --git a/llvm/test/CodeGen/AMDGPU/idot8s.ll b/llvm/test/CodeGen/AMDGPU/idot8s.ll
index b9d3763e7def1..87aff7cec142d 100644
--- a/llvm/test/CodeGen/AMDGPU/idot8s.ll
+++ b/llvm/test/CodeGen/AMDGPU/idot8s.ll
@@ -201,7 +201,7 @@ define amdgpu_kernel void @idot8_acc32(ptr addrspace(1) %src1,
; GFX10-DL-XNACK-NEXT: s_clause 0x1
; GFX10-DL-XNACK-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-XNACK-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-XNACK-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-XNACK-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-XNACK-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-XNACK-NEXT: v_mov_b32_e32 v0, 0
; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1576,7 +1576,7 @@ define amdgpu_kernel void @idot8_multiuses_mul1(ptr addrspace(1) %src1,
; GFX10-DL-XNACK-NEXT: s_clause 0x1
; GFX10-DL-XNACK-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-XNACK-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-XNACK-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-XNACK-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-XNACK-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-XNACK-NEXT: v_bfe_i32 v0, v1, 0, 4
@@ -1932,7 +1932,7 @@ define amdgpu_kernel void @idot8_acc32_vecMul(ptr addrspace(1) %src1,
; GFX10-DL-XNACK-NEXT: s_clause 0x1
; GFX10-DL-XNACK-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-XNACK-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-XNACK-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-XNACK-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-XNACK-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-XNACK-NEXT: v_mov_b32_e32 v0, 0
; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/idot8u.ll b/llvm/test/CodeGen/AMDGPU/idot8u.ll
index 02cca4abc87b4..c03802e144d5b 100644
--- a/llvm/test/CodeGen/AMDGPU/idot8u.ll
+++ b/llvm/test/CodeGen/AMDGPU/idot8u.ll
@@ -199,7 +199,7 @@ define amdgpu_kernel void @udot8_acc32(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1755,7 +1755,7 @@ define amdgpu_kernel void @udot8_multiuses_mul1(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NEXT: v_and_b32_e32 v8, 15, v1
@@ -2058,7 +2058,7 @@ define amdgpu_kernel void @udot8_acc32_vecMul(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -3278,7 +3278,7 @@ define amdgpu_kernel void @udot8_variant1(ptr addrspace(1) %v1addr,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-DL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-DL-NEXT: s_load_dword s0, s[6:7], 0x0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
; GFX10-DL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll b/llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
index e1a9935b790f3..d4867dbaa14b3 100644
--- a/llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
@@ -276,9 +276,9 @@ define i32 @atomic_nand_i32_global(ptr addrspace(1) %ptr) nounwind {
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SYS
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB1_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -397,10 +397,10 @@ define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) {
; GFX12-NEXT: scratch_load_b32 v32, off, s32
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_getpc_b64 s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_sext_i32_i16 s1, s1
; GFX12-NEXT: s_add_co_u32 s0, s0, byval_align16_f64_arg at rel32@lo+12
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_ci_u32 s1, s1, byval_align16_f64_arg at rel32@hi+24
; GFX12-NEXT: scratch_store_b32 off, v32, s32
; GFX12-NEXT: s_wait_storecnt 0x0
@@ -408,7 +408,7 @@ define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) {
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: scratch_store_b64 off, v[32:33], s32 offset:16
; GFX12-NEXT: s_wait_storecnt 0x0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[0:1]
entry:
%alloca = alloca double, align 8, addrspace(5)
@@ -548,7 +548,7 @@ define amdgpu_kernel void @udiv_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {
; GFX11-NEXT: s_sub_i32 s5, 0, s3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
@@ -586,31 +586,31 @@ define amdgpu_kernel void @udiv_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {
; GFX12-NEXT: v_rcp_iflag_f32_e32 v0, s4
; GFX12-NEXT: v_readfirstlane_b32 s4, v0
; GFX12-NEXT: s_mul_f32 s4, s4, 0x4f7ffffe
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
; GFX12-NEXT: s_cvt_u32_f32 s4, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mul_i32 s5, s5, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mul_hi_u32 s5, s4, s5
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_i32 s4, s4, s5
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mul_hi_u32 s4, s2, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mul_i32 s5, s4, s3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_sub_co_i32 s2, s2, s5
; GFX12-NEXT: s_add_co_i32 s5, s4, 1
; GFX12-NEXT: s_sub_co_i32 s6, s2, s3
; GFX12-NEXT: s_cmp_ge_u32 s2, s3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_cselect_b32 s4, s5, s4
; GFX12-NEXT: s_cselect_b32 s2, s6, s2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_i32 s5, s4, 1
; GFX12-NEXT: s_cmp_ge_u32 s2, s3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_cselect_b32 s2, s5, s4
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
@@ -795,9 +795,9 @@ define amdgpu_kernel void @atomic_add_local(ptr addrspace(3) %local) {
; GFX12-NEXT: s_load_b32 s1, s[4:5], 0x24
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_bcnt1_i32_b32 s0, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mul_i32 s0, s0, 5
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v0, s1
; GFX12-NEXT: ds_add_u32 v0, v1
; GFX12-NEXT: s_wait_dscnt 0x0
@@ -959,7 +959,7 @@ define amdgpu_kernel void @atomic_add_ret_local(ptr addrspace(1) %out, ptr addrs
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: .LBB7_2:
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
@@ -1043,9 +1043,9 @@ define amdgpu_kernel void @atomic_add_ret_local(ptr addrspace(1) %out, ptr addrs
; GFX12-NEXT: s_load_b32 s2, s[4:5], 0x2c
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_bcnt1_i32_b32 s1, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mul_i32 s1, s1, 5
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s2
; GFX12-NEXT: ds_add_rtn_u32 v1, v1, v2
; GFX12-NEXT: s_wait_dscnt 0x0
@@ -1057,7 +1057,7 @@ define amdgpu_kernel void @atomic_add_ret_local(ptr addrspace(1) %out, ptr addrs
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_readfirstlane_b32 s2, v1
; GFX12-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT: v_mad_u32_u24 v0, v0, 5, s2
; GFX12-NEXT: global_store_b32 v1, v0, s[0:1]
@@ -1147,7 +1147,7 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX10-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: .LBB8_2:
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
@@ -1229,9 +1229,9 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12-NEXT: s_load_b128 s[8:11], s[4:5], 0x34
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_bcnt1_i32_b32 s1, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mul_i32 s1, s1, 5
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v1, s1
; GFX12-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll b/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
index 8d0131ccc6f7b..69bd0687b71af 100644
--- a/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
+++ b/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
@@ -6080,7 +6080,7 @@ define i64 @clpeak_imad_pat_i64(i64 %x, i64 %y) {
; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX1200-SDAG-NEXT: v_add_co_u32 v4, vcc_lo, v0, 1
-; GFX1200-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v1, vcc_lo
; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-SDAG-NEXT: v_mul_lo_u32 v7, v4, v3
@@ -6092,7 +6092,7 @@ define i64 @clpeak_imad_pat_i64(i64 %x, i64 %y) {
; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1200-SDAG-NEXT: v_mul_lo_u32 v6, v4, v3
; GFX1200-SDAG-NEXT: v_mad_co_u64_u32 v[3:4], null, v4, v2, 0
-; GFX1200-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-NEXT: v_add_co_ci_u32_e64 v5, null, v1, v5, vcc_lo
; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-NEXT: v_mul_lo_u32 v2, v5, v2
@@ -6118,7 +6118,7 @@ define i64 @clpeak_imad_pat_i64(i64 %x, i64 %y) {
; GFX1200-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1200-GISEL-NEXT: v_add_co_u32 v4, vcc_lo, v0, 1
-; GFX1200-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX1200-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v1, vcc_lo
; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-GISEL-NEXT: v_mul_hi_u32 v0, v4, v2
@@ -6130,12 +6130,12 @@ define i64 @clpeak_imad_pat_i64(i64 %x, i64 %y) {
; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[0:1], null, v5, v2, v[0:1]
; GFX1200-GISEL-NEXT: v_mul_hi_u32 v1, v4, v2
-; GFX1200-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX1200-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v0, v5, vcc_lo
; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[3:4], null, v4, v3, v[1:2]
; GFX1200-GISEL-NEXT: v_add_co_u32 v4, vcc_lo, v6, 1
-; GFX1200-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX1200-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e64 v6, null, 0, v0, vcc_lo
; GFX1200-GISEL-NEXT: v_add_co_u32 v8, vcc_lo, v7, 1
; GFX1200-GISEL-NEXT: v_mul_hi_u32 v0, v7, v4
@@ -6143,7 +6143,7 @@ define i64 @clpeak_imad_pat_i64(i64 %x, i64 %y) {
; GFX1200-GISEL-NEXT: v_mul_lo_u32 v5, v7, v4
; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[2:3], null, v7, v6, v[0:1]
-; GFX1200-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX1200-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v1, vcc_lo
; GFX1200-GISEL-NEXT: v_mul_hi_u32 v0, v5, v8
; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -6944,10 +6944,10 @@ define <2 x i64> @clpeak_imad_pat_v2i64(<2 x i64> %x, <2 x i64> %y) {
; GFX1200-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX1200-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX1200-SDAG-NEXT: v_add_co_u32 v8, vcc_lo, v0, 1
-; GFX1200-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v1, vcc_lo
; GFX1200-SDAG-NEXT: v_add_co_u32 v10, vcc_lo, v2, 1
-; GFX1200-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v3, vcc_lo
; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX1200-SDAG-NEXT: v_mul_lo_u32 v12, v9, v4
@@ -6960,11 +6960,11 @@ define <2 x i64> @clpeak_imad_pat_v2i64(<2 x i64> %x, <2 x i64> %y) {
; GFX1200-SDAG-NEXT: v_add3_u32 v12, v1, v13, v12
; GFX1200-SDAG-NEXT: v_add_co_u32 v1, vcc_lo, v0, v8
; GFX1200-SDAG-NEXT: v_add3_u32 v13, v3, v15, v14
-; GFX1200-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1200-SDAG-NEXT: v_add_co_ci_u32_e64 v3, null, v12, v9, vcc_lo
; GFX1200-SDAG-NEXT: v_add_co_u32 v8, vcc_lo, v2, v10
-; GFX1200-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-NEXT: v_add_co_ci_u32_e64 v9, null, v13, v11, vcc_lo
; GFX1200-SDAG-NEXT: v_mul_lo_u32 v10, v3, v4
; GFX1200-SDAG-NEXT: v_mul_lo_u32 v11, v1, v5
@@ -7008,12 +7008,12 @@ define <2 x i64> @clpeak_imad_pat_v2i64(<2 x i64> %x, <2 x i64> %y) {
; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1200-GISEL-NEXT: v_add_co_u32 v8, vcc_lo, v0, 1
; GFX1200-GISEL-NEXT: v_add_co_u32 v9, s0, v2, 1
-; GFX1200-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX1200-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e64 v10, null, 0, v1, vcc_lo
; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-GISEL-NEXT: v_mul_hi_u32 v0, v8, v4
; GFX1200-GISEL-NEXT: v_mul_hi_u32 v1, v9, v6
-; GFX1200-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX1200-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v3, s0
; GFX1200-GISEL-NEXT: v_mul_lo_u32 v12, v8, v4
; GFX1200-GISEL-NEXT: v_mul_lo_u32 v13, v9, v6
@@ -7028,9 +7028,9 @@ define <2 x i64> @clpeak_imad_pat_v2i64(<2 x i64> %x, <2 x i64> %y) {
; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[2:3], null, v11, v6, v[0:1]
; GFX1200-GISEL-NEXT: v_mul_hi_u32 v0, v14, v4
; GFX1200-GISEL-NEXT: v_mul_hi_u32 v3, v15, v6
-; GFX1200-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX1200-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e64 v16, null, v1, v10, vcc_lo
-; GFX1200-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX1200-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e64 v11, null, v2, v11, s0
; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[8:9], null, v14, v5, v[0:1]
@@ -7042,17 +7042,17 @@ define <2 x i64> @clpeak_imad_pat_v2i64(<2 x i64> %x, <2 x i64> %y) {
; GFX1200-GISEL-NEXT: v_add_co_u32 v8, vcc_lo, v12, 1
; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[4:5], null, v11, v6, v[9:10]
-; GFX1200-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX1200-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v1, vcc_lo
; GFX1200-GISEL-NEXT: v_add_co_u32 v9, vcc_lo, v13, 1
; GFX1200-GISEL-NEXT: v_mul_hi_u32 v0, v7, v8
-; GFX1200-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX1200-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e64 v2, null, 0, v2, vcc_lo
; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1200-GISEL-NEXT: v_mul_hi_u32 v1, v10, v9
; GFX1200-GISEL-NEXT: v_mul_lo_u32 v15, v10, v9
; GFX1200-GISEL-NEXT: v_add_co_u32 v12, vcc_lo, v7, 1
-; GFX1200-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX1200-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e64 v13, null, 0, v3, vcc_lo
; GFX1200-GISEL-NEXT: v_add_co_u32 v14, vcc_lo, v10, 1
; GFX1200-GISEL-NEXT: v_mul_lo_u32 v11, v7, v8
@@ -7060,7 +7060,7 @@ define <2 x i64> @clpeak_imad_pat_v2i64(<2 x i64> %x, <2 x i64> %y) {
; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[1:2], null, v10, v2, v[1:2]
; GFX1200-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX1200-GISEL-NEXT: v_mul_hi_u32 v2, v15, v14
-; GFX1200-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX1200-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-GISEL-NEXT: v_add_co_ci_u32_e64 v10, null, 0, v4, vcc_lo
; GFX1200-GISEL-NEXT: v_mul_hi_u32 v0, v11, v12
; GFX1200-GISEL-NEXT: v_mad_co_u64_u32 v[5:6], null, v3, v8, v[5:6]
@@ -11140,7 +11140,7 @@ define i64 @mul_u24_zext_add64(i32 %x, i32 %y, i64 %z) {
; GFX1200-NEXT: v_mul_u32_u24_e32 v0, v0, v1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX1200-NEXT: s_wait_alu 0xfffd
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx11.mir b/llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx11.mir
index 0c273f06ffa19..5b9c3eaf21c3f 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx11.mir
+++ b/llvm/test/CodeGen/AMDGPU/lds-direct-hazards-gfx11.mir
@@ -183,7 +183,7 @@ body: |
; GCN-LABEL: name: lds_param_load_valu_war_trans
; GCN: $vgpr0 = V_MUL_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec
; GCN-NEXT: $vgpr2 = V_SQRT_F32_e32 $vgpr2, implicit $mode, implicit $exec
- ; GCN-NEXT: S_WAITCNT_DEPCTR 4095
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 3999
; GCN-NEXT: $vgpr3 = V_MUL_F32_e32 $vgpr2, $vgpr2, implicit $mode, implicit $exec
; GCN-NEXT: $vgpr4 = V_MUL_F32_e32 $vgpr2, $vgpr2, implicit $mode, implicit $exec
; GCN-NEXT: $vgpr5 = V_MUL_F32_e32 $vgpr2, $vgpr2, implicit $mode, implicit $exec
@@ -298,7 +298,7 @@ body: |
bb.0:
; GCN-LABEL: name: lds_param_load_vmem_war
; GCN: $vgpr0 = IMAGE_LOAD_V1_V4 $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, 2, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s32))
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65507
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65411
; GCN-NEXT: $vgpr1 = LDS_PARAM_LOAD 0, 0, 15, implicit $m0, implicit $exec
; GCN-NEXT: S_ENDPGM 0
$vgpr0 = IMAGE_LOAD_V1_V4 $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, 2, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 4)
@@ -373,7 +373,7 @@ body: |
; GCN-LABEL: name: lds_param_load_vmem_war_waitcnt_depctr2
; GCN: $vgpr0 = IMAGE_LOAD_V1_V4 $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, 2, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s32))
; GCN-NEXT: S_WAITCNT_DEPCTR 65535
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65507
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65411
; GCN-NEXT: $vgpr1 = LDS_PARAM_LOAD 0, 0, 15, implicit $m0, implicit $exec
; GCN-NEXT: S_ENDPGM 0
$vgpr0 = IMAGE_LOAD_V1_V4 $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, 2, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 4)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
index 4e61cb4831545..6cc6ba732d805 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
@@ -25,7 +25,7 @@ define i32 @dead_i32(i1 %cond, i32 %x, ptr addrspace(1) %ptr1) #0 {
; ASM-DAG-NEXT: global_store_b32 v[2:3], v0, off
; ASM-DAG-NEXT: ; implicit-def: $vgpr0
; ASM-DAG-NEXT: .LBB0_2: ; %if.end
-; ASM-DAG-NEXT: s_wait_alu 0xfffe
+; ASM-DAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; ASM-DAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; ASM-DAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -48,7 +48,7 @@ define i32 @dead_i32(i1 %cond, i32 %x, ptr addrspace(1) %ptr1) #0 {
; ASM-GISEL-TRUE16-NEXT: global_store_b32 v[2:3], v0, off
; ASM-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0
; ASM-GISEL-TRUE16-NEXT: .LBB0_2: ; %if.end
-; ASM-GISEL-TRUE16-NEXT: s_wait_alu 0xfffe
+; ASM-GISEL-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; ASM-GISEL-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; ASM-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -71,7 +71,7 @@ define i32 @dead_i32(i1 %cond, i32 %x, ptr addrspace(1) %ptr1) #0 {
; ASM-GISEL-FAKE16-NEXT: global_store_b32 v[2:3], v0, off
; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr0
; ASM-GISEL-FAKE16-NEXT: .LBB0_2: ; %if.end
-; ASM-GISEL-FAKE16-NEXT: s_wait_alu 0xfffe
+; ASM-GISEL-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; ASM-GISEL-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; ASM-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -120,7 +120,7 @@ define %trivial_types @dead_struct(i1 %cond, %trivial_types %x, ptr addrspace(1)
; ASM-DAG-NEXT: global_store_b32 v[17:18], v0, off
; ASM-DAG-NEXT: ; implicit-def: $vgpr0
; ASM-DAG-NEXT: .LBB1_2: ; %if.end
-; ASM-DAG-NEXT: s_wait_alu 0xfffe
+; ASM-DAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; ASM-DAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; ASM-DAG-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v3
; ASM-DAG-NEXT: v_dual_mov_b32 v3, v4 :: v_dual_mov_b32 v4, v5
@@ -149,11 +149,11 @@ define %trivial_types @dead_struct(i1 %cond, %trivial_types %x, ptr addrspace(1)
; ASM-GISEL-TRUE16-NEXT: ; %bb.1: ; %if.then
; ASM-GISEL-TRUE16-NEXT: s_mov_b32 s4, 0
; ASM-GISEL-TRUE16-NEXT: s_mov_b32 s1, 0x3fc00000
-; ASM-GISEL-TRUE16-NEXT: s_wait_alu 0xfffe
+; ASM-GISEL-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; ASM-GISEL-TRUE16-NEXT: s_mov_b32 s7, s4
; ASM-GISEL-TRUE16-NEXT: s_mov_b32 s5, s4
; ASM-GISEL-TRUE16-NEXT: s_mov_b32 s6, s4
-; ASM-GISEL-TRUE16-NEXT: s_wait_alu 0xfffe
+; ASM-GISEL-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; ASM-GISEL-TRUE16-NEXT: v_dual_mov_b32 v14, s7 :: v_dual_mov_b32 v13, s6
; ASM-GISEL-TRUE16-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_add_nc_u32 v0, 15, v19
; ASM-GISEL-TRUE16-NEXT: v_dual_mov_b32 v12, s5 :: v_dual_mov_b32 v11, s4
@@ -166,7 +166,7 @@ define %trivial_types @dead_struct(i1 %cond, %trivial_types %x, ptr addrspace(1)
; ASM-GISEL-TRUE16-NEXT: global_store_b32 v[17:18], v0, off
; ASM-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0
; ASM-GISEL-TRUE16-NEXT: .LBB1_2: ; %if.end
-; ASM-GISEL-TRUE16-NEXT: s_wait_alu 0xfffe
+; ASM-GISEL-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; ASM-GISEL-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; ASM-GISEL-TRUE16-NEXT: v_dual_mov_b32 v2, v3 :: v_dual_mov_b32 v3, v4
; ASM-GISEL-TRUE16-NEXT: v_dual_mov_b32 v4, v5 :: v_dual_mov_b32 v5, v6
@@ -194,11 +194,11 @@ define %trivial_types @dead_struct(i1 %cond, %trivial_types %x, ptr addrspace(1)
; ASM-GISEL-FAKE16-NEXT: ; %bb.1: ; %if.then
; ASM-GISEL-FAKE16-NEXT: s_mov_b32 s4, 0
; ASM-GISEL-FAKE16-NEXT: s_mov_b32 s1, 0x3fc00000
-; ASM-GISEL-FAKE16-NEXT: s_wait_alu 0xfffe
+; ASM-GISEL-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; ASM-GISEL-FAKE16-NEXT: s_mov_b32 s7, s4
; ASM-GISEL-FAKE16-NEXT: s_mov_b32 s5, s4
; ASM-GISEL-FAKE16-NEXT: s_mov_b32 s6, s4
-; ASM-GISEL-FAKE16-NEXT: s_wait_alu 0xfffe
+; ASM-GISEL-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; ASM-GISEL-FAKE16-NEXT: v_dual_mov_b32 v14, s7 :: v_dual_mov_b32 v13, s6
; ASM-GISEL-FAKE16-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_add_nc_u32 v0, 15, v19
; ASM-GISEL-FAKE16-NEXT: v_dual_mov_b32 v12, s5 :: v_dual_mov_b32 v11, s4
@@ -211,7 +211,7 @@ define %trivial_types @dead_struct(i1 %cond, %trivial_types %x, ptr addrspace(1)
; ASM-GISEL-FAKE16-NEXT: global_store_b32 v[17:18], v0, off
; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr0
; ASM-GISEL-FAKE16-NEXT: .LBB1_2: ; %if.end
-; ASM-GISEL-FAKE16-NEXT: s_wait_alu 0xfffe
+; ASM-GISEL-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; ASM-GISEL-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; ASM-GISEL-FAKE16-NEXT: v_dual_mov_b32 v2, v3 :: v_dual_mov_b32 v3, v4
; ASM-GISEL-FAKE16-NEXT: v_dual_mov_b32 v4, v5 :: v_dual_mov_b32 v5, v6
@@ -340,7 +340,7 @@ define [32 x i32] @dead_array(i1 %cond, [32 x i32] %x, ptr addrspace(1) %ptr1, i
; ASM-DAG-NEXT: global_store_b32 v[34:35], v0, off
; ASM-DAG-NEXT: ; implicit-def: $vgpr0
; ASM-DAG-NEXT: .LBB2_2: ; %if.end
-; ASM-DAG-NEXT: s_wait_alu 0xfffe
+; ASM-DAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; ASM-DAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
; ASM-DAG-NEXT: s_wait_loadcnt 0x0
; ASM-DAG-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v3
@@ -398,7 +398,7 @@ define [32 x i32] @dead_array(i1 %cond, [32 x i32] %x, ptr addrspace(1) %ptr1, i
; ASM-GISEL-TRUE16-NEXT: s_mov_b32 s1, 15
; ASM-GISEL-TRUE16-NEXT: s_mov_b32 s2, 13
; ASM-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0
-; ASM-GISEL-TRUE16-NEXT: s_wait_alu 0xfffe
+; ASM-GISEL-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; ASM-GISEL-TRUE16-NEXT: v_dual_mov_b32 v7, s1 :: v_dual_add_nc_u32 v0, 15, v35
; ASM-GISEL-TRUE16-NEXT: v_mov_b32_e32 v6, s2
; ASM-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr1
@@ -433,7 +433,7 @@ define [32 x i32] @dead_array(i1 %cond, [32 x i32] %x, ptr addrspace(1) %ptr1, i
; ASM-GISEL-TRUE16-NEXT: global_store_b32 v[33:34], v0, off
; ASM-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr0
; ASM-GISEL-TRUE16-NEXT: .LBB2_2: ; %if.end
-; ASM-GISEL-TRUE16-NEXT: s_wait_alu 0xfffe
+; ASM-GISEL-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; ASM-GISEL-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; ASM-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0
; ASM-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -476,7 +476,7 @@ define [32 x i32] @dead_array(i1 %cond, [32 x i32] %x, ptr addrspace(1) %ptr1, i
; ASM-GISEL-FAKE16-NEXT: s_mov_b32 s1, 15
; ASM-GISEL-FAKE16-NEXT: s_mov_b32 s2, 13
; ASM-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x0
-; ASM-GISEL-FAKE16-NEXT: s_wait_alu 0xfffe
+; ASM-GISEL-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; ASM-GISEL-FAKE16-NEXT: v_dual_mov_b32 v7, s1 :: v_dual_add_nc_u32 v0, 15, v35
; ASM-GISEL-FAKE16-NEXT: v_mov_b32_e32 v6, s2
; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr1
@@ -511,7 +511,7 @@ define [32 x i32] @dead_array(i1 %cond, [32 x i32] %x, ptr addrspace(1) %ptr1, i
; ASM-GISEL-FAKE16-NEXT: global_store_b32 v[33:34], v0, off
; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr0
; ASM-GISEL-FAKE16-NEXT: .LBB2_2: ; %if.end
-; ASM-GISEL-FAKE16-NEXT: s_wait_alu 0xfffe
+; ASM-GISEL-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; ASM-GISEL-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; ASM-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x0
; ASM-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -652,7 +652,7 @@ define %non_trivial_types @dead_non_trivial(i1 %cond, %non_trivial_types %x, ptr
; ASM-GISEL-TRUE16-NEXT: s_mov_b32 s1, 0
; ASM-GISEL-TRUE16-NEXT: s_movk_i32 s2, 0x3e00
; ASM-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0
-; ASM-GISEL-TRUE16-NEXT: s_wait_alu 0xfffe
+; ASM-GISEL-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; ASM-GISEL-TRUE16-NEXT: v_dual_mov_b32 v8, s1 :: v_dual_add_nc_u32 v1, 15, v68
; ASM-GISEL-TRUE16-NEXT: v_mov_b16_e32 v4.l, s2
; ASM-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr2
@@ -696,7 +696,7 @@ define %non_trivial_types @dead_non_trivial(i1 %cond, %non_trivial_types %x, ptr
; ASM-GISEL-TRUE16-NEXT: ; implicit-def: $vgpr67
; ASM-GISEL-TRUE16-NEXT: global_store_b32 v[31:32], v1, off
; ASM-GISEL-TRUE16-NEXT: .LBB3_2: ; %if.end
-; ASM-GISEL-TRUE16-NEXT: s_wait_alu 0xfffe
+; ASM-GISEL-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; ASM-GISEL-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; ASM-GISEL-TRUE16-NEXT: s_clause 0x16
; ASM-GISEL-TRUE16-NEXT: scratch_store_b8 v0, v2, off
@@ -802,7 +802,7 @@ define %non_trivial_types @dead_non_trivial(i1 %cond, %non_trivial_types %x, ptr
; ASM-GISEL-FAKE16-NEXT: s_mov_b32 s1, 0
; ASM-GISEL-FAKE16-NEXT: s_movk_i32 s2, 0x3e00
; ASM-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x0
-; ASM-GISEL-FAKE16-NEXT: s_wait_alu 0xfffe
+; ASM-GISEL-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; ASM-GISEL-FAKE16-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_add_nc_u32 v1, 15, v68
; ASM-GISEL-FAKE16-NEXT: v_mov_b32_e32 v8, s1
; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr2
@@ -846,7 +846,7 @@ define %non_trivial_types @dead_non_trivial(i1 %cond, %non_trivial_types %x, ptr
; ASM-GISEL-FAKE16-NEXT: ; implicit-def: $vgpr67
; ASM-GISEL-FAKE16-NEXT: global_store_b32 v[31:32], v1, off
; ASM-GISEL-FAKE16-NEXT: .LBB3_2: ; %if.end
-; ASM-GISEL-FAKE16-NEXT: s_wait_alu 0xfffe
+; ASM-GISEL-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; ASM-GISEL-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; ASM-GISEL-FAKE16-NEXT: s_clause 0x16
; ASM-GISEL-FAKE16-NEXT: scratch_store_b8 v0, v2, off
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
index d82d6bcb437cc..f5b534c179019 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
@@ -15,13 +15,13 @@ define amdgpu_cs_chain void @basic(<3 x i32> inreg %sgpr, ptr inreg %callee, i32
; GISEL12-NEXT: s_or_saveexec_b32 s8, -1
; GISEL12-NEXT: s_mov_b32 s6, s3
; GISEL12-NEXT: s_mov_b32 s7, s4
-; GISEL12-NEXT: s_wait_alu 0xfffe
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: s_and_saveexec_b32 s3, s8
; GISEL12-NEXT: ; %bb.1: ; %shader
; GISEL12-NEXT: v_add_nc_u32_e32 v12, 42, v12
; GISEL12-NEXT: v_add_nc_u32_e32 v8, 5, v8
; GISEL12-NEXT: ; %bb.2: ; %tail
-; GISEL12-NEXT: s_wait_alu 0xfffe
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GISEL12-NEXT: v_add_nc_u32_e32 v11, 32, v12
@@ -38,13 +38,13 @@ define amdgpu_cs_chain void @basic(<3 x i32> inreg %sgpr, ptr inreg %callee, i32
; DAGISEL12-NEXT: s_or_saveexec_b32 s8, -1
; DAGISEL12-NEXT: s_mov_b32 s7, s4
; DAGISEL12-NEXT: s_mov_b32 s6, s3
-; DAGISEL12-NEXT: s_wait_alu 0xfffe
+; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: s_and_saveexec_b32 s3, s8
; DAGISEL12-NEXT: ; %bb.1: ; %shader
; DAGISEL12-NEXT: v_add_nc_u32_e32 v12, 42, v12
; DAGISEL12-NEXT: v_add_nc_u32_e32 v8, 5, v8
; DAGISEL12-NEXT: ; %bb.2: ; %tail
-; DAGISEL12-NEXT: s_wait_alu 0xfffe
+; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: s_or_b32 exec_lo, exec_lo, s3
; DAGISEL12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; DAGISEL12-NEXT: v_add_nc_u32_e32 v11, 32, v12
@@ -115,15 +115,15 @@ define amdgpu_cs_chain void @wwm_in_shader(<3 x i32> inreg %sgpr, ptr inreg %cal
; GISEL12-NEXT: v_dual_mov_b32 v10, v12 :: v_dual_mov_b32 v11, v13
; GISEL12-NEXT: s_mov_b32 s6, s3
; GISEL12-NEXT: s_mov_b32 s7, s4
-; GISEL12-NEXT: s_wait_alu 0xfffe
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: s_and_saveexec_b32 s3, s8
; GISEL12-NEXT: ; %bb.1: ; %shader
; GISEL12-NEXT: s_or_saveexec_b32 s4, -1
-; GISEL12-NEXT: s_wait_alu 0xfffe
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: v_cndmask_b32_e64 v0, 0x47, v10, s4
; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GISEL12-NEXT: v_cmp_ne_u32_e64 s8, 0, v0
-; GISEL12-NEXT: s_wait_alu 0xf1ff
+; GISEL12-NEXT: s_wait_alu depctr_va_sdst(0)
; GISEL12-NEXT: v_mov_b32_e32 v0, s8
; GISEL12-NEXT: s_mov_b32 exec_lo, s4
; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -144,11 +144,11 @@ define amdgpu_cs_chain void @wwm_in_shader(<3 x i32> inreg %sgpr, ptr inreg %cal
; DAGISEL12-NEXT: v_dual_mov_b32 v11, v13 :: v_dual_mov_b32 v10, v12
; DAGISEL12-NEXT: s_mov_b32 s7, s4
; DAGISEL12-NEXT: s_mov_b32 s6, s3
-; DAGISEL12-NEXT: s_wait_alu 0xfffe
+; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: s_and_saveexec_b32 s3, s8
; DAGISEL12-NEXT: ; %bb.1: ; %shader
; DAGISEL12-NEXT: s_or_saveexec_b32 s4, -1
-; DAGISEL12-NEXT: s_wait_alu 0xfffe
+; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: v_cndmask_b32_e64 v0, 0x47, v10, s4
; DAGISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; DAGISEL12-NEXT: v_cmp_ne_u32_e64 s8, 0, v0
@@ -235,15 +235,15 @@ define amdgpu_cs_chain void @phi_whole_struct(<3 x i32> inreg %sgpr, ptr inreg %
; GISEL12-NEXT: s_or_saveexec_b32 s8, -1
; GISEL12-NEXT: s_mov_b32 s6, s3
; GISEL12-NEXT: s_mov_b32 s7, s4
-; GISEL12-NEXT: s_wait_alu 0xfffe
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: s_and_saveexec_b32 s3, s8
; GISEL12-NEXT: ; %bb.1: ; %shader
; GISEL12-NEXT: s_or_saveexec_b32 s4, -1
-; GISEL12-NEXT: s_wait_alu 0xfffe
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: v_cndmask_b32_e64 v0, 0x47, v12, s4
; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GISEL12-NEXT: v_cmp_ne_u32_e64 s8, 0, v0
-; GISEL12-NEXT: s_wait_alu 0xf1ff
+; GISEL12-NEXT: s_wait_alu depctr_va_sdst(0)
; GISEL12-NEXT: v_mov_b32_e32 v0, s8
; GISEL12-NEXT: s_mov_b32 exec_lo, s4
; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -263,11 +263,11 @@ define amdgpu_cs_chain void @phi_whole_struct(<3 x i32> inreg %sgpr, ptr inreg %
; DAGISEL12-NEXT: s_or_saveexec_b32 s8, -1
; DAGISEL12-NEXT: s_mov_b32 s7, s4
; DAGISEL12-NEXT: s_mov_b32 s6, s3
-; DAGISEL12-NEXT: s_wait_alu 0xfffe
+; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: s_and_saveexec_b32 s3, s8
; DAGISEL12-NEXT: ; %bb.1: ; %shader
; DAGISEL12-NEXT: s_or_saveexec_b32 s4, -1
-; DAGISEL12-NEXT: s_wait_alu 0xfffe
+; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: v_cndmask_b32_e64 v0, 0x47, v12, s4
; DAGISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; DAGISEL12-NEXT: v_cmp_ne_u32_e64 s8, 0, v0
@@ -350,7 +350,7 @@ define amdgpu_cs_chain void @control_flow(<3 x i32> inreg %sgpr, ptr inreg %call
; GISEL12-NEXT: s_or_saveexec_b32 s8, -1
; GISEL12-NEXT: s_mov_b32 s6, s3
; GISEL12-NEXT: s_mov_b32 s7, s4
-; GISEL12-NEXT: s_wait_alu 0xfffe
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: s_and_saveexec_b32 s3, s8
; GISEL12-NEXT: s_cbranch_execz .LBB3_4
; GISEL12-NEXT: ; %bb.1: ; %shader.preheader
@@ -361,36 +361,36 @@ define amdgpu_cs_chain void @control_flow(<3 x i32> inreg %sgpr, ptr inreg %call
; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GISEL12-NEXT: v_add_nc_u32_e32 v1, 1, v1
; GISEL12-NEXT: s_or_saveexec_b32 s8, -1
-; GISEL12-NEXT: s_wait_alu 0xfffe
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: v_cndmask_b32_e64 v0, 0x47, v1, s8
; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GISEL12-NEXT: v_cmp_ne_u32_e64 s9, 0, v0
-; GISEL12-NEXT: s_wait_alu 0xf1ff
+; GISEL12-NEXT: s_wait_alu depctr_va_sdst(0)
; GISEL12-NEXT: v_mov_b32_e32 v0, s9
; GISEL12-NEXT: s_mov_b32 exec_lo, s8
; GISEL12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v13, v1
; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GISEL12-NEXT: v_mov_b32_e32 v11, v0
; GISEL12-NEXT: s_or_b32 s4, vcc_lo, s4
-; GISEL12-NEXT: s_wait_alu 0xfffe
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; GISEL12-NEXT: s_cbranch_execnz .LBB3_2
; GISEL12-NEXT: ; %bb.3: ; %tail.loopexit
; GISEL12-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GISEL12-NEXT: v_add_nc_u32_e32 v10, 42, v1
; GISEL12-NEXT: .LBB3_4: ; %Flow1
-; GISEL12-NEXT: s_wait_alu 0xfffe
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GISEL12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL12-NEXT: s_mov_b32 s3, exec_lo
; GISEL12-NEXT: ; implicit-def: $vgpr8
; GISEL12-NEXT: v_cmpx_lt_i32_e64 v12, v13
-; GISEL12-NEXT: s_wait_alu 0xfffe
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: s_xor_b32 s3, exec_lo, s3
; GISEL12-NEXT: ; %bb.5: ; %tail.else
; GISEL12-NEXT: s_or_saveexec_b32 s4, -1
; GISEL12-NEXT: v_mov_b32_e32 v0, 15
-; GISEL12-NEXT: s_wait_alu 0xfffe
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: s_mov_b32 exec_lo, s4
; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL12-NEXT: v_mov_b32_e32 v8, v0
@@ -398,7 +398,7 @@ define amdgpu_cs_chain void @control_flow(<3 x i32> inreg %sgpr, ptr inreg %call
; GISEL12-NEXT: s_and_not1_saveexec_b32 s3, s3
; GISEL12-NEXT: ; %bb.7: ; %tail.then
; GISEL12-NEXT: s_mov_b32 s4, 44
-; GISEL12-NEXT: s_wait_alu 0xfffe
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: v_mov_b32_e32 v8, s4
; GISEL12-NEXT: ; %bb.8: ; %tail.end
; GISEL12-NEXT: s_or_b32 exec_lo, exec_lo, s3
@@ -415,7 +415,7 @@ define amdgpu_cs_chain void @control_flow(<3 x i32> inreg %sgpr, ptr inreg %call
; DAGISEL12-NEXT: s_or_saveexec_b32 s8, -1
; DAGISEL12-NEXT: s_mov_b32 s7, s4
; DAGISEL12-NEXT: s_mov_b32 s6, s3
-; DAGISEL12-NEXT: s_wait_alu 0xfffe
+; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: s_and_saveexec_b32 s3, s8
; DAGISEL12-NEXT: s_cbranch_execz .LBB3_4
; DAGISEL12-NEXT: ; %bb.1: ; %shader.preheader
@@ -426,7 +426,7 @@ define amdgpu_cs_chain void @control_flow(<3 x i32> inreg %sgpr, ptr inreg %call
; DAGISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; DAGISEL12-NEXT: v_add_nc_u32_e32 v1, 1, v1
; DAGISEL12-NEXT: s_or_saveexec_b32 s8, -1
-; DAGISEL12-NEXT: s_wait_alu 0xfffe
+; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: v_cndmask_b32_e64 v0, 0x47, v1, s8
; DAGISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; DAGISEL12-NEXT: v_cmp_ne_u32_e64 s9, 0, v0
@@ -434,31 +434,31 @@ define amdgpu_cs_chain void @control_flow(<3 x i32> inreg %sgpr, ptr inreg %call
; DAGISEL12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v13, v1
; DAGISEL12-NEXT: v_mov_b32_e32 v11, s9
; DAGISEL12-NEXT: s_or_b32 s4, vcc_lo, s4
-; DAGISEL12-NEXT: s_wait_alu 0xfffe
+; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
; DAGISEL12-NEXT: s_cbranch_execnz .LBB3_2
; DAGISEL12-NEXT: ; %bb.3: ; %tail.loopexit
; DAGISEL12-NEXT: s_or_b32 exec_lo, exec_lo, s4
; DAGISEL12-NEXT: v_add_nc_u32_e32 v10, 42, v1
; DAGISEL12-NEXT: .LBB3_4: ; %Flow1
-; DAGISEL12-NEXT: s_wait_alu 0xfffe
+; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: s_or_b32 exec_lo, exec_lo, s3
; DAGISEL12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; DAGISEL12-NEXT: s_mov_b32 s3, exec_lo
; DAGISEL12-NEXT: ; implicit-def: $vgpr8
; DAGISEL12-NEXT: v_cmpx_lt_i32_e64 v12, v13
-; DAGISEL12-NEXT: s_wait_alu 0xfffe
+; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: s_xor_b32 s3, exec_lo, s3
; DAGISEL12-NEXT: ; %bb.5: ; %tail.else
; DAGISEL12-NEXT: s_mov_b32 s4, 15
-; DAGISEL12-NEXT: s_wait_alu 0xfffe
+; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: v_mov_b32_e32 v8, s4
; DAGISEL12-NEXT: ; %bb.6: ; %Flow
; DAGISEL12-NEXT: s_and_not1_saveexec_b32 s3, s3
; DAGISEL12-NEXT: ; %bb.7: ; %tail.then
; DAGISEL12-NEXT: v_mov_b32_e32 v8, 44
; DAGISEL12-NEXT: ; %bb.8: ; %tail.end
-; DAGISEL12-NEXT: s_wait_alu 0xfffe
+; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: s_or_b32 exec_lo, exec_lo, s3
; DAGISEL12-NEXT: s_mov_b32 exec_lo, s5
; DAGISEL12-NEXT: s_setpc_b64 s[6:7]
@@ -607,16 +607,16 @@ define amdgpu_cs_chain void @use_v0_7(<3 x i32> inreg %sgpr, ptr inreg %callee,
; GISEL12-NEXT: s_or_saveexec_b32 s8, -1
; GISEL12-NEXT: s_mov_b32 s6, s3
; GISEL12-NEXT: s_mov_b32 s7, s4
-; GISEL12-NEXT: s_wait_alu 0xfffe
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: s_and_saveexec_b32 s3, s8
; GISEL12-NEXT: s_cbranch_execz .LBB4_2
; GISEL12-NEXT: ; %bb.1: ; %shader
; GISEL12-NEXT: s_or_saveexec_b32 s4, -1
-; GISEL12-NEXT: s_wait_alu 0xfffe
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: v_cndmask_b32_e64 v13, 0x47, v12, s4
; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GISEL12-NEXT: v_cmp_ne_u32_e64 s8, 0, v13
-; GISEL12-NEXT: s_wait_alu 0xf1ff
+; GISEL12-NEXT: s_wait_alu depctr_va_sdst(0)
; GISEL12-NEXT: v_mov_b32_e32 v13, s8
; GISEL12-NEXT: s_mov_b32 exec_lo, s4
; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -625,7 +625,7 @@ define amdgpu_cs_chain void @use_v0_7(<3 x i32> inreg %sgpr, ptr inreg %callee,
; GISEL12-NEXT: ; use v0-7
; GISEL12-NEXT: ;;#ASMEND
; GISEL12-NEXT: .LBB4_2: ; %tail
-; GISEL12-NEXT: s_wait_alu 0xfffe
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GISEL12-NEXT: s_mov_b32 exec_lo, s5
; GISEL12-NEXT: s_setpc_b64 s[6:7]
@@ -640,12 +640,12 @@ define amdgpu_cs_chain void @use_v0_7(<3 x i32> inreg %sgpr, ptr inreg %callee,
; DAGISEL12-NEXT: s_or_saveexec_b32 s8, -1
; DAGISEL12-NEXT: s_mov_b32 s7, s4
; DAGISEL12-NEXT: s_mov_b32 s6, s3
-; DAGISEL12-NEXT: s_wait_alu 0xfffe
+; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: s_and_saveexec_b32 s3, s8
; DAGISEL12-NEXT: s_cbranch_execz .LBB4_2
; DAGISEL12-NEXT: ; %bb.1: ; %shader
; DAGISEL12-NEXT: s_or_saveexec_b32 s4, -1
-; DAGISEL12-NEXT: s_wait_alu 0xfffe
+; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: v_cndmask_b32_e64 v13, 0x47, v12, s4
; DAGISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; DAGISEL12-NEXT: v_cmp_ne_u32_e64 s8, 0, v13
@@ -655,7 +655,7 @@ define amdgpu_cs_chain void @use_v0_7(<3 x i32> inreg %sgpr, ptr inreg %callee,
; DAGISEL12-NEXT: ; use v0-7
; DAGISEL12-NEXT: ;;#ASMEND
; DAGISEL12-NEXT: .LBB4_2: ; %tail
-; DAGISEL12-NEXT: s_wait_alu 0xfffe
+; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: s_or_b32 exec_lo, exec_lo, s3
; DAGISEL12-NEXT: s_mov_b32 exec_lo, s5
; DAGISEL12-NEXT: s_setpc_b64 s[6:7]
@@ -758,17 +758,17 @@ define amdgpu_cs_chain void @wwm_write_to_arg_reg(<3 x i32> inreg %sgpr, ptr inr
; GISEL12-NEXT: v_dual_mov_b32 v34, v18 :: v_dual_mov_b32 v35, v19
; GISEL12-NEXT: v_dual_mov_b32 v36, v20 :: v_dual_mov_b32 v37, v21
; GISEL12-NEXT: v_dual_mov_b32 v38, v22 :: v_dual_mov_b32 v39, v23
-; GISEL12-NEXT: s_wait_alu 0xfffe
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: s_mov_b32 exec_lo, s12
; GISEL12-NEXT: s_and_saveexec_b32 s4, s9
; GISEL12-NEXT: s_cbranch_execz .LBB5_2
; GISEL12-NEXT: ; %bb.1: ; %shader
; GISEL12-NEXT: s_or_saveexec_b32 s9, -1
; GISEL12-NEXT: s_getpc_b64 s[0:1]
-; GISEL12-NEXT: s_wait_alu 0xfffe
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: s_sext_i32_i16 s1, s1
; GISEL12-NEXT: s_add_co_u32 s0, s0, write_v0_v15 at gotpcrel32@lo+12
-; GISEL12-NEXT: s_wait_alu 0xfffe
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: s_add_co_ci_u32 s1, s1, write_v0_v15 at gotpcrel32@hi+24
; GISEL12-NEXT: v_dual_mov_b32 v0, v24 :: v_dual_mov_b32 v1, v25
; GISEL12-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
@@ -799,7 +799,7 @@ define amdgpu_cs_chain void @wwm_write_to_arg_reg(<3 x i32> inreg %sgpr, ptr inr
; GISEL12-NEXT: v_dual_mov_b32 v36, v52 :: v_dual_mov_b32 v37, v53
; GISEL12-NEXT: v_dual_mov_b32 v38, v54 :: v_dual_mov_b32 v39, v55
; GISEL12-NEXT: .LBB5_2: ; %tail
-; GISEL12-NEXT: s_wait_alu 0xfffe
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GISEL12-NEXT: v_dual_mov_b32 v8, v24 :: v_dual_mov_b32 v9, v25
; GISEL12-NEXT: v_dual_mov_b32 v10, v26 :: v_dual_mov_b32 v11, v27
@@ -813,7 +813,7 @@ define amdgpu_cs_chain void @wwm_write_to_arg_reg(<3 x i32> inreg %sgpr, ptr inr
; GISEL12-NEXT: s_mov_b32 s1, s7
; GISEL12-NEXT: s_mov_b32 s2, s8
; GISEL12-NEXT: s_mov_b32 exec_lo, s5
-; GISEL12-NEXT: s_wait_alu 0xfffe
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: s_setpc_b64 s[10:11]
;
; DAGISEL12-LABEL: wwm_write_to_arg_reg:
@@ -834,7 +834,7 @@ define amdgpu_cs_chain void @wwm_write_to_arg_reg(<3 x i32> inreg %sgpr, ptr inr
; DAGISEL12-NEXT: v_dual_mov_b32 v29, v13 :: v_dual_mov_b32 v28, v12
; DAGISEL12-NEXT: v_dual_mov_b32 v27, v11 :: v_dual_mov_b32 v26, v10
; DAGISEL12-NEXT: v_dual_mov_b32 v25, v9 :: v_dual_mov_b32 v24, v8
-; DAGISEL12-NEXT: s_wait_alu 0xfffe
+; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: s_mov_b32 exec_lo, s6
; DAGISEL12-NEXT: s_mov_b32 s9, s4
; DAGISEL12-NEXT: s_mov_b32 s8, s3
@@ -846,10 +846,10 @@ define amdgpu_cs_chain void @wwm_write_to_arg_reg(<3 x i32> inreg %sgpr, ptr inr
; DAGISEL12-NEXT: ; %bb.1: ; %shader
; DAGISEL12-NEXT: s_or_saveexec_b32 s11, -1
; DAGISEL12-NEXT: s_getpc_b64 s[0:1]
-; DAGISEL12-NEXT: s_wait_alu 0xfffe
+; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: s_sext_i32_i16 s1, s1
; DAGISEL12-NEXT: s_add_co_u32 s0, s0, write_v0_v15 at gotpcrel32@lo+12
-; DAGISEL12-NEXT: s_wait_alu 0xfffe
+; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: s_add_co_ci_u32 s1, s1, write_v0_v15 at gotpcrel32@hi+24
; DAGISEL12-NEXT: v_dual_mov_b32 v0, v24 :: v_dual_mov_b32 v1, v25
; DAGISEL12-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
@@ -880,7 +880,7 @@ define amdgpu_cs_chain void @wwm_write_to_arg_reg(<3 x i32> inreg %sgpr, ptr inr
; DAGISEL12-NEXT: v_dual_mov_b32 v36, v52 :: v_dual_mov_b32 v37, v53
; DAGISEL12-NEXT: v_dual_mov_b32 v38, v54 :: v_dual_mov_b32 v39, v55
; DAGISEL12-NEXT: .LBB5_2: ; %tail
-; DAGISEL12-NEXT: s_wait_alu 0xfffe
+; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: s_or_b32 exec_lo, exec_lo, s10
; DAGISEL12-NEXT: v_dual_mov_b32 v8, v24 :: v_dual_mov_b32 v9, v25
; DAGISEL12-NEXT: v_dual_mov_b32 v10, v26 :: v_dual_mov_b32 v11, v27
@@ -894,7 +894,7 @@ define amdgpu_cs_chain void @wwm_write_to_arg_reg(<3 x i32> inreg %sgpr, ptr inr
; DAGISEL12-NEXT: s_mov_b32 s1, s6
; DAGISEL12-NEXT: s_mov_b32 s2, s4
; DAGISEL12-NEXT: s_mov_b32 exec_lo, s5
-; DAGISEL12-NEXT: s_wait_alu 0xfffe
+; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: s_setpc_b64 s[8:9]
;
; GISEL10-LABEL: wwm_write_to_arg_reg:
@@ -1155,7 +1155,7 @@ define amdgpu_cs_chain void @with_inactive_vgprs(ptr inreg %callee, i32 inreg %e
; GISEL12-NEXT: s_mov_b32 s4, s0
; GISEL12-NEXT: s_mov_b32 s5, s1
; GISEL12-NEXT: s_mov_b32 s0, s3
-; GISEL12-NEXT: s_wait_alu 0xfffe
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: s_and_saveexec_b32 s1, s6
; GISEL12-NEXT: s_cbranch_execz .LBB6_2
; GISEL12-NEXT: ; %bb.1: ; %shader
@@ -1169,7 +1169,7 @@ define amdgpu_cs_chain void @with_inactive_vgprs(ptr inreg %callee, i32 inreg %e
; GISEL12-NEXT: flat_store_b32 v[9:10], v11
; GISEL12-NEXT: ; implicit-def: $vgpr9
; GISEL12-NEXT: .LBB6_2: ; %tail.block
-; GISEL12-NEXT: s_wait_alu 0xfffe
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GISEL12-NEXT: s_mov_b32 exec_lo, s2
; GISEL12-NEXT: s_setpc_b64 s[4:5]
@@ -1184,7 +1184,7 @@ define amdgpu_cs_chain void @with_inactive_vgprs(ptr inreg %callee, i32 inreg %e
; DAGISEL12-NEXT: s_or_saveexec_b32 s6, -1
; DAGISEL12-NEXT: s_mov_b32 s5, s1
; DAGISEL12-NEXT: s_mov_b32 s4, s0
-; DAGISEL12-NEXT: s_wait_alu 0xfffe
+; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: s_and_saveexec_b32 s0, s6
; DAGISEL12-NEXT: s_cbranch_execz .LBB6_2
; DAGISEL12-NEXT: ; %bb.1: ; %shader
@@ -1198,11 +1198,11 @@ define amdgpu_cs_chain void @with_inactive_vgprs(ptr inreg %callee, i32 inreg %e
; DAGISEL12-NEXT: flat_store_b32 v[9:10], v11
; DAGISEL12-NEXT: ; implicit-def: $vgpr9
; DAGISEL12-NEXT: .LBB6_2: ; %tail.block
-; DAGISEL12-NEXT: s_wait_alu 0xfffe
+; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: s_or_b32 exec_lo, exec_lo, s0
; DAGISEL12-NEXT: s_mov_b32 s0, s3
; DAGISEL12-NEXT: s_mov_b32 exec_lo, s2
-; DAGISEL12-NEXT: s_wait_alu 0xfffe
+; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: s_setpc_b64 s[4:5]
;
; GISEL10-LABEL: with_inactive_vgprs:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
index 613d557636a86..5a27a72de274d 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
@@ -19,16 +19,16 @@ define amdgpu_cs_chain void @basic(<3 x i32> inreg %sgpr, ptr inreg %callee, i64
; GISEL12-NEXT: s_mov_b32 s9, s4
; GISEL12-NEXT: s_mov_b32 s4, s5
; GISEL12-NEXT: s_mov_b32 s5, s6
-; GISEL12-NEXT: s_wait_alu 0xfffe
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: s_and_saveexec_b64 s[6:7], s[10:11]
; GISEL12-NEXT: s_cbranch_execz .LBB0_2
; GISEL12-NEXT: ; %bb.1: ; %shader
; GISEL12-NEXT: s_or_saveexec_b64 s[10:11], -1
-; GISEL12-NEXT: s_wait_alu 0xfffe
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: v_cndmask_b32_e64 v0, 0x47, v13, s[10:11]
; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GISEL12-NEXT: v_cmp_ne_u32_e64 s[12:13], 0, v0
-; GISEL12-NEXT: s_wait_alu 0xf1ff
+; GISEL12-NEXT: s_wait_alu depctr_va_sdst(0)
; GISEL12-NEXT: v_mov_b32_e32 v0, s12
; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GISEL12-NEXT: v_mov_b32_e32 v1, s13
@@ -38,7 +38,7 @@ define amdgpu_cs_chain void @basic(<3 x i32> inreg %sgpr, ptr inreg %callee, i64
; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GISEL12-NEXT: v_mov_b32_e32 v12, v1
; GISEL12-NEXT: .LBB0_2: ; %tail
-; GISEL12-NEXT: s_wait_alu 0xfffe
+; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: s_or_b64 exec, exec, s[6:7]
; GISEL12-NEXT: s_mov_b64 exec, s[4:5]
; GISEL12-NEXT: s_setpc_b64 s[8:9]
@@ -55,11 +55,11 @@ define amdgpu_cs_chain void @basic(<3 x i32> inreg %sgpr, ptr inreg %callee, i64
; DAGISEL12-NEXT: s_mov_b32 s6, s5
; DAGISEL12-NEXT: s_mov_b32 s5, s4
; DAGISEL12-NEXT: s_mov_b32 s4, s3
-; DAGISEL12-NEXT: s_wait_alu 0xfffe
+; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: s_and_saveexec_b64 s[8:9], s[10:11]
; DAGISEL12-NEXT: ; %bb.1: ; %shader
; DAGISEL12-NEXT: s_or_saveexec_b64 s[10:11], -1
-; DAGISEL12-NEXT: s_wait_alu 0xfffe
+; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: v_cndmask_b32_e64 v0, 0x47, v13, s[10:11]
; DAGISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; DAGISEL12-NEXT: v_cmp_ne_u32_e64 s[12:13], 0, v0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
index 7a03a31acc634..614566a230f68 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
@@ -98,13 +98,13 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16(i32 inreg %node_ptr, f
; GFX12-SDAG-NEXT: s_lshr_b32 s2, s7, 16
; GFX12-SDAG-NEXT: s_lshr_b32 s3, s5, 16
; GFX12-SDAG-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v7, s1
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: s_pack_ll_b32_b16 s2, s3, s2
; GFX12-SDAG-NEXT: s_pack_ll_b32_b16 s3, s5, s7
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s3
; GFX12-SDAG-NEXT: s_pack_ll_b32_b16 s4, s6, s8
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s4
; GFX12-SDAG-NEXT: s_mov_b32 s15, s12
; GFX12-SDAG-NEXT: s_mov_b32 s14, s11
@@ -239,14 +239,14 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16(i64 inreg %node_ptr,
; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v7, s1
; GFX12-SDAG-NEXT: s_lshr_b32 s3, s6, 16
; GFX12-SDAG-NEXT: s_pack_ll_b32_b16 s1, s6, s8
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v3, s1
; GFX12-SDAG-NEXT: s_lshr_b32 s0, s8, 16
; GFX12-SDAG-NEXT: v_mov_b32_e32 v8, s2
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: s_pack_ll_b32_b16 s0, s3, s0
; GFX12-SDAG-NEXT: s_pack_ll_b32_b16 s3, s7, s9
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v5, s3
; GFX12-SDAG-NEXT: s_mov_b32 s15, s13
; GFX12-SDAG-NEXT: s_mov_b32 s14, s12
@@ -396,10 +396,10 @@ define amdgpu_kernel void @image_bvh_intersect_ray_nsa_reassign(ptr %p_node_ptr,
; GFX12-SDAG-NEXT: v_mov_b32_e32 v4, 4.0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_add_co_u32 v0, s0, s0, v2
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, s1, 0, s0
; GFX12-SDAG-NEXT: v_add_co_u32 v2, s0, s2, v2
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s0
; GFX12-SDAG-NEXT: flat_load_b32 v9, v[0:1]
; GFX12-SDAG-NEXT: flat_load_b32 v10, v[2:3]
@@ -436,11 +436,11 @@ define amdgpu_kernel void @image_bvh_intersect_ray_nsa_reassign(ptr %p_node_ptr,
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX12-GISEL-NEXT: flat_load_b32 v9, v[0:1]
; GFX12-GISEL-NEXT: flat_load_b32 v10, v[2:3]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s8
; GFX12-GISEL-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
; GFX12-GISEL-NEXT: v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v5, s10
@@ -549,10 +549,10 @@ define amdgpu_kernel void @image_bvh_intersect_ray_a16_nsa_reassign(ptr %p_node_
; GFX12-SDAG-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_add_co_u32 v0, s0, s0, v2
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, s1, 0, s0
; GFX12-SDAG-NEXT: v_add_co_u32 v2, s0, s2, v2
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s0
; GFX12-SDAG-NEXT: flat_load_b32 v6, v[0:1]
; GFX12-SDAG-NEXT: flat_load_b32 v7, v[2:3]
@@ -584,11 +584,11 @@ define amdgpu_kernel void @image_bvh_intersect_ray_a16_nsa_reassign(ptr %p_node_
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX12-GISEL-NEXT: flat_load_b32 v6, v[0:1]
; GFX12-GISEL-NEXT: flat_load_b32 v7, v[2:3]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s8
; GFX12-GISEL-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
; GFX12-GISEL-NEXT: v_dual_mov_b32 v4, s9 :: v_dual_mov_b32 v5, s10
@@ -753,7 +753,7 @@ define amdgpu_kernel void @image_bvh64_intersect_ray_nsa_reassign(ptr %p_ray, <4
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-GISEL-NEXT: flat_load_b32 v11, v[0:1]
; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT: image_bvh64_intersect_ray v[0:3], [v[9:10], v11, v[0:2], v[3:5], v[6:8]], s[0:3]
@@ -903,7 +903,7 @@ define amdgpu_kernel void @image_bvh64_intersect_ray_a16_nsa_reassign(ptr %p_ray
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-GISEL-NEXT: flat_load_b32 v8, v[0:1]
; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT: image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[0:2], v[3:5]], s[0:3] a16
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
index 114c81fedb963..193fbdf35ec74 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
@@ -192,7 +192,7 @@ define amdgpu_cs void @sgpr_inverse_ballot(i64 inreg %input, ptr addrspace(1) %o
; SDAG_W64: ; %bb.0: ; %entry
; SDAG_W64-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; SDAG_W64-NEXT: s_mov_b32 s0, 0
-; SDAG_W64-NEXT: s_waitcnt_depctr 0xfffe
+; SDAG_W64-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; SDAG_W64-NEXT: v_mov_b32_e32 v3, s0
; SDAG_W64-NEXT: global_store_b64 v[0:1], v[2:3], off
; SDAG_W64-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
index 8103140f2a587..d37a6c9319899 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
@@ -1185,7 +1185,7 @@ define amdgpu_ps void @fcmp_x2(float %a) #0 {
; GFX11-NEXT: v_cmp_lt_f32_e32 vcc, 0x3e800000, v0
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc
; GFX11-NEXT: v_cmp_nle_f32_e32 vcc, 0, v0
-; GFX11-NEXT: s_waitcnt_depctr 0xfffd
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc
; GFX11-NEXT: s_cbranch_scc0 .LBB21_1
; GFX11-NEXT: s_endpgm
@@ -1596,7 +1596,7 @@ define amdgpu_ps void @kill_with_loop_exit(float inreg %inp0, float inreg %inp1,
; GFX11-NEXT: s_mov_b64 s[2:3], exec
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX11-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xf1ff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_sdst(0)
; GFX11-NEXT: .LBB26_2: ; %bb
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: v_add_f32_e32 v0, 0x3e800000, v0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
index 4c6095ee594b0..22a198e415eed 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
@@ -537,7 +537,7 @@ define amdgpu_kernel void @v_permlane16_b32_vll_i32(ptr addrspace(1) %out, i32 %
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX12-NEXT: s_movk_i32 s2, 0x1234
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_permlane16_b32 v0, v0, s2, 0xc1d1
; GFX12-NEXT: global_store_b32 v1, v0, s[0:1]
@@ -609,7 +609,7 @@ define amdgpu_kernel void @v_permlane16_b32_vll_i64(ptr addrspace(1) %out, i64 %
; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s2
; GFX12-SDAG-NEXT: s_movk_i32 s2, 0x1234
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_permlane16_b32 v1, v1, s2, 0xc1d1
; GFX12-SDAG-NEXT: v_permlane16_b32 v0, v0, s2, 0xc1d1
@@ -623,7 +623,7 @@ define amdgpu_kernel void @v_permlane16_b32_vll_i64(ptr addrspace(1) %out, i64 %
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-GISEL-NEXT: s_movk_i32 s2, 0x1234
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_permlane16_b32 v0, v0, s2, 0xc1d1
; GFX12-GISEL-NEXT: v_permlane16_b32 v1, v1, s2, 0xc1d1
@@ -667,7 +667,7 @@ define amdgpu_kernel void @v_permlane16_b32_vll_f32(ptr addrspace(1) %out,float
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX12-NEXT: s_movk_i32 s2, 0x1234
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_permlane16_b32 v0, v0, s2, 0xc1d1
; GFX12-NEXT: global_store_b32 v1, v0, s[0:1]
@@ -739,7 +739,7 @@ define amdgpu_kernel void @v_permlane16_b32_vll_f64(ptr addrspace(1) %out, doubl
; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s2
; GFX12-SDAG-NEXT: s_movk_i32 s2, 0x1234
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_permlane16_b32 v1, v1, s2, 0xc1d1
; GFX12-SDAG-NEXT: v_permlane16_b32 v0, v0, s2, 0xc1d1
@@ -753,7 +753,7 @@ define amdgpu_kernel void @v_permlane16_b32_vll_f64(ptr addrspace(1) %out, doubl
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-GISEL-NEXT: s_movk_i32 s2, 0x1234
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_permlane16_b32 v0, v0, s2, 0xc1d1
; GFX12-GISEL-NEXT: v_permlane16_b32 v1, v1, s2, 0xc1d1
@@ -840,7 +840,7 @@ define amdgpu_kernel void @v_permlane16_b32_vvv_i32(ptr addrspace(1) %out, i32 %
; GFX12-SDAG-NEXT: v_mov_b32_e32 v1, s2
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s2, v0
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 0
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_permlane16_b32 v1, v1, s3, s2
; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
@@ -857,7 +857,7 @@ define amdgpu_kernel void @v_permlane16_b32_vvv_i32(ptr addrspace(1) %out, i32 %
; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_permlane16_b32 v0, v0, s3, s4
; GFX12-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
@@ -1018,7 +1018,7 @@ define amdgpu_kernel void @v_permlane16_b32_vvv_f32(ptr addrspace(1) %out, float
; GFX12-SDAG-NEXT: v_mov_b32_e32 v1, s2
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s2, v0
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 0
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_permlane16_b32 v1, v1, s3, s2
; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
@@ -1035,7 +1035,7 @@ define amdgpu_kernel void @v_permlane16_b32_vvv_f32(ptr addrspace(1) %out, float
; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_permlane16_b32 v0, v0, s3, s4
; GFX12-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
@@ -1176,7 +1176,7 @@ define amdgpu_kernel void @v_permlane16_b32_vvs_i32(ptr addrspace(1) %out, i32 %
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s2, v0
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 0
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_permlane16_b32 v1, v1, s2, s3
; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12-SDAG-NEXT: s_endpgm
@@ -1326,7 +1326,7 @@ define amdgpu_kernel void @v_permlane16_b32_vvs_f32(ptr addrspace(1) %out, float
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s2, v0
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 0
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_permlane16_b32 v1, v1, s2, s3
; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12-SDAG-NEXT: s_endpgm
@@ -1479,7 +1479,7 @@ define amdgpu_kernel void @v_permlane16_b32_vsv_i32(ptr addrspace(1) %out, i32 %
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s2, v0
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 0
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_permlane16_b32 v1, v1, s3, s2
; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12-SDAG-NEXT: s_endpgm
@@ -1667,7 +1667,7 @@ define amdgpu_kernel void @v_permlane16_b32_vsv_f32(ptr addrspace(1) %out, float
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s2, v0
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 0
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_permlane16_b32 v1, v1, s3, s2
; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12-SDAG-NEXT: s_endpgm
@@ -3102,7 +3102,7 @@ define amdgpu_kernel void @v_permlanex16_b32_vll_i32(ptr addrspace(1) %out, i32
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX12-NEXT: s_movk_i32 s2, 0x1234
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_permlanex16_b32 v0, v0, s2, 0xc1d1
; GFX12-NEXT: global_store_b32 v1, v0, s[0:1]
@@ -3145,7 +3145,7 @@ define amdgpu_kernel void @v_permlanex16_b32_vll_f32(ptr addrspace(1) %out, floa
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX12-NEXT: s_movk_i32 s2, 0x1234
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_permlanex16_b32 v0, v0, s2, 0xc1d1
; GFX12-NEXT: global_store_b32 v1, v0, s[0:1]
@@ -3217,7 +3217,7 @@ define amdgpu_kernel void @v_permlanex16_b32_vll_i64(ptr addrspace(1) %out, i64
; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s2
; GFX12-SDAG-NEXT: s_movk_i32 s2, 0x1234
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_permlanex16_b32 v1, v1, s2, 0xc1d1
; GFX12-SDAG-NEXT: v_permlanex16_b32 v0, v0, s2, 0xc1d1
@@ -3231,7 +3231,7 @@ define amdgpu_kernel void @v_permlanex16_b32_vll_i64(ptr addrspace(1) %out, i64
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-GISEL-NEXT: s_movk_i32 s2, 0x1234
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_permlanex16_b32 v0, v0, s2, 0xc1d1
; GFX12-GISEL-NEXT: v_permlanex16_b32 v1, v1, s2, 0xc1d1
@@ -3304,7 +3304,7 @@ define amdgpu_kernel void @v_permlanex16_b32_vll_f64(ptr addrspace(1) %out, doub
; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s2
; GFX12-SDAG-NEXT: s_movk_i32 s2, 0x1234
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_permlanex16_b32 v1, v1, s2, 0xc1d1
; GFX12-SDAG-NEXT: v_permlanex16_b32 v0, v0, s2, 0xc1d1
@@ -3318,7 +3318,7 @@ define amdgpu_kernel void @v_permlanex16_b32_vll_f64(ptr addrspace(1) %out, doub
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-GISEL-NEXT: s_movk_i32 s2, 0x1234
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_permlanex16_b32 v0, v0, s2, 0xc1d1
; GFX12-GISEL-NEXT: v_permlanex16_b32 v1, v1, s2, 0xc1d1
@@ -3405,7 +3405,7 @@ define amdgpu_kernel void @v_permlanex16_b32_vvv_i32(ptr addrspace(1) %out, i32
; GFX12-SDAG-NEXT: v_mov_b32_e32 v1, s2
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s2, v0
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 0
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_permlanex16_b32 v1, v1, s3, s2
; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
@@ -3422,7 +3422,7 @@ define amdgpu_kernel void @v_permlanex16_b32_vvv_i32(ptr addrspace(1) %out, i32
; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_permlanex16_b32 v0, v0, s3, s4
; GFX12-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
@@ -3510,7 +3510,7 @@ define amdgpu_kernel void @v_permlanex16_b32_vvv_f32(ptr addrspace(1) %out, floa
; GFX12-SDAG-NEXT: v_mov_b32_e32 v1, s2
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s2, v0
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 0
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_permlanex16_b32 v1, v1, s3, s2
; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
@@ -3527,7 +3527,7 @@ define amdgpu_kernel void @v_permlanex16_b32_vvv_f32(ptr addrspace(1) %out, floa
; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_permlanex16_b32 v0, v0, s3, s4
; GFX12-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
@@ -3741,7 +3741,7 @@ define amdgpu_kernel void @v_permlanex16_b32_vvs_i32(ptr addrspace(1) %out, i32
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s2, v0
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 0
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_permlanex16_b32 v1, v1, s2, s3
; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12-SDAG-NEXT: s_endpgm
@@ -3819,7 +3819,7 @@ define amdgpu_kernel void @v_permlanex16_b32_vvs_f32(ptr addrspace(1) %out, floa
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s2, v0
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 0
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_permlanex16_b32 v1, v1, s2, s3
; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12-SDAG-NEXT: s_endpgm
@@ -4044,7 +4044,7 @@ define amdgpu_kernel void @v_permlanex16_b32_vsv_i32(ptr addrspace(1) %out, i32
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s2, v0
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 0
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_permlanex16_b32 v1, v1, s3, s2
; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12-SDAG-NEXT: s_endpgm
@@ -4126,7 +4126,7 @@ define amdgpu_kernel void @v_permlanex16_b32_vsv_f32(ptr addrspace(1) %out, floa
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s2, v0
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 0
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_permlanex16_b32 v1, v1, s3, s2
; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12-SDAG-NEXT: s_endpgm
@@ -8570,7 +8570,7 @@ define void @v_permlane16_half(ptr addrspace(1) %out, half %src0, i32 %src1, i32
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_readfirstlane_b32 s0, v3
; GFX12-NEXT: v_readfirstlane_b32 s1, v4
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_permlane16_b32 v2, v2, s0, s1
; GFX12-NEXT: global_store_b16 v[0:1], v2, off
@@ -8609,7 +8609,7 @@ define void @v_permlanex16_half(ptr addrspace(1) %out, half %src0, i32 %src1, i3
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_readfirstlane_b32 s0, v3
; GFX12-NEXT: v_readfirstlane_b32 s1, v4
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_permlanex16_b32 v2, v2, s0, s1
; GFX12-NEXT: global_store_b16 v[0:1], v2, off
@@ -8648,7 +8648,7 @@ define void @v_permlane16_bfloat(ptr addrspace(1) %out, bfloat %src0, i32 %src1,
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_readfirstlane_b32 s0, v3
; GFX12-NEXT: v_readfirstlane_b32 s1, v4
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_permlane16_b32 v2, v2, s0, s1
; GFX12-NEXT: global_store_b16 v[0:1], v2, off
@@ -8687,7 +8687,7 @@ define void @v_permlanex16_bfloat(ptr addrspace(1) %out, bfloat %src0, i32 %src1
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_readfirstlane_b32 s0, v3
; GFX12-NEXT: v_readfirstlane_b32 s1, v4
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_permlanex16_b32 v2, v2, s0, s1
; GFX12-NEXT: global_store_b16 v[0:1], v2, off
@@ -8726,7 +8726,7 @@ define void @v_permlane16_i16(ptr addrspace(1) %out, i16 %src0, i32 %src1, i32 %
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_readfirstlane_b32 s0, v3
; GFX12-NEXT: v_readfirstlane_b32 s1, v4
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_permlane16_b32 v2, v2, s0, s1
; GFX12-NEXT: global_store_b16 v[0:1], v2, off
@@ -8765,7 +8765,7 @@ define void @v_permlanex16_i16(ptr addrspace(1) %out, i16 %src0, i32 %src1, i32
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_readfirstlane_b32 s0, v3
; GFX12-NEXT: v_readfirstlane_b32 s1, v4
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_permlanex16_b32 v2, v2, s0, s1
; GFX12-NEXT: global_store_b16 v[0:1], v2, off
@@ -8804,7 +8804,7 @@ define void @v_permlane16_v2f16(ptr addrspace(1) %out, <2 x half> %src0, i32 %sr
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_readfirstlane_b32 s0, v3
; GFX12-NEXT: v_readfirstlane_b32 s1, v4
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_permlane16_b32 v2, v2, s0, s1
; GFX12-NEXT: global_store_b32 v[0:1], v2, off
@@ -8843,7 +8843,7 @@ define void @v_permlanex16_v2f16(ptr addrspace(1) %out, <2 x half> %src0, i32 %s
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_readfirstlane_b32 s0, v3
; GFX12-NEXT: v_readfirstlane_b32 s1, v4
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_permlanex16_b32 v2, v2, s0, s1
; GFX12-NEXT: global_store_b32 v[0:1], v2, off
@@ -8905,7 +8905,7 @@ define void @v_permlane16_v2f32(ptr addrspace(1) %out, <2 x float> %src0, i32 %s
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v4
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v5
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlane16_b32 v3, v3, s0, s1
; GFX12-SDAG-NEXT: v_permlane16_b32 v2, v2, s0, s1
@@ -8921,7 +8921,7 @@ define void @v_permlane16_v2f32(ptr addrspace(1) %out, <2 x float> %src0, i32 %s
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v4
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v5
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_permlane16_b32 v2, v2, s0, s1
; GFX12-GISEL-NEXT: v_permlane16_b32 v3, v3, s0, s1
@@ -8984,7 +8984,7 @@ define void @v_permlanex16_v2f32(ptr addrspace(1) %out, <2 x float> %src0, i32 %
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v4
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v5
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlanex16_b32 v3, v3, s0, s1
; GFX12-SDAG-NEXT: v_permlanex16_b32 v2, v2, s0, s1
@@ -9000,7 +9000,7 @@ define void @v_permlanex16_v2f32(ptr addrspace(1) %out, <2 x float> %src0, i32 %
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v4
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v5
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_permlanex16_b32 v2, v2, s0, s1
; GFX12-GISEL-NEXT: v_permlanex16_b32 v3, v3, s0, s1
@@ -9089,7 +9089,7 @@ define void @v_permlane16_v7i32(ptr addrspace(1) %out, <7 x i32> %src0, i32 %src
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v9
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v10
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlane16_b32 v8, v8, s0, s1
; GFX12-SDAG-NEXT: v_permlane16_b32 v7, v7, s0, s1
@@ -9112,7 +9112,7 @@ define void @v_permlane16_v7i32(ptr addrspace(1) %out, <7 x i32> %src0, i32 %src
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v9
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v10
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_permlane16_b32 v2, v2, s0, s1
; GFX12-GISEL-NEXT: v_permlane16_b32 v3, v3, s0, s1
@@ -9208,7 +9208,7 @@ define void @v_permlanex16_v7i32(ptr addrspace(1) %out, <7 x i32> %src0, i32 %sr
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v9
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v10
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlanex16_b32 v8, v8, s0, s1
; GFX12-SDAG-NEXT: v_permlanex16_b32 v7, v7, s0, s1
@@ -9231,7 +9231,7 @@ define void @v_permlanex16_v7i32(ptr addrspace(1) %out, <7 x i32> %src0, i32 %sr
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v9
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v10
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_permlanex16_b32 v2, v2, s0, s1
; GFX12-GISEL-NEXT: v_permlanex16_b32 v3, v3, s0, s1
@@ -9309,7 +9309,7 @@ define void @v_permlane16_v8i16(ptr addrspace(1) %out, <8 x i16> %src0, i32 %src
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v6
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v7
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlane16_b32 v5, v5, s0, s1
; GFX12-SDAG-NEXT: v_permlane16_b32 v4, v4, s0, s1
@@ -9327,7 +9327,7 @@ define void @v_permlane16_v8i16(ptr addrspace(1) %out, <8 x i16> %src0, i32 %src
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v6
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v7
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_permlane16_b32 v2, v2, s0, s1
; GFX12-GISEL-NEXT: v_permlane16_b32 v3, v3, s0, s1
@@ -9400,7 +9400,7 @@ define void @v_permlanex16_v8i16(ptr addrspace(1) %out, <8 x i16> %src0, i32 %sr
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v6
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v7
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlanex16_b32 v5, v5, s0, s1
; GFX12-SDAG-NEXT: v_permlanex16_b32 v4, v4, s0, s1
@@ -9418,7 +9418,7 @@ define void @v_permlanex16_v8i16(ptr addrspace(1) %out, <8 x i16> %src0, i32 %sr
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v6
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v7
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_permlanex16_b32 v2, v2, s0, s1
; GFX12-GISEL-NEXT: v_permlanex16_b32 v3, v3, s0, s1
@@ -9491,7 +9491,7 @@ define void @v_permlane16_v2i64(ptr addrspace(1) %out, <2 x i64> %src0, i32 %src
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v6
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v7
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlane16_b32 v5, v5, s0, s1
; GFX12-SDAG-NEXT: v_permlane16_b32 v4, v4, s0, s1
@@ -9509,7 +9509,7 @@ define void @v_permlane16_v2i64(ptr addrspace(1) %out, <2 x i64> %src0, i32 %src
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v6
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v7
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_permlane16_b32 v2, v2, s0, s1
; GFX12-GISEL-NEXT: v_permlane16_b32 v3, v3, s0, s1
@@ -9596,7 +9596,7 @@ define void @v_permlane16_v3i64(ptr addrspace(1) %out, <3 x i64> %src0, i32 %src
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v8
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v9
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlane16_b32 v7, v7, s0, s1
; GFX12-SDAG-NEXT: v_permlane16_b32 v6, v6, s0, s1
@@ -9618,7 +9618,7 @@ define void @v_permlane16_v3i64(ptr addrspace(1) %out, <3 x i64> %src0, i32 %src
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v8
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v9
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_permlane16_b32 v2, v2, s0, s1
; GFX12-GISEL-NEXT: v_permlane16_b32 v3, v3, s0, s1
@@ -9717,7 +9717,7 @@ define void @v_permlane16_v4f64(ptr addrspace(1) %out, <4 x double> %src0, i32 %
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v10
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v11
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlane16_b32 v9, v9, s0, s1
; GFX12-SDAG-NEXT: v_permlane16_b32 v8, v8, s0, s1
@@ -9741,7 +9741,7 @@ define void @v_permlane16_v4f64(ptr addrspace(1) %out, <4 x double> %src0, i32 %
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v10
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v11
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_permlane16_b32 v2, v2, s0, s1
; GFX12-GISEL-NEXT: v_permlane16_b32 v3, v3, s0, s1
@@ -9882,7 +9882,7 @@ define void @v_permlane16_v8f64(ptr addrspace(1) %out, <8 x double> %src0, i32 %
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v18
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v19
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlane16_b32 v17, v17, s0, s1
; GFX12-SDAG-NEXT: v_permlane16_b32 v16, v16, s0, s1
@@ -9916,7 +9916,7 @@ define void @v_permlane16_v8f64(ptr addrspace(1) %out, <8 x double> %src0, i32 %
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v18
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v19
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_permlane16_b32 v2, v2, s0, s1
; GFX12-GISEL-NEXT: v_permlane16_b32 v3, v3, s0, s1
@@ -10005,7 +10005,7 @@ define void @v_permlanex16_v2i64(ptr addrspace(1) %out, <2 x i64> %src0, i32 %sr
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v6
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v7
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlanex16_b32 v5, v5, s0, s1
; GFX12-SDAG-NEXT: v_permlanex16_b32 v4, v4, s0, s1
@@ -10023,7 +10023,7 @@ define void @v_permlanex16_v2i64(ptr addrspace(1) %out, <2 x i64> %src0, i32 %sr
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v6
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v7
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_permlanex16_b32 v2, v2, s0, s1
; GFX12-GISEL-NEXT: v_permlanex16_b32 v3, v3, s0, s1
@@ -10110,7 +10110,7 @@ define void @v_permlanex16_v3i64(ptr addrspace(1) %out, <3 x i64> %src0, i32 %sr
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v8
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v9
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlanex16_b32 v7, v7, s0, s1
; GFX12-SDAG-NEXT: v_permlanex16_b32 v6, v6, s0, s1
@@ -10132,7 +10132,7 @@ define void @v_permlanex16_v3i64(ptr addrspace(1) %out, <3 x i64> %src0, i32 %sr
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v8
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v9
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_permlanex16_b32 v2, v2, s0, s1
; GFX12-GISEL-NEXT: v_permlanex16_b32 v3, v3, s0, s1
@@ -10231,7 +10231,7 @@ define void @v_permlanex16_v4f64(ptr addrspace(1) %out, <4 x double> %src0, i32
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v10
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v11
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlanex16_b32 v9, v9, s0, s1
; GFX12-SDAG-NEXT: v_permlanex16_b32 v8, v8, s0, s1
@@ -10255,7 +10255,7 @@ define void @v_permlanex16_v4f64(ptr addrspace(1) %out, <4 x double> %src0, i32
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v10
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v11
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_permlanex16_b32 v2, v2, s0, s1
; GFX12-GISEL-NEXT: v_permlanex16_b32 v3, v3, s0, s1
@@ -10396,7 +10396,7 @@ define void @v_permlanex16_v8f64(ptr addrspace(1) %out, <8 x double> %src0, i32
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v18
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v19
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlanex16_b32 v17, v17, s0, s1
; GFX12-SDAG-NEXT: v_permlanex16_b32 v16, v16, s0, s1
@@ -10430,7 +10430,7 @@ define void @v_permlanex16_v8f64(ptr addrspace(1) %out, <8 x double> %src0, i32
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v18
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v19
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_permlanex16_b32 v2, v2, s0, s1
; GFX12-GISEL-NEXT: v_permlanex16_b32 v3, v3, s0, s1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ptr.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ptr.ll
index 3d1359306fd65..5c91a61c4b092 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ptr.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ptr.ll
@@ -34,7 +34,7 @@ define void @v_permlane16_p0(ptr addrspace(1) %out, ptr %src0, i32 %src1, i32 %s
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v4
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v5
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlane16_b32 v3, v3, s0, s1
; GFX12-SDAG-NEXT: v_permlane16_b32 v2, v2, s0, s1
@@ -76,7 +76,7 @@ define void @v_permlanex16_p0(ptr addrspace(1) %out, ptr %src0, i32 %src1, i32 %
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v4
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v5
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlanex16_b32 v3, v3, s0, s1
; GFX12-SDAG-NEXT: v_permlanex16_b32 v2, v2, s0, s1
@@ -129,7 +129,7 @@ define void @v_permlane16_v3p0(ptr addrspace(1) %out, <3 x ptr> %src0, i32 %src1
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v8
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v9
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlane16_b32 v7, v7, s0, s1
; GFX12-SDAG-NEXT: v_permlane16_b32 v6, v6, s0, s1
@@ -188,7 +188,7 @@ define void @v_permlanex16_v3p0(ptr addrspace(1) %out, <3 x ptr> %src0, i32 %src
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v8
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v9
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlanex16_b32 v7, v7, s0, s1
; GFX12-SDAG-NEXT: v_permlanex16_b32 v6, v6, s0, s1
@@ -234,7 +234,7 @@ define void @v_permlane16_p3(ptr addrspace(1) %out, ptr addrspace(3) %src0, i32
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v3
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v4
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlane16_b32 v2, v2, s0, s1
; GFX12-SDAG-NEXT: global_store_b32 v[0:1], v2, off
@@ -273,7 +273,7 @@ define void @v_permlanex16_p3(ptr addrspace(1) %out, ptr addrspace(3) %src0, i32
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v3
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v4
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlanex16_b32 v2, v2, s0, s1
; GFX12-SDAG-NEXT: global_store_b32 v[0:1], v2, off
@@ -316,7 +316,7 @@ define void @v_permlane16_v3p3(ptr addrspace(1) %out, <3 x ptr addrspace(3)> %sr
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v5
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v6
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlane16_b32 v4, v4, s0, s1
; GFX12-SDAG-NEXT: v_permlane16_b32 v3, v3, s0, s1
@@ -361,7 +361,7 @@ define void @v_permlanex16_v3p3(ptr addrspace(1) %out, <3 x ptr addrspace(3)> %s
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v5
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v6
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlanex16_b32 v4, v4, s0, s1
; GFX12-SDAG-NEXT: v_permlanex16_b32 v3, v3, s0, s1
@@ -402,7 +402,7 @@ define void @v_permlane16_p5(ptr addrspace(1) %out, ptr addrspace(5) %src0, i32
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v3
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v4
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlane16_b32 v2, v2, s0, s1
; GFX12-SDAG-NEXT: global_store_b32 v[0:1], v2, off
@@ -441,7 +441,7 @@ define void @v_permlanex16_p5(ptr addrspace(1) %out, ptr addrspace(5) %src0, i32
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v3
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v4
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlanex16_b32 v2, v2, s0, s1
; GFX12-SDAG-NEXT: global_store_b32 v[0:1], v2, off
@@ -484,7 +484,7 @@ define void @v_permlane16_v3p5(ptr addrspace(1) %out, <3 x ptr addrspace(5)> %sr
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v5
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v6
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlane16_b32 v4, v4, s0, s1
; GFX12-SDAG-NEXT: v_permlane16_b32 v3, v3, s0, s1
@@ -529,7 +529,7 @@ define void @v_permlanex16_v3p5(ptr addrspace(1) %out, <3 x ptr addrspace(5)> %s
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v5
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v6
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlanex16_b32 v4, v4, s0, s1
; GFX12-SDAG-NEXT: v_permlanex16_b32 v3, v3, s0, s1
@@ -570,7 +570,7 @@ define void @v_permlane16_p6(ptr addrspace(1) %out, ptr addrspace(6) %src0, i32
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v3
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v4
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlane16_b32 v2, v2, s0, s1
; GFX12-SDAG-NEXT: global_store_b32 v[0:1], v2, off
@@ -609,7 +609,7 @@ define void @v_permlanex16_p6(ptr addrspace(1) %out, ptr addrspace(6) %src0, i32
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v3
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v4
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlanex16_b32 v2, v2, s0, s1
; GFX12-SDAG-NEXT: global_store_b32 v[0:1], v2, off
@@ -652,7 +652,7 @@ define void @v_permlane16_v3p6(ptr addrspace(1) %out, <3 x ptr addrspace(6)> %sr
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v5
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v6
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlane16_b32 v4, v4, s0, s1
; GFX12-SDAG-NEXT: v_permlane16_b32 v3, v3, s0, s1
@@ -697,7 +697,7 @@ define void @v_permlanex16_v3p6(ptr addrspace(1) %out, <3 x ptr addrspace(6)> %s
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v5
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v6
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_permlanex16_b32 v4, v4, s0, s1
; GFX12-SDAG-NEXT: v_permlanex16_b32 v3, v3, s0, s1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
index 2c3b5210ae7bd..874b336a929a5 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
@@ -111,15 +111,15 @@ define <2 x bfloat> @raw_ptr_buffer_atomic_add_v2bf16_rtn__vgpr_val__vgpr_rsrc__
; GFX1200-NEXT: v_readfirstlane_b32 s6, v3
; GFX1200-NEXT: v_readfirstlane_b32 s7, v4
; GFX1200-NEXT: v_readfirstlane_b32 s3, v6
-; GFX1200-NEXT: s_wait_alu 0xf1ff
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[1:2]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[3:4]
; GFX1200-NEXT: v_cmp_eq_u32_e64 s1, s3, v6
; GFX1200-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_b32 s0, s0, s1
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_saveexec_b32 s0, s0
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: buffer_atomic_pk_add_bf16 v0, v5, s[4:7], s3 offen offset:128 th:TH_ATOMIC_RETURN
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
index 2cb1811ff4f09..83b0847cd2589 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
@@ -445,7 +445,7 @@ define amdgpu_kernel void @divergent_value(ptr addrspace(1) %out) {
; GFX12DAGISEL-NEXT: s_mov_b32 s2, 0
; GFX12DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s4, s3
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: v_readlane_b32 s5, v0, s4
; GFX12DAGISEL-NEXT: s_bitset0_b32 s3, s4
; GFX12DAGISEL-NEXT: s_add_co_i32 s2, s2, s5
@@ -958,11 +958,11 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX12DAGISEL-NEXT: s_mov_b32 s1, 0
; GFX12DAGISEL-NEXT: .LBB2_4: ; =>This Inner Loop Header: Depth=1
; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s3, s2
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: v_readlane_b32 s6, v0, s3
; GFX12DAGISEL-NEXT: s_bitset0_b32 s2, s3
; GFX12DAGISEL-NEXT: s_add_co_i32 s1, s1, s6
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_cmp_lg_u32 s2, 0
; GFX12DAGISEL-NEXT: s_cbranch_scc1 .LBB2_4
; GFX12DAGISEL-NEXT: ; %bb.5:
@@ -1466,18 +1466,18 @@ define void @divergent_value_i64(ptr addrspace(1) %out, i64 %id.x) {
; GFX12DAGISEL-NEXT: s_mov_b64 s[0:1], 0
; GFX12DAGISEL-NEXT: s_mov_b32 s2, exec_lo
; GFX12DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s3, s2
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: v_readlane_b32 s4, v2, s3
; GFX12DAGISEL-NEXT: v_readlane_b32 s5, v3, s3
; GFX12DAGISEL-NEXT: s_bitset0_b32 s2, s3
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_cmp_lg_u32 s2, 0
; GFX12DAGISEL-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5]
; GFX12DAGISEL-NEXT: s_cbranch_scc1 .LBB4_1
; GFX12DAGISEL-NEXT: ; %bb.2:
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX12DAGISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX12DAGISEL-NEXT: s_setpc_b64 s[30:31]
@@ -1993,7 +1993,7 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX12DAGISEL-NEXT: s_mul_hi_u32 s6, s4, s3
; GFX12DAGISEL-NEXT: s_mul_i32 s5, s5, s3
; GFX12DAGISEL-NEXT: s_mul_i32 s4, s4, s3
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_add_co_u32 s5, s6, s5
; GFX12DAGISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
; GFX12DAGISEL-NEXT: ; %bb.4: ; %endif
@@ -2221,7 +2221,7 @@ define amdgpu_kernel void @uniform_value_float(ptr addrspace(1) %out, float %in)
; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12DAGISEL-NEXT: v_mul_f32_e32 v0, s2, v0
; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12DAGISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12DAGISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX12DAGISEL-NEXT: global_store_b32 v0, v1, s[0:1]
@@ -2475,19 +2475,19 @@ define void @divergent_value_float(ptr addrspace(1) %out, float %id.x) {
; GFX12DAGISEL-NEXT: s_mov_b32 s0, exec_lo
; GFX12DAGISEL-NEXT: s_brev_b32 s1, 1
; GFX12DAGISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s2, s0
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: v_readlane_b32 s3, v2, s2
; GFX12DAGISEL-NEXT: s_bitset0_b32 s0, s2
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_cmp_lg_u32 s0, 0
; GFX12DAGISEL-NEXT: v_add_f32_e64 v3, s1, s3
; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s1, v3
; GFX12DAGISEL-NEXT: s_cbranch_scc1 .LBB7_1
; GFX12DAGISEL-NEXT: ; %bb.2:
-; GFX12DAGISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12DAGISEL-NEXT: v_mov_b32_e32 v2, s1
; GFX12DAGISEL-NEXT: global_store_b32 v[0:1], v2, off
; GFX12DAGISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2980,19 +2980,19 @@ define amdgpu_kernel void @divergent_cfg_float(ptr addrspace(1) %out, float %in,
; GFX12DAGISEL-NEXT: s_or_saveexec_b32 s0, s2
; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12DAGISEL-NEXT: v_mov_b32_e32 v0, s3
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX12DAGISEL-NEXT: s_cbranch_execz .LBB8_4
; GFX12DAGISEL-NEXT: ; %bb.3: ; %if
; GFX12DAGISEL-NEXT: s_mov_b32 s2, exec_lo
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_bcnt1_i32_b32 s2, s2
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: v_cvt_f32_i32_e32 v0, s2
; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12DAGISEL-NEXT: v_mul_f32_e32 v0, s1, v0
; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s1, v0
-; GFX12DAGISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12DAGISEL-NEXT: v_mov_b32_e32 v0, s1
; GFX12DAGISEL-NEXT: .LBB8_4: ; %endif
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
index 50ec375d04626..e9a163c214011 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
@@ -460,7 +460,7 @@ define amdgpu_kernel void @divergent_value(ptr addrspace(1) %out) {
; GFX12DAGISEL-NEXT: s_mov_b32 s2, 0
; GFX12DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s4, s3
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: v_readlane_b32 s5, v0, s4
; GFX12DAGISEL-NEXT: s_bitset0_b32 s3, s4
; GFX12DAGISEL-NEXT: s_sub_co_i32 s2, s2, s5
@@ -986,11 +986,11 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX12DAGISEL-NEXT: s_mov_b32 s1, 0
; GFX12DAGISEL-NEXT: .LBB2_4: ; =>This Inner Loop Header: Depth=1
; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s3, s2
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: v_readlane_b32 s6, v0, s3
; GFX12DAGISEL-NEXT: s_bitset0_b32 s2, s3
; GFX12DAGISEL-NEXT: s_sub_co_i32 s1, s1, s6
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_cmp_lg_u32 s2, 0
; GFX12DAGISEL-NEXT: s_cbranch_scc1 .LBB2_4
; GFX12DAGISEL-NEXT: ; %bb.5:
@@ -1551,18 +1551,18 @@ define void @divergent_value_i64(ptr addrspace(1) %out, i64 %id.x) {
; GFX12DAGISEL-NEXT: s_mov_b64 s[0:1], 0
; GFX12DAGISEL-NEXT: s_mov_b32 s2, exec_lo
; GFX12DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s3, s2
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: v_readlane_b32 s4, v2, s3
; GFX12DAGISEL-NEXT: v_readlane_b32 s5, v3, s3
; GFX12DAGISEL-NEXT: s_bitset0_b32 s2, s3
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_cmp_lg_u32 s2, 0
; GFX12DAGISEL-NEXT: s_sub_nc_u64 s[0:1], s[0:1], s[4:5]
; GFX12DAGISEL-NEXT: s_cbranch_scc1 .LBB4_1
; GFX12DAGISEL-NEXT: ; %bb.2:
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX12DAGISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX12DAGISEL-NEXT: s_setpc_b64 s[30:31]
@@ -2189,11 +2189,11 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX12DAGISEL-NEXT: s_ashr_i32 s6, s3, 31
; GFX12DAGISEL-NEXT: s_mul_hi_u32 s7, s4, s3
; GFX12DAGISEL-NEXT: s_mul_i32 s5, s5, s3
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_mul_i32 s6, s4, s6
; GFX12DAGISEL-NEXT: s_add_co_u32 s5, s7, s5
; GFX12DAGISEL-NEXT: s_mul_i32 s4, s4, s3
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_add_co_u32 s5, s5, s6
; GFX12DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12DAGISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
@@ -2422,7 +2422,7 @@ define amdgpu_kernel void @uniform_value_float(ptr addrspace(1) %out, float %in)
; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12DAGISEL-NEXT: v_mul_f32_e64 v0, -s2, v0
; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12DAGISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12DAGISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX12DAGISEL-NEXT: global_store_b32 v0, v1, s[0:1]
@@ -2676,19 +2676,19 @@ define void @divergent_value_float(ptr addrspace(1) %out, float %id.x) {
; GFX12DAGISEL-NEXT: s_mov_b32 s0, exec_lo
; GFX12DAGISEL-NEXT: s_mov_b32 s1, 0
; GFX12DAGISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s2, s0
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: v_readlane_b32 s3, v2, s2
; GFX12DAGISEL-NEXT: s_bitset0_b32 s0, s2
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_cmp_lg_u32 s0, 0
; GFX12DAGISEL-NEXT: v_sub_f32_e64 v3, s1, s3
; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s1, v3
; GFX12DAGISEL-NEXT: s_cbranch_scc1 .LBB7_1
; GFX12DAGISEL-NEXT: ; %bb.2:
-; GFX12DAGISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12DAGISEL-NEXT: v_mov_b32_e32 v2, s1
; GFX12DAGISEL-NEXT: global_store_b32 v[0:1], v2, off
; GFX12DAGISEL-NEXT: s_setpc_b64 s[30:31]
@@ -3181,19 +3181,19 @@ define amdgpu_kernel void @divergent_cfg_float(ptr addrspace(1) %out, float %in,
; GFX12DAGISEL-NEXT: s_or_saveexec_b32 s0, s2
; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12DAGISEL-NEXT: v_mov_b32_e32 v0, s3
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX12DAGISEL-NEXT: s_cbranch_execz .LBB8_4
; GFX12DAGISEL-NEXT: ; %bb.3: ; %if
; GFX12DAGISEL-NEXT: s_mov_b32 s2, exec_lo
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_bcnt1_i32_b32 s2, s2
-; GFX12DAGISEL-NEXT: s_wait_alu 0xfffe
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: v_cvt_f32_i32_e32 v0, s2
; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12DAGISEL-NEXT: v_mul_f32_e64 v0, -s1, v0
; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s1, v0
-; GFX12DAGISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12DAGISEL-NEXT: v_mov_b32_e32 v0, s1
; GFX12DAGISEL-NEXT: .LBB8_4: ; %endif
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.ll
index 7ff13908eda4f..d92255e1bb1b7 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.ll
@@ -14,7 +14,7 @@ define i1 @func1() {
; GFX12-SDAG-NEXT: s_barrier_signal_isfirst -1
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: s_cselect_b32 s0, -1, 0
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -29,7 +29,7 @@ define i1 @func1() {
; GFX12-GISEL-NEXT: s_barrier_signal_isfirst -1
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: s_cselect_b32 s0, 1, 0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
%r = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)
@@ -48,7 +48,7 @@ define i1 @signal_isfirst_same_barrier_wait() {
; GFX12-SDAG-NEXT: s_barrier_signal_isfirst -1
; GFX12-SDAG-NEXT: s_barrier_wait -1
; GFX12-SDAG-NEXT: s_cselect_b32 s0, -1, 0
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -63,7 +63,7 @@ define i1 @signal_isfirst_same_barrier_wait() {
; GFX12-GISEL-NEXT: s_barrier_signal_isfirst -1
; GFX12-GISEL-NEXT: s_barrier_wait -1
; GFX12-GISEL-NEXT: s_cselect_b32 s0, 1, 0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
%r = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)
@@ -84,7 +84,7 @@ define i1 @signal_isfirst_
diff erent_barrier_wait() {
; GFX12-SDAG-NEXT: s_barrier_wait 0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: s_cselect_b32 s0, -1, 0
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -100,7 +100,7 @@ define i1 @signal_isfirst_
diff erent_barrier_wait() {
; GFX12-GISEL-NEXT: s_barrier_wait 0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: s_cselect_b32 s0, 1, 0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
%r = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
index 43323e70461c5..24fcb933bf801 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
@@ -25,7 +25,7 @@ define amdgpu_gs void @main(<4 x i32> %arg, i32 %arg1) {
; GFX10-NEXT: buffer_load_format_d16_xyz v[5:6], v4, s[4:7], 0 idxen
; GFX10-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX10-NEXT: ; implicit-def: $vgpr4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX10-NEXT: s_cbranch_execnz .LBB0_1
; GFX10-NEXT: ; %bb.2:
@@ -151,7 +151,7 @@ define amdgpu_gs void @main(<4 x i32> %arg, i32 %arg1) {
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-TRUE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
@@ -180,7 +180,7 @@ define amdgpu_gs void @main(<4 x i32> %arg, i32 %arg1) {
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-FAKE16-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
index 148a5ba75d98b..6921cca5a2394 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
@@ -47,15 +47,15 @@ define <2 x bfloat> @struct_ptr_buffer_atomic_add_v2bf16_rtn__vgpr_val__vgpr_rsr
; GFX1200-NEXT: v_readfirstlane_b32 s6, v3
; GFX1200-NEXT: v_readfirstlane_b32 s7, v4
; GFX1200-NEXT: v_readfirstlane_b32 s3, v7
-; GFX1200-NEXT: s_wait_alu 0xf1ff
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[1:2]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[3:4]
; GFX1200-NEXT: v_cmp_eq_u32_e64 s1, s3, v7
; GFX1200-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_b32 s0, s0, s1
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_saveexec_b32 s0, s0
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: buffer_atomic_pk_add_bf16 v0, v[5:6], s[4:7], s3 idxen offen th:TH_ATOMIC_RETURN
@@ -87,15 +87,15 @@ define void @struct_ptr_buffer_atomic_add_v2bf16_noret__vgpr_val__vgpr_rsrc__vgp
; GFX1200-NEXT: v_readfirstlane_b32 s6, v3
; GFX1200-NEXT: v_readfirstlane_b32 s7, v4
; GFX1200-NEXT: v_readfirstlane_b32 s3, v7
-; GFX1200-NEXT: s_wait_alu 0xf1ff
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[1:2]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[3:4]
; GFX1200-NEXT: v_cmp_eq_u32_e64 s1, s3, v7
; GFX1200-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_b32 s0, s0, s1
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_saveexec_b32 s0, s0
; GFX1200-NEXT: buffer_atomic_pk_add_bf16 v0, v[5:6], s[4:7], s3 idxen offen
; GFX1200-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
index 4366472c73a0e..d6e140c14d4cc 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
@@ -303,15 +303,15 @@ define void @struct_ptr_buffer_atomic_add_f32_noret__vgpr_val__vgpr_rsrc__vgpr_v
; GFX1200-NEXT: v_readfirstlane_b32 s6, v3
; GFX1200-NEXT: v_readfirstlane_b32 s7, v4
; GFX1200-NEXT: v_readfirstlane_b32 s3, v7
-; GFX1200-NEXT: s_wait_alu 0xf1ff
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[1:2]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[3:4]
; GFX1200-NEXT: v_cmp_eq_u32_e64 s1, s3, v7
; GFX1200-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_b32 s0, s0, s1
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_saveexec_b32 s0, s0
; GFX1200-NEXT: buffer_atomic_add_f32 v0, v[5:6], s[4:7], s3 idxen offen
; GFX1200-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4
@@ -477,15 +477,15 @@ define void @struct_ptr_buffer_atomic_add_v2f16_noret__vgpr_val__vgpr_rsrc__vgpr
; GFX1200-NEXT: v_readfirstlane_b32 s6, v3
; GFX1200-NEXT: v_readfirstlane_b32 s7, v4
; GFX1200-NEXT: v_readfirstlane_b32 s3, v7
-; GFX1200-NEXT: s_wait_alu 0xf1ff
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[1:2]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[3:4]
; GFX1200-NEXT: v_cmp_eq_u32_e64 s1, s3, v7
; GFX1200-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_b32 s0, s0, s1
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_saveexec_b32 s0, s0
; GFX1200-NEXT: buffer_atomic_pk_add_f16 v0, v[5:6], s[4:7], s3 idxen offen
; GFX1200-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
index 0191a85b33888..d99f1a4a5b996 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
@@ -252,15 +252,15 @@ define float @struct_ptr_buffer_atomic_add_f32_rtn__vgpr_val__vgpr_rsrc__vgpr_vo
; GFX1200-NEXT: v_readfirstlane_b32 s6, v3
; GFX1200-NEXT: v_readfirstlane_b32 s7, v4
; GFX1200-NEXT: v_readfirstlane_b32 s3, v7
-; GFX1200-NEXT: s_wait_alu 0xf1ff
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[1:2]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[3:4]
; GFX1200-NEXT: v_cmp_eq_u32_e64 s1, s3, v7
; GFX1200-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_b32 s0, s0, s1
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_saveexec_b32 s0, s0
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: buffer_atomic_add_f32 v0, v[5:6], s[4:7], s3 idxen offen th:TH_ATOMIC_RETURN
@@ -398,15 +398,15 @@ define <2 x half> @struct_ptr_buffer_atomic_add_v2f16_rtn__vgpr_val__vgpr_rsrc__
; GFX1200-NEXT: v_readfirstlane_b32 s6, v3
; GFX1200-NEXT: v_readfirstlane_b32 s7, v4
; GFX1200-NEXT: v_readfirstlane_b32 s3, v7
-; GFX1200-NEXT: s_wait_alu 0xf1ff
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[1:2]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[3:4]
; GFX1200-NEXT: v_cmp_eq_u32_e64 s1, s3, v7
; GFX1200-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_b32 s0, s0, s1
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_saveexec_b32 s0, s0
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: buffer_atomic_pk_add_f16 v0, v[5:6], s[4:7], s3 idxen offen th:TH_ATOMIC_RETURN
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
index d551d91e5ab12..3a6cea74de9e9 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
@@ -475,7 +475,7 @@ define float @struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__vgpr_rsrc__vgpr_vo
; GFX10-NEXT: buffer_atomic_fmax v0, v[5:6], s[8:11], s16 idxen offen offset:256 glc
; GFX10-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4
; GFX10-NEXT: ; implicit-def: $vgpr5_vgpr6
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB8_1
; GFX10-NEXT: ; %bb.2:
@@ -522,12 +522,12 @@ define float @struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__vgpr_rsrc__vgpr_vo
; GFX1200-NEXT: v_readfirstlane_b32 s5, v2
; GFX1200-NEXT: v_readfirstlane_b32 s6, v3
; GFX1200-NEXT: v_readfirstlane_b32 s7, v4
-; GFX1200-NEXT: s_wait_alu 0xf1ff
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[1:2]
; GFX1200-NEXT: v_cmp_eq_u64_e64 s1, s[6:7], v[3:4]
; GFX1200-NEXT: s_and_b32 s1, vcc_lo, s1
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_saveexec_b32 s1, s1
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: buffer_atomic_max_num_f32 v0, v[5:6], s[4:7], s0 idxen offen offset:256 th:TH_ATOMIC_RETURN
@@ -655,7 +655,7 @@ define float @struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_vo
; GFX10-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4
; GFX10-NEXT: ; implicit-def: $vgpr7
; GFX10-NEXT: ; implicit-def: $vgpr5_vgpr6
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB9_1
; GFX10-NEXT: ; %bb.2:
@@ -708,15 +708,15 @@ define float @struct_ptr_buffer_atomic_add_f32_ret__vgpr_val__sgpr_rsrc__vgpr_vo
; GFX1200-NEXT: v_readfirstlane_b32 s6, v3
; GFX1200-NEXT: v_readfirstlane_b32 s7, v4
; GFX1200-NEXT: v_readfirstlane_b32 s3, v7
-; GFX1200-NEXT: s_wait_alu 0xf1ff
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[1:2]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[3:4]
; GFX1200-NEXT: v_cmp_eq_u32_e64 s1, s3, v7
; GFX1200-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_b32 s0, s0, s1
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_saveexec_b32 s0, s0
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: buffer_atomic_max_num_f32 v0, v[5:6], s[4:7], s3 idxen offen offset:256 th:TH_ATOMIC_RETURN
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
index 0096289f39acc..a9f843f4a184a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
@@ -475,7 +475,7 @@ define float @struct_ptr_buffer_atomic_fmin_f32_ret__vgpr_val__vgpr_rsrc__vgpr_v
; GFX10-NEXT: buffer_atomic_fmin v0, v[5:6], s[8:11], s16 idxen offen offset:256 glc
; GFX10-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4
; GFX10-NEXT: ; implicit-def: $vgpr5_vgpr6
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB8_1
; GFX10-NEXT: ; %bb.2:
@@ -522,12 +522,12 @@ define float @struct_ptr_buffer_atomic_fmin_f32_ret__vgpr_val__vgpr_rsrc__vgpr_v
; GFX1200-NEXT: v_readfirstlane_b32 s5, v2
; GFX1200-NEXT: v_readfirstlane_b32 s6, v3
; GFX1200-NEXT: v_readfirstlane_b32 s7, v4
-; GFX1200-NEXT: s_wait_alu 0xf1ff
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[1:2]
; GFX1200-NEXT: v_cmp_eq_u64_e64 s1, s[6:7], v[3:4]
; GFX1200-NEXT: s_and_b32 s1, vcc_lo, s1
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_saveexec_b32 s1, s1
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: buffer_atomic_min_num_f32 v0, v[5:6], s[4:7], s0 idxen offen offset:256 th:TH_ATOMIC_RETURN
@@ -655,7 +655,7 @@ define float @struct_ptr_buffer_atomic_fmin_f32_ret__vgpr_val__sgpr_rsrc__vgpr_v
; GFX10-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4
; GFX10-NEXT: ; implicit-def: $vgpr7
; GFX10-NEXT: ; implicit-def: $vgpr5_vgpr6
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB9_1
; GFX10-NEXT: ; %bb.2:
@@ -708,15 +708,15 @@ define float @struct_ptr_buffer_atomic_fmin_f32_ret__vgpr_val__sgpr_rsrc__vgpr_v
; GFX1200-NEXT: v_readfirstlane_b32 s6, v3
; GFX1200-NEXT: v_readfirstlane_b32 s7, v4
; GFX1200-NEXT: v_readfirstlane_b32 s3, v7
-; GFX1200-NEXT: s_wait_alu 0xf1ff
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[1:2]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[3:4]
; GFX1200-NEXT: v_cmp_eq_u32_e64 s1, s3, v7
; GFX1200-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_b32 s0, s0, s1
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_saveexec_b32 s0, s0
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: buffer_atomic_min_num_f32 v0, v[5:6], s[4:7], s3 idxen offen offset:256 th:TH_ATOMIC_RETURN
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
index 0fbb302254294..f64f8a81a256f 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
@@ -22,7 +22,7 @@ define amdgpu_gs void @main(ptr addrspace(8) %arg, i32 %arg1) {
; GFX10-NEXT: buffer_load_format_d16_xyz v[5:6], v4, s[4:7], 0 idxen
; GFX10-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX10-NEXT: ; implicit-def: $vgpr4
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX10-NEXT: s_cbranch_execnz .LBB0_1
; GFX10-NEXT: ; %bb.2:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
index c95db198da4e7..2261556ead3c4 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
@@ -58,7 +58,7 @@ define amdgpu_gfx void @test_wave_id_callable(ptr addrspace(1) %out) {
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: s_bfe_u32 s0, ttmp8, 0x50019
-; GFX1200-NEXT: s_wait_alu 0xfffe
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_mov_b32_e32 v2, s0
; GFX1200-NEXT: global_store_b32 v[0:1], v2, off
; GFX1200-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
index 192b4983ed7f8..2752649550b69 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
@@ -673,7 +673,7 @@ define amdgpu_kernel void @test_writelane_vreg_lane_i32(ptr addrspace(1) %out, p
; GFX1010-SDAG-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX1010-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1010-SDAG-NEXT: global_load_dword v0, v0, s[2:3] offset:4
-; GFX1010-SDAG-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010-SDAG-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010-SDAG-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX1010-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1010-SDAG-NEXT: v_mov_b32_e32 v1, s2
@@ -736,7 +736,7 @@ define amdgpu_kernel void @test_writelane_vreg_lane_i32(ptr addrspace(1) %out, p
; GFX1010-GISEL-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX1010-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1010-GISEL-NEXT: global_load_dword v0, v0, s[2:3] offset:4
-; GFX1010-GISEL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010-GISEL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010-GISEL-NEXT: s_load_dword s2, s[0:1], 0x0
; GFX1010-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1010-GISEL-NEXT: v_mov_b32_e32 v1, s2
@@ -811,7 +811,7 @@ define amdgpu_kernel void @test_writelane_vreg_lane_i64(ptr addrspace(1) %out, p
; GFX1010-SDAG-NEXT: v_mov_b32_e32 v2, 0
; GFX1010-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1010-SDAG-NEXT: global_load_dword v0, v0, s[2:3] offset:8
-; GFX1010-SDAG-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010-SDAG-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
; GFX1010-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1010-SDAG-NEXT: v_mov_b32_e32 v1, s3
@@ -878,7 +878,7 @@ define amdgpu_kernel void @test_writelane_vreg_lane_i64(ptr addrspace(1) %out, p
; GFX1010-GISEL-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; GFX1010-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1010-GISEL-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3] offset:8
-; GFX1010-GISEL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010-GISEL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
; GFX1010-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1010-GISEL-NEXT: v_mov_b32_e32 v1, s2
@@ -958,7 +958,7 @@ define amdgpu_kernel void @test_writelane_vreg_lane_f64(ptr addrspace(1) %out, p
; GFX1010-SDAG-NEXT: v_mov_b32_e32 v2, 0
; GFX1010-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1010-SDAG-NEXT: global_load_dword v0, v0, s[2:3] offset:8
-; GFX1010-SDAG-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010-SDAG-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
; GFX1010-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1010-SDAG-NEXT: v_mov_b32_e32 v1, s3
@@ -1029,7 +1029,7 @@ define amdgpu_kernel void @test_writelane_vreg_lane_f64(ptr addrspace(1) %out, p
; GFX1010-GISEL-NEXT: v_lshlrev_b32_e32 v0, 4, v0
; GFX1010-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1010-GISEL-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3] offset:8
-; GFX1010-GISEL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010-GISEL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
; GFX1010-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX1010-GISEL-NEXT: v_mov_b32_e32 v1, s2
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
index 7d63e22d84b72..e5fcc2609333b 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
@@ -226,7 +226,7 @@ define amdgpu_kernel void @cos_v2f16(ptr addrspace(1) %r, ptr addrspace(1) %a) {
; GFX11-TRUE16-NEXT: v_cos_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cos_f16_e32 v0.h, v0.h
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
; GFX11-TRUE16-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
@@ -245,7 +245,7 @@ define amdgpu_kernel void @cos_v2f16(ptr addrspace(1) %r, ptr addrspace(1) %a) {
; GFX11-FAKE16-NEXT: v_cos_f16_e32 v1, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cos_f16_e32 v2, v2
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v1, v1, v2
; GFX11-FAKE16-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
index 2ead741b454d3..f3bca31e3fd9e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
@@ -20,7 +20,7 @@ define bfloat @v_exp2_bf16(bfloat %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 0x42800000, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v1, v0
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
@@ -32,7 +32,7 @@ define bfloat @v_exp2_bf16(bfloat %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
@@ -48,7 +48,7 @@ define bfloat @v_exp2_bf16(bfloat %in) {
; GFX1200-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: v_add_f32_e32 v0, v0, v2
@@ -60,7 +60,7 @@ define bfloat @v_exp2_bf16(bfloat %in) {
; GFX1200-SDAG-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX1200-SDAG-FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
@@ -95,7 +95,7 @@ define bfloat @v_exp2_fabs_bf16(bfloat %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_and_b16 v1.h, 0x7fff, v0.l
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 0x42800000, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v1, v0
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
@@ -107,7 +107,7 @@ define bfloat @v_exp2_fabs_bf16(bfloat %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
@@ -124,7 +124,7 @@ define bfloat @v_exp2_fabs_bf16(bfloat %in) {
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-SDAG-FAKE16-NEXT: v_add_f32_e32 v0, v0, v1
@@ -137,7 +137,7 @@ define bfloat @v_exp2_fabs_bf16(bfloat %in) {
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
@@ -173,7 +173,7 @@ define bfloat @v_exp2_fneg_fabs_bf16(bfloat %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_or_b16 v1.h, 0x8000, v0.l
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 0x42800000, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v1, v0
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
@@ -185,7 +185,7 @@ define bfloat @v_exp2_fneg_fabs_bf16(bfloat %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
@@ -202,7 +202,7 @@ define bfloat @v_exp2_fneg_fabs_bf16(bfloat %in) {
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-SDAG-FAKE16-NEXT: v_add_f32_e32 v0, v0, v1
@@ -215,7 +215,7 @@ define bfloat @v_exp2_fneg_fabs_bf16(bfloat %in) {
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
@@ -252,7 +252,7 @@ define bfloat @v_exp2_fneg_bf16(bfloat %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_xor_b16 v1.h, 0x8000, v0.l
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 0x42800000, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v1, v0
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
@@ -264,7 +264,7 @@ define bfloat @v_exp2_fneg_bf16(bfloat %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
@@ -281,7 +281,7 @@ define bfloat @v_exp2_fneg_bf16(bfloat %in) {
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-SDAG-FAKE16-NEXT: v_add_f32_e32 v0, v0, v1
@@ -294,7 +294,7 @@ define bfloat @v_exp2_fneg_bf16(bfloat %in) {
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
@@ -330,7 +330,7 @@ define bfloat @v_exp2_bf16_fast(bfloat %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 0x42800000, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v1, v0
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
@@ -342,7 +342,7 @@ define bfloat @v_exp2_bf16_fast(bfloat %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
@@ -358,7 +358,7 @@ define bfloat @v_exp2_bf16_fast(bfloat %in) {
; GFX1200-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: v_add_f32_e32 v0, v0, v2
@@ -370,7 +370,7 @@ define bfloat @v_exp2_bf16_fast(bfloat %in) {
; GFX1200-SDAG-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX1200-SDAG-FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
@@ -405,14 +405,14 @@ define <2 x bfloat> @v_exp2_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, s0
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v0, v3
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0
; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v0, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v1, v1, v2
@@ -430,11 +430,11 @@ define <2 x bfloat> @v_exp2_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX1200-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -450,14 +450,14 @@ define <2 x bfloat> @v_exp2_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v0
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, s0
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1200-SDAG-FAKE16-NEXT: v_add_f32_e32 v0, v0, v3
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0
; GFX1200-SDAG-FAKE16-NEXT: v_exp_f32_e32 v0, v0
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_add_f32_e32 v1, v1, v2
@@ -475,11 +475,11 @@ define <2 x bfloat> @v_exp2_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX1200-SDAG-FAKE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
; GFX1200-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -519,7 +519,7 @@ define <2 x bfloat> @v_exp2_fabs_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff0000, v0
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, s0
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-SDAG-TRUE16-NEXT: v_dual_add_f32 v0, v0, v3 :: v_dual_lshlrev_b32 v1, 16, v1
@@ -527,7 +527,7 @@ define <2 x bfloat> @v_exp2_fabs_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v0, v0
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v0, v3
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
@@ -545,10 +545,10 @@ define <2 x bfloat> @v_exp2_fabs_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
@@ -565,7 +565,7 @@ define <2 x bfloat> @v_exp2_fabs_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0x7fff0000, v0
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: v_add_f32_e32 v0, v0, v2
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
@@ -577,11 +577,11 @@ define <2 x bfloat> @v_exp2_fabs_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX1200-SDAG-FAKE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_dual_cndmask_b32 v0, v2, v4 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v1
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, s0
; GFX1200-SDAG-FAKE16-NEXT: v_add_f32_e32 v1, v1, v3
@@ -594,7 +594,7 @@ define <2 x bfloat> @v_exp2_fabs_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX1200-SDAG-FAKE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
@@ -642,7 +642,7 @@ define <2 x bfloat> @v_exp2_fneg_fabs_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_xor_b16 v2.h, 0x8000, v1.l
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v2
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
@@ -652,7 +652,7 @@ define <2 x bfloat> @v_exp2_fneg_fabs_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v1, v1
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v2
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 0x42800000, s0
; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v1, v1, v3
@@ -671,10 +671,10 @@ define <2 x bfloat> @v_exp2_fneg_fabs_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
@@ -694,7 +694,7 @@ define <2 x bfloat> @v_exp2_fneg_fabs_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v0
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, s0
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1200-SDAG-FAKE16-NEXT: v_add_f32_e32 v0, v0, v3
@@ -706,7 +706,7 @@ define <2 x bfloat> @v_exp2_fneg_fabs_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1200-SDAG-FAKE16-NEXT: v_ldexp_f32 v0, v0, v3
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
@@ -722,11 +722,11 @@ define <2 x bfloat> @v_exp2_fneg_fabs_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX1200-SDAG-FAKE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
; GFX1200-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -773,13 +773,13 @@ define <2 x bfloat> @v_exp2_fneg_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_xor_b16 v1.h, 0x8000, v0.l
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v2, v1, v2
; GFX1200-SDAG-TRUE16-NEXT: v_xor_b16 v1.h, 0x8000, v0.h
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v1
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 0x42800000, s0
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
@@ -800,10 +800,10 @@ define <2 x bfloat> @v_exp2_fneg_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
@@ -823,7 +823,7 @@ define <2 x bfloat> @v_exp2_fneg_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v1
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, s0
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_dual_add_f32 v1, v1, v3 :: v_dual_lshlrev_b32 v0, 16, v0
@@ -831,7 +831,7 @@ define <2 x bfloat> @v_exp2_fneg_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_exp_f32_e32 v1, v1
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: v_add_f32_e32 v0, v0, v2
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
@@ -849,10 +849,10 @@ define <2 x bfloat> @v_exp2_fneg_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
@@ -894,14 +894,14 @@ define <2 x bfloat> @v_exp2_v2bf16_fast(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, s0
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v0, v3
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0
; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v0, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v1, v1, v2
@@ -919,11 +919,11 @@ define <2 x bfloat> @v_exp2_v2bf16_fast(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX1200-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -939,14 +939,14 @@ define <2 x bfloat> @v_exp2_v2bf16_fast(<2 x bfloat> %in) {
; GFX1200-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v0
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, s0
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1200-SDAG-FAKE16-NEXT: v_add_f32_e32 v0, v0, v3
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0
; GFX1200-SDAG-FAKE16-NEXT: v_exp_f32_e32 v0, v0
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_add_f32_e32 v1, v1, v2
@@ -964,11 +964,11 @@ define <2 x bfloat> @v_exp2_v2bf16_fast(<2 x bfloat> %in) {
; GFX1200-SDAG-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX1200-SDAG-FAKE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX1200-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
; GFX1200-SDAG-FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x7060302
; GFX1200-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log.ll b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
index fc6b2d95b2af8..7c06ae2f39f45 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
@@ -203,7 +203,7 @@ define amdgpu_kernel void @s_log_f32(ptr addrspace(1) %out, float %in) {
; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317217, v1
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
; GFX1100-SDAG-NEXT: v_fma_f32 v3, 0x3f317217, v1, -v2
@@ -229,7 +229,7 @@ define amdgpu_kernel void @s_log_f32(ptr addrspace(1) %out, float %in) {
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -599,7 +599,7 @@ define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, v1
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v3, v3
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v4, 0x3f317217, v1
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v5, 0x3f317217, v3
@@ -631,7 +631,7 @@ define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s3, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_dual_mul_f32 v3, 0x3f317217, v1 :: v_dual_lshlrev_b32 v0, 5, v0
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -639,7 +639,7 @@ define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v5, 0x3377d1cf, v1
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_dual_add_f32 v3, v3, v5 :: v_dual_mul_f32 v2, 0x3f317217, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 0x41b17218, s5
@@ -1152,7 +1152,7 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v5, v5
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_dual_mul_f32 v6, 0x3f317217, v2 :: v_dual_mul_f32 v7, 0x3f317217, v4
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
; GFX1100-SDAG-NEXT: v_fma_f32 v9, 0x3f317217, v2, -v6
@@ -1197,7 +1197,7 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, v2
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_dual_mul_f32 v5, 0x3f317217, v2 :: v_dual_lshlrev_b32 v0, 5, v0
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -1206,7 +1206,7 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v8, 0x3377d1cf, v2
; GFX1100-GISEL-NEXT: v_add_f32_e32 v5, v5, v8
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v3, 0x3f317217, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1219,7 +1219,7 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 0x41b17218, s7
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317217, v1
; GFX1100-GISEL-NEXT: v_fma_f32 v7, 0x3f317217, v1, -v4
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1875,7 +1875,7 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
; GFX1100-SDAG-NEXT: v_dual_mul_f32 v8, 0x3f317217, v2 :: v_dual_mul_f32 v9, 0x3f317217, v3
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_dual_mul_f32 v10, 0x3f317217, v6 :: v_dual_mul_f32 v11, 0x3f317217, v7
; GFX1100-SDAG-NEXT: v_fma_f32 v12, 0x3f317217, v2, -v8
; GFX1100-SDAG-NEXT: v_fma_f32 v13, 0x3f317217, v3, -v9
@@ -1930,7 +1930,7 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
; GFX1100-GISEL-NEXT: v_log_f32_e32 v3, v3
; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317217, v2
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v8, 0x3f317217, v3
@@ -1943,7 +1943,7 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v12, 0x3377d1cf, v2 :: v_dual_fmac_f32 v13, 0x3377d1cf, v3
; GFX1100-GISEL-NEXT: v_add_f32_e32 v7, v7, v12
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317217, v1
@@ -2303,7 +2303,7 @@ define float @v_log_f32(float %in) {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -2327,7 +2327,7 @@ define float @v_log_f32(float %in) {
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
@@ -2504,7 +2504,7 @@ define float @v_log_fabs_f32(float %in) {
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, |v0|, v1
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
@@ -2527,7 +2527,7 @@ define float @v_log_fabs_f32(float %in) {
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -2706,7 +2706,7 @@ define float @v_log_fneg_fabs_f32(float %in) {
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, -|v0|, v1
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
@@ -2729,7 +2729,7 @@ define float @v_log_fneg_fabs_f32(float %in) {
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, -|v0|, v1
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -2908,7 +2908,7 @@ define float @v_log_fneg_f32(float %in) {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, -v0, v1
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -2932,7 +2932,7 @@ define float @v_log_fneg_f32(float %in) {
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, -v0, v1
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -3048,7 +3048,7 @@ define float @v_log_f32_fast(float %in) {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_fmamk_f32 v0, v0, 0x3f317218, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3058,7 +3058,7 @@ define float @v_log_f32_fast(float %in) {
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc1b17218, vcc_lo
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3f317218, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -3225,7 +3225,7 @@ define float @v_log_f32_ninf(float %in) {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -3249,7 +3249,7 @@ define float @v_log_f32_ninf(float %in) {
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
@@ -3363,7 +3363,7 @@ define float @v_log_f32_afn(float %in) {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_fmamk_f32 v0, v0, 0x3f317218, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3373,7 +3373,7 @@ define float @v_log_f32_afn(float %in) {
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc1b17218, vcc_lo
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3f317218, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -3402,7 +3402,7 @@ define float @v_log_f32_afn_daz(float %in) #0 {
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
@@ -3507,7 +3507,7 @@ define float @v_log_f32_afn_dynamic(float %in) #1 {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_fmamk_f32 v0, v0, 0x3f317218, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3517,7 +3517,7 @@ define float @v_log_f32_afn_dynamic(float %in) #1 {
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc1b17218, vcc_lo
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3f317218, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -3623,7 +3623,7 @@ define float @v_fabs_log_f32_afn(float %in) {
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, |v0|, v2
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_fmamk_f32 v0, v0, 0x3f317218, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3634,7 +3634,7 @@ define float @v_fabs_log_f32_afn(float %in) {
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc1b17218, s0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3f317218, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -3753,7 +3753,7 @@ define float @v_log_f32_daz(float %in) #0 {
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -3768,7 +3768,7 @@ define float @v_log_f32_daz(float %in) #0 {
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -3942,7 +3942,7 @@ define float @v_log_f32_nnan(float %in) {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -3966,7 +3966,7 @@ define float @v_log_f32_nnan(float %in) {
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
@@ -4093,7 +4093,7 @@ define float @v_log_f32_nnan_daz(float %in) #0 {
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4108,7 +4108,7 @@ define float @v_log_f32_nnan_daz(float %in) #0 {
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4282,7 +4282,7 @@ define float @v_log_f32_nnan_dynamic(float %in) #1 {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4306,7 +4306,7 @@ define float @v_log_f32_nnan_dynamic(float %in) #1 {
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
@@ -4433,7 +4433,7 @@ define float @v_log_f32_ninf_daz(float %in) #0 {
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4448,7 +4448,7 @@ define float @v_log_f32_ninf_daz(float %in) #0 {
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4622,7 +4622,7 @@ define float @v_log_f32_ninf_dynamic(float %in) #1 {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4646,7 +4646,7 @@ define float @v_log_f32_ninf_dynamic(float %in) #1 {
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
@@ -4804,7 +4804,7 @@ define float @v_log_f32_nnan_ninf(float %in) {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
@@ -4825,7 +4825,7 @@ define float @v_log_f32_nnan_ninf(float %in) {
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4917,7 +4917,7 @@ define float @v_log_f32_nnan_ninf_daz(float %in) #0 {
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
@@ -4930,7 +4930,7 @@ define float @v_log_f32_nnan_ninf_daz(float %in) #0 {
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
@@ -5084,7 +5084,7 @@ define float @v_log_f32_nnan_ninf_dynamic(float %in) #1 {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
@@ -5105,7 +5105,7 @@ define float @v_log_f32_nnan_ninf_dynamic(float %in) #1 {
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -5141,7 +5141,7 @@ define float @v_log_f32_fast_daz(float %in) #0 {
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
@@ -5308,7 +5308,7 @@ define float @v_log_f32_dynamic_mode(float %in) #1 {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -5332,7 +5332,7 @@ define float @v_log_f32_dynamic_mode(float %in) #1 {
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
@@ -5489,7 +5489,7 @@ define float @v_log_f32_0() {
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, 0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -5506,7 +5506,7 @@ define float @v_log_f32_0() {
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, 0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -5641,7 +5641,7 @@ define float @v_log_f32_from_fpext_f16(i16 %src.i) {
; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-SDAG-TRUE16-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
@@ -5658,7 +5658,7 @@ define float @v_log_f32_from_fpext_f16(i16 %src.i) {
; GFX1100-SDAG-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-SDAG-FAKE16-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
@@ -5675,7 +5675,7 @@ define float @v_log_f32_from_fpext_f16(i16 %src.i) {
; GFX1100-GISEL-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-GISEL-TRUE16-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-TRUE16-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
@@ -5692,7 +5692,7 @@ define float @v_log_f32_from_fpext_f16(i16 %src.i) {
; GFX1100-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-GISEL-FAKE16-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-FAKE16-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
@@ -5845,7 +5845,7 @@ define float @v_log_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -5863,7 +5863,7 @@ define float @v_log_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX1100-SDAG-FAKE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -5881,7 +5881,7 @@ define float @v_log_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-GISEL-TRUE16-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -5899,7 +5899,7 @@ define float @v_log_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-GISEL-FAKE16-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -6010,7 +6010,7 @@ define float @v_log_f32_from_fpext_bf16(bfloat %src) {
; GFX1100-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v1, v0
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-SDAG-TRUE16-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
@@ -6033,7 +6033,7 @@ define float @v_log_f32_from_fpext_bf16(bfloat %src) {
; GFX1100-SDAG-FAKE16-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-SDAG-FAKE16-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
@@ -6057,7 +6057,7 @@ define float @v_log_f32_from_fpext_bf16(bfloat %src) {
; GFX1100-GISEL-TRUE16-NEXT: v_ldexp_f32 v0, v1, v0
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-GISEL-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-GISEL-TRUE16-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
@@ -6080,7 +6080,7 @@ define float @v_log_f32_from_fpext_bf16(bfloat %src) {
; GFX1100-GISEL-FAKE16-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
; GFX1100-GISEL-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-GISEL-FAKE16-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
@@ -6146,7 +6146,7 @@ define half @v_log_f16(half %in) {
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6154,7 +6154,7 @@ define half @v_log_f16(half %in) {
; GFX1100-SDAG-FAKE16: ; %bb.0:
; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v0, v0
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6162,7 +6162,7 @@ define half @v_log_f16(half %in) {
; GFX1100-GISEL-TRUE16: ; %bb.0:
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6170,7 +6170,7 @@ define half @v_log_f16(half %in) {
; GFX1100-GISEL-FAKE16: ; %bb.0:
; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6226,7 +6226,7 @@ define half @v_log_fabs_f16(half %in) {
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.l, |v0.l|
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6234,7 +6234,7 @@ define half @v_log_fabs_f16(half %in) {
; GFX1100-SDAG-FAKE16: ; %bb.0:
; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e64 v0, |v0|
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6242,7 +6242,7 @@ define half @v_log_fabs_f16(half %in) {
; GFX1100-GISEL-TRUE16: ; %bb.0:
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e64 v0.l, |v0.l|
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6250,7 +6250,7 @@ define half @v_log_fabs_f16(half %in) {
; GFX1100-GISEL-FAKE16: ; %bb.0:
; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e64 v0, |v0|
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6307,7 +6307,7 @@ define half @v_log_fneg_fabs_f16(half %in) {
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.l, -|v0.l|
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6315,7 +6315,7 @@ define half @v_log_fneg_fabs_f16(half %in) {
; GFX1100-SDAG-FAKE16: ; %bb.0:
; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e64 v0, -|v0|
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6323,7 +6323,7 @@ define half @v_log_fneg_fabs_f16(half %in) {
; GFX1100-GISEL-TRUE16: ; %bb.0:
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e64 v0.l, -|v0.l|
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6331,7 +6331,7 @@ define half @v_log_fneg_fabs_f16(half %in) {
; GFX1100-GISEL-FAKE16: ; %bb.0:
; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e64 v0, -|v0|
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6389,7 +6389,7 @@ define half @v_log_fneg_f16(half %in) {
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.l, -v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6397,7 +6397,7 @@ define half @v_log_fneg_f16(half %in) {
; GFX1100-SDAG-FAKE16: ; %bb.0:
; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e64 v0, -v0
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6405,7 +6405,7 @@ define half @v_log_fneg_f16(half %in) {
; GFX1100-GISEL-TRUE16: ; %bb.0:
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e64 v0.l, -v0.l
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6413,7 +6413,7 @@ define half @v_log_fneg_f16(half %in) {
; GFX1100-GISEL-FAKE16: ; %bb.0:
; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e64 v0, -v0
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6468,7 +6468,7 @@ define half @v_log_f16_fast(half %in) {
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6476,7 +6476,7 @@ define half @v_log_f16_fast(half %in) {
; GFX1100-SDAG-FAKE16: ; %bb.0:
; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v0, v0
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6484,7 +6484,7 @@ define half @v_log_f16_fast(half %in) {
; GFX1100-GISEL-TRUE16: ; %bb.0:
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6492,7 +6492,7 @@ define half @v_log_f16_fast(half %in) {
; GFX1100-GISEL-FAKE16: ; %bb.0:
; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6577,7 +6577,7 @@ define <2 x half> @v_log_v2f16(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x398c, v0.h
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -6591,7 +6591,7 @@ define <2 x half> @v_log_v2f16(<2 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v1, v1
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX1100-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
@@ -6602,7 +6602,7 @@ define <2 x half> @v_log_v2f16(<2 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x398c, v0.h
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -6616,7 +6616,7 @@ define <2 x half> @v_log_v2f16(<2 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v1, v1
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
@@ -6720,7 +6720,7 @@ define <2 x half> @v_log_fabs_v2f16(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.l, |v0.l|
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.h, |v0.h|
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x398c, v0.h
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -6734,7 +6734,7 @@ define <2 x half> @v_log_fabs_v2f16(<2 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e64 v0, |v0|
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e64 v1, |v1|
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX1100-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
@@ -6747,7 +6747,7 @@ define <2 x half> @v_log_fabs_v2f16(<2 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x398c, v0.h
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -6762,7 +6762,7 @@ define <2 x half> @v_log_fabs_v2f16(<2 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v1, v1
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -6872,7 +6872,7 @@ define <2 x half> @v_log_fneg_fabs_v2f16(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.l, -|v0.l|
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.h, -|v0.h|
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x398c, v0.h
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -6886,7 +6886,7 @@ define <2 x half> @v_log_fneg_fabs_v2f16(<2 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e64 v0, -|v0|
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e64 v1, -|v1|
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX1100-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
@@ -6899,7 +6899,7 @@ define <2 x half> @v_log_fneg_fabs_v2f16(<2 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x398c, v0.h
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -6914,7 +6914,7 @@ define <2 x half> @v_log_fneg_fabs_v2f16(<2 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v1, v1
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -7025,7 +7025,7 @@ define <2 x half> @v_log_fneg_v2f16(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.l, -v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.h, -v0.h
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x398c, v0.h
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -7039,7 +7039,7 @@ define <2 x half> @v_log_fneg_v2f16(<2 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e64 v0, -v0
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e64 v1, -v1
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX1100-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
@@ -7052,7 +7052,7 @@ define <2 x half> @v_log_fneg_v2f16(<2 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x398c, v0.h
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -7067,7 +7067,7 @@ define <2 x half> @v_log_fneg_v2f16(<2 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v1, v1
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -7152,7 +7152,7 @@ define <2 x half> @v_log_v2f16_fast(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x398c, v0.h
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -7166,7 +7166,7 @@ define <2 x half> @v_log_v2f16_fast(<2 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v1, v1
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX1100-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
@@ -7177,7 +7177,7 @@ define <2 x half> @v_log_v2f16_fast(<2 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x398c, v0.h
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -7191,7 +7191,7 @@ define <2 x half> @v_log_v2f16_fast(<2 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v1, v1
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
@@ -7284,7 +7284,7 @@ define <3 x half> @v_log_v3f16(<3 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x398c, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.l, 0x398c, v1.l
; GFX1100-SDAG-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
@@ -7299,7 +7299,7 @@ define <3 x half> @v_log_v3f16(<3 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v2, v2
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v2, 0x398c, v2
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -7314,7 +7314,7 @@ define <3 x half> @v_log_v3f16(<3 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x398c, v0.h
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v1.l, 0x398c, v1.l
; GFX1100-GISEL-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
@@ -7329,7 +7329,7 @@ define <3 x half> @v_log_v3f16(<3 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v2, v2
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v2, 0x398c, v2
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -7417,7 +7417,7 @@ define <3 x half> @v_log_v3f16_fast(<3 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x398c, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.l, 0x398c, v1.l
; GFX1100-SDAG-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
@@ -7432,7 +7432,7 @@ define <3 x half> @v_log_v3f16_fast(<3 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v2, v2
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v2, 0x398c, v2
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -7447,7 +7447,7 @@ define <3 x half> @v_log_v3f16_fast(<3 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x398c, v0.h
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v1.l, 0x398c, v1.l
; GFX1100-GISEL-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
@@ -7462,7 +7462,7 @@ define <3 x half> @v_log_v3f16_fast(<3 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v2, v2
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v2, 0x398c, v2
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -7605,7 +7605,7 @@ define <4 x half> @v_log_v4f16(<4 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.l, 0x398c, v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x398c, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.h, 0x398c, v1.h
; GFX1100-SDAG-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
@@ -7626,7 +7626,7 @@ define <4 x half> @v_log_v4f16(<4 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v2, 0x398c, v2
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v3, 0x398c, v3
; GFX1100-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v2
@@ -7644,7 +7644,7 @@ define <4 x half> @v_log_v4f16(<4 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x398c, v0.h
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v1.l, 0x398c, v1.l
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v1.h, 0x398c, v1.h
; GFX1100-GISEL-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
@@ -7664,7 +7664,7 @@ define <4 x half> @v_log_v4f16(<4 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v1, 0x398c, v1
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v2, 0x398c, v2
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v3, 0x398c, v3
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v2
@@ -7800,7 +7800,7 @@ define <4 x half> @v_log_v4f16_fast(<4 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.l, 0x398c, v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x398c, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.h, 0x398c, v1.h
; GFX1100-SDAG-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
@@ -7821,7 +7821,7 @@ define <4 x half> @v_log_v4f16_fast(<4 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v2, 0x398c, v2
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v3, 0x398c, v3
; GFX1100-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v2
@@ -7839,7 +7839,7 @@ define <4 x half> @v_log_v4f16_fast(<4 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x398c, v0.h
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v1.l, 0x398c, v1.l
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v1.h, 0x398c, v1.h
; GFX1100-GISEL-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
@@ -7859,7 +7859,7 @@ define <4 x half> @v_log_v4f16_fast(<4 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v1, 0x398c, v1
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v2, 0x398c, v2
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v3, 0x398c, v3
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v2
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
index a141bceb3ce86..24e2fb4c8d9d7 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
@@ -203,7 +203,7 @@ define amdgpu_kernel void @s_log10_f32(ptr addrspace(1) %out, float %in) {
; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v1
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
; GFX1100-SDAG-NEXT: v_fma_f32 v3, 0x3e9a209a, v1, -v2
@@ -229,7 +229,7 @@ define amdgpu_kernel void @s_log10_f32(ptr addrspace(1) %out, float %in) {
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -599,7 +599,7 @@ define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, v1
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v3, v3
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v1
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v3
@@ -631,7 +631,7 @@ define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s3, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_dual_mul_f32 v3, 0x3e9a209a, v1 :: v_dual_lshlrev_b32 v0, 5, v0
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -639,7 +639,7 @@ define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v5, 0x3284fbcf, v1
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_dual_add_f32 v3, v3, v5 :: v_dual_mul_f32 v2, 0x3e9a209a, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 0x411a209b, s5
@@ -1152,7 +1152,7 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v5, v5
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_dual_mul_f32 v6, 0x3e9a209a, v2 :: v_dual_mul_f32 v7, 0x3e9a209a, v4
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
; GFX1100-SDAG-NEXT: v_fma_f32 v9, 0x3e9a209a, v2, -v6
@@ -1197,7 +1197,7 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, v2
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_dual_mul_f32 v5, 0x3e9a209a, v2 :: v_dual_lshlrev_b32 v0, 5, v0
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -1206,7 +1206,7 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v8, 0x3284fbcf, v2
; GFX1100-GISEL-NEXT: v_add_f32_e32 v5, v5, v8
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v3, 0x3e9a209a, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1219,7 +1219,7 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 0x411a209b, s7
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v1
; GFX1100-GISEL-NEXT: v_fma_f32 v7, 0x3e9a209a, v1, -v4
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1875,7 +1875,7 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX1100-SDAG-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
; GFX1100-SDAG-NEXT: v_dual_mul_f32 v8, 0x3e9a209a, v2 :: v_dual_mul_f32 v9, 0x3e9a209a, v3
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_dual_mul_f32 v10, 0x3e9a209a, v6 :: v_dual_mul_f32 v11, 0x3e9a209a, v7
; GFX1100-SDAG-NEXT: v_fma_f32 v12, 0x3e9a209a, v2, -v8
; GFX1100-SDAG-NEXT: v_fma_f32 v13, 0x3e9a209a, v3, -v9
@@ -1930,7 +1930,7 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0
; GFX1100-GISEL-NEXT: v_log_f32_e32 v3, v3
; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a209a, v2
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v3
@@ -1943,7 +1943,7 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v12, 0x3284fbcf, v2 :: v_dual_fmac_f32 v13, 0x3284fbcf, v3
; GFX1100-GISEL-NEXT: v_add_f32_e32 v7, v7, v12
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a209a, v1
@@ -2303,7 +2303,7 @@ define float @v_log10_f32(float %in) {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -2327,7 +2327,7 @@ define float @v_log10_f32(float %in) {
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
@@ -2504,7 +2504,7 @@ define float @v_log10_fabs_f32(float %in) {
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, |v0|, v1
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
@@ -2527,7 +2527,7 @@ define float @v_log10_fabs_f32(float %in) {
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -2706,7 +2706,7 @@ define float @v_log10_fneg_fabs_f32(float %in) {
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, -|v0|, v1
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
@@ -2729,7 +2729,7 @@ define float @v_log10_fneg_fabs_f32(float %in) {
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, -|v0|, v1
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -2908,7 +2908,7 @@ define float @v_log10_fneg_f32(float %in) {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, -v0, v1
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -2932,7 +2932,7 @@ define float @v_log10_fneg_f32(float %in) {
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, -v0, v1
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -3048,7 +3048,7 @@ define float @v_log10_f32_fast(float %in) {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_fmamk_f32 v0, v0, 0x3e9a209b, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3058,7 +3058,7 @@ define float @v_log10_f32_fast(float %in) {
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc11a209b, vcc_lo
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3e9a209b, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -3225,7 +3225,7 @@ define float @v_log10_f32_ninf(float %in) {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -3249,7 +3249,7 @@ define float @v_log10_f32_ninf(float %in) {
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
@@ -3363,7 +3363,7 @@ define float @v_log10_f32_afn(float %in) {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_fmamk_f32 v0, v0, 0x3e9a209b, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3373,7 +3373,7 @@ define float @v_log10_f32_afn(float %in) {
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc11a209b, vcc_lo
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3e9a209b, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -3402,7 +3402,7 @@ define float @v_log10_f32_afn_daz(float %in) #0 {
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
@@ -3507,7 +3507,7 @@ define float @v_log10_f32_afn_dynamic(float %in) #1 {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_fmamk_f32 v0, v0, 0x3e9a209b, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3517,7 +3517,7 @@ define float @v_log10_f32_afn_dynamic(float %in) #1 {
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc11a209b, vcc_lo
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3e9a209b, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -3623,7 +3623,7 @@ define float @v_fabs_log10_f32_afn(float %in) {
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, |v0|, v2
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_fmamk_f32 v0, v0, 0x3e9a209b, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3634,7 +3634,7 @@ define float @v_fabs_log10_f32_afn(float %in) {
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc11a209b, s0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3e9a209b, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -3753,7 +3753,7 @@ define float @v_log10_f32_daz(float %in) #0 {
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -3768,7 +3768,7 @@ define float @v_log10_f32_daz(float %in) #0 {
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -3942,7 +3942,7 @@ define float @v_log10_f32_nnan(float %in) {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -3966,7 +3966,7 @@ define float @v_log10_f32_nnan(float %in) {
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
@@ -4093,7 +4093,7 @@ define float @v_log10_f32_nnan_daz(float %in) #0 {
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4108,7 +4108,7 @@ define float @v_log10_f32_nnan_daz(float %in) #0 {
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4282,7 +4282,7 @@ define float @v_log10_f32_nnan_dynamic(float %in) #1 {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4306,7 +4306,7 @@ define float @v_log10_f32_nnan_dynamic(float %in) #1 {
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
@@ -4433,7 +4433,7 @@ define float @v_log10_f32_ninf_daz(float %in) #0 {
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4448,7 +4448,7 @@ define float @v_log10_f32_ninf_daz(float %in) #0 {
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4622,7 +4622,7 @@ define float @v_log10_f32_ninf_dynamic(float %in) #1 {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4646,7 +4646,7 @@ define float @v_log10_f32_ninf_dynamic(float %in) #1 {
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
@@ -4804,7 +4804,7 @@ define float @v_log10_f32_nnan_ninf(float %in) {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
@@ -4825,7 +4825,7 @@ define float @v_log10_f32_nnan_ninf(float %in) {
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4917,7 +4917,7 @@ define float @v_log10_f32_nnan_ninf_daz(float %in) #0 {
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
@@ -4930,7 +4930,7 @@ define float @v_log10_f32_nnan_ninf_daz(float %in) #0 {
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
@@ -5084,7 +5084,7 @@ define float @v_log10_f32_nnan_ninf_dynamic(float %in) #1 {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
@@ -5105,7 +5105,7 @@ define float @v_log10_f32_nnan_ninf_dynamic(float %in) #1 {
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -5141,7 +5141,7 @@ define float @v_log10_f32_fast_daz(float %in) #0 {
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
@@ -5308,7 +5308,7 @@ define float @v_log10_f32_dynamic_mode(float %in) #1 {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -5332,7 +5332,7 @@ define float @v_log10_f32_dynamic_mode(float %in) #1 {
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
@@ -5489,7 +5489,7 @@ define float @v_log10_f32_0() {
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, 0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -5506,7 +5506,7 @@ define float @v_log10_f32_0() {
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, 0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -5641,7 +5641,7 @@ define float @v_log10_f32_from_fpext_f16(i16 %src.i) {
; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-SDAG-TRUE16-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
@@ -5658,7 +5658,7 @@ define float @v_log10_f32_from_fpext_f16(i16 %src.i) {
; GFX1100-SDAG-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-SDAG-FAKE16-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
@@ -5675,7 +5675,7 @@ define float @v_log10_f32_from_fpext_f16(i16 %src.i) {
; GFX1100-GISEL-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-GISEL-TRUE16-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-TRUE16-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
@@ -5692,7 +5692,7 @@ define float @v_log10_f32_from_fpext_f16(i16 %src.i) {
; GFX1100-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-GISEL-FAKE16-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-FAKE16-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
@@ -5845,7 +5845,7 @@ define float @v_log10_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -5863,7 +5863,7 @@ define float @v_log10_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX1100-SDAG-FAKE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -5881,7 +5881,7 @@ define float @v_log10_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-GISEL-TRUE16-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -5899,7 +5899,7 @@ define float @v_log10_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-GISEL-FAKE16-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -6010,7 +6010,7 @@ define float @v_log10_f32_from_fpext_bf16(bfloat %src) {
; GFX1100-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v1, v0
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-SDAG-TRUE16-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
@@ -6033,7 +6033,7 @@ define float @v_log10_f32_from_fpext_bf16(bfloat %src) {
; GFX1100-SDAG-FAKE16-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-SDAG-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-SDAG-FAKE16-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
@@ -6057,7 +6057,7 @@ define float @v_log10_f32_from_fpext_bf16(bfloat %src) {
; GFX1100-GISEL-TRUE16-NEXT: v_ldexp_f32 v0, v1, v0
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-GISEL-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-GISEL-TRUE16-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
@@ -6080,7 +6080,7 @@ define float @v_log10_f32_from_fpext_bf16(bfloat %src) {
; GFX1100-GISEL-FAKE16-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
; GFX1100-GISEL-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-GISEL-FAKE16-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
@@ -6146,7 +6146,7 @@ define half @v_log10_f16(half %in) {
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6154,7 +6154,7 @@ define half @v_log10_f16(half %in) {
; GFX1100-SDAG-FAKE16: ; %bb.0:
; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v0, v0
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6162,7 +6162,7 @@ define half @v_log10_f16(half %in) {
; GFX1100-GISEL-TRUE16: ; %bb.0:
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6170,7 +6170,7 @@ define half @v_log10_f16(half %in) {
; GFX1100-GISEL-FAKE16: ; %bb.0:
; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6226,7 +6226,7 @@ define half @v_log10_fabs_f16(half %in) {
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.l, |v0.l|
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6234,7 +6234,7 @@ define half @v_log10_fabs_f16(half %in) {
; GFX1100-SDAG-FAKE16: ; %bb.0:
; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e64 v0, |v0|
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6242,7 +6242,7 @@ define half @v_log10_fabs_f16(half %in) {
; GFX1100-GISEL-TRUE16: ; %bb.0:
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e64 v0.l, |v0.l|
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6250,7 +6250,7 @@ define half @v_log10_fabs_f16(half %in) {
; GFX1100-GISEL-FAKE16: ; %bb.0:
; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e64 v0, |v0|
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6307,7 +6307,7 @@ define half @v_log10_fneg_fabs_f16(half %in) {
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.l, -|v0.l|
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6315,7 +6315,7 @@ define half @v_log10_fneg_fabs_f16(half %in) {
; GFX1100-SDAG-FAKE16: ; %bb.0:
; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e64 v0, -|v0|
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6323,7 +6323,7 @@ define half @v_log10_fneg_fabs_f16(half %in) {
; GFX1100-GISEL-TRUE16: ; %bb.0:
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e64 v0.l, -|v0.l|
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6331,7 +6331,7 @@ define half @v_log10_fneg_fabs_f16(half %in) {
; GFX1100-GISEL-FAKE16: ; %bb.0:
; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e64 v0, -|v0|
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6389,7 +6389,7 @@ define half @v_log10_fneg_f16(half %in) {
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.l, -v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6397,7 +6397,7 @@ define half @v_log10_fneg_f16(half %in) {
; GFX1100-SDAG-FAKE16: ; %bb.0:
; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e64 v0, -v0
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6405,7 +6405,7 @@ define half @v_log10_fneg_f16(half %in) {
; GFX1100-GISEL-TRUE16: ; %bb.0:
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e64 v0.l, -v0.l
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6413,7 +6413,7 @@ define half @v_log10_fneg_f16(half %in) {
; GFX1100-GISEL-FAKE16: ; %bb.0:
; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e64 v0, -v0
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6468,7 +6468,7 @@ define half @v_log10_f16_fast(half %in) {
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6476,7 +6476,7 @@ define half @v_log10_f16_fast(half %in) {
; GFX1100-SDAG-FAKE16: ; %bb.0:
; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v0, v0
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6484,7 +6484,7 @@ define half @v_log10_f16_fast(half %in) {
; GFX1100-GISEL-TRUE16: ; %bb.0:
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6492,7 +6492,7 @@ define half @v_log10_f16_fast(half %in) {
; GFX1100-GISEL-FAKE16: ; %bb.0:
; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6577,7 +6577,7 @@ define <2 x half> @v_log10_v2f16(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x34d1, v0.h
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -6591,7 +6591,7 @@ define <2 x half> @v_log10_v2f16(<2 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v1, v1
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX1100-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
@@ -6602,7 +6602,7 @@ define <2 x half> @v_log10_v2f16(<2 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x34d1, v0.h
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -6616,7 +6616,7 @@ define <2 x half> @v_log10_v2f16(<2 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v1, v1
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
@@ -6720,7 +6720,7 @@ define <2 x half> @v_log10_fabs_v2f16(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.l, |v0.l|
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.h, |v0.h|
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x34d1, v0.h
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -6734,7 +6734,7 @@ define <2 x half> @v_log10_fabs_v2f16(<2 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e64 v0, |v0|
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e64 v1, |v1|
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX1100-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
@@ -6747,7 +6747,7 @@ define <2 x half> @v_log10_fabs_v2f16(<2 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x34d1, v0.h
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -6762,7 +6762,7 @@ define <2 x half> @v_log10_fabs_v2f16(<2 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v1, v1
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -6872,7 +6872,7 @@ define <2 x half> @v_log10_fneg_fabs_v2f16(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.l, -|v0.l|
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.h, -|v0.h|
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x34d1, v0.h
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -6886,7 +6886,7 @@ define <2 x half> @v_log10_fneg_fabs_v2f16(<2 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e64 v0, -|v0|
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e64 v1, -|v1|
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX1100-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
@@ -6899,7 +6899,7 @@ define <2 x half> @v_log10_fneg_fabs_v2f16(<2 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x34d1, v0.h
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -6914,7 +6914,7 @@ define <2 x half> @v_log10_fneg_fabs_v2f16(<2 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v1, v1
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -7025,7 +7025,7 @@ define <2 x half> @v_log10_fneg_v2f16(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.l, -v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.h, -v0.h
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x34d1, v0.h
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -7039,7 +7039,7 @@ define <2 x half> @v_log10_fneg_v2f16(<2 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e64 v0, -v0
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e64 v1, -v1
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX1100-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
@@ -7052,7 +7052,7 @@ define <2 x half> @v_log10_fneg_v2f16(<2 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x34d1, v0.h
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -7067,7 +7067,7 @@ define <2 x half> @v_log10_fneg_v2f16(<2 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v1, v1
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -7152,7 +7152,7 @@ define <2 x half> @v_log10_v2f16_fast(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x34d1, v0.h
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -7166,7 +7166,7 @@ define <2 x half> @v_log10_v2f16_fast(<2 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v1, v1
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX1100-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
@@ -7177,7 +7177,7 @@ define <2 x half> @v_log10_v2f16_fast(<2 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x34d1, v0.h
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -7191,7 +7191,7 @@ define <2 x half> @v_log10_v2f16_fast(<2 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v1, v1
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
@@ -7284,7 +7284,7 @@ define <3 x half> @v_log10_v3f16(<3 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x34d1, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.l, 0x34d1, v1.l
; GFX1100-SDAG-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
@@ -7299,7 +7299,7 @@ define <3 x half> @v_log10_v3f16(<3 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v2, v2
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v2, 0x34d1, v2
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -7314,7 +7314,7 @@ define <3 x half> @v_log10_v3f16(<3 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x34d1, v0.h
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v1.l, 0x34d1, v1.l
; GFX1100-GISEL-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
@@ -7329,7 +7329,7 @@ define <3 x half> @v_log10_v3f16(<3 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v2, v2
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v2, 0x34d1, v2
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -7417,7 +7417,7 @@ define <3 x half> @v_log10_v3f16_fast(<3 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x34d1, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.l, 0x34d1, v1.l
; GFX1100-SDAG-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
@@ -7432,7 +7432,7 @@ define <3 x half> @v_log10_v3f16_fast(<3 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v2, v2
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v2, 0x34d1, v2
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -7447,7 +7447,7 @@ define <3 x half> @v_log10_v3f16_fast(<3 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x34d1, v0.h
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v1.l, 0x34d1, v1.l
; GFX1100-GISEL-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
@@ -7462,7 +7462,7 @@ define <3 x half> @v_log10_v3f16_fast(<3 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v2, v2
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v2, 0x34d1, v2
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -7605,7 +7605,7 @@ define <4 x half> @v_log10_v4f16(<4 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.l, 0x34d1, v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x34d1, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.h, 0x34d1, v1.h
; GFX1100-SDAG-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
@@ -7626,7 +7626,7 @@ define <4 x half> @v_log10_v4f16(<4 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v2, 0x34d1, v2
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v3, 0x34d1, v3
; GFX1100-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v2
@@ -7644,7 +7644,7 @@ define <4 x half> @v_log10_v4f16(<4 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x34d1, v0.h
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v1.l, 0x34d1, v1.l
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v1.h, 0x34d1, v1.h
; GFX1100-GISEL-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
@@ -7664,7 +7664,7 @@ define <4 x half> @v_log10_v4f16(<4 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v2, 0x34d1, v2
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v3, 0x34d1, v3
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v2
@@ -7800,7 +7800,7 @@ define <4 x half> @v_log10_v4f16_fast(<4 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.l, 0x34d1, v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x34d1, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.h, 0x34d1, v1.h
; GFX1100-SDAG-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
@@ -7821,7 +7821,7 @@ define <4 x half> @v_log10_v4f16_fast(<4 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v2, 0x34d1, v2
; GFX1100-SDAG-FAKE16-NEXT: v_mul_f16_e32 v3, 0x34d1, v3
; GFX1100-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v2
@@ -7839,7 +7839,7 @@ define <4 x half> @v_log10_v4f16_fast(<4 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x34d1, v0.h
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v1.l, 0x34d1, v1.l
; GFX1100-GISEL-TRUE16-NEXT: v_mul_f16_e32 v1.h, 0x34d1, v1.h
; GFX1100-GISEL-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
@@ -7859,7 +7859,7 @@ define <4 x half> @v_log10_v4f16_fast(<4 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v2, 0x34d1, v2
; GFX1100-GISEL-FAKE16-NEXT: v_mul_f16_e32 v3, 0x34d1, v3
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v2
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
index b1407d39674ad..e24fd1f22bfa6 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
@@ -142,7 +142,7 @@ define amdgpu_kernel void @s_log2_f32(ptr addrspace(1) %out, float %in) {
; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1100-SDAG-NEXT: v_ldexp_f32 v1, s2, s3
; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: global_store_b32 v2, v0, s[0:1]
@@ -163,7 +163,7 @@ define amdgpu_kernel void @s_log2_f32(ptr addrspace(1) %out, float %in) {
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-GISEL-NEXT: global_store_b32 v2, v0, s[0:1]
; GFX1100-GISEL-NEXT: s_endpgm
@@ -388,7 +388,7 @@ define amdgpu_kernel void @s_log2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, v1
; GFX1100-SDAG-NEXT: v_log_f32_e32 v3, v3
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_sub_f32 v1, v1, v0
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v3, v2
; GFX1100-SDAG-NEXT: global_store_b64 v4, v[0:1], s[0:1]
@@ -411,12 +411,12 @@ define amdgpu_kernel void @s_log2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s3, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_dual_sub_f32 v1, v1, v3 :: v_dual_lshlrev_b32 v0, 5, v0
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v2
; GFX1100-GISEL-NEXT: global_store_b64 v4, v[0:1], s[0:1]
; GFX1100-GISEL-NEXT: s_endpgm
@@ -720,7 +720,7 @@ define amdgpu_kernel void @s_log2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v5, v5
; GFX1100-SDAG-NEXT: v_mov_b32_e32 v6, 0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_dual_sub_f32 v2, v2, v0 :: v_dual_sub_f32 v1, v4, v1
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v5, v3
; GFX1100-SDAG-NEXT: global_store_b96 v6, v[0:2], s[4:5]
@@ -753,13 +753,13 @@ define amdgpu_kernel void @s_log2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v1, v1, v4
; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, v2
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v3
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v2, v2, v5
; GFX1100-GISEL-NEXT: global_store_b96 v6, v[0:2], s[4:5]
; GFX1100-GISEL-NEXT: s_endpgm
@@ -1137,7 +1137,7 @@ define amdgpu_kernel void @s_log2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX1100-SDAG-NEXT: v_mov_b32_e32 v9, 0
; GFX1100-SDAG-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
; GFX1100-SDAG-NEXT: v_dual_sub_f32 v3, v2, v0 :: v_dual_sub_f32 v2, v8, v1
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_dual_sub_f32 v1, v6, v4 :: v_dual_sub_f32 v0, v7, v5
; GFX1100-SDAG-NEXT: global_store_b128 v9, v[0:3], s[4:5]
; GFX1100-SDAG-NEXT: s_endpgm
@@ -1166,22 +1166,22 @@ define amdgpu_kernel void @s_log2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s1, v1
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_dual_sub_f32 v1, v1, v5 :: v_dual_lshlrev_b32 v0, 5, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_dual_sub_f32 v0, v0, v4 :: v_dual_lshlrev_b32 v3, 5, v3
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_ldexp_f32 v3, s3, v3
; GFX1100-GISEL-NEXT: v_log_f32_e32 v3, v3
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_dual_sub_f32 v3, v3, v7 :: v_dual_lshlrev_b32 v2, 5, v2
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, v2
; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v2, v2, v6
; GFX1100-GISEL-NEXT: global_store_b128 v8, v[0:3], s[4:5]
; GFX1100-GISEL-NEXT: s_endpgm
@@ -1375,7 +1375,7 @@ define float @v_log2_f32(float %in) {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -1390,7 +1390,7 @@ define float @v_log2_f32(float %in) {
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -1499,7 +1499,7 @@ define float @v_log2_fabs_f32(float %in) {
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, |v0|, v2
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -1514,7 +1514,7 @@ define float @v_log2_fabs_f32(float %in) {
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s0
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -1624,7 +1624,7 @@ define float @v_log2_fneg_fabs_f32(float %in) {
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, -|v0|, v2
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -1639,7 +1639,7 @@ define float @v_log2_fneg_fabs_f32(float %in) {
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, -|v0|, v1
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s0
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -1749,7 +1749,7 @@ define float @v_log2_fneg_f32(float %in) {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, -v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -1764,7 +1764,7 @@ define float @v_log2_fneg_f32(float %in) {
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, -v0, v1
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s0
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -1873,7 +1873,7 @@ define float @v_log2_f32_fast(float %in) {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -1888,7 +1888,7 @@ define float @v_log2_f32_fast(float %in) {
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -1996,7 +1996,7 @@ define float @v_log2_f32_unsafe_math_attr(float %in) {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2011,7 +2011,7 @@ define float @v_log2_f32_unsafe_math_attr(float %in) {
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2119,7 +2119,7 @@ define float @v_log2_f32_ninf(float %in) {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2134,7 +2134,7 @@ define float @v_log2_f32_ninf(float %in) {
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2242,7 +2242,7 @@ define float @v_log2_f32_afn(float %in) {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2257,7 +2257,7 @@ define float @v_log2_f32_afn(float %in) {
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2391,7 +2391,7 @@ define float @v_log2_f32_afn_dynamic(float %in) #1 {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2406,7 +2406,7 @@ define float @v_log2_f32_afn_dynamic(float %in) #1 {
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2515,7 +2515,7 @@ define float @v_fabs_log2_f32_afn(float %in) {
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, |v0|, v2
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2530,7 +2530,7 @@ define float @v_fabs_log2_f32_afn(float %in) {
; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s0
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2665,7 +2665,7 @@ define float @v_log2_f32_nnan(float %in) {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2680,7 +2680,7 @@ define float @v_log2_f32_nnan(float %in) {
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2814,7 +2814,7 @@ define float @v_log2_f32_nnan_dynamic(float %in) #1 {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2829,7 +2829,7 @@ define float @v_log2_f32_nnan_dynamic(float %in) #1 {
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2963,7 +2963,7 @@ define float @v_log2_f32_ninf_dynamic(float %in) #1 {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2978,7 +2978,7 @@ define float @v_log2_f32_ninf_dynamic(float %in) #1 {
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -3086,7 +3086,7 @@ define float @v_log2_f32_nnan_ninf(float %in) {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3101,7 +3101,7 @@ define float @v_log2_f32_nnan_ninf(float %in) {
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -3235,7 +3235,7 @@ define float @v_log2_f32_nnan_ninf_dynamic(float %in) #1 {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3250,7 +3250,7 @@ define float @v_log2_f32_nnan_ninf_dynamic(float %in) #1 {
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -3384,7 +3384,7 @@ define float @v_log2_f32_dynamic_mode(float %in) #1 {
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3399,7 +3399,7 @@ define float @v_log2_f32_dynamic_mode(float %in) #1 {
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -3458,7 +3458,7 @@ define float @v_log2_f32_0() {
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, 0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_add_f32_e32 v0, 0xc2000000, v0
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3687,7 +3687,7 @@ define float @v_log2_f32_from_fpext_bf16(bfloat %src) {
; GFX1100-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3702,7 +3702,7 @@ define float @v_log2_f32_from_fpext_bf16(bfloat %src) {
; GFX1100-SDAG-FAKE16-NEXT: v_ldexp_f32 v0, v0, v2
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3718,7 +3718,7 @@ define float @v_log2_f32_from_fpext_bf16(bfloat %src) {
; GFX1100-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3733,7 +3733,7 @@ define float @v_log2_f32_from_fpext_bf16(bfloat %src) {
; GFX1100-GISEL-FAKE16-NEXT: v_ldexp_f32 v0, v0, v2
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4157,7 +4157,7 @@ define <2 x half> @v_log2_v2f16(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4168,7 +4168,7 @@ define <2 x half> @v_log2_v2f16(<2 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v1, v1
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4177,7 +4177,7 @@ define <2 x half> @v_log2_v2f16(<2 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4188,7 +4188,7 @@ define <2 x half> @v_log2_v2f16(<2 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v1, v1
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4276,7 +4276,7 @@ define <2 x half> @v_log2_fabs_v2f16(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.h, |v0.h|
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.l, |v0.l|
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4287,7 +4287,7 @@ define <2 x half> @v_log2_fabs_v2f16(<2 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e64 v0, |v0|
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e64 v1, |v1|
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4298,7 +4298,7 @@ define <2 x half> @v_log2_fabs_v2f16(<2 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4310,7 +4310,7 @@ define <2 x half> @v_log2_fabs_v2f16(<2 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v1, v1
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4403,7 +4403,7 @@ define <2 x half> @v_log2_fneg_fabs_v2f16(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.h, -|v0.h|
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.l, -|v0.l|
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4414,7 +4414,7 @@ define <2 x half> @v_log2_fneg_fabs_v2f16(<2 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e64 v0, -|v0|
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e64 v1, -|v1|
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4425,7 +4425,7 @@ define <2 x half> @v_log2_fneg_fabs_v2f16(<2 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4437,7 +4437,7 @@ define <2 x half> @v_log2_fneg_fabs_v2f16(<2 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v1, v1
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4531,7 +4531,7 @@ define <2 x half> @v_log2_fneg_v2f16(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.h, -v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.l, -v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4542,7 +4542,7 @@ define <2 x half> @v_log2_fneg_v2f16(<2 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e64 v0, -v0
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e64 v1, -v1
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4553,7 +4553,7 @@ define <2 x half> @v_log2_fneg_v2f16(<2 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4565,7 +4565,7 @@ define <2 x half> @v_log2_fneg_v2f16(<2 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v1, v1
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4643,7 +4643,7 @@ define <2 x half> @v_log2_v2f16_fast(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4654,7 +4654,7 @@ define <2 x half> @v_log2_v2f16_fast(<2 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v1, v1
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4663,7 +4663,7 @@ define <2 x half> @v_log2_v2f16_fast(<2 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4674,7 +4674,7 @@ define <2 x half> @v_log2_v2f16_fast(<2 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v1, v1
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4768,7 +4768,7 @@ define <3 x half> @v_log2_v3f16(<3 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4780,7 +4780,7 @@ define <3 x half> @v_log2_v3f16(<3 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v1, v1
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v2, v2
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v2
; GFX1100-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4790,7 +4790,7 @@ define <3 x half> @v_log2_v3f16(<3 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4802,7 +4802,7 @@ define <3 x half> @v_log2_v3f16(<3 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v1, v1
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v2, v2
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v2
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4890,7 +4890,7 @@ define <3 x half> @v_log2_v3f16_fast(<3 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4902,7 +4902,7 @@ define <3 x half> @v_log2_v3f16_fast(<3 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v1, v1
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v2, v2
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v2
; GFX1100-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4912,7 +4912,7 @@ define <3 x half> @v_log2_v3f16_fast(<3 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4924,7 +4924,7 @@ define <3 x half> @v_log2_v3f16_fast(<3 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v1, v1
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v2, v2
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v2
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -5035,7 +5035,7 @@ define <4 x half> @v_log2_v4f16(<4 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_pack_b32_f16 v1, v1.l, v1.h
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -5050,7 +5050,7 @@ define <4 x half> @v_log2_v4f16(<4 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v2, v2
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v3, v3
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v2
; GFX1100-SDAG-FAKE16-NEXT: v_pack_b32_f16 v1, v1, v3
; GFX1100-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -5064,7 +5064,7 @@ define <4 x half> @v_log2_v4f16(<4 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v1.h, v1.h
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
; GFX1100-GISEL-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_pack_b32_f16 v1, v1.l, v1.h
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -5078,7 +5078,7 @@ define <4 x half> @v_log2_v4f16(<4 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v2, v2
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v3, v3
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v2
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v1, v1, v3
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -5182,7 +5182,7 @@ define <4 x half> @v_log2_v4f16_fast(<4 x half> %in) {
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
-; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_pack_b32_f16 v1, v1.l, v1.h
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -5197,7 +5197,7 @@ define <4 x half> @v_log2_v4f16_fast(<4 x half> %in) {
; GFX1100-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v2, v2
; GFX1100-SDAG-FAKE16-NEXT: v_log_f16_e32 v3, v3
-; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-SDAG-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v2
; GFX1100-SDAG-FAKE16-NEXT: v_pack_b32_f16 v1, v1, v3
; GFX1100-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -5211,7 +5211,7 @@ define <4 x half> @v_log2_v4f16_fast(<4 x half> %in) {
; GFX1100-GISEL-TRUE16-NEXT: v_log_f16_e32 v1.h, v1.h
; GFX1100-GISEL-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
; GFX1100-GISEL-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
-; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-TRUE16-NEXT: v_pack_b32_f16 v1, v1.l, v1.h
; GFX1100-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -5225,7 +5225,7 @@ define <4 x half> @v_log2_v4f16_fast(<4 x half> %in) {
; GFX1100-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v2, v2
; GFX1100-GISEL-FAKE16-NEXT: v_log_f16_e32 v3, v3
-; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX1100-GISEL-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v2
; GFX1100-GISEL-FAKE16-NEXT: v_pack_b32_f16 v1, v1, v3
; GFX1100-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
index 068a989fa2366..7fd70de81af6f 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
@@ -613,13 +613,13 @@ define void @s_maximum_f16(half inreg %src0, half inreg %src1) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_maximum_f16 s0, s0, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX12-NEXT: s_and_b32 s0, 0xffff, s0
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; use s0
; GFX12-NEXT: ;;#ASMEND
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[30:31]
%op = call half @llvm.maximum.f16(half %src0, half %src1)
%cast = bitcast half %op to i16
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
index 6c4f13a4eab8f..97eafd07d4b37 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
@@ -454,7 +454,7 @@ define void @s_maximum_f32(float inreg %src0, float inreg %src1) {
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; use s0
; GFX12-NEXT: ;;#ASMEND
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[30:31]
%op = call float @llvm.maximum.f32(float %src0, float %src1)
call void asm sideeffect "; use $0", "s"(float %op)
@@ -824,7 +824,7 @@ define void @s_maximum_v2f32(<2 x float> inreg %src0, <2 x float> inreg %src1) {
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; use s[0:1]
; GFX12-NEXT: ;;#ASMEND
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[30:31]
%op = call <2 x float> @llvm.maximum.v2f32(<2 x float> %src0, <2 x float> %src1)
call void asm sideeffect "; use $0", "s"(<2 x float> %op)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
index 2482d106b8053..b5dab396f0bf1 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
@@ -523,13 +523,13 @@ define void @s_minimum_f16(half inreg %src0, half inreg %src1) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_minimum_f16 s0, s0, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX12-NEXT: s_and_b32 s0, 0xffff, s0
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; use s0
; GFX12-NEXT: ;;#ASMEND
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[30:31]
%op = call half @llvm.minimum.f16(half %src0, half %src1)
%cast = bitcast half %op to i16
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
index 8adbe861fe6f0..3e98599fc4c7f 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
@@ -454,7 +454,7 @@ define void @s_minimum_f32(float inreg %src0, float inreg %src1) {
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; use s0
; GFX12-NEXT: ;;#ASMEND
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[30:31]
%op = call float @llvm.minimum.f32(float %src0, float %src1)
call void asm sideeffect "; use $0", "s"(float %op)
@@ -824,7 +824,7 @@ define void @s_minimum_v2f32(<2 x float> inreg %src0, <2 x float> inreg %src1) {
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; use s[0:1]
; GFX12-NEXT: ;;#ASMEND
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[30:31]
%op = call <2 x float> @llvm.minimum.v2f32(<2 x float> %src0, <2 x float> %src1)
call void asm sideeffect "; use $0", "s"(<2 x float> %op)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll b/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
index 6ae058b38e74f..2263231b77fb2 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
@@ -108,22 +108,22 @@ define { i64, i1 } @umulo_i64_v_v(i64 %x, i64 %y) {
; GFX12-NEXT: v_mad_co_u64_u32 v[7:8], null, v4, v2, 0
; GFX12-NEXT: v_mad_co_u64_u32 v[2:3], null, v4, v3, 0
; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, v1, v5
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v6, null, 0, v6, vcc_lo
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-NEXT: v_add3_u32 v1, v1, v5, v7
; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, v4, v7
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v6, v8, vcc_lo
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
; GFX12-NEXT: v_add_co_u32 v2, vcc_lo, v4, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[2:3]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
bb:
@@ -290,40 +290,40 @@ define { i64, i1 } @smulo_i64_v_v(i64 %x, i64 %y) {
; GFX12-NEXT: v_mad_co_i64_i32 v[10:11], null, v5, v3, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX12-NEXT: v_add_co_u32 v12, vcc_lo, v1, v6
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
; GFX12-NEXT: v_add3_u32 v1, v1, v6, v8
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-NEXT: v_add_co_u32 v12, vcc_lo, v12, v8
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0, v11, vcc_lo
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_add_co_u32 v7, vcc_lo, v7, v10
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_sub_co_u32 v2, vcc_lo, v7, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_subrev_co_ci_u32_e64 v10, null, 0, v9, vcc_lo
; GFX12-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v5
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v6, v7, v2, vcc_lo
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc_lo
; GFX12-NEXT: v_ashrrev_i32_e32 v2, 31, v1
; GFX12-NEXT: v_sub_co_u32 v4, vcc_lo, v6, v4
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-NEXT: v_subrev_co_ci_u32_e64 v7, null, 0, v5, vcc_lo
; GFX12-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v3
; GFX12-NEXT: v_mov_b32_e32 v3, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_dual_cndmask_b32 v4, v6, v4 :: v_dual_cndmask_b32 v5, v5, v7
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[2:3]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
bb:
@@ -773,7 +773,7 @@ define { i64, i1 } @smulo_i64_v_4(i64 %i) {
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[5:6], v[0:1]
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v3
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
bb:
@@ -846,7 +846,7 @@ define { i64, i1 } @umulo_i64_v_4(i64 %i) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[0:1]
; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v3
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
bb:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.powi.ll b/llvm/test/CodeGen/AMDGPU/llvm.powi.ll
index 64cd94134f8f9..049ac099a89f7 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.powi.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.powi.ll
@@ -23,10 +23,10 @@ define i16 @v_powi_f16(i16 %l, i32 %r) {
; GFX11-TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -37,10 +37,10 @@ define i16 @v_powi_f16(i16 %l, i32 %r) {
; GFX11-FAKE16-NEXT: v_cvt_f32_i32_e32 v1, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: v_exp_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%l.cast = bitcast i16 %l to half
@@ -64,7 +64,7 @@ define float @v_powi_f32(float %l, i32 %r) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_log_f32_e32 v0, v0
; GFX11-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
@@ -142,7 +142,7 @@ define float @v_powi_neg1_f32(float %l) {
; GFX11-NEXT: v_div_scale_f32 v1, null, v0, v0, 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f32_e32 v2, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v3, -v1, v2, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v2, v3, v2
; GFX11-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v0, 1.0
@@ -218,7 +218,7 @@ define float @v_powi_neg2_f32(float %l) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_div_scale_f32 v1, null, v0, v0, 1.0
; GFX11-NEXT: v_rcp_f32_e32 v2, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v3, -v1, v2, 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fmac_f32_e32 v2, v3, v2
@@ -395,7 +395,7 @@ define float @v_powi_neg128_f32(float %l) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_div_scale_f32 v1, null, v0, v0, 1.0
; GFX11-NEXT: v_rcp_f32_e32 v2, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v3, -v1, v2, 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fmac_f32_e32 v2, v3, v2
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
index ba03115c51536..48cd7c0f3286b 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
@@ -226,7 +226,7 @@ define amdgpu_kernel void @sin_v2f16(ptr addrspace(1) %r, ptr addrspace(1) %a) {
; GFX11-TRUE16-NEXT: v_sin_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_sin_f16_e32 v0.h, v0.h
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
; GFX11-TRUE16-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
@@ -245,7 +245,7 @@ define amdgpu_kernel void @sin_v2f16(ptr addrspace(1) %r, ptr addrspace(1) %a) {
; GFX11-FAKE16-NEXT: v_sin_f16_e32 v1, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_sin_f16_e32 v2, v2
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v1, v1, v2
; GFX11-FAKE16-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
index 3e56fa32ef1ea..84a27bb84c442 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
@@ -200,7 +200,7 @@ define amdgpu_kernel void @sqrt_v2f16(
; GFX11-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_sqrt_f16_e32 v0.h, v1.l
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[4:7], 0
; GFX11-TRUE16-NEXT: s_endpgm
@@ -223,7 +223,7 @@ define amdgpu_kernel void @sqrt_v2f16(
; GFX11-FAKE16-NEXT: v_sqrt_f16_e32 v0, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_sqrt_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX11-FAKE16-NEXT: buffer_store_b32 v0, off, s[4:7], 0
; GFX11-FAKE16-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
index a21a405164b6a..81e407de9c324 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
@@ -1629,7 +1629,7 @@ define amdgpu_kernel void @constant_zextload_v8i1_to_v8i32(ptr addrspace(1) %out
; GFX12-NEXT: v_lshrrev_b32_e32 v3, 7, v0
; GFX12-NEXT: v_bfe_u32 v2, v0, 6, 1
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v7, s3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v4, s6
; GFX12-NEXT: v_mov_b32_e32 v6, s7
; GFX12-NEXT: s_clause 0x1
@@ -3859,7 +3859,7 @@ define amdgpu_kernel void @constant_zextload_v64i1_to_v64i32(ptr addrspace(1) %o
; GFX12-NEXT: v_dual_mov_b32 v10, s53 :: v_dual_mov_b32 v13, s20
; GFX12-NEXT: v_dual_mov_b32 v12, s51 :: v_dual_mov_b32 v15, s19
; GFX12-NEXT: v_dual_mov_b32 v14, s52 :: v_dual_mov_b32 v17, s18
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v16, s2 :: v_dual_mov_b32 v19, s17
; GFX12-NEXT: v_dual_mov_b32 v18, s50 :: v_dual_mov_b32 v21, s16
; GFX12-NEXT: v_dual_mov_b32 v20, s49 :: v_dual_mov_b32 v23, s15
@@ -4756,7 +4756,7 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i32(ptr addrspace(1) %o
; GFX12-NEXT: v_dual_mov_b32 v10, s41 :: v_dual_mov_b32 v13, s38
; GFX12-NEXT: v_dual_mov_b32 v12, s39 :: v_dual_mov_b32 v15, s36
; GFX12-NEXT: v_dual_mov_b32 v14, s37 :: v_dual_mov_b32 v17, s35
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v16, s2 :: v_dual_mov_b32 v19, s33
; GFX12-NEXT: v_dual_mov_b32 v18, s34 :: v_dual_mov_b32 v21, s30
; GFX12-NEXT: v_dual_mov_b32 v20, s31 :: v_dual_mov_b32 v23, s28
@@ -5821,11 +5821,11 @@ define amdgpu_kernel void @constant_zextload_v4i1_to_v4i64(ptr addrspace(1) %out
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX12-NEXT: s_and_b32 s2, s2, 1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_b32 s3, 0xffff, s3
; GFX12-NEXT: s_and_b32 s2, 0xffff, s2
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:16
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1]
@@ -6377,7 +6377,7 @@ define amdgpu_kernel void @constant_sextload_v8i1_to_v8i64(ptr addrspace(1) %out
; GFX12-NEXT: s_lshr_b32 s10, s3, 2
; GFX12-NEXT: s_lshr_b32 s12, s3, 3
; GFX12-NEXT: s_lshr_b32 s14, s3, 1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
; GFX12-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x10000
; GFX12-NEXT: v_bfe_i32 v12, v9, 0, 1
@@ -6385,7 +6385,7 @@ define amdgpu_kernel void @constant_sextload_v8i1_to_v8i64(ptr addrspace(1) %out
; GFX12-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
; GFX12-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
; GFX12-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
; GFX12-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
@@ -6693,11 +6693,11 @@ define amdgpu_kernel void @constant_zextload_v16i1_to_v16i64(ptr addrspace(1) %o
; GFX12-NEXT: v_bfe_u32 v0, v6, 8, 1
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x1000c
; GFX12-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:80
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x1000d
; GFX12-NEXT: v_lshrrev_b32_e32 v8, 15, v6
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v4, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10007
; GFX12-NEXT: global_store_b128 v3, v[0:3], s[0:1] offset:64
@@ -6706,24 +6706,24 @@ define amdgpu_kernel void @constant_zextload_v16i1_to_v16i64(ptr addrspace(1) %o
; GFX12-NEXT: v_bfe_u32 v0, v6, 5, 1
; GFX12-NEXT: v_bfe_u32 v6, v6, 14, 1
; GFX12-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:96
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v2, s4
; GFX12-NEXT: v_mov_b32_e32 v4, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10004
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10002
; GFX12-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:48
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: v_mov_b32_e32 v4, v0
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10003
; GFX12-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:32
; GFX12-NEXT: v_mov_b32_e32 v2, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v4, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10001
; GFX12-NEXT: s_and_b32 s2, s2, 1
; GFX12-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:16
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v2, s2
; GFX12-NEXT: v_mov_b32_e32 v4, s3
; GFX12-NEXT: s_clause 0x1
@@ -7101,7 +7101,7 @@ define amdgpu_kernel void @constant_sextload_v16i1_to_v16i64(ptr addrspace(1) %o
; GFX12-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
; GFX12-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
; GFX12-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v5, s7
; GFX12-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v2, s4
; GFX12-NEXT: v_dual_mov_b32 v7, s9 :: v_dual_mov_b32 v4, s6
@@ -7646,91 +7646,91 @@ define amdgpu_kernel void @constant_zextload_v32i1_to_v32i64(ptr addrspace(1) %o
; GFX12-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, v1
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x1001c
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:240
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x1001b
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x1001a
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:224
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10019
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10018
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:208
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10017
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10016
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:192
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10014
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10015
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:176
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s3
; GFX12-NEXT: v_mov_b32_e32 v2, s4
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10013
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10012
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:160
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10011
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10010
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:144
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x1000f
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x1000e
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:128
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x1000d
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x1000c
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:112
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x1000b
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x1000a
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:96
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10009
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10008
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:80
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10007
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10006
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:64
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10005
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10004
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:48
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10003
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10002
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10001
; GFX12-NEXT: s_and_b32 s2, s2, 1
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:16
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1]
@@ -9507,191 +9507,191 @@ define amdgpu_kernel void @constant_zextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s4
; GFX12-NEXT: s_bfe_u32 s5, s3, 0x10015
; GFX12-NEXT: s_lshr_b32 s4, s3, 31
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v3, v1
; GFX12-NEXT: s_bfe_u32 s5, s3, 0x1001e
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:416
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s5
; GFX12-NEXT: v_mov_b32_e32 v2, s4
; GFX12-NEXT: s_bfe_u32 s4, s3, 0x1001d
; GFX12-NEXT: s_bfe_u32 s5, s3, 0x1001c
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:496
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s5
; GFX12-NEXT: v_mov_b32_e32 v2, s4
; GFX12-NEXT: s_bfe_u32 s4, s3, 0x1001b
; GFX12-NEXT: s_bfe_u32 s5, s3, 0x1001a
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:480
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s5
; GFX12-NEXT: v_mov_b32_e32 v2, s4
; GFX12-NEXT: s_bfe_u32 s4, s3, 0x10019
; GFX12-NEXT: s_bfe_u32 s5, s3, 0x10018
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:464
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s5
; GFX12-NEXT: v_mov_b32_e32 v2, s4
; GFX12-NEXT: s_bfe_u32 s4, s3, 0x10017
; GFX12-NEXT: s_bfe_u32 s5, s3, 0x10016
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:448
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s5
; GFX12-NEXT: v_mov_b32_e32 v2, s4
; GFX12-NEXT: s_bfe_u32 s4, s3, 0x10013
; GFX12-NEXT: s_bfe_u32 s5, s3, 0x10012
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:432
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s5
; GFX12-NEXT: v_mov_b32_e32 v2, s4
; GFX12-NEXT: s_bfe_u32 s4, s3, 0x10011
; GFX12-NEXT: s_bfe_u32 s5, s3, 0x10010
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:400
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s5
; GFX12-NEXT: v_mov_b32_e32 v2, s4
; GFX12-NEXT: s_bfe_u32 s4, s3, 0x1000f
; GFX12-NEXT: s_bfe_u32 s5, s3, 0x1000e
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:384
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s5
; GFX12-NEXT: v_mov_b32_e32 v2, s4
; GFX12-NEXT: s_bfe_u32 s4, s3, 0x1000d
; GFX12-NEXT: s_bfe_u32 s5, s3, 0x1000c
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:368
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s5
; GFX12-NEXT: v_mov_b32_e32 v2, s4
; GFX12-NEXT: s_bfe_u32 s4, s3, 0x1000b
; GFX12-NEXT: s_bfe_u32 s5, s3, 0x1000a
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:352
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s5
; GFX12-NEXT: v_mov_b32_e32 v2, s4
; GFX12-NEXT: s_bfe_u32 s4, s3, 0x10009
; GFX12-NEXT: s_bfe_u32 s5, s3, 0x10008
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:336
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s5
; GFX12-NEXT: v_mov_b32_e32 v2, s4
; GFX12-NEXT: s_bfe_u32 s4, s3, 0x10007
; GFX12-NEXT: s_bfe_u32 s5, s3, 0x10006
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:320
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s5
; GFX12-NEXT: v_mov_b32_e32 v2, s4
; GFX12-NEXT: s_bfe_u32 s4, s3, 0x10005
; GFX12-NEXT: s_bfe_u32 s5, s3, 0x10004
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:304
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s5
; GFX12-NEXT: v_mov_b32_e32 v2, s4
; GFX12-NEXT: s_bfe_u32 s4, s3, 0x10003
; GFX12-NEXT: s_bfe_u32 s5, s3, 0x10002
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:288
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s5
; GFX12-NEXT: v_mov_b32_e32 v2, s4
; GFX12-NEXT: s_bfe_u32 s4, s3, 0x10001
; GFX12-NEXT: s_and_b32 s3, s3, 1
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:272
; GFX12-NEXT: v_mov_b32_e32 v0, s3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v2, s4
; GFX12-NEXT: s_lshr_b32 s3, s2, 31
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x1001e
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:256
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x1001d
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x1001c
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:240
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x1001b
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x1001a
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:224
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10019
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10018
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:208
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10017
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10016
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:192
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10014
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10015
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:176
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s3
; GFX12-NEXT: v_mov_b32_e32 v2, s4
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10013
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10012
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:160
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10011
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10010
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:144
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x1000f
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x1000e
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:128
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x1000d
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x1000c
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:112
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x1000b
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x1000a
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:96
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10009
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10008
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:80
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10007
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10006
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:64
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10005
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10004
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:48
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10003
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10002
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10001
; GFX12-NEXT: s_and_b32 s2, s2, 1
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:16
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1]
@@ -11203,7 +11203,7 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX12-NEXT: s_lshr_b32 s44, s10, 4
; GFX12-NEXT: s_lshr_b32 s30, s10, 2
; GFX12-NEXT: s_bfe_i64 s[18:19], s[10:11], 0x10000
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_bfe_i64 s[10:11], s[26:27], 0x10000
; GFX12-NEXT: s_bfe_i64 s[26:27], s[40:41], 0x10000
; GFX12-NEXT: s_bfe_i64 s[40:41], s[52:53], 0x10000
@@ -11218,7 +11218,7 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX12-NEXT: s_bfe_i64 s[78:79], s[78:79], 0x10000
; GFX12-NEXT: s_bfe_i64 s[92:93], s[92:93], 0x10000
; GFX12-NEXT: v_dual_mov_b32 v14, s91 :: v_dual_mov_b32 v15, s98
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v16, s99 :: v_dual_mov_b32 v17, s96
; GFX12-NEXT: s_bfe_i64 s[66:67], s[66:67], 0x10000
; GFX12-NEXT: v_dual_mov_b32 v18, s97 :: v_dual_mov_b32 v19, s94
@@ -11235,14 +11235,14 @@ define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %o
; GFX12-NEXT: global_store_b128 v0, v[21:24], s[0:1] offset:96
; GFX12-NEXT: v_dual_mov_b32 v1, s78 :: v_dual_mov_b32 v2, s79
; GFX12-NEXT: v_dual_mov_b32 v3, s74 :: v_dual_mov_b32 v4, s75
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v5, s66
; GFX12-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x10000
; GFX12-NEXT: v_dual_mov_b32 v6, s67 :: v_dual_mov_b32 v7, s62
; GFX12-NEXT: v_dual_mov_b32 v8, s63 :: v_dual_mov_b32 v9, s56
; GFX12-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
; GFX12-NEXT: v_dual_mov_b32 v10, s57 :: v_dual_mov_b32 v11, s52
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v12, s53 :: v_dual_mov_b32 v13, s44
; GFX12-NEXT: v_dual_mov_b32 v14, s45 :: v_dual_mov_b32 v15, s40
; GFX12-NEXT: v_dual_mov_b32 v16, s41 :: v_dual_mov_b32 v17, s30
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
index a135b43bad0fe..0194e3c6ce37b 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
@@ -3047,7 +3047,7 @@ define amdgpu_kernel void @constant_zextload_v32i16_to_v32i32(ptr addrspace(1) %
; GFX12-NEXT: s_and_b32 s7, s7, 0xffff
; GFX12-NEXT: s_lshr_b32 s25, s6, 16
; GFX12-NEXT: s_and_b32 s6, s6, 0xffff
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v11, s28
; GFX12-NEXT: v_mov_b32_e32 v10, s11
; GFX12-NEXT: s_lshr_b32 s22, s5, 16
@@ -3541,7 +3541,7 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i32(ptr addrspace(1) %
; GFX12-NEXT: s_ashr_i32 s25, s6, 16
; GFX12-NEXT: s_sext_i32_i16 s7, s7
; GFX12-NEXT: s_sext_i32_i16 s6, s6
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v11, s28
; GFX12-NEXT: v_mov_b32_e32 v10, s11
; GFX12-NEXT: s_ashr_i32 s22, s5, 16
@@ -5925,7 +5925,7 @@ define amdgpu_kernel void @constant_zextload_v2i16_to_v2i64(ptr addrspace(1) %ou
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s3
; GFX12-NEXT: s_pack_hl_b32_b16 s2, s2, 0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, v1
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1]
; GFX12-NEXT: s_endpgm
@@ -6159,7 +6159,7 @@ define amdgpu_kernel void @constant_zextload_v4i16_to_v4i64(ptr addrspace(1) %ou
; GFX12-NEXT: s_pack_hl_b32_b16 s2, s3, 0
; GFX12-NEXT: s_and_b32 s3, 0xffff, s3
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s3
; GFX12-NEXT: v_mov_b32_e32 v2, s2
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:16
@@ -6508,23 +6508,23 @@ define amdgpu_kernel void @constant_zextload_v8i16_to_v8i64(ptr addrspace(1) %ou
; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX12-NEXT: s_pack_hl_b32_b16 s3, s7, 0
; GFX12-NEXT: s_pack_hl_b32_b16 s2, s6, 0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v2, s3 :: v_dual_mov_b32 v3, v1
; GFX12-NEXT: s_and_b32 s3, 0xffff, s6
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:48
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s3
; GFX12-NEXT: v_mov_b32_e32 v2, s2
; GFX12-NEXT: s_pack_hl_b32_b16 s2, s5, 0
; GFX12-NEXT: s_and_b32 s3, 0xffff, s5
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s3
; GFX12-NEXT: v_mov_b32_e32 v2, s2
; GFX12-NEXT: s_pack_hl_b32_b16 s2, s4, 0
; GFX12-NEXT: s_and_b32 s3, 0xffff, s4
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:16
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s3
; GFX12-NEXT: v_mov_b32_e32 v2, s2
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1]
@@ -7110,43 +7110,43 @@ define amdgpu_kernel void @constant_zextload_v16i16_to_v16i64(ptr addrspace(1) %
; GFX12-NEXT: s_lshr_b32 s5, s4, 16
; GFX12-NEXT: s_and_b32 s4, s4, 0xffff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[8:9] offset:80
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s5
; GFX12-NEXT: s_lshr_b32 s4, s7, 16
; GFX12-NEXT: s_and_b32 s5, s7, 0xffff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[8:9] offset:64
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s5
; GFX12-NEXT: v_mov_b32_e32 v2, s4
; GFX12-NEXT: s_lshr_b32 s4, s6, 16
; GFX12-NEXT: s_and_b32 s5, s6, 0xffff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[8:9] offset:112
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s5
; GFX12-NEXT: v_mov_b32_e32 v2, s4
; GFX12-NEXT: s_lshr_b32 s4, s3, 16
; GFX12-NEXT: s_and_b32 s3, s3, 0xffff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[8:9] offset:96
; GFX12-NEXT: v_mov_b32_e32 v0, s3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v2, s4
; GFX12-NEXT: s_lshr_b32 s3, s2, 16
; GFX12-NEXT: s_and_b32 s2, s2, 0xffff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[8:9] offset:48
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_lshr_b32 s2, s1, 16
; GFX12-NEXT: s_and_b32 s1, s1, 0xffff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[8:9] offset:32
; GFX12-NEXT: v_mov_b32_e32 v0, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v2, s2
; GFX12-NEXT: s_lshr_b32 s1, s0, 16
; GFX12-NEXT: s_and_b32 s0, s0, 0xffff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[8:9] offset:16
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: v_mov_b32_e32 v2, s1
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[8:9]
@@ -8208,91 +8208,91 @@ define amdgpu_kernel void @constant_zextload_v32i16_to_v32i64(ptr addrspace(1) %
; GFX12-NEXT: s_lshr_b32 s15, s14, 16
; GFX12-NEXT: s_and_b32 s14, s14, 0xffff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[16:17] offset:240
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s14
; GFX12-NEXT: v_mov_b32_e32 v2, s15
; GFX12-NEXT: s_lshr_b32 s14, s13, 16
; GFX12-NEXT: s_and_b32 s13, s13, 0xffff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[16:17] offset:224
; GFX12-NEXT: v_mov_b32_e32 v0, s13
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v2, s14
; GFX12-NEXT: s_lshr_b32 s13, s12, 16
; GFX12-NEXT: s_and_b32 s12, s12, 0xffff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[16:17] offset:208
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s12
; GFX12-NEXT: v_mov_b32_e32 v2, s13
; GFX12-NEXT: s_lshr_b32 s12, s11, 16
; GFX12-NEXT: s_and_b32 s11, s11, 0xffff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[16:17] offset:192
; GFX12-NEXT: v_mov_b32_e32 v0, s11
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v2, s12
; GFX12-NEXT: s_lshr_b32 s11, s10, 16
; GFX12-NEXT: s_and_b32 s10, s10, 0xffff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[16:17] offset:176
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s10
; GFX12-NEXT: v_mov_b32_e32 v2, s11
; GFX12-NEXT: s_lshr_b32 s10, s9, 16
; GFX12-NEXT: s_and_b32 s9, s9, 0xffff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[16:17] offset:160
; GFX12-NEXT: v_mov_b32_e32 v0, s9
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v2, s10
; GFX12-NEXT: s_lshr_b32 s9, s8, 16
; GFX12-NEXT: s_and_b32 s8, s8, 0xffff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[16:17] offset:144
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s8
; GFX12-NEXT: v_mov_b32_e32 v2, s9
; GFX12-NEXT: s_lshr_b32 s8, s7, 16
; GFX12-NEXT: s_and_b32 s7, s7, 0xffff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[16:17] offset:128
; GFX12-NEXT: v_mov_b32_e32 v0, s7
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v2, s8
; GFX12-NEXT: s_lshr_b32 s7, s6, 16
; GFX12-NEXT: s_and_b32 s6, s6, 0xffff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[16:17] offset:112
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s6
; GFX12-NEXT: v_mov_b32_e32 v2, s7
; GFX12-NEXT: s_lshr_b32 s6, s5, 16
; GFX12-NEXT: s_and_b32 s5, s5, 0xffff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[16:17] offset:96
; GFX12-NEXT: v_mov_b32_e32 v0, s5
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v2, s6
; GFX12-NEXT: s_lshr_b32 s5, s4, 16
; GFX12-NEXT: s_and_b32 s4, s4, 0xffff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[16:17] offset:80
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s5
; GFX12-NEXT: s_lshr_b32 s4, s3, 16
; GFX12-NEXT: s_and_b32 s3, s3, 0xffff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[16:17] offset:64
; GFX12-NEXT: v_mov_b32_e32 v0, s3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v2, s4
; GFX12-NEXT: s_lshr_b32 s3, s2, 16
; GFX12-NEXT: s_and_b32 s2, s2, 0xffff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[16:17] offset:48
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_lshr_b32 s2, s1, 16
; GFX12-NEXT: s_and_b32 s1, s1, 0xffff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[16:17] offset:32
; GFX12-NEXT: v_mov_b32_e32 v0, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v2, s2
; GFX12-NEXT: s_lshr_b32 s1, s0, 16
; GFX12-NEXT: s_and_b32 s0, s0, 0xffff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[16:17] offset:16
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: v_mov_b32_e32 v2, s1
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[16:17]
@@ -9129,7 +9129,7 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GFX12-NEXT: global_store_b128 v24, v[4:7], s[16:17] offset:224
; GFX12-NEXT: global_store_b128 v24, v[8:11], s[16:17] offset:208
; GFX12-NEXT: global_store_b128 v24, v[12:15], s[16:17] offset:192
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v0, s50 :: v_dual_mov_b32 v3, s13
; GFX12-NEXT: v_dual_mov_b32 v1, s51 :: v_dual_mov_b32 v2, s12
; GFX12-NEXT: v_dual_mov_b32 v5, s57 :: v_dual_mov_b32 v4, s56
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i32.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
index 8812dfd9ed280..9d3a9f1dff8e8 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
@@ -4831,7 +4831,7 @@ define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %
; GFX12-NEXT: global_store_b128 v24, v[8:11], s[36:37] offset:208
; GFX12-NEXT: global_store_b128 v24, v[12:15], s[36:37] offset:192
; GFX12-NEXT: v_dual_mov_b32 v0, s22 :: v_dual_mov_b32 v3, s57
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v1, s24 :: v_dual_mov_b32 v2, s23
; GFX12-NEXT: v_mov_b32_e32 v5, s56
; GFX12-NEXT: s_ashr_i32 s51, s17, 31
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
index 2d60c5729ed52..a71a5bbf95645 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
@@ -2817,7 +2817,7 @@ define amdgpu_kernel void @constant_zextload_v32i8_to_v32i32(ptr addrspace(1) %o
; GFX12-NEXT: s_bfe_u32 s17, s7, 0x80008
; GFX12-NEXT: s_and_b32 s29, s7, 0xff
; GFX12-NEXT: s_bfe_u32 s7, s7, 0x80010
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v8, s31 :: v_dual_mov_b32 v11, s20
; GFX12-NEXT: v_mov_b32_e32 v10, s9
; GFX12-NEXT: s_lshr_b32 s14, s6, 24
@@ -3326,7 +3326,7 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i32(ptr addrspace(1) %o
; GFX12-NEXT: s_bfe_i32 s21, s7, 0x80008
; GFX12-NEXT: s_sext_i32_i8 s7, s7
; GFX12-NEXT: v_dual_mov_b32 v8, s9 :: v_dual_mov_b32 v11, s25
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v10, s26
; GFX12-NEXT: s_ashr_i32 s16, s6, 24
; GFX12-NEXT: s_bfe_i32 s17, s6, 0x80010
@@ -4270,7 +4270,7 @@ define amdgpu_kernel void @constant_zextload_v64i8_to_v64i32(ptr addrspace(1) %o
; GFX12-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v17, s21
; GFX12-NEXT: v_dual_mov_b32 v16, s52 :: v_dual_mov_b32 v19, s20
; GFX12-NEXT: v_dual_mov_b32 v18, s1 :: v_dual_mov_b32 v21, s19
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v20, s51 :: v_dual_mov_b32 v23, s18
; GFX12-NEXT: v_mov_b32_e32 v22, s0
; GFX12-NEXT: s_clause 0x5
@@ -6007,7 +6007,7 @@ define amdgpu_kernel void @constant_zextload_v4i8_to_v4i64(ptr addrspace(1) %out
; GFX12-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, v1
; GFX12-NEXT: s_and_b32 s2, s2, 0xff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:16
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1]
@@ -6362,7 +6362,7 @@ define amdgpu_kernel void @constant_zextload_v8i8_to_v8i64(ptr addrspace(1) %out
; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s4
; GFX12-NEXT: s_lshr_b32 s5, s3, 24
; GFX12-NEXT: s_bfe_u32 s4, s3, 0x80008
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v3, v1
; GFX12-NEXT: s_and_b32 s3, s3, 0xff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:48
@@ -6371,13 +6371,13 @@ define amdgpu_kernel void @constant_zextload_v8i8_to_v8i64(ptr addrspace(1) %out
; GFX12-NEXT: s_lshr_b32 s3, s2, 24
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x80010
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x80008
; GFX12-NEXT: s_and_b32 s2, s2, 0xff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:16
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1]
@@ -6973,47 +6973,47 @@ define amdgpu_kernel void @constant_zextload_v16i8_to_v16i64(ptr addrspace(1) %o
; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX12-NEXT: s_lshr_b32 s3, s7, 24
; GFX12-NEXT: s_lshr_b32 s2, s5, 24
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v2, s3 :: v_dual_mov_b32 v3, v1
; GFX12-NEXT: s_bfe_u32 s3, s5, 0x80010
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:112
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s3
; GFX12-NEXT: v_mov_b32_e32 v2, s2
; GFX12-NEXT: s_lshr_b32 s2, s6, 24
; GFX12-NEXT: s_bfe_u32 s3, s6, 0x80010
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:48
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s3
; GFX12-NEXT: v_mov_b32_e32 v2, s2
; GFX12-NEXT: s_bfe_u32 s2, s6, 0x80008
; GFX12-NEXT: s_and_b32 s3, s6, 0xff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:80
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s3
; GFX12-NEXT: v_mov_b32_e32 v2, s2
; GFX12-NEXT: s_bfe_u32 s2, s7, 0x80008
; GFX12-NEXT: s_and_b32 s3, s7, 0xff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:64
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s3
; GFX12-NEXT: v_mov_b32_e32 v2, s2
; GFX12-NEXT: s_bfe_u32 s2, s5, 0x80008
; GFX12-NEXT: s_and_b32 s3, s5, 0xff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:96
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s3
; GFX12-NEXT: v_mov_b32_e32 v2, s2
; GFX12-NEXT: s_lshr_b32 s2, s4, 24
; GFX12-NEXT: s_bfe_u32 s3, s4, 0x80010
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s3
; GFX12-NEXT: v_mov_b32_e32 v2, s2
; GFX12-NEXT: s_bfe_u32 s2, s4, 0x80008
; GFX12-NEXT: s_and_b32 s3, s4, 0xff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:16
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s3
; GFX12-NEXT: v_mov_b32_e32 v2, s2
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1]
@@ -8100,95 +8100,95 @@ define amdgpu_kernel void @constant_zextload_v32i8_to_v32i64(ptr addrspace(1) %o
; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s10
; GFX12-NEXT: s_lshr_b32 s11, s7, 24
; GFX12-NEXT: s_lshr_b32 s10, s5, 24
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v2, s11 :: v_dual_mov_b32 v3, v1
; GFX12-NEXT: s_bfe_u32 s11, s5, 0x80010
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[8:9] offset:240
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s11
; GFX12-NEXT: v_mov_b32_e32 v2, s10
; GFX12-NEXT: s_lshr_b32 s10, s3, 24
; GFX12-NEXT: s_bfe_u32 s11, s3, 0x80010
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[8:9] offset:176
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s11
; GFX12-NEXT: v_mov_b32_e32 v2, s10
; GFX12-NEXT: s_lshr_b32 s10, s1, 24
; GFX12-NEXT: s_bfe_u32 s11, s1, 0x80010
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[8:9] offset:112
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s11
; GFX12-NEXT: v_mov_b32_e32 v2, s10
; GFX12-NEXT: s_bfe_u32 s10, s7, 0x80008
; GFX12-NEXT: s_and_b32 s7, s7, 0xff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[8:9] offset:48
; GFX12-NEXT: v_mov_b32_e32 v0, s7
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v2, s10
; GFX12-NEXT: s_lshr_b32 s7, s6, 24
; GFX12-NEXT: s_bfe_u32 s10, s6, 0x80010
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[8:9] offset:224
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s10
; GFX12-NEXT: v_mov_b32_e32 v2, s7
; GFX12-NEXT: s_bfe_u32 s7, s6, 0x80008
; GFX12-NEXT: s_and_b32 s6, s6, 0xff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[8:9] offset:208
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s6
; GFX12-NEXT: v_mov_b32_e32 v2, s7
; GFX12-NEXT: s_bfe_u32 s6, s5, 0x80008
; GFX12-NEXT: s_and_b32 s5, s5, 0xff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[8:9] offset:192
; GFX12-NEXT: v_mov_b32_e32 v0, s5
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v2, s6
; GFX12-NEXT: s_lshr_b32 s5, s4, 24
; GFX12-NEXT: s_bfe_u32 s6, s4, 0x80010
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[8:9] offset:160
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s6
; GFX12-NEXT: v_mov_b32_e32 v2, s5
; GFX12-NEXT: s_bfe_u32 s5, s4, 0x80008
; GFX12-NEXT: s_and_b32 s4, s4, 0xff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[8:9] offset:144
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s5
; GFX12-NEXT: s_bfe_u32 s4, s3, 0x80008
; GFX12-NEXT: s_and_b32 s3, s3, 0xff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[8:9] offset:128
; GFX12-NEXT: v_mov_b32_e32 v0, s3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v2, s4
; GFX12-NEXT: s_lshr_b32 s3, s2, 24
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x80010
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[8:9] offset:96
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s4
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x80008
; GFX12-NEXT: s_and_b32 s2, s2, 0xff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[8:9] offset:80
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: v_mov_b32_e32 v2, s3
; GFX12-NEXT: s_bfe_u32 s2, s1, 0x80008
; GFX12-NEXT: s_and_b32 s1, s1, 0xff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[8:9] offset:64
; GFX12-NEXT: v_mov_b32_e32 v0, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v2, s2
; GFX12-NEXT: s_lshr_b32 s1, s0, 24
; GFX12-NEXT: s_bfe_u32 s2, s0, 0x80010
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[8:9] offset:32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: v_mov_b32_e32 v2, s1
; GFX12-NEXT: s_bfe_u32 s1, s0, 0x80008
; GFX12-NEXT: s_and_b32 s0, s0, 0xff
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[8:9] offset:16
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: v_mov_b32_e32 v2, s1
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
index c0d41b5cc1d70..0a7e662975b41 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
@@ -504,9 +504,9 @@ define double @local_atomic_fadd_ret_f64(ptr addrspace(3) %ptr) nounwind {
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[3:4]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB4_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -696,9 +696,9 @@ define double @local_atomic_fadd_ret_f64__offset(ptr addrspace(3) %ptr) nounwind
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[3:4]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB5_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -887,9 +887,9 @@ define void @local_atomic_fadd_noret_f64(ptr addrspace(3) %ptr) nounwind {
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[1:2]
; GFX12-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB6_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1070,9 +1070,9 @@ define void @local_atomic_fadd_noret_f64__offset(ptr addrspace(3) %ptr) nounwind
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[1:2]
; GFX12-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB7_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1271,9 +1271,9 @@ define half @local_atomic_fadd_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB8_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1314,9 +1314,9 @@ define half @local_atomic_fadd_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB8_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1656,9 +1656,9 @@ define half @local_atomic_fadd_ret_f16__offset(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB9_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1701,9 +1701,9 @@ define half @local_atomic_fadd_ret_f16__offset(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB9_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2053,9 +2053,9 @@ define void @local_atomic_fadd_noret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB10_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2095,9 +2095,9 @@ define void @local_atomic_fadd_noret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB10_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2425,9 +2425,9 @@ define void @local_atomic_fadd_noret_f16__offset(ptr addrspace(3) %ptr) nounwind
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB11_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2468,9 +2468,9 @@ define void @local_atomic_fadd_noret_f16__offset(ptr addrspace(3) %ptr) nounwind
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB11_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2798,9 +2798,9 @@ define half @local_atomic_fadd_ret_f16__offset__align4(ptr addrspace(3) %ptr) no
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB12_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2832,9 +2832,9 @@ define half @local_atomic_fadd_ret_f16__offset__align4(ptr addrspace(3) %ptr) no
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB12_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3096,9 +3096,9 @@ define void @local_atomic_fadd_noret_f16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB13_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3128,9 +3128,9 @@ define void @local_atomic_fadd_noret_f16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB13_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3392,7 +3392,7 @@ define bfloat @local_atomic_fadd_ret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -3405,9 +3405,9 @@ define bfloat @local_atomic_fadd_ret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB14_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3445,7 +3445,7 @@ define bfloat @local_atomic_fadd_ret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -3457,9 +3457,9 @@ define bfloat @local_atomic_fadd_ret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB14_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3848,7 +3848,7 @@ define bfloat @local_atomic_fadd_ret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -3861,9 +3861,9 @@ define bfloat @local_atomic_fadd_ret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB15_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3903,7 +3903,7 @@ define bfloat @local_atomic_fadd_ret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -3915,9 +3915,9 @@ define bfloat @local_atomic_fadd_ret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB15_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4315,7 +4315,7 @@ define void @local_atomic_fadd_noret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4329,9 +4329,9 @@ define void @local_atomic_fadd_noret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB16_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4367,7 +4367,7 @@ define void @local_atomic_fadd_noret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
@@ -4380,9 +4380,9 @@ define void @local_atomic_fadd_noret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB16_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4757,7 +4757,7 @@ define void @local_atomic_fadd_noret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
@@ -4771,9 +4771,9 @@ define void @local_atomic_fadd_noret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB17_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4810,7 +4810,7 @@ define void @local_atomic_fadd_noret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
@@ -4823,9 +4823,9 @@ define void @local_atomic_fadd_noret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB17_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5202,7 +5202,7 @@ define bfloat @local_atomic_fadd_ret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
@@ -5214,9 +5214,9 @@ define bfloat @local_atomic_fadd_ret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB18_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5246,7 +5246,7 @@ define bfloat @local_atomic_fadd_ret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-FAKE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
@@ -5257,9 +5257,9 @@ define bfloat @local_atomic_fadd_ret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB18_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5577,7 +5577,7 @@ define void @local_atomic_fadd_noret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -5589,9 +5589,9 @@ define void @local_atomic_fadd_noret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB19_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5619,7 +5619,7 @@ define void @local_atomic_fadd_noret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -5630,9 +5630,9 @@ define void @local_atomic_fadd_noret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB19_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8220,7 +8220,7 @@ define amdgpu_kernel void @local_ds_fadd(ptr addrspace(1) %out, ptr addrspace(3)
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_cvt_f32_ubyte0_e32 v1, s3
; GFX12-NEXT: s_lshl_b32 s3, s1, 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v2, s3 :: v_dual_mul_f32 v1, 0x42280000, v1
; GFX12-NEXT: ds_add_rtn_f32 v1, v2, v1
; GFX12-NEXT: s_wait_dscnt 0x0
@@ -8230,7 +8230,7 @@ define amdgpu_kernel void @local_ds_fadd(ptr addrspace(1) %out, ptr addrspace(3)
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX12-NEXT: s_mov_b32 s7, exec_lo
; GFX12-NEXT: v_readfirstlane_b32 s3, v1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mbcnt_lo_u32_b32 v2, s7, 0
; GFX12-NEXT: s_mov_b32 s6, exec_lo
; GFX12-NEXT: v_cmpx_eq_u32_e32 0, v2
@@ -8240,14 +8240,14 @@ define amdgpu_kernel void @local_ds_fadd(ptr addrspace(1) %out, ptr addrspace(3)
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_cvt_f32_ubyte0_e32 v1, s0
; GFX12-NEXT: s_lshl_b32 s0, s1, 4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mul_f32 v1, 0x42280000, v1
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: ds_add_f32 v2, v1
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: .LBB28_4:
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s6
; GFX12-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
; GFX12-NEXT: s_mov_b32 s1, exec_lo
@@ -8260,14 +8260,14 @@ define amdgpu_kernel void @local_ds_fadd(ptr addrspace(1) %out, ptr addrspace(3)
; GFX12-NEXT: ; implicit-def: $vgpr0
; GFX12-NEXT: .LBB28_5: ; %ComputeLoop
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_ctz_i32_b32 s3, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_readlane_b32 s6, v1, s3
; GFX12-NEXT: v_writelane_b32 v0, s0, s3
; GFX12-NEXT: s_lshl_b32 s3, 1, s3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 s1, s1, s3
; GFX12-NEXT: s_add_f32 s0, s0, s6
; GFX12-NEXT: s_cbranch_scc1 .LBB28_5
@@ -8277,7 +8277,7 @@ define amdgpu_kernel void @local_ds_fadd(ptr addrspace(1) %out, ptr addrspace(3)
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX12-NEXT: ; implicit-def: $vgpr1
; GFX12-NEXT: s_and_saveexec_b32 s1, vcc_lo
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_xor_b32 s1, exec_lo, s1
; GFX12-NEXT: s_cbranch_execz .LBB28_8
; GFX12-NEXT: ; %bb.7:
@@ -8287,11 +8287,11 @@ define amdgpu_kernel void @local_ds_fadd(ptr addrspace(1) %out, ptr addrspace(3)
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: .LBB28_8:
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX12-NEXT: v_readfirstlane_b32 s2, v1
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_f32 v0, s2, v0
; GFX12-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
@@ -8491,7 +8491,7 @@ define amdgpu_kernel void @local_ds_fadd(ptr addrspace(1) %out, ptr addrspace(3)
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: .LBB28_2:
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX10-NEXT: s_mov_b32 s7, exec_lo
; GFX10-NEXT: v_readfirstlane_b32 s3, v1
@@ -8510,7 +8510,7 @@ define amdgpu_kernel void @local_ds_fadd(ptr addrspace(1) %out, ptr addrspace(3)
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: .LBB28_4:
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s6
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
; GFX10-NEXT: v_bfrev_b32_e32 v1, 1
@@ -8543,7 +8543,7 @@ define amdgpu_kernel void @local_ds_fadd(ptr addrspace(1) %out, ptr addrspace(3)
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
; GFX10-NEXT: .LBB28_8:
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-NEXT: v_readfirstlane_b32 s2, v2
@@ -9080,7 +9080,7 @@ define amdgpu_kernel void @local_ds_fadd_one_as(ptr addrspace(1) %out, ptr addrs
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_cvt_f32_ubyte0_e32 v1, s3
; GFX12-NEXT: s_lshl_b32 s3, s1, 3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v2, s3 :: v_dual_mul_f32 v1, 0x42280000, v1
; GFX12-NEXT: ds_add_rtn_f32 v1, v2, v1
; GFX12-NEXT: .LBB29_2:
@@ -9089,7 +9089,7 @@ define amdgpu_kernel void @local_ds_fadd_one_as(ptr addrspace(1) %out, ptr addrs
; GFX12-NEXT: s_mov_b32 s7, exec_lo
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: v_readfirstlane_b32 s3, v1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mbcnt_lo_u32_b32 v2, s7, 0
; GFX12-NEXT: s_mov_b32 s6, exec_lo
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -9100,11 +9100,11 @@ define amdgpu_kernel void @local_ds_fadd_one_as(ptr addrspace(1) %out, ptr addrs
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_cvt_f32_ubyte0_e32 v1, s0
; GFX12-NEXT: s_lshl_b32 s0, s1, 4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mul_f32 v1, 0x42280000, v1
; GFX12-NEXT: ds_add_f32 v2, v1
; GFX12-NEXT: .LBB29_4:
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s6
; GFX12-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
; GFX12-NEXT: s_mov_b32 s1, exec_lo
@@ -9117,14 +9117,14 @@ define amdgpu_kernel void @local_ds_fadd_one_as(ptr addrspace(1) %out, ptr addrs
; GFX12-NEXT: ; implicit-def: $vgpr0
; GFX12-NEXT: .LBB29_5: ; %ComputeLoop
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_ctz_i32_b32 s3, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_readlane_b32 s6, v1, s3
; GFX12-NEXT: v_writelane_b32 v0, s0, s3
; GFX12-NEXT: s_lshl_b32 s3, 1, s3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 s1, s1, s3
; GFX12-NEXT: s_add_f32 s0, s0, s6
; GFX12-NEXT: s_cbranch_scc1 .LBB29_5
@@ -9134,18 +9134,18 @@ define amdgpu_kernel void @local_ds_fadd_one_as(ptr addrspace(1) %out, ptr addrs
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX12-NEXT: ; implicit-def: $vgpr1
; GFX12-NEXT: s_and_saveexec_b32 s1, vcc_lo
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_xor_b32 s1, exec_lo, s1
; GFX12-NEXT: ; %bb.7:
; GFX12-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s0
; GFX12-NEXT: ds_add_rtn_f32 v1, v1, v2
; GFX12-NEXT: ; %bb.8:
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: v_readfirstlane_b32 s2, v1
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_f32 v0, s2, v0
; GFX12-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
@@ -9334,7 +9334,7 @@ define amdgpu_kernel void @local_ds_fadd_one_as(ptr addrspace(1) %out, ptr addrs
; GFX10-NEXT: v_mul_f32_e32 v1, 0x42280000, v1
; GFX10-NEXT: ds_add_rtn_f32 v1, v2, v1
; GFX10-NEXT: .LBB29_2:
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX10-NEXT: s_mov_b32 s7, exec_lo
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
@@ -9351,7 +9351,7 @@ define amdgpu_kernel void @local_ds_fadd_one_as(ptr addrspace(1) %out, ptr addrs
; GFX10-NEXT: v_mul_f32_e32 v1, 0x42280000, v1
; GFX10-NEXT: ds_add_f32 v2, v1
; GFX10-NEXT: .LBB29_4:
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s6
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
; GFX10-NEXT: v_bfrev_b32_e32 v1, 1
@@ -9380,7 +9380,7 @@ define amdgpu_kernel void @local_ds_fadd_one_as(ptr addrspace(1) %out, ptr addrs
; GFX10-NEXT: v_mov_b32_e32 v2, s2
; GFX10-NEXT: ds_add_rtn_f32 v2, v2, v1
; GFX10-NEXT: ; %bb.8:
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
index 65d6c4428cbec..657a90d71b8ee 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
@@ -817,9 +817,9 @@ define half @local_atomic_fmax_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB8_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -861,9 +861,9 @@ define half @local_atomic_fmax_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB8_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1213,9 +1213,9 @@ define half @local_atomic_fmax_ret_f16__offset(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB9_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1259,9 +1259,9 @@ define half @local_atomic_fmax_ret_f16__offset(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB9_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1621,9 +1621,9 @@ define void @local_atomic_fmax_noret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB10_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1664,9 +1664,9 @@ define void @local_atomic_fmax_noret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB10_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2003,9 +2003,9 @@ define void @local_atomic_fmax_noret_f16__offset(ptr addrspace(3) %ptr) nounwind
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB11_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2048,9 +2048,9 @@ define void @local_atomic_fmax_noret_f16__offset(ptr addrspace(3) %ptr) nounwind
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB11_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2388,9 +2388,9 @@ define half @local_atomic_fmax_ret_f16__offset__align4(ptr addrspace(3) %ptr) no
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB12_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2423,9 +2423,9 @@ define half @local_atomic_fmax_ret_f16__offset__align4(ptr addrspace(3) %ptr) no
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB12_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2696,9 +2696,9 @@ define void @local_atomic_fmax_noret_f16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB13_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2730,9 +2730,9 @@ define void @local_atomic_fmax_noret_f16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB13_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3002,7 +3002,7 @@ define bfloat @local_atomic_fmax_ret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -3015,9 +3015,9 @@ define bfloat @local_atomic_fmax_ret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB14_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3055,7 +3055,7 @@ define bfloat @local_atomic_fmax_ret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -3067,9 +3067,9 @@ define bfloat @local_atomic_fmax_ret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB14_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3460,7 +3460,7 @@ define bfloat @local_atomic_fmax_ret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -3473,9 +3473,9 @@ define bfloat @local_atomic_fmax_ret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB15_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3515,7 +3515,7 @@ define bfloat @local_atomic_fmax_ret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -3527,9 +3527,9 @@ define bfloat @local_atomic_fmax_ret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB15_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3929,7 +3929,7 @@ define void @local_atomic_fmax_noret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -3943,9 +3943,9 @@ define void @local_atomic_fmax_noret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB16_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3981,7 +3981,7 @@ define void @local_atomic_fmax_noret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
@@ -3994,9 +3994,9 @@ define void @local_atomic_fmax_noret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB16_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4373,7 +4373,7 @@ define void @local_atomic_fmax_noret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
@@ -4387,9 +4387,9 @@ define void @local_atomic_fmax_noret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB17_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4426,7 +4426,7 @@ define void @local_atomic_fmax_noret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
@@ -4439,9 +4439,9 @@ define void @local_atomic_fmax_noret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB17_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4820,7 +4820,7 @@ define bfloat @local_atomic_fmax_ret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
@@ -4832,9 +4832,9 @@ define bfloat @local_atomic_fmax_ret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB18_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4864,7 +4864,7 @@ define bfloat @local_atomic_fmax_ret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-FAKE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
@@ -4875,9 +4875,9 @@ define bfloat @local_atomic_fmax_ret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB18_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5197,7 +5197,7 @@ define void @local_atomic_fmax_noret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -5209,9 +5209,9 @@ define void @local_atomic_fmax_noret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB19_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5239,7 +5239,7 @@ define void @local_atomic_fmax_noret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -5250,9 +5250,9 @@ define void @local_atomic_fmax_noret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB19_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5566,9 +5566,9 @@ define <2 x half> @local_atomic_fmax_ret_v2f16(ptr addrspace(3) %ptr, <2 x half>
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB20_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5838,9 +5838,9 @@ define <2 x half> @local_atomic_fmax_ret_v2f16__offset(ptr addrspace(3) %ptr, <2
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB21_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6110,9 +6110,9 @@ define void @local_atomic_fmax_noret_v2f16(ptr addrspace(3) %ptr, <2 x half> %va
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v2
; GFX12-NEXT: v_mov_b32_e32 v2, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB22_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6372,9 +6372,9 @@ define void @local_atomic_fmax_noret_v2f16__offset(ptr addrspace(3) %ptr, <2 x h
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v2
; GFX12-NEXT: v_mov_b32_e32 v2, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB23_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6648,10 +6648,10 @@ define <2 x bfloat> @local_atomic_fmax_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.h
@@ -6660,9 +6660,9 @@ define <2 x bfloat> @local_atomic_fmax_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB24_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6694,7 +6694,7 @@ define <2 x bfloat> @local_atomic_fmax_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v7, v9 :: v_dual_lshlrev_b32 v2, 16, v4
; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v2, v2, v3
@@ -6703,7 +6703,7 @@ define <2 x bfloat> @local_atomic_fmax_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v6, v8, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v5, v2, 0x7060302
@@ -6712,9 +6712,9 @@ define <2 x bfloat> @local_atomic_fmax_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB24_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7126,10 +7126,10 @@ define <2 x bfloat> @local_atomic_fmax_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.h
@@ -7138,9 +7138,9 @@ define <2 x bfloat> @local_atomic_fmax_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB25_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7172,7 +7172,7 @@ define <2 x bfloat> @local_atomic_fmax_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v7, v9 :: v_dual_lshlrev_b32 v2, 16, v4
; GFX12-FAKE16-NEXT: v_max_num_f32_e32 v2, v2, v3
@@ -7181,7 +7181,7 @@ define <2 x bfloat> @local_atomic_fmax_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v6, v8, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v5, v2, 0x7060302
@@ -7190,9 +7190,9 @@ define <2 x bfloat> @local_atomic_fmax_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB25_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7601,11 +7601,11 @@ define void @local_atomic_fmax_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v4, v6, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -7614,9 +7614,9 @@ define void @local_atomic_fmax_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB26_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7651,10 +7651,10 @@ define void @local_atomic_fmax_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v4, v6, v8, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v4, v5, v4, 0x7060302
@@ -7664,9 +7664,9 @@ define void @local_atomic_fmax_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB26_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8059,11 +8059,11 @@ define void @local_atomic_fmax_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v4, v6, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -8072,9 +8072,9 @@ define void @local_atomic_fmax_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8109,10 +8109,10 @@ define void @local_atomic_fmax_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v4, v6, v8, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v4, v5, v4, 0x7060302
@@ -8122,9 +8122,9 @@ define void @local_atomic_fmax_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
index 0423fc36d9131..1144291ec95d7 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
@@ -817,9 +817,9 @@ define half @local_atomic_fmin_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB8_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -861,9 +861,9 @@ define half @local_atomic_fmin_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB8_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1213,9 +1213,9 @@ define half @local_atomic_fmin_ret_f16__offset(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB9_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1259,9 +1259,9 @@ define half @local_atomic_fmin_ret_f16__offset(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB9_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1621,9 +1621,9 @@ define void @local_atomic_fmin_noret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB10_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1664,9 +1664,9 @@ define void @local_atomic_fmin_noret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB10_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2003,9 +2003,9 @@ define void @local_atomic_fmin_noret_f16__offset(ptr addrspace(3) %ptr) nounwind
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB11_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2048,9 +2048,9 @@ define void @local_atomic_fmin_noret_f16__offset(ptr addrspace(3) %ptr) nounwind
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB11_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2388,9 +2388,9 @@ define half @local_atomic_fmin_ret_f16__offset__align4(ptr addrspace(3) %ptr) no
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB12_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2423,9 +2423,9 @@ define half @local_atomic_fmin_ret_f16__offset__align4(ptr addrspace(3) %ptr) no
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB12_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2696,9 +2696,9 @@ define void @local_atomic_fmin_noret_f16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB13_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2730,9 +2730,9 @@ define void @local_atomic_fmin_noret_f16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB13_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3002,7 +3002,7 @@ define bfloat @local_atomic_fmin_ret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -3015,9 +3015,9 @@ define bfloat @local_atomic_fmin_ret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB14_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3055,7 +3055,7 @@ define bfloat @local_atomic_fmin_ret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -3067,9 +3067,9 @@ define bfloat @local_atomic_fmin_ret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB14_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3460,7 +3460,7 @@ define bfloat @local_atomic_fmin_ret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -3473,9 +3473,9 @@ define bfloat @local_atomic_fmin_ret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB15_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3515,7 +3515,7 @@ define bfloat @local_atomic_fmin_ret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -3527,9 +3527,9 @@ define bfloat @local_atomic_fmin_ret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB15_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3929,7 +3929,7 @@ define void @local_atomic_fmin_noret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -3943,9 +3943,9 @@ define void @local_atomic_fmin_noret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB16_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3981,7 +3981,7 @@ define void @local_atomic_fmin_noret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
@@ -3994,9 +3994,9 @@ define void @local_atomic_fmin_noret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB16_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4373,7 +4373,7 @@ define void @local_atomic_fmin_noret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
@@ -4387,9 +4387,9 @@ define void @local_atomic_fmin_noret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB17_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4426,7 +4426,7 @@ define void @local_atomic_fmin_noret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
@@ -4439,9 +4439,9 @@ define void @local_atomic_fmin_noret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB17_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4820,7 +4820,7 @@ define bfloat @local_atomic_fmin_ret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
@@ -4832,9 +4832,9 @@ define bfloat @local_atomic_fmin_ret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB18_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4864,7 +4864,7 @@ define bfloat @local_atomic_fmin_ret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-FAKE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
@@ -4875,9 +4875,9 @@ define bfloat @local_atomic_fmin_ret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB18_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5197,7 +5197,7 @@ define void @local_atomic_fmin_noret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -5209,9 +5209,9 @@ define void @local_atomic_fmin_noret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB19_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5239,7 +5239,7 @@ define void @local_atomic_fmin_noret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -5250,9 +5250,9 @@ define void @local_atomic_fmin_noret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB19_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5566,9 +5566,9 @@ define <2 x half> @local_atomic_fmin_ret_v2f16(ptr addrspace(3) %ptr, <2 x half>
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB20_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5838,9 +5838,9 @@ define <2 x half> @local_atomic_fmin_ret_v2f16__offset(ptr addrspace(3) %ptr, <2
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB21_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6110,9 +6110,9 @@ define void @local_atomic_fmin_noret_v2f16(ptr addrspace(3) %ptr, <2 x half> %va
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v2
; GFX12-NEXT: v_mov_b32_e32 v2, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB22_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6372,9 +6372,9 @@ define void @local_atomic_fmin_noret_v2f16__offset(ptr addrspace(3) %ptr, <2 x h
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v2
; GFX12-NEXT: v_mov_b32_e32 v2, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB23_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6648,10 +6648,10 @@ define <2 x bfloat> @local_atomic_fmin_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.h
@@ -6660,9 +6660,9 @@ define <2 x bfloat> @local_atomic_fmin_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB24_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6694,7 +6694,7 @@ define <2 x bfloat> @local_atomic_fmin_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v7, v9 :: v_dual_lshlrev_b32 v2, 16, v4
; GFX12-FAKE16-NEXT: v_min_num_f32_e32 v2, v2, v3
@@ -6703,7 +6703,7 @@ define <2 x bfloat> @local_atomic_fmin_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v6, v8, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v5, v2, 0x7060302
@@ -6712,9 +6712,9 @@ define <2 x bfloat> @local_atomic_fmin_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB24_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7126,10 +7126,10 @@ define <2 x bfloat> @local_atomic_fmin_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.h
@@ -7138,9 +7138,9 @@ define <2 x bfloat> @local_atomic_fmin_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB25_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7172,7 +7172,7 @@ define <2 x bfloat> @local_atomic_fmin_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v7, v9 :: v_dual_lshlrev_b32 v2, 16, v4
; GFX12-FAKE16-NEXT: v_min_num_f32_e32 v2, v2, v3
@@ -7181,7 +7181,7 @@ define <2 x bfloat> @local_atomic_fmin_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v6, v8, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v5, v2, 0x7060302
@@ -7190,9 +7190,9 @@ define <2 x bfloat> @local_atomic_fmin_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB25_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7601,11 +7601,11 @@ define void @local_atomic_fmin_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v4, v6, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -7614,9 +7614,9 @@ define void @local_atomic_fmin_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB26_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7651,10 +7651,10 @@ define void @local_atomic_fmin_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v4, v6, v8, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v4, v5, v4, 0x7060302
@@ -7664,9 +7664,9 @@ define void @local_atomic_fmin_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB26_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8059,11 +8059,11 @@ define void @local_atomic_fmin_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v4, v6, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -8072,9 +8072,9 @@ define void @local_atomic_fmin_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8109,10 +8109,10 @@ define void @local_atomic_fmin_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v4, v6, v8, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v4, v5, v4, 0x7060302
@@ -8122,9 +8122,9 @@ define void @local_atomic_fmin_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
index 2b1030e3d5b40..dfe37fda186cb 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
@@ -36,9 +36,9 @@ define float @local_atomic_fsub_ret_f32(ptr addrspace(3) %ptr) nounwind {
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB0_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -248,9 +248,9 @@ define float @local_atomic_fsub_ret_f32__offset(ptr addrspace(3) %ptr) nounwind
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB1_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -460,9 +460,9 @@ define void @local_atomic_fsub_noret_f32(ptr addrspace(3) %ptr) nounwind {
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX12-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB2_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -661,9 +661,9 @@ define void @local_atomic_fsub_noret_f32__offset(ptr addrspace(3) %ptr) nounwind
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX12-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB3_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -870,9 +870,9 @@ define double @local_atomic_fsub_ret_f64(ptr addrspace(3) %ptr) nounwind {
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[3:4]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB4_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1087,9 +1087,9 @@ define double @local_atomic_fsub_ret_f64__offset(ptr addrspace(3) %ptr) nounwind
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[3:4]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB5_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1303,9 +1303,9 @@ define void @local_atomic_fsub_noret_f64(ptr addrspace(3) %ptr) nounwind {
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[1:2]
; GFX12-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB6_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1509,9 +1509,9 @@ define void @local_atomic_fsub_noret_f64__offset(ptr addrspace(3) %ptr) nounwind
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[1:2]
; GFX12-NEXT: v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB7_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1733,9 +1733,9 @@ define half @local_atomic_fsub_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB8_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -1776,9 +1776,9 @@ define half @local_atomic_fsub_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB8_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2118,9 +2118,9 @@ define half @local_atomic_fsub_ret_f16__offset(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB9_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2163,9 +2163,9 @@ define half @local_atomic_fsub_ret_f16__offset(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB9_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2515,9 +2515,9 @@ define void @local_atomic_fsub_noret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB10_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2557,9 +2557,9 @@ define void @local_atomic_fsub_noret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB10_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2887,9 +2887,9 @@ define void @local_atomic_fsub_noret_f16__offset(ptr addrspace(3) %ptr) nounwind
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB11_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2930,9 +2930,9 @@ define void @local_atomic_fsub_noret_f16__offset(ptr addrspace(3) %ptr) nounwind
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB11_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3260,9 +3260,9 @@ define half @local_atomic_fsub_ret_f16__offset__align4(ptr addrspace(3) %ptr) no
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB12_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3294,9 +3294,9 @@ define half @local_atomic_fsub_ret_f16__offset__align4(ptr addrspace(3) %ptr) no
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB12_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3558,9 +3558,9 @@ define void @local_atomic_fsub_noret_f16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB13_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3590,9 +3590,9 @@ define void @local_atomic_fsub_noret_f16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB13_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3854,7 +3854,7 @@ define bfloat @local_atomic_fsub_ret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -3867,9 +3867,9 @@ define bfloat @local_atomic_fsub_ret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB14_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3907,7 +3907,7 @@ define bfloat @local_atomic_fsub_ret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -3919,9 +3919,9 @@ define bfloat @local_atomic_fsub_ret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB14_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4310,7 +4310,7 @@ define bfloat @local_atomic_fsub_ret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4323,9 +4323,9 @@ define bfloat @local_atomic_fsub_ret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB15_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4365,7 +4365,7 @@ define bfloat @local_atomic_fsub_ret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
@@ -4377,9 +4377,9 @@ define bfloat @local_atomic_fsub_ret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB15_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4777,7 +4777,7 @@ define void @local_atomic_fsub_noret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4791,9 +4791,9 @@ define void @local_atomic_fsub_noret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB16_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -4829,7 +4829,7 @@ define void @local_atomic_fsub_noret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
@@ -4842,9 +4842,9 @@ define void @local_atomic_fsub_noret_bf16(ptr addrspace(3) %ptr) nounwind {
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB16_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5219,7 +5219,7 @@ define void @local_atomic_fsub_noret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0
@@ -5233,9 +5233,9 @@ define void @local_atomic_fsub_noret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB17_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5272,7 +5272,7 @@ define void @local_atomic_fsub_noret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX12-FAKE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
@@ -5285,9 +5285,9 @@ define void @local_atomic_fsub_noret_bf16__offset(ptr addrspace(3) %ptr) nounwin
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB17_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5664,7 +5664,7 @@ define bfloat @local_atomic_fsub_ret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
@@ -5676,9 +5676,9 @@ define bfloat @local_atomic_fsub_ret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB18_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5708,7 +5708,7 @@ define bfloat @local_atomic_fsub_ret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-FAKE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
@@ -5719,9 +5719,9 @@ define bfloat @local_atomic_fsub_ret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB18_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6039,7 +6039,7 @@ define void @local_atomic_fsub_noret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -6051,9 +6051,9 @@ define void @local_atomic_fsub_noret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB19_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6081,7 +6081,7 @@ define void @local_atomic_fsub_noret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -6092,9 +6092,9 @@ define void @local_atomic_fsub_noret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB19_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6404,9 +6404,9 @@ define <2 x half> @local_atomic_fsub_ret_v2f16(ptr addrspace(3) %ptr, <2 x half>
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB20_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6659,9 +6659,9 @@ define <2 x half> @local_atomic_fsub_ret_v2f16__offset(ptr addrspace(3) %ptr, <2
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB21_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -6913,9 +6913,9 @@ define void @local_atomic_fsub_noret_v2f16(ptr addrspace(3) %ptr, <2 x half> %va
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v2
; GFX12-NEXT: v_mov_b32_e32 v2, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB22_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7156,9 +7156,9 @@ define void @local_atomic_fsub_noret_v2f16__offset(ptr addrspace(3) %ptr, <2 x h
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v2
; GFX12-NEXT: v_mov_b32_e32 v2, v3
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB23_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7416,10 +7416,10 @@ define <2 x bfloat> @local_atomic_fsub_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.h
@@ -7428,9 +7428,9 @@ define <2 x bfloat> @local_atomic_fsub_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB24_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7462,7 +7462,7 @@ define <2 x bfloat> @local_atomic_fsub_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v7, v9 :: v_dual_lshlrev_b32 v2, 16, v4
; GFX12-FAKE16-NEXT: v_sub_f32_e32 v2, v2, v3
@@ -7471,7 +7471,7 @@ define <2 x bfloat> @local_atomic_fsub_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v6, v8, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v5, v2, 0x7060302
@@ -7480,9 +7480,9 @@ define <2 x bfloat> @local_atomic_fsub_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB24_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7894,10 +7894,10 @@ define <2 x bfloat> @local_atomic_fsub_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.h
@@ -7906,9 +7906,9 @@ define <2 x bfloat> @local_atomic_fsub_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB25_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -7940,7 +7940,7 @@ define <2 x bfloat> @local_atomic_fsub_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v7, v9 :: v_dual_lshlrev_b32 v2, 16, v4
; GFX12-FAKE16-NEXT: v_sub_f32_e32 v2, v2, v3
@@ -7949,7 +7949,7 @@ define <2 x bfloat> @local_atomic_fsub_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
; GFX12-FAKE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v2, v6, v8, s0
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v5, v2, 0x7060302
@@ -7958,9 +7958,9 @@ define <2 x bfloat> @local_atomic_fsub_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX12-FAKE16-NEXT: s_wait_dscnt 0x0
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB25_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8369,11 +8369,11 @@ define void @local_atomic_fsub_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v4, v6, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -8382,9 +8382,9 @@ define void @local_atomic_fsub_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB26_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8419,10 +8419,10 @@ define void @local_atomic_fsub_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v4, v6, v8, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v4, v5, v4, 0x7060302
@@ -8432,9 +8432,9 @@ define void @local_atomic_fsub_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB26_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8827,11 +8827,11 @@ define void @local_atomic_fsub_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v4, v6, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
@@ -8840,9 +8840,9 @@ define void @local_atomic_fsub_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX12-TRUE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -8877,10 +8877,10 @@ define void @local_atomic_fsub_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX12-FAKE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX12-FAKE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v4, v6, v8, s0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v4, v5, v4, 0x7060302
@@ -8890,9 +8890,9 @@ define void @local_atomic_fsub_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX12-FAKE16-NEXT: global_inv scope:SCOPE_SE
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v3
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9285,9 +9285,9 @@ define float @local_atomic_fsub_ret_f32__amdgpu_ignore_denormal_mode(ptr addrspa
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB28_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -9496,9 +9496,9 @@ define void @local_atomic_fsub_noret_f32__amdgpu_ignore_denormal_mode(ptr addrsp
; GFX12-NEXT: global_inv scope:SCOPE_SE
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
; GFX12-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-NEXT: s_cbranch_execnz .LBB29_1
; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end
diff --git a/llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll b/llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
index 5eb6bf6d8179a..bd4d2d50738d5 100644
--- a/llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
+++ b/llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
@@ -20,7 +20,7 @@ define amdgpu_kernel void @copy_flat(ptr nocapture %d, ptr nocapture readonly %s
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-NEXT: s_add_nc_u64 s[8:9], s[2:3], s[4:5]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v5, s1 :: v_dual_mov_b32 v4, s0
; GFX12-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
; GFX12-NEXT: s_add_co_i32 s6, s6, -1
@@ -314,7 +314,7 @@ define amdgpu_kernel void @copy_local(ptr addrspace(3) nocapture %d, ptr addrspa
; GFX12-NEXT: s_cbranch_scc1 .LBB3_2
; GFX12-NEXT: .LBB3_1: ; %for.body
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v2, s1
; GFX12-NEXT: v_mov_b32_e32 v4, s0
; GFX12-NEXT: s_add_co_i32 s2, s2, -1
@@ -339,7 +339,7 @@ define amdgpu_kernel void @copy_local(ptr addrspace(3) nocapture %d, ptr addrspa
; GFX12-SPREFETCH-NEXT: s_cbranch_scc1 .LBB3_2
; GFX12-SPREFETCH-NEXT: .LBB3_1: ; %for.body
; GFX12-SPREFETCH-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12-SPREFETCH-NEXT: s_wait_alu 0xfffe
+; GFX12-SPREFETCH-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SPREFETCH-NEXT: v_mov_b32_e32 v2, s1
; GFX12-SPREFETCH-NEXT: v_mov_b32_e32 v4, s0
; GFX12-SPREFETCH-NEXT: s_add_co_i32 s2, s2, -1
@@ -416,26 +416,26 @@ define amdgpu_kernel void @copy_flat_divergent(ptr nocapture %d, ptr nocapture r
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s7, 0, s1
; GFX12-NEXT: v_add_co_u32 v0, s1, s4, v0
; GFX12-NEXT: v_add_co_u32 v2, vcc_lo, 0xb0, v2
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s1
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX12-NEXT: .LBB4_2: ; %for.body
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, 0xffffff50, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v5, null, -1, v3, vcc_lo
; GFX12-NEXT: v_add_co_u32 v2, vcc_lo, v2, 16
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX12-NEXT: flat_load_b128 v[4:7], v[4:5]
; GFX12-NEXT: s_add_co_i32 s0, s0, -1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_cmp_lg_u32 s0, 0
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: flat_store_b128 v[0:1], v[4:7]
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, 16
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-NEXT: s_cbranch_scc1 .LBB4_2
; GFX12-NEXT: .LBB4_3: ; %for.end
@@ -458,26 +458,26 @@ define amdgpu_kernel void @copy_flat_divergent(ptr nocapture %d, ptr nocapture r
; GFX12-SPREFETCH-NEXT: v_add_co_ci_u32_e64 v3, null, s7, 0, s1
; GFX12-SPREFETCH-NEXT: v_add_co_u32 v0, s1, s4, v0
; GFX12-SPREFETCH-NEXT: v_add_co_u32 v2, vcc_lo, 0xb0, v2
-; GFX12-SPREFETCH-NEXT: s_wait_alu 0xf1ff
+; GFX12-SPREFETCH-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SPREFETCH-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s1
; GFX12-SPREFETCH-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX12-SPREFETCH-NEXT: .LBB4_2: ; %for.body
; GFX12-SPREFETCH-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-SPREFETCH-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SPREFETCH-NEXT: v_add_co_u32 v4, vcc_lo, 0xffffff50, v2
-; GFX12-SPREFETCH-NEXT: s_wait_alu 0xfffd
+; GFX12-SPREFETCH-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SPREFETCH-NEXT: v_add_co_ci_u32_e64 v5, null, -1, v3, vcc_lo
; GFX12-SPREFETCH-NEXT: v_add_co_u32 v2, vcc_lo, v2, 16
-; GFX12-SPREFETCH-NEXT: s_wait_alu 0xfffd
+; GFX12-SPREFETCH-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SPREFETCH-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX12-SPREFETCH-NEXT: flat_load_b128 v[4:7], v[4:5]
; GFX12-SPREFETCH-NEXT: s_add_co_i32 s0, s0, -1
-; GFX12-SPREFETCH-NEXT: s_wait_alu 0xfffe
+; GFX12-SPREFETCH-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SPREFETCH-NEXT: s_cmp_lg_u32 s0, 0
; GFX12-SPREFETCH-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-SPREFETCH-NEXT: flat_store_b128 v[0:1], v[4:7]
; GFX12-SPREFETCH-NEXT: v_add_co_u32 v0, vcc_lo, v0, 16
-; GFX12-SPREFETCH-NEXT: s_wait_alu 0xfffd
+; GFX12-SPREFETCH-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SPREFETCH-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-SPREFETCH-NEXT: s_cbranch_scc1 .LBB4_2
; GFX12-SPREFETCH-NEXT: .LBB4_3: ; %for.end
@@ -558,22 +558,22 @@ define amdgpu_kernel void @copy_global_divergent(ptr addrspace(1) nocapture %d,
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s7, 0, s1
; GFX12-NEXT: v_add_co_u32 v0, s1, s4, v0
; GFX12-NEXT: v_add_co_u32 v2, vcc_lo, 0xb0, v2
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s1
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX12-NEXT: .LBB5_2: ; %for.body
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: global_load_b128 v[4:7], v[2:3], off offset:-176
; GFX12-NEXT: v_add_co_u32 v2, vcc_lo, v2, 16
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX12-NEXT: s_add_co_i32 s0, s0, -1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_cmp_lg_u32 s0, 0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_store_b128 v[0:1], v[4:7], off
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, 16
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-NEXT: s_cbranch_scc1 .LBB5_2
; GFX12-NEXT: .LBB5_3: ; %for.end
@@ -596,22 +596,22 @@ define amdgpu_kernel void @copy_global_divergent(ptr addrspace(1) nocapture %d,
; GFX12-SPREFETCH-NEXT: v_add_co_ci_u32_e64 v3, null, s7, 0, s1
; GFX12-SPREFETCH-NEXT: v_add_co_u32 v0, s1, s4, v0
; GFX12-SPREFETCH-NEXT: v_add_co_u32 v2, vcc_lo, 0xb0, v2
-; GFX12-SPREFETCH-NEXT: s_wait_alu 0xf1ff
+; GFX12-SPREFETCH-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SPREFETCH-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s1
; GFX12-SPREFETCH-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX12-SPREFETCH-NEXT: .LBB5_2: ; %for.body
; GFX12-SPREFETCH-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-SPREFETCH-NEXT: global_load_b128 v[4:7], v[2:3], off offset:-176
; GFX12-SPREFETCH-NEXT: v_add_co_u32 v2, vcc_lo, v2, 16
-; GFX12-SPREFETCH-NEXT: s_wait_alu 0xfffd
+; GFX12-SPREFETCH-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SPREFETCH-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX12-SPREFETCH-NEXT: s_add_co_i32 s0, s0, -1
-; GFX12-SPREFETCH-NEXT: s_wait_alu 0xfffe
+; GFX12-SPREFETCH-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SPREFETCH-NEXT: s_cmp_lg_u32 s0, 0
; GFX12-SPREFETCH-NEXT: s_wait_loadcnt 0x0
; GFX12-SPREFETCH-NEXT: global_store_b128 v[0:1], v[4:7], off
; GFX12-SPREFETCH-NEXT: v_add_co_u32 v0, vcc_lo, v0, 16
-; GFX12-SPREFETCH-NEXT: s_wait_alu 0xfffd
+; GFX12-SPREFETCH-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SPREFETCH-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-SPREFETCH-NEXT: s_cbranch_scc1 .LBB5_2
; GFX12-SPREFETCH-NEXT: .LBB5_3: ; %for.end
diff --git a/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll b/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
index 4eeb98bc11ea3..932c66b77e9bf 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
@@ -132,7 +132,7 @@ define amdgpu_kernel void @buffer_nontemporal_load_store(ptr addrspace(7) %in, p
; GFX10-SDAG-NEXT: s_load_dword s11, s[8:9], 0x30
; GFX10-SDAG-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x20
; GFX10-SDAG-NEXT: buffer_load_dword v0, v0, s[4:7], 0 offen slc
-; GFX10-SDAG-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SDAG-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SDAG-NEXT: s_mov_b32 s5, s10
; GFX10-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-SDAG-NEXT: s_mov_b32 s4, s3
@@ -159,7 +159,7 @@ define amdgpu_kernel void @buffer_nontemporal_load_store(ptr addrspace(7) %in, p
; GFX10-GISEL-NEXT: buffer_load_dword v0, v0, s[4:7], 0 offen slc
; GFX10-GISEL-NEXT: s_clause 0x1
; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x20
-; GFX10-GISEL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-GISEL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-GISEL-NEXT: s_load_dword s7, s[8:9], 0x30
; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s0
@@ -416,7 +416,7 @@ define amdgpu_kernel void @buffer_nontemporal_and_volatile_load_store(ptr addrsp
; GFX10-SDAG-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x20
; GFX10-SDAG-NEXT: buffer_load_dword v0, v0, s[4:7], 0 offen glc dlc
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX10-SDAG-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-SDAG-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-SDAG-NEXT: s_mov_b32 s5, s10
; GFX10-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-SDAG-NEXT: s_mov_b32 s4, s3
@@ -444,7 +444,7 @@ define amdgpu_kernel void @buffer_nontemporal_and_volatile_load_store(ptr addrsp
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10-GISEL-NEXT: s_clause 0x1
; GFX10-GISEL-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x20
-; GFX10-GISEL-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-GISEL-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-GISEL-NEXT: s_load_dword s7, s[8:9], 0x30
; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s0
diff --git a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
index 169a84ff1f86b..09225709a1acf 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
@@ -270,10 +270,10 @@ define void @workgroup_ids_device_func(ptr addrspace(1) %outx, ptr addrspace(1)
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_and_b32 s0, ttmp7, 0xffff
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v6, ttmp9 :: v_dual_mov_b32 v7, s0
; GFX12-NEXT: s_lshr_b32 s1, ttmp7, 16
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v8, s1
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_store_b32 v[0:1], v6, off scope:SCOPE_SYS
diff --git a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
index 48128989cdca3..c90f6e9c2be4b 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
@@ -145,7 +145,7 @@ define amdgpu_cs void @caller() {
; GFX12-SDAG-NEXT: s_mov_b32 s1, callee at abs32@hi
; GFX12-SDAG-NEXT: s_mov_b32 s0, callee at abs32@lo
; GFX12-SDAG-NEXT: s_mov_b32 s32, 0
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -155,7 +155,7 @@ define amdgpu_cs void @caller() {
; GFX12-GISEL-NEXT: s_mov_b32 s0, callee at abs32@lo
; GFX12-GISEL-NEXT: s_mov_b32 s1, callee at abs32@hi
; GFX12-GISEL-NEXT: s_mov_b32 s32, 0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX12-GISEL-NEXT: s_endpgm
%idx = call i32 @llvm.amdgcn.workgroup.id.x()
@@ -222,10 +222,10 @@ define amdgpu_gfx void @workgroup_ids_gfx(ptr addrspace(1) %outx, ptr addrspace(
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_and_b32 s0, ttmp7, 0xffff
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v6, ttmp9 :: v_dual_mov_b32 v7, s0
; GFX12-NEXT: s_lshr_b32 s1, ttmp7, 16
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_mov_b32_e32 v8, s1
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: global_store_b32 v[0:1], v6, off scope:SCOPE_SYS
diff --git a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
index 48363d627839b..2f3ca8b795f7d 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
@@ -323,7 +323,7 @@ define amdgpu_cs void @caller() {
; GFX12-SDAG-NEXT: s_mov_b32 s1, callee at abs32@hi
; GFX12-SDAG-NEXT: s_mov_b32 s0, callee at abs32@lo
; GFX12-SDAG-NEXT: s_mov_b32 s32, 0
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -333,7 +333,7 @@ define amdgpu_cs void @caller() {
; GFX12-GISEL-NEXT: s_mov_b32 s0, callee at abs32@lo
; GFX12-GISEL-NEXT: s_mov_b32 s1, callee at abs32@hi
; GFX12-GISEL-NEXT: s_mov_b32 s32, 0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX12-GISEL-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/mad_64_32.ll b/llvm/test/CodeGen/AMDGPU/mad_64_32.ll
index 66e3f9866268e..fc8467cb73ab6 100644
--- a/llvm/test/CodeGen/AMDGPU/mad_64_32.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad_64_32.ll
@@ -405,22 +405,22 @@ define i128 @mad_i64_i32_sextops_i32_i128(i32 %arg0, i32 %arg1, i128 %arg2) #0 {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_mad_co_i64_i32 v[0:1], null, v14, v0, v[11:12]
; GFX12-NEXT: v_add_co_u32 v8, s0, v10, v8
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v9, null, 0, 0, s0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_mad_co_u64_u32 v[8:9], null, v13, v14, v[8:9]
; GFX12-NEXT: v_add_co_u32 v8, vcc_lo, v8, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT: v_add_co_ci_u32_e64 v9, null, v9, v1, vcc_lo
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v6, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v7, v3, vcc_lo
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v8, v4, vcc_lo
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v9, v5, vcc_lo
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: mad_i64_i32_sextops_i32_i128:
@@ -1325,13 +1325,13 @@ define i64 @mad_i64_i32_thrice(i32 %arg0, i32 %arg1, i64 %arg2, i64 %arg3, i64 %
; GFX12-NEXT: v_mad_co_i64_i32 v[0:1], null, v0, v1, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_add_co_u32 v2, vcc_lo, v0, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, v1, v3, vcc_lo
; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, v0, v4
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v5, null, v1, v5, vcc_lo
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v6
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v7, vcc_lo
; GFX12-NEXT: v_xor_b32_e32 v2, v2, v4
; GFX12-NEXT: v_xor_b32_e32 v3, v3, v5
@@ -1435,7 +1435,7 @@ define i64 @mad_i64_i32_secondary_use(i32 %arg0, i32 %arg1, i64 %arg2) #0 {
; GFX12-NEXT: v_mad_co_i64_i32 v[0:1], null, v0, v1, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_add_co_u32 v2, vcc_lo, v0, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, v1, v3, vcc_lo
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_xor_b32_e32 v0, v2, v0
@@ -2063,11 +2063,11 @@ define i64 @lshr_mad_i64_negative_3(i64 %arg0) #0 {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_and_b32_e32 v2, 0xfffffc00, v2
; GFX12-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_sub_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, 1
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/madak.ll b/llvm/test/CodeGen/AMDGPU/madak.ll
index 9bee6bdc7d9d1..b2813b392d253 100644
--- a/llvm/test/CodeGen/AMDGPU/madak.ll
+++ b/llvm/test/CodeGen/AMDGPU/madak.ll
@@ -823,7 +823,7 @@ define amdgpu_kernel void @v_s_madak_f32(ptr addrspace(1) noalias %out, float %a
; GFX10-MAD-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-MAD-NEXT: s_clause 0x1
; GFX10-MAD-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX10-MAD-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-MAD-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-MAD-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-MAD-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-MAD-NEXT: v_madak_f32 v1, s2, v1, 0x41200000
@@ -871,7 +871,7 @@ define amdgpu_kernel void @v_s_madak_f32(ptr addrspace(1) noalias %out, float %a
; GFX10-FMA-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-FMA-NEXT: s_clause 0x1
; GFX10-FMA-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX10-FMA-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-FMA-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-FMA-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-FMA-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-FMA-NEXT: v_fmaak_f32 v1, s2, v1, 0x41200000
diff --git a/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll b/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
index 8dea9e87e140f..7c5e406bd07cc 100644
--- a/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
+++ b/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
@@ -15,7 +15,7 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc() #0 {
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x80880
; GFX10_1-NEXT: buffer_store_dword v1, off, s[0:3], s5 ; 4-byte Folded Spill
-; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10_1-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: v_lshrrev_b32_e64 v0, 5, s32
; GFX10_1-NEXT: v_writelane_b32 v1, s55, 0
@@ -34,7 +34,7 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc() #0 {
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x80880
; GFX10_1-NEXT: buffer_load_dword v1, off, s[0:3], s5 ; 4-byte Folded Reload
-; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10_1-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: s_waitcnt vmcnt(0)
; GFX10_1-NEXT: s_setpc_b64 s[30:31]
@@ -106,20 +106,20 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc() #0 {
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_store_b32 off, v1, s32 offset:16388 ; 4-byte Folded Spill
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-NEXT: s_and_b32 s0, 0, exec_lo
; GFX12-NEXT: v_writelane_b32 v1, s55, 0
; GFX12-NEXT: s_add_co_ci_u32 s0, s32, 0x4000
; GFX12-NEXT: v_mov_b32_e32 v0, s32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_bitcmp1_b32 s0, 0
; GFX12-NEXT: s_bitset0_b32 s0, 0
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; use alloca0 v0
; GFX12-NEXT: ;;#ASMEND
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 s55, s0
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; use s55, scc
@@ -127,7 +127,7 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc() #0 {
; GFX12-NEXT: v_readlane_b32 s55, v1, 0
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_load_b32 v1, off, s32 offset:16388 ; 4-byte Folded Reload
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -233,7 +233,7 @@ define void @scalar_mov_materializes_frame_index_dead_scc() #0 {
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x80880
; GFX10_1-NEXT: buffer_store_dword v1, off, s[0:3], s5 ; 4-byte Folded Spill
-; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10_1-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: v_writelane_b32 v1, s55, 0
; GFX10_1-NEXT: v_lshrrev_b32_e64 v0, 5, s32
@@ -250,7 +250,7 @@ define void @scalar_mov_materializes_frame_index_dead_scc() #0 {
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x80880
; GFX10_1-NEXT: buffer_load_dword v1, off, s[0:3], s5 ; 4-byte Folded Reload
-; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10_1-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: s_waitcnt vmcnt(0)
; GFX10_1-NEXT: s_setpc_b64 s[30:31]
@@ -317,12 +317,12 @@ define void @scalar_mov_materializes_frame_index_dead_scc() #0 {
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_store_b32 off, v1, s32 offset:16388 ; 4-byte Folded Spill
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: v_writelane_b32 v1, s55, 0
; GFX12-NEXT: s_add_co_i32 s0, s32, 0x4000
; GFX12-NEXT: v_mov_b32_e32 v0, s32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 s55, s0
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; use alloca0 v0
@@ -333,7 +333,7 @@ define void @scalar_mov_materializes_frame_index_dead_scc() #0 {
; GFX12-NEXT: v_readlane_b32 s55, v1, 0
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_load_b32 v1, off, s32 offset:16388 ; 4-byte Folded Reload
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -431,7 +431,7 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_fp() #1 {
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s6, s33, 0x80880
; GFX10_1-NEXT: buffer_store_dword v1, off, s[0:3], s6 ; 4-byte Folded Spill
-; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10_1-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: v_lshrrev_b32_e64 v0, 5, s33
; GFX10_1-NEXT: v_writelane_b32 v1, s55, 0
@@ -452,7 +452,7 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_fp() #1 {
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s6, s33, 0x80880
; GFX10_1-NEXT: buffer_load_dword v1, off, s[0:3], s6 ; 4-byte Folded Reload
-; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10_1-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: s_mov_b32 s33, s5
; GFX10_1-NEXT: s_waitcnt vmcnt(0)
@@ -536,20 +536,20 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_fp() #1 {
; GFX12-NEXT: s_mov_b32 s33, s32
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_store_b32 off, v1, s33 offset:16388 ; 4-byte Folded Spill
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: s_addk_co_i32 s32, 0x4040
; GFX12-NEXT: s_and_b32 s0, 0, exec_lo
; GFX12-NEXT: v_writelane_b32 v1, s55, 0
; GFX12-NEXT: s_add_co_ci_u32 s0, s33, 0x4000
; GFX12-NEXT: v_mov_b32_e32 v0, s33
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_bitcmp1_b32 s0, 0
; GFX12-NEXT: s_bitset0_b32 s0, 0
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; use alloca0 v0
; GFX12-NEXT: ;;#ASMEND
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 s55, s0
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; use s55, scc
@@ -558,11 +558,11 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_fp() #1 {
; GFX12-NEXT: s_mov_b32 s32, s33
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_load_b32 v1, off, s33 offset:16388 ; 4-byte Folded Reload
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: s_mov_b32 s33, s1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: scalar_mov_materializes_frame_index_unavailable_scc_fp:
@@ -679,7 +679,7 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset()
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x80800
; GFX10_1-NEXT: buffer_store_dword v0, off, s[0:3], s5 ; 4-byte Folded Spill
-; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10_1-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: v_lshrrev_b32_e64 v1, 5, s32
; GFX10_1-NEXT: v_writelane_b32 v0, s55, 0
@@ -693,7 +693,7 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset()
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x80800
; GFX10_1-NEXT: buffer_load_dword v0, off, s[0:3], s5 ; 4-byte Folded Reload
-; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10_1-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: s_waitcnt vmcnt(0)
; GFX10_1-NEXT: s_setpc_b64 s[30:31]
@@ -756,7 +756,7 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset()
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_store_b32 off, v0, s32 offset:16384 ; 4-byte Folded Spill
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: v_writelane_b32 v0, s55, 0
; GFX12-NEXT: s_mov_b32 s55, s32
@@ -768,7 +768,7 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset()
; GFX12-NEXT: v_readlane_b32 s55, v0, 0
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_load_b32 v0, off, s32 offset:16384 ; 4-byte Folded Reload
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -855,7 +855,7 @@ define void @scalar_mov_materializes_frame_index_available_scc_small_offset() #0
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x80800
; GFX10_1-NEXT: buffer_store_dword v0, off, s[0:3], s5 ; 4-byte Folded Spill
-; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10_1-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: v_writelane_b32 v0, s55, 0
; GFX10_1-NEXT: s_lshr_b32 s55, s32, 5
@@ -867,7 +867,7 @@ define void @scalar_mov_materializes_frame_index_available_scc_small_offset() #0
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x80800
; GFX10_1-NEXT: buffer_load_dword v0, off, s[0:3], s5 ; 4-byte Folded Reload
-; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10_1-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: s_waitcnt vmcnt(0)
; GFX10_1-NEXT: s_setpc_b64 s[30:31]
@@ -924,7 +924,7 @@ define void @scalar_mov_materializes_frame_index_available_scc_small_offset() #0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_store_b32 off, v0, s32 offset:16384 ; 4-byte Folded Spill
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: v_writelane_b32 v0, s55, 0
; GFX12-NEXT: s_mov_b32 s55, s32
@@ -935,7 +935,7 @@ define void @scalar_mov_materializes_frame_index_available_scc_small_offset() #0
; GFX12-NEXT: v_readlane_b32 s55, v0, 0
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_load_b32 v0, off, s32 offset:16384 ; 4-byte Folded Reload
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -1016,7 +1016,7 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset_fp
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s6, s33, 0x80800
; GFX10_1-NEXT: buffer_store_dword v0, off, s[0:3], s6 ; 4-byte Folded Spill
-; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10_1-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: v_lshrrev_b32_e64 v1, 5, s33
; GFX10_1-NEXT: v_writelane_b32 v0, s55, 0
@@ -1032,7 +1032,7 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset_fp
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s6, s33, 0x80800
; GFX10_1-NEXT: buffer_load_dword v0, off, s[0:3], s6 ; 4-byte Folded Reload
-; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10_1-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: s_mov_b32 s33, s5
; GFX10_1-NEXT: s_waitcnt vmcnt(0)
@@ -1107,7 +1107,7 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset_fp
; GFX12-NEXT: s_mov_b32 s33, s32
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_store_b32 off, v0, s33 offset:16384 ; 4-byte Folded Spill
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: v_writelane_b32 v0, s55, 0
; GFX12-NEXT: s_addk_co_i32 s32, 0x4040
@@ -1120,11 +1120,11 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset_fp
; GFX12-NEXT: s_mov_b32 s32, s33
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_load_b32 v0, off, s33 offset:16384 ; 4-byte Folded Reload
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: s_mov_b32 s33, s1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: scalar_mov_materializes_frame_index_unavailable_scc_small_offset_fp:
@@ -1226,7 +1226,7 @@ define void @scalar_mov_materializes_frame_index_available_scc_small_offset_fp()
; GFX10_1-NEXT: s_xor_saveexec_b32 s5, -1
; GFX10_1-NEXT: s_add_i32 s6, s33, 0x80800
; GFX10_1-NEXT: buffer_store_dword v0, off, s[0:3], s6 ; 4-byte Folded Spill
-; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10_1-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10_1-NEXT: s_mov_b32 exec_lo, s5
; GFX10_1-NEXT: v_writelane_b32 v0, s55, 0
; GFX10_1-NEXT: s_add_i32 s32, s32, 0x81000
@@ -1240,7 +1240,7 @@ define void @scalar_mov_materializes_frame_index_available_scc_small_offset_fp()
; GFX10_1-NEXT: s_xor_saveexec_b32 s5, -1
; GFX10_1-NEXT: s_add_i32 s6, s33, 0x80800
; GFX10_1-NEXT: buffer_load_dword v0, off, s[0:3], s6 ; 4-byte Folded Reload
-; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10_1-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10_1-NEXT: s_mov_b32 exec_lo, s5
; GFX10_1-NEXT: s_mov_b32 s33, s4
; GFX10_1-NEXT: s_waitcnt vmcnt(0)
@@ -1309,7 +1309,7 @@ define void @scalar_mov_materializes_frame_index_available_scc_small_offset_fp()
; GFX12-NEXT: s_mov_b32 s33, s32
; GFX12-NEXT: s_xor_saveexec_b32 s1, -1
; GFX12-NEXT: scratch_store_b32 off, v0, s33 offset:16384 ; 4-byte Folded Spill
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s1
; GFX12-NEXT: v_writelane_b32 v0, s55, 0
; GFX12-NEXT: s_addk_co_i32 s32, 0x4040
@@ -1321,11 +1321,11 @@ define void @scalar_mov_materializes_frame_index_available_scc_small_offset_fp()
; GFX12-NEXT: v_readlane_b32 s55, v0, 0
; GFX12-NEXT: s_xor_saveexec_b32 s1, -1
; GFX12-NEXT: scratch_load_b32 v0, off, s33 offset:16384 ; 4-byte Folded Reload
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s1
; GFX12-NEXT: s_mov_b32 s33, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: scalar_mov_materializes_frame_index_available_scc_small_offset_fp:
@@ -1417,7 +1417,7 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_immoffset(
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x100800
; GFX10_1-NEXT: buffer_store_dword v1, off, s[0:3], s5 ; 4-byte Folded Spill
-; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10_1-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: v_writelane_b32 v1, s55, 0
; GFX10_1-NEXT: v_lshrrev_b32_e64 v0, 5, s32
@@ -1435,7 +1435,7 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_immoffset(
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x100800
; GFX10_1-NEXT: buffer_load_dword v1, off, s[0:3], s5 ; 4-byte Folded Reload
-; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10_1-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: s_waitcnt vmcnt(0)
; GFX10_1-NEXT: s_setpc_b64 s[30:31]
@@ -1502,7 +1502,7 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_immoffset(
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_store_b32 off, v1, s32 offset:32768 ; 4-byte Folded Spill
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: v_writelane_b32 v1, s55, 0
; GFX12-NEXT: s_add_co_i32 s55, s32, 0x43ec
@@ -1517,7 +1517,7 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_immoffset(
; GFX12-NEXT: v_readlane_b32 s55, v1, 0
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_load_b32 v1, off, s32 offset:32768 ; 4-byte Folded Reload
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -1616,7 +1616,7 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_sgpr_offse
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x100800
; GFX10_1-NEXT: buffer_store_dword v1, off, s[0:3], s5 ; 4-byte Folded Spill
-; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10_1-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: v_writelane_b32 v1, s55, 0
; GFX10_1-NEXT: v_lshrrev_b32_e64 v0, 5, s32
@@ -1635,7 +1635,7 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_sgpr_offse
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x100800
; GFX10_1-NEXT: buffer_load_dword v1, off, s[0:3], s5 ; 4-byte Folded Reload
-; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10_1-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: s_waitcnt vmcnt(0)
; GFX10_1-NEXT: s_setpc_b64 s[30:31]
@@ -1705,12 +1705,12 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_sgpr_offse
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_xor_saveexec_b32 s1, -1
; GFX12-NEXT: scratch_store_b32 off, v1, s32 offset:32768 ; 4-byte Folded Spill
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s1
; GFX12-NEXT: v_writelane_b32 v1, s55, 0
; GFX12-NEXT: s_add_co_i32 s1, s32, 0x4000
; GFX12-NEXT: v_mov_b32_e32 v0, s32
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_lshl2_add_u32 s55, s0, s1
; GFX12-NEXT: s_and_b32 s0, 0, exec_lo
; GFX12-NEXT: ;;#ASMSTART
@@ -1722,7 +1722,7 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_sgpr_offse
; GFX12-NEXT: v_readlane_b32 s55, v1, 0
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_load_b32 v1, off, s32 offset:32768 ; 4-byte Folded Reload
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll b/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
index 17581bcb61e99..481eb1bc3d91a 100644
--- a/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
@@ -303,7 +303,7 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x80880
; GFX10_1-NEXT: buffer_store_dword v23, off, s[0:3], s5 ; 4-byte Folded Spill
-; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10_1-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: v_writelane_b32 v23, s30, 0
; GFX10_1-NEXT: v_lshrrev_b32_e64 v0, 5, s32
@@ -358,7 +358,7 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x80880
; GFX10_1-NEXT: buffer_load_dword v23, off, s[0:3], s5 ; 4-byte Folded Reload
-; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10_1-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: s_waitcnt vmcnt(0)
; GFX10_1-NEXT: s_setpc_b64 s[30:31]
@@ -503,7 +503,7 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_store_b32 off, v23, s32 offset:16388 ; 4-byte Folded Spill
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: v_writelane_b32 v23, s30, 0
; GFX12-NEXT: v_mov_b32_e32 v0, s32
@@ -532,10 +532,10 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX12-NEXT: ;;#ASMEND
; GFX12-NEXT: s_add_co_ci_u32 s59, s32, 0x4000
; GFX12-NEXT: ; kill: def $sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55 killed $sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55 def $sgpr54
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_bitcmp1_b32 s59, 0
; GFX12-NEXT: s_bitset0_b32 s59, 0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 s54, s59
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc, s54, scc
@@ -559,7 +559,7 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX12-NEXT: v_readlane_b32 s30, v23, 0
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_load_b32 v23, off, s32 offset:16388 ; 4-byte Folded Reload
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -848,7 +848,7 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x80200
; GFX10_1-NEXT: buffer_store_dword v21, off, s[0:3], s5 ; 4-byte Folded Spill
-; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10_1-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: v_writelane_b32 v21, s30, 0
; GFX10_1-NEXT: s_and_b32 s59, 0, exec_lo
@@ -898,7 +898,7 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x80200
; GFX10_1-NEXT: buffer_load_dword v21, off, s[0:3], s5 ; 4-byte Folded Reload
-; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10_1-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: s_waitcnt vmcnt(0)
; GFX10_1-NEXT: s_setpc_b64 s[30:31]
@@ -1032,7 +1032,7 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_store_b32 off, v21, s32 offset:16384 ; 4-byte Folded Spill
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: v_writelane_b32 v21, s30, 0
; GFX12-NEXT: s_and_b32 s59, 0, exec_lo
@@ -1080,7 +1080,7 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX12-NEXT: v_readlane_b32 s30, v21, 0
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_load_b32 v21, off, s32 offset:16384 ; 4-byte Folded Reload
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -1406,7 +1406,7 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x100800
; GFX10_1-NEXT: buffer_store_dword v22, off, s[0:3], s5 ; 4-byte Folded Spill
-; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10_1-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: v_writelane_b32 v22, s30, 0
; GFX10_1-NEXT: v_lshrrev_b32_e64 v0, 5, s32
@@ -1461,7 +1461,7 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x100800
; GFX10_1-NEXT: buffer_load_dword v22, off, s[0:3], s5 ; 4-byte Folded Reload
-; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10_1-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: s_waitcnt vmcnt(0)
; GFX10_1-NEXT: s_setpc_b64 s[30:31]
@@ -1603,7 +1603,7 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_store_b32 off, v22, s32 offset:32768 ; 4-byte Folded Spill
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: v_writelane_b32 v22, s30, 0
; GFX12-NEXT: s_add_co_i32 s58, s32, 0x4200
@@ -1632,7 +1632,7 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX12-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc
; GFX12-NEXT: ;;#ASMEND
; GFX12-NEXT: ; kill: def $sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55 killed $sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55 def $sgpr54
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 s54, s58
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc, s54, scc
@@ -1656,7 +1656,7 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX12-NEXT: v_readlane_b32 s30, v22, 0
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_load_b32 v22, off, s32 offset:32768 ; 4-byte Folded Reload
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll b/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
index ca16e251d51cf..2385035c02073 100644
--- a/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
@@ -183,26 +183,26 @@ define bfloat @v_maximumnum_bf16(bfloat %x, bfloat %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v0.l, v0.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v0.h, v1.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v1, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v1.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v1.h, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -216,29 +216,29 @@ define bfloat @v_maximumnum_bf16(bfloat %x, bfloat %y) {
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call bfloat @llvm.maximumnum.bf16(bfloat %x, bfloat %y)
@@ -377,16 +377,16 @@ define bfloat @v_maximumnum_bf16_nnan(bfloat %x, bfloat %y) {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.l, v0.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v0.l, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -402,17 +402,17 @@ define bfloat @v_maximumnum_bf16_nnan(bfloat %x, bfloat %y) {
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_lshlrev_b32 v3, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -725,44 +725,44 @@ define <2 x bfloat> @v_maximumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v4.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v0.h, v1.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.h, v4.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.h, v4.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v4.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v4.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.h, v2.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v0.l, v1.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v1.l, v3.h, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v3.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v3.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.l, v3.h, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v2.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.h, v0.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, s1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v0.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -779,50 +779,50 @@ define <2 x bfloat> @v_maximumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v3 :: v_dual_lshlrev_b32 v5, 16, v0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v0 :: v_dual_lshlrev_b32 v4, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v3, v2 :: v_dual_lshlrev_b32 v7, 16, v1
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_lshlrev_b32 v7, 16, v5
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
@@ -1057,28 +1057,28 @@ define <2 x bfloat> @v_maximumnum_v2bf16_nnan(<2 x bfloat> %x, <2 x bfloat> %y)
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v2
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v1.l, v0.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v3.h, v0.l, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.h, v0.l, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v1.h, v0.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v0.h, s1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v1.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v0.h, vcc_lo
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1097,31 +1097,31 @@ define <2 x bfloat> @v_maximumnum_v2bf16_nnan(<2 x bfloat> %x, <2 x bfloat> %y)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v7, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v3, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
@@ -1551,25 +1551,25 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v0.h, v2.h, vcc_lo
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v2.h, v6.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.h, v6.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v6.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v6.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v4.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v1.l, v3.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
@@ -1577,13 +1577,13 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v5.h
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v6.h, v5.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v5.h, s1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v3, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v0.h, v6.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v1.l
@@ -1593,26 +1593,26 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v6
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v2.l, v0.h, s2
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v2.h, s0
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v0, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.h, v0.h, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v6.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, s2
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v4.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v6.h, s1
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v0.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v4.h, s2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v0.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1630,71 +1630,71 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v4 :: v_dual_lshlrev_b32 v6, 16, v1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v9, 16, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v10, 16, v6
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v7, 16, v0
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v8
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v6, v1 :: v_dual_lshlrev_b32 v2, 16, v6
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v4, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x bfloat> @llvm.maximumnum.v3bf16(<3 x bfloat> %x, <3 x bfloat> %y)
@@ -2004,42 +2004,42 @@ define <3 x bfloat> @v_maximumnum_v3bf16_nnan(<3 x bfloat> %x, <3 x bfloat> %y)
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, 0
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v3.l, v1.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v4.h, v1.l, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v5
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v2
; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v4.h, v1.l, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v2.l, v0.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.h, v0.l, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v4
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.h, v2.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v0.l, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v2.h, v0.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v0.h, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v0.h, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2059,46 +2059,46 @@ define <3 x bfloat> @v_maximumnum_v3bf16_nnan(<3 x bfloat> %x, <3 x bfloat> %y)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v6
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
; GFX12-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v11, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v5, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v6
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v5, v7 :: v_dual_lshlrev_b32 v9, 16, v4
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -2655,45 +2655,45 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v6.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v1.h, v3.h, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v3.h, v6.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v5.h, v6.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v6.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.l, v6.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v4.l
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v8, v8
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v0.h, v2.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v2.h, v6.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v7.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v7.h, v6.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v6.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v6.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v5.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v1.l, v3.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
@@ -2701,14 +2701,14 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v8.h
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v8, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v6.h, v8.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v8.h, s2
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v3, v3
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.h, v7.h, s4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v0.h, v6.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v1.l
@@ -2718,17 +2718,17 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v2.l, v0.h, s3
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v0.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v2.h, s0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v0, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.h, v0.h, s2
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v6.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, s3
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v5.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v6.h, s2
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v0.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -2736,9 +2736,9 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v0.h, s1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v3.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2755,96 +2755,96 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v11
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v5, v4 :: v_dual_and_b32 v9, 0xffff0000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v13, 16, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v6 :: v_dual_lshlrev_b32 v14, 16, v0
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v9, 16, v7
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v5, 16, v6
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v8
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v3, 16, v7
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v6 :: v_dual_lshlrev_b32 v2, 16, v8
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x5040100
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -3245,56 +3245,56 @@ define <4 x bfloat> @v_maximumnum_v4bf16_nnan(<4 x bfloat> %x, <4 x bfloat> %y)
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v1.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, 0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v3.l, v1.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v5.h, v1.l, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v4.l, v3.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v6
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.h, v1.l, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v3.h, v1.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.h, v1.h, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v5
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v3.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v4
; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.h, v1.h, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v2.l, v0.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v5.h, v0.l, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v5
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.h, v0.l, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v2.h, v0.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.h, v0.h, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.h, v0.h, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3313,62 +3313,62 @@ define <4 x bfloat> @v_maximumnum_v4bf16_nnan(<4 x bfloat> %x, <4 x bfloat> %y)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1
; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v3 :: v_dual_lshlrev_b32 v10, 16, v0
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v6
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v1 :: v_dual_and_b32 v12, 0xffff0000, v0
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v9
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v6, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v11
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v4, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v7
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v4 :: v_dual_lshlrev_b32 v4, 16, v6
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v9, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
@@ -4176,10 +4176,10 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v9.l
; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
; GFX12-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v2.h, v5.h, vcc_lo
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v5.h, v9.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v9.h
@@ -4188,52 +4188,52 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v8
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v13, v13
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v8.h, v9.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v6.l, v9.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.h, v6.l
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v9.l
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v1.h, v4.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.h, v4.h, v9.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v9.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v10
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v10.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v10.h, v9.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.l, v9.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.h, v7.l
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v9
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v0.h, v3.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v3.h, v9.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v9.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v11
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v11.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v11.h, v9.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v9.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v8.l, v9.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.h, v8.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v2.l, v5.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
@@ -4241,7 +4241,7 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v12.h
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v12, v9
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v9.h, v12.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v9.h
@@ -4249,7 +4249,7 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v5, v5
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v1.h, v9.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.h, v2.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.l, v4.l, s3
@@ -4260,17 +4260,17 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v4.l, v1.h, s4
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v1.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v2.h, v11.h, s7
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v4.h, s0
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v1, v9
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v9.h, v1.h, s3
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v9.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v1.h, s4
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v5, v5
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v7.h, v10.h, s6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v0.h, v9.h, s3
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.h, v1.l
@@ -4281,17 +4281,17 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v3.l, v0.h, s5
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v0.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.h, s3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s4, v0, v9
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v9.h, v0.h, s4
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v9.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, s5
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v8.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v0.h, v9.h, s4
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.h, v0.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -4299,9 +4299,9 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v9
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v6.l, v0.h, s1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s4
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4320,139 +4320,139 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX12-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v5
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX12-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX12-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v10, v9 :: v_dual_lshlrev_b32 v13, 16, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v6
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v13
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v7, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v15, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v15, v12 :: v_dual_lshlrev_b32 v14, 16, v9
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v14
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v12
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v9, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v6, v10, v6 :: v_dual_lshlrev_b32 v13, 16, v11
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v11, v8 :: v_dual_lshlrev_b32 v15, 16, v7
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v15
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v7, v12, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v10, v12, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v2 :: v_dual_lshlrev_b32 v10, 16, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v3 :: v_dual_lshlrev_b32 v11, 16, v2
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v0 :: v_dual_lshlrev_b32 v12, 16, v1
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v5, v2 :: v_dual_lshlrev_b32 v10, 16, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v4, v1 :: v_dual_lshlrev_b32 v11, 16, v3
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v9, v2 :: v_dual_lshlrev_b32 v13, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v11
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v3, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_lshlrev_b32 v4, 16, v10
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v3 :: v_dual_lshlrev_b32 v3, 16, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v11
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v7, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v1, v8, v1, 0x5040100
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -5505,12 +5505,12 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v12.l
; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v2
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v12.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v3.h, v7.h, vcc_lo
; GFX12-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v4
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v7
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v7.h, v12.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v12.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
@@ -5519,68 +5519,68 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v11
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v17, v17
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v11.h, v12.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v8.l, v12.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.h, v8.l
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v12
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v2.h, v6.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v6.h, v12.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v12.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v13
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v13.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v13.h, v12.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v9.l, v12.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.h, v9.l
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v14, v14
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v12.l
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v12
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v1.h, v5.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v5.h, v12.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v12.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v14
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v14.h, v12.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v12.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.h, v10.l, v12.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v16, v16
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v3
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v12
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v0.h, v4.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v4.h, v12.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v12.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v15
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v15.h, v12.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v12.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v11.l, v12.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.h, v11.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v3.l, v7.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v12
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
@@ -5588,7 +5588,7 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v16.h
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v16, v12
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v12.h, v16.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v12.h
@@ -5596,7 +5596,7 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v7, v7
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v2.h, v12.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.h, v3.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v2.l, v6.l, s4
@@ -5608,10 +5608,10 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v2.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v16, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v6.h, s0
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s4, v2, v12
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v12.h, v2.h, s4
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v12.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -5619,7 +5619,7 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v7, v7
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v9.h, v13.h, s8
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v1.h, v12.h, s4
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.h, v2.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.l, v5.l, s5
@@ -5629,17 +5629,17 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v12
; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v5.l, v1.h, s6
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v1.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.h, s4
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s5, v1, v12
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v12.h, v1.h, s5
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v12.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v1.h, s6
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v7, v7
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v0.h, v12.h, s5
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.h, v1.l
@@ -5649,33 +5649,33 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v12
; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v4.l, v0.h, s7
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v0.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.h, s5
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s6, v0, v12
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v12.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v12.h, v0.h, s6
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v11.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, s7
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v8.h, v11.h, s6
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v14.h
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v15.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.h, v12.h, s9
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.h, v0.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v10.h, v14.h, s6
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v15.h, s7
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v8.l, v1.h, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v12
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v10.l, v0.h, s3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v11.l, v5.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s1
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -5694,189 +5694,189 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX12-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v7
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v8 :: v_dual_and_b32 v10, 0xffff0000, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v8
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v12, v11, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v14
; GFX12-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v6
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v9, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v12, v8 :: v_dual_and_b32 v13, 0xffff0000, v1
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v9 :: v_dual_lshlrev_b32 v15, 16, v11
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v15
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v14, v11, v10 :: v_dual_and_b32 v15, 0xffff0000, v5
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v16, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v14, v10 :: v_dual_lshlrev_b32 v13, 16, v12
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v16, v9, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
; GFX12-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v0
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v12, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v15
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v11 :: v_dual_lshlrev_b32 v11, 16, v9
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v12
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v11, v15, v9 :: v_dual_lshlrev_b32 v18, 16, v14
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v12, v17, v16 :: v_dual_lshlrev_b32 v17, 16, v7
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v14, v10 :: v_dual_and_b32 v13, 0xffff0000, v4
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v11, v9 :: v_dual_lshlrev_b32 v14, 16, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v16, v12, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v15
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v15 :: v_dual_lshlrev_b32 v16, 16, v13
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v12
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v16
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v11
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v15, v13, v12 :: v_dual_lshlrev_b32 v16, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v11, v9 :: v_dual_lshlrev_b32 v14, 16, v3
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v11, v15, v12 :: v_dual_lshlrev_b32 v12, 16, v7
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v12
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v7, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v6 :: v_dual_lshlrev_b32 v13, 16, v15
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v12, v3 :: v_dual_lshlrev_b32 v16, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v15, v11, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v6, v6, v2 :: v_dual_lshlrev_b32 v15, 16, v0
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v7 :: v_dual_lshlrev_b32 v14, 16, v6
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v16, v14
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v14, v6, v2 :: v_dual_lshlrev_b32 v7, 16, v12
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v0 :: v_dual_lshlrev_b32 v13, 16, v5
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v14, v2 :: v_dual_lshlrev_b32 v15, 16, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v13
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v14
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v5, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v17, v16
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v4, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v4 :: v_dual_lshlrev_b32 v5, 16, v6
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v14, v2, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v10, v2, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v13
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v11, v0, 0x5040100
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v1, v9, v1, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v3, v8, v3, 0x5040100
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -7924,14 +7924,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v12
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v20, v20
; GFX12-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v7.h, v15.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v16.l
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v21, v21
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v16.l
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v16.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.h, v15.h, v16.h, vcc_lo
; GFX12-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v4
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v22, v22
@@ -7942,13 +7942,13 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v16.l
; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v10
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v16.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.h, v16.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v23, v23
; GFX12-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v2
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v24, v24
; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v17.l, v16.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v17.l
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v18, v18
@@ -7956,7 +7956,7 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v9
; GFX12-TRUE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v0
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v6.h, v14.h, s0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v8
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v29, v29
@@ -7969,7 +7969,7 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v32, v32
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v16, v18
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v14
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.h, v16.h, s0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v32, v32
@@ -7982,7 +7982,7 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v12
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v5.h, v13.h, s1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v32, v32
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v11
@@ -7995,7 +7995,7 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v16, v25
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s17, 0, v25.h
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v32, v32
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v25.h, v16.h, s1
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v9
@@ -8006,13 +8006,13 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v32, v32
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v32.l, v16.l
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v4.h, v12.h, s2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.h, v12.h, v16.h, s3
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v16.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v16, v26
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v26.h, v16.h, s2
; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.h, v21.l, v16.h, s3
@@ -8020,13 +8020,13 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v22, v22
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v3.h, v11.h, s3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.h, v11.h, v16.h, s4
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v16.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v16, v27
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v27.h, v16.h, s3
; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.h, v22.l, v16.h, s4
@@ -8034,13 +8034,13 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v23, v23
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v2.h, v10.h, s4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.h, v10.h, v16.h, s5
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v16.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s4, v16, v28
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v28.h, v16.h, s4
; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.h, v23.l, v16.h, s5
@@ -8048,13 +8048,13 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v24, v24
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v1.h, v9.h, s5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.h, v9.h, v16.h, s6
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v16.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s5, v16, v29
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v29.h, v16.h, s5
; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.h, v24.l, v16.h, s6
@@ -8063,20 +8063,20 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v30.l, v16.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v0.h, v8.h, s6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.h, v8.h, v16.h, s7
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v16.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s6, v16, v30
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v30.h, v16.h, s6
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v31, v31
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v6
; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.l, v15.h, v16.h, s7
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v15.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.l, v15.l, s6
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v16.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
@@ -8085,14 +8085,14 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v7.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s7, v7, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v16.h, v7.h, s7
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v16.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v7.l, v7.h, s8
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v31, v31
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v6.h, v16.h, s7
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v7.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v6.l, v14.l, s8
@@ -8101,18 +8101,18 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s7, 0, v16
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v14.l, v6.h, s9
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v6.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v14.h, s7
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s8, v6, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v16.h, v6.h, s8
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v16.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v6.l, v6.h, s9
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v31, v31
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v5.h, v16.h, s8
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v6.l
@@ -8122,18 +8122,18 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v13.l, v5.h, s10
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v5.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v13.h, s8
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s9, v5, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v16.h, v5.h, s9
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v16.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v5.l, v5.h, s10
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v31, v31
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v4.h, v16.h, s9
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v5.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.l, v12.l, s10
@@ -8142,18 +8142,18 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s9, 0, v16
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v12.l, v4.h, s11
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0, v4.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v12.h, s9
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s10, v4, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v16.h, v4.h, s10
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v16.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v4.l, v4.h, s11
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v31, v31
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v3.h, v16.h, s10
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v4.l
@@ -8163,18 +8163,18 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v11.l, v3.h, s12
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0, v3.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v11.h, s10
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s11, v3, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v16.h, v3.h, s11
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0, v16.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.l, v3.h, s12
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v31, v31
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.h, v2.h, v16.h, s11
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v3.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v2.l, v10.l, s12
@@ -8183,18 +8183,18 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s11, 0, v16
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v10.l, v2.h, s13
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0, v2.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v10.h, s11
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s12, v2, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v16.h, v2.h, s12
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0, v16.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v2.l, v2.h, s13
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v31, v31
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v1.h, v16.h, s12
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v2.l
@@ -8206,62 +8206,62 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v31, v31
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0, v1.h
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v8
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v9.h, s12
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s13, v1, v16
; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.h, v0.l, v8.l, s14
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0, v16.h
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v31, v31
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v16.h, v1.h, s13
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0, v17.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v1.h, s15
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v19.l, v17.h, s13
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0, v18.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v20.h, v25.h, s17
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0, v32.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v16.h, s16
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v1.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v17.l, v0.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v19.h, v18.h, s13
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v26.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v20.l, v1.h, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s13, 0, v16
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v8.l, v32.h, s14
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v18.l, v0.h, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v21.h, v26.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v28.h
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v27.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v32, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s13
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v21.l, v0.h, s2
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v29.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v23.h, v28.h, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v16.h, v32.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v16.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v22.h, v27.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v24.h, v29.h, s2
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v30.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v8.l, v32.h, s15
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v23.l, v1.h, s4
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v22.l, v0.h, s3
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v24.l, v8.h, s5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v25.l, v30.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v9.l, v16.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v8.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v15.h, v0.h, s6
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v8.h, vcc_lo
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -8283,390 +8283,390 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v4
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v1
; GFX12-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v17, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
; GFX12-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v13
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v16
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v16, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v17
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v18, v19
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v17, v16, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v20, v22, v21 :: v_dual_and_b32 v19, 0xffff0000, v14
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v16
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v21, v20, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v17
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v20
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v19
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v17 :: v_dual_lshlrev_b32 v17, 16, v18
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v21, v22
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v13
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v17, v19, v20 :: v_dual_and_b32 v18, 0xffff0000, v5
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v20
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v17, v20, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v22, v21, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
; GFX12-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v18
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v18, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX12-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v12
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v22, v25, v24 :: v_dual_lshlrev_b32 v25, 16, v21
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v19
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v24, v22, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v17
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v22
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v23, v21, v18 :: v_dual_lshlrev_b32 v26, 16, v20
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v18
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v23, v18, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v26
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v21
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v18, v18, v21 :: v_dual_lshlrev_b32 v27, 16, v19
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v22
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v19, v22, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v23, v18, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v20
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v20, v22, v20 :: v_dual_and_b32 v23, 0xffff0000, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v21, v26, v25 :: v_dual_and_b32 v22, 0xffff0000, v11
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v25, v21, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
; GFX12-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v24, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v20, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v24, v24, v23 :: v_dual_and_b32 v25, 0xffff0000, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v24
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v20, v26
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v22, v21, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v28, v27, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v23
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v21
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v20, v21, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v29
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v26, v24, v23 :: v_dual_lshlrev_b32 v29, 16, v20
; GFX12-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v9
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v27, v27, v25, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v22
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v21, v21, v22 :: v_dual_lshlrev_b32 v28, 16, v27
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v23
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v22, v26, v23 :: v_dual_lshlrev_b32 v23, 16, v25
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v24
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v24, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v28
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v23, v27, v25 :: v_dual_lshlrev_b32 v24, 16, v26
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v29
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v21, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v21, v26, v22 :: v_dual_and_b32 v24, 0xffff0000, v0
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v25
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v23, v25, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v27
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v27, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v7
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v26, v25, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v23
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v15 :: v_dual_and_b32 v26, 0xffff0000, v8
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v15
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v25, v24, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v15, v15, v7 :: v_dual_lshlrev_b32 v26, 16, v24
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v22, v23, v22 :: v_dual_lshlrev_b32 v27, 16, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v6
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v15
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v27
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v26, v25, v24 :: v_dual_lshlrev_b32 v23, 16, v14
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v29, v28
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v27, v15, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v24
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v24, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v27, v7 :: v_dual_lshlrev_b32 v24, 16, v14
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v25
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v23, v25, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v15
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v26
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v15 :: v_dual_lshlrev_b32 v28, 16, v6
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v28, v24
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v15, v14, v6 :: v_dual_lshlrev_b32 v24, 16, v27
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v23, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v27, v7 :: v_dual_lshlrev_b32 v24, 16, v5
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v14
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_perm_b32 v7, v16, v7, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v13 :: v_dual_lshlrev_b32 v24, 16, v4
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_perm_b32 v6, v17, v6, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v13, v13, v5 :: v_dual_lshlrev_b32 v14, 16, v12
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v24
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v15, v13, v5 :: v_dual_lshlrev_b32 v24, 16, v12
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v11
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v4
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v24
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v11
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v12, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v14, v4 :: v_dual_lshlrev_b32 v13, 16, v15
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v24
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v11, v3, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v18, v5, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v11 :: v_dual_lshlrev_b32 v12, 16, v2
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v10
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v10 :: v_dual_lshlrev_b32 v15, 16, v24
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0
; GFX12-FAKE16-NEXT: v_perm_b32 v3, v20, v3, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v8 :: v_dual_lshlrev_b32 v11, 16, v9
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v1 :: v_dual_lshlrev_b32 v12, 16, v8
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v10
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v0 :: v_dual_lshlrev_b32 v15, 16, v2
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v9
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v11
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v10, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v24, v12
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v9, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v11, v2 :: v_dual_lshlrev_b32 v15, 16, v8
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v15
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v8, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v12, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v15, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v12
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v15
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v12, v1 :: v_dual_lshlrev_b32 v8, 16, v11
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_perm_b32 v1, v22, v1, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v15, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v23, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v21, v2, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v4, v19, v4, 0x5040100
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -12831,38 +12831,38 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v83.l, v36.l
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s42, v86, v86
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v36.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v96.h, v0.l, v16.l, s42
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s43, 0, v96.h
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v68
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v15.h, v68.h, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v36.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.h, v68.h, v36.h, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v36, v35
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s42, 0, v35.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v35.h, v36.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.h, v31.l, v36.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v31.l
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v32, v32
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v14.h, v30.h, s0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.h, v30.h, v36.h, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v36.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v36, v37
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s44, 0, v37.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v37.h, v36.h, s0
; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.h, v32.l, v36.h, s1
@@ -12870,13 +12870,13 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v33, v33
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v13.h, v29.h, s1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.h, v29.h, v36.h, s2
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v36.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v36, v38
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v38.h, v36.h, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.h, v33.l, v36.h, s2
@@ -12884,13 +12884,13 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v34, v34
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v12.h, v28.h, s2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.h, v28.h, v36.h, s3
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v36.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v36, v39
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v39.h, v36.h, s2
; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.h, v34.l, v36.h, s3
@@ -12899,13 +12899,13 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v48.l, v36.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v11.h, v27.h, s3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.h, v27.h, v36.h, s4
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v36.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v36, v48
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v48.h, v36.h, s3
; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v35.l, v36.h, s4
@@ -12914,13 +12914,13 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v49.l, v36.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v10.h, v26.h, s4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.h, v26.h, v36.h, s5
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v36.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s4, v36, v49
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v49.h, v36.h, s4
; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.l, v38.l, v36.h, s5
@@ -12929,13 +12929,13 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v36.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v9.h, v25.h, s5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v50.h, v25.h, v36.h, s6
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v36.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s5, v36, v50
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.l, v50.h, v36.h, s5
; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.l, v48.l, v36.h, s6
@@ -12944,13 +12944,13 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v36.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v8.h, v24.h, s6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v51.h, v24.h, v36.h, s7
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v36.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s6, v36, v51
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v50.l, v51.h, v36.h, s6
; GFX12-TRUE16-NEXT: v_cndmask_b16 v51.l, v50.l, v36.h, s7
@@ -12959,13 +12959,13 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v36.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v7.h, v23.h, s7
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v52.h, v23.h, v36.h, s8
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v36.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s7, v36, v52
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v52.l, v52.h, v36.h, s7
; GFX12-TRUE16-NEXT: v_cndmask_b16 v69.l, v52.l, v36.h, s8
@@ -12974,13 +12974,13 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v36.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s7, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v6.h, v22.h, s8
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v53.h, v22.h, v36.h, s9
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v36.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s8, v36, v53
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v53.l, v53.h, v36.h, s8
; GFX12-TRUE16-NEXT: v_cndmask_b16 v69.h, v53.l, v36.h, s9
@@ -12989,13 +12989,13 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v54.l, v36.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s8, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v5.h, v21.h, s9
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v54.h, v21.h, v36.h, s10
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v36.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s9, v36, v54
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v54.l, v54.h, v36.h, s9
; GFX12-TRUE16-NEXT: v_cndmask_b16 v70.l, v54.l, v36.h, s10
@@ -13004,13 +13004,13 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v55.l, v36.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s9, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v4.h, v20.h, s10
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v55.h, v20.h, v36.h, s11
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0, v36.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s10, v36, v55
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v55.l, v55.h, v36.h, s10
; GFX12-TRUE16-NEXT: v_cndmask_b16 v70.h, v55.l, v36.h, s11
@@ -13019,13 +13019,13 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v64.l, v36.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s10, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v3.h, v19.h, s11
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v64.h, v19.h, v36.h, s12
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0, v36.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s11, v36, v64
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v64.l, v64.h, v36.h, s11
; GFX12-TRUE16-NEXT: v_cndmask_b16 v71.l, v64.l, v36.h, s12
@@ -13034,13 +13034,13 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v65.l, v36.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s11, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v2.h, v18.h, s12
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v65.h, v18.h, v36.h, s13
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0, v36.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s12, v36, v65
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v65.l, v65.h, v36.h, s12
; GFX12-TRUE16-NEXT: v_cndmask_b16 v71.h, v65.l, v36.h, s13
@@ -13049,13 +13049,13 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v66.l, v36.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s12, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v1.h, v17.h, s13
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v66.h, v17.h, v36.h, s14
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0, v36.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s13, v36, v66
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v66.l, v66.h, v36.h, s13
; GFX12-TRUE16-NEXT: v_cndmask_b16 v80.l, v66.l, v36.h, s14
@@ -13064,7 +13064,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v67.l, v36.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s13, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v0.h, v16.h, s14
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v67.h, v16.h, v36.h, s15
@@ -13072,7 +13072,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0, v36.h
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v68
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s14, v36, v67
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v82.h, v15.l, v68.l, s15
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v81, v81
@@ -13083,10 +13083,10 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0, v82.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s14, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v68.l, v82.h, s15
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s15, v82, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v68.l, v36.h, v82.h, s15
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0, v36.h
@@ -13094,7 +13094,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s16, v81, v81
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v13
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v29
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.h, v14.h, v36.h, s15
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v68.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v14.l, v30.l, s16
@@ -13110,7 +13110,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s16, v14, v36
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v82, v82
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v36.h, v14.h, s16
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0, v36.h
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v26
@@ -13120,7 +13120,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v12
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v82, v82
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v25
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.h, v13.h, v36.h, s16
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v14.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v13.l, v29.l, s17
@@ -13134,7 +13134,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v82, v82
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v23
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s17, v13, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v29.h, s16
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v82, v82
@@ -13147,7 +13147,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v11
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v82, v82
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v21
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.h, v12.h, v36.h, s17
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v13.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v12.l, v28.l, s18
@@ -13161,7 +13161,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v82, v82
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v19
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s18, v12, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v28.h, s17
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s28, v82, v82
@@ -13172,7 +13172,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v12.l, v12.h, s19
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v81, v81
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v10
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.h, v11.h, v36.h, s18
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v12.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v11.l, v27.l, s19
@@ -13181,18 +13181,18 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v36
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v27.l, v11.h, s20
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s20, 0, v11.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v27.h, s18
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s19, v11, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v36.h, v11.h, s19
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s19, 0, v36.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.h, v11.l, v11.h, s20
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v81, v81
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v9
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.h, v10.h, v36.h, s19
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v11.l
@@ -13202,18 +13202,18 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v26.l, v10.h, s21
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s21, 0, v10.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v26.h, s19
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s20, v10, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v36.h, v10.h, s20
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s20, 0, v36.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v10.l, v10.h, s21
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v81, v81
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v8
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.h, v9.h, v36.h, s20
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v10.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v9.l, v25.l, s21
@@ -13222,18 +13222,18 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v36
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v25.l, v9.h, s22
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s22, 0, v9.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v25.h, s20
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s21, v9, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v36.h, v9.h, s21
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s21, 0, v36.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v9.l, v9.h, s22
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v81, v81
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v7
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.h, v8.h, v36.h, s21
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v9.l
@@ -13243,18 +13243,18 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v24.l, v8.h, s23
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s23, 0, v8.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v24.h, s21
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s22, v8, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v36.h, v8.h, s22
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s22, 0, v36.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v8.l, v8.h, s23
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v81, v81
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.h, v7.h, v36.h, s22
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v8.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.l, v23.l, s23
@@ -13263,18 +13263,18 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v36
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v23.l, v7.h, s24
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s24, 0, v7.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v23.h, s22
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s23, v7, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v36.h, v7.h, s23
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s23, 0, v36.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v7.l, v7.h, s24
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v81, v81
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.h, v6.h, v36.h, s23
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v7.l
@@ -13284,18 +13284,18 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v22.l, v6.h, s25
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s25, 0, v6.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v22.h, s23
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s24, v6, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v36.h, v6.h, s24
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s24, 0, v36.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v6.l, v6.h, s25
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v81, v81
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.h, v5.h, v36.h, s24
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v6.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v5.l, v21.l, s25
@@ -13304,18 +13304,18 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v36
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v21.l, v5.h, s26
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s26, 0, v5.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v21.h, s24
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s25, v5, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v36.h, v5.h, s25
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s25, 0, v36.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v5.l, v5.h, s26
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s26, v81, v81
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.h, v4.h, v36.h, s25
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v5.l
@@ -13325,18 +13325,18 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v20.l, v4.h, s27
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s27, 0, v4.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v20.h, s25
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s26, v4, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v36.h, v4.h, s26
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s26, 0, v36.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v4.l, v4.h, s27
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v81, v81
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v18
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.h, v3.h, v36.h, s26
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v4.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v83.h, v3.l, v19.l, s27
@@ -13350,7 +13350,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s41, 0, v83.h
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v36.l
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s27, v83, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v82.h, v2.l, v18.l, s28
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s28, 0, v36.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.h, v1.l, v17.l, s40
@@ -13362,7 +13362,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v32.l, v1.l, s0
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, v83.h, s41
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s41, v87, v87
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.h, v36.h, s28
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v3.l
@@ -13372,18 +13372,18 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s45, 0, v36
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v18.l, v82.h, s29
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s29, 0, v38.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v31.l, v0.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v34.h, v39.h, s42
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v48.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s44, v82, v36
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v33.h, v38.h, s29
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v36.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v34.l, v1.h, s2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v37.l, v48.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v36.h, v82.h, s44
; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v33.l, v0.h, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v49.h
@@ -13392,12 +13392,12 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v82.h, s40
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v51.h
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v54.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v49.l, v50.h, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s45
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v36.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v1.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v39.l, v49.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v52.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v51.l, v51.h, s2
@@ -13405,14 +13405,14 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v36
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v17.l, v19.h, s27
; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.h, v38.l, v0.h, s4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v69.l, v52.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v55.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v48.l, v1.h, s5
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v19, v36
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v36.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v69.h, v53.h, s2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v70.h, v55.h, s4
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v66.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v36.h, v19.h, s1
@@ -13422,7 +13422,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v52.l, v0.h, s7
; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v16.h, v19.h, s28
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v53.l, v1.h, s8
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v71.h, v65.h, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v54.l, v2.h, s9
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v67.h
@@ -13430,33 +13430,33 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v16.h
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v64.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v65.l, v1.h, s12
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v67.h, s3
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v55.l, v3.h, s10
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v36
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v16.l, v96.h, s41
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v71.l, v64.h, s0
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v80.l, v66.h, s2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v1.l, v2.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v16.h, v17.l, s4
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v96, v36
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v64.l, v0.h, s11
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v66.l, v16.l, s13
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v67.l, v15.l, s14
; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v68.l, v30.h, s15
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v36.h, v96.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v36.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.h, v16.l, v96.h, s43
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.h, v17.h, v36.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v16.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v16.l, v17.h, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -13478,7 +13478,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v14
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v24
; GFX12-FAKE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v52, v52, v51, s1
; GFX12-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v13
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9
@@ -13490,7 +13490,7 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v22
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v48, v48, v39, s0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14
; GFX12-FAKE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
@@ -13502,494 +13502,494 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v19
; GFX12-FAKE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v36, v36, v35, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v70, v70
; GFX12-FAKE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v29
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18
; GFX12-FAKE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v70, v80, v71, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v82, v82
; GFX12-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v28
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v2
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v80, v84, v83, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86
; GFX12-FAKE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v26
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v17
; GFX12-FAKE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v1
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v27
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v82, v96, v87, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v98
; GFX12-FAKE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v25
; GFX12-FAKE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v11
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v1
; GFX12-FAKE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v84, v100, v99, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v102, v102
; GFX12-FAKE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v24
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v147, 16, v16
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v54, v54
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v86, v112, v103, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v114, v114
; GFX12-FAKE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v22
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v14
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v26
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v96, v116, v115, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v118, v118
; GFX12-FAKE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v64, v64, v55, s2
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v10
; GFX12-FAKE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v98, v128, v119, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v130, v130
; GFX12-FAKE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v100, v132, v131, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v134, v134
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v102, v144, v135 :: v_dual_and_b32 v133, 0xffff0000, v18
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v146, v146
; GFX12-FAKE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v112, 16, v96
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v147, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54
; GFX12-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v27
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v54, v14, v30 :: v_dual_and_b32 v97, 0xffff0000, v23
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
; GFX12-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v15
; GFX12-FAKE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v39, v48, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v51, v51, v52, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v116, 16, v100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v55, v55, v64 :: v_dual_lshlrev_b32 v130, 16, v51
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v69, v69
; GFX12-FAKE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v10
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v128, 16, v34
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v66, v66
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v68, v68, v67, s3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v67, v67, v68, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v81, v81
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v68
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v80
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v71, v71, v70 :: v_dual_lshlrev_b32 v132, 16, v67
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v85, v85
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v83, v83, v80, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v97, v97
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v30
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v84
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v87, v87, v82 :: v_dual_lshlrev_b32 v134, 16, v83
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v101, v101
; GFX12-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v16
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v99, v99, v84, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v113, v113
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v103, v103, v86 :: v_dual_lshlrev_b32 v144, 16, v99
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v117, v117
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v36
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v113, v115, v96, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v129, v129
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v82
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v115, v119, v98 :: v_dual_lshlrev_b32 v146, 16, v113
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v133, v133
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v48
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v117, v131, v100, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v145, v145
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v86
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v119, v135, v102, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v38, v147, v34 :: v_dual_lshlrev_b32 v49, 16, v52
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v49, v130
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v66, v30, v54 :: v_dual_lshlrev_b32 v53, 16, v64
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v35
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v30
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v70
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v117
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v130, v35, v36 :: v_dual_lshlrev_b32 v129, 16, v39
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v37, v129
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v129, v51, v52, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v37, v39, v48 :: v_dual_lshlrev_b32 v118, 16, v102
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v131, 16, v55
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v53, v131
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v53, v55, v64 :: v_dual_lshlrev_b32 v50, 16, v15
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v71
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v65, v132
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v65, v67, v68, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v69, v133
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v135, 16, v87
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v69, v71, v70 :: v_dual_lshlrev_b32 v132, 16, v65
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v81, v134
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v81, v83, v80, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v85, v135
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v145, 16, v103
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v85, v87, v82, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v97, v144
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v97, v99, v84 :: v_dual_lshlrev_b32 v114, 16, v98
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v101, v145
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v147, 16, v115
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v101, v103, v86 :: v_dual_lshlrev_b32 v144, 16, v97
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v112, v146
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v112, v113, v96, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v114, v147
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v119
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v38
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v114, v115, v98, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v116, v14
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v116, v117, v100, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v118, v30
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v118, v119, v102, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v128, v49
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v128, v38, v34, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v36
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v130, v36, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v48
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v36, v37, v48, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v52
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v49, v129, v52, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v64
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v52, 16, v129
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v64, v53, v64, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v68
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v68, v65, v68, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v70
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v70, v69, v70, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v80
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v80, v81, v80, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v82
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v82, v85, v82, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v84
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v84, v97, v84, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v86
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v86, v101, v86, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v96
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v96, v112, v96, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v98
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v98, v114, v98 :: v_dual_lshlrev_b32 v131, 16, v53
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v100, v116, v100 :: v_dual_lshlrev_b32 v133, 16, v69
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v35
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v35 :: v_dual_lshlrev_b32 v135, 16, v85
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v102
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v118, v102, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v39
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v36, v36, v39 :: v_dual_lshlrev_b32 v145, 16, v101
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v34
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v34, v128, v34, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v51
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v49, v51, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v55
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v51, 16, v128
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v49, v64, v55, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v67
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v68, v67, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v71
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v64, v70, v71 :: v_dual_lshlrev_b32 v147, 16, v114
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v83
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v67, v80, v83, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v87
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v68, v82, v87, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v99
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v70, v84, v99, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v103
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v71, v86, v103 :: v_dual_lshlrev_b32 v30, 16, v130
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v113
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v37
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v80, v96, v113, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v115
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v82, v98, v115, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v117
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v81
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v83, v100, v117, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v119
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v84, v35, v119, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v38
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v86, v34, v38, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v30
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v130, v14, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v48
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v30, v37, v36, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v52
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v31
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v34, v129, v39, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v131
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v53, v49, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v132
; GFX12-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v31
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v36, v65, v55, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v133
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v37, v69, v64, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v134
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v38, v81, v67, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v135
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v85, v68, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v144
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v48, v97, v70, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v145
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v49, v101, v71, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v15, v31, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v32, 16, v31
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v148, 16, v116
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v55
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v52, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v146, 16, v112
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v33
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v146
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v112, v80, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v52, v52, v33, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v118
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v53, v31, v55 :: v_dual_lshlrev_b32 v64, 16, v52
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v147
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v53
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v31, v114, v82, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v148
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v32, v116, v83, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v50, v64
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v64, v52, v33, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v65, v67
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v64
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v65, v53, v55, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v102
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v65
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v50, v118, v84, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v33
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v33, v64, v33, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v55
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v65, v55, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v52
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v52, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v53
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v53, v55, v53, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v67
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v33, v64, v33, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v52, v128, v86, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v68
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v51, v65, v53, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v66
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v29
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v12
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v13, v13, v29 :: v_dual_lshlrev_b32 v64, 16, v54
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v64, v53
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v53, v66, v54, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v29, v29, v13, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v28
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v29
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v54
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v54, v53, v54, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v28, v28, v12, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v66
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v54, v54, v66, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v65, v64
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v53
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v28
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v55, v29, v13 :: v_dual_lshlrev_b32 v66, 16, v12
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v64
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v53, v53, v54 :: v_dual_lshlrev_b32 v64, 16, v55
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v66, v65
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v27
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_perm_b32 v14, v14, v53, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v54, v28, v12, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v29
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v11
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v54, v12, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v28
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v27, v27, v11 :: v_dual_lshlrev_b32 v28, 16, v54
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v64
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v26
; GFX12-FAKE16-NEXT: v_perm_b32 v13, v30, v13, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v54, v12, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v11
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v26 :: v_dual_lshlrev_b32 v29, 16, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v27
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v54, v28
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v28, v27, v11, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v26, v26, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v25
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v11, v28, v11 :: v_dual_lshlrev_b32 v54, 16, v26
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v25, v9, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v27
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v10
@@ -13998,258 +13998,258 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v55, v54
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v29, v26, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v29
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_perm_b32 v11, v35, v11, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v29, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v55, v54
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v27, v25, v9, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v26
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v27, v9, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v23
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v29, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v25
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v25 :: v_dual_lshlrev_b32 v26, 16, v8
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v7
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v27
; GFX12-FAKE16-NEXT: v_perm_b32 v10, v36, v10, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v26, 16, v24
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v7
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v23, v23, v7 :: v_dual_lshlrev_b32 v26, 16, v24
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v27, v9 :: v_dual_lshlrev_b32 v28, 16, v23
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v8
; GFX12-FAKE16-NEXT: v_perm_b32 v9, v37, v9, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v27, v26
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v26, v24, v8 :: v_dual_lshlrev_b32 v25, 16, v22
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v29, v28
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v27, v23, v7, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v24
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v23
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v24, 16, v26
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v22
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v6
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v28, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v27
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v22, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v21
; GFX12-FAKE16-NEXT: v_perm_b32 v8, v38, v8, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v22
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_perm_b32 v7, v39, v7, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v21 :: v_dual_lshlrev_b32 v24, 16, v4
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v20
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v21
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v24
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v4
; GFX12-FAKE16-NEXT: v_perm_b32 v6, v48, v6, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v23, v21, v5 :: v_dual_lshlrev_b32 v22, 16, v19
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v24
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v19
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v20, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v21
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v22, v4 :: v_dual_lshlrev_b32 v21, 16, v23
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v24
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v19, v3, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v20
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v49, v5, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v19
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v19 :: v_dual_lshlrev_b32 v20, 16, v2
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v18
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v18 :: v_dual_lshlrev_b32 v23, 16, v24
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v0
; GFX12-FAKE16-NEXT: v_perm_b32 v3, v31, v3, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v18, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v17
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v17, v17, v1 :: v_dual_lshlrev_b32 v20, 16, v16
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v0 :: v_dual_lshlrev_b32 v19, 16, v18
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v17
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v19
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v18, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v24, v20
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v17, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v19, v2 :: v_dual_lshlrev_b32 v23, 16, v16
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v23
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v16, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v20, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v18
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v23, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v17
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v20
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v16
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v23
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v20, v1 :: v_dual_lshlrev_b32 v16, 16, v19
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_perm_b32 v1, v50, v1, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v23, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v16
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v52, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v32, v2, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v4, v15, v4, 0x5040100
; GFX12-FAKE16-NEXT: v_perm_b32 v15, v33, v51, 0x5040100
@@ -14432,26 +14432,26 @@ define bfloat @v_maximumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v0.l, v0.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v0.h, v1.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v1, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v1.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v1.h, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -14465,29 +14465,29 @@ define bfloat @v_maximumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 {
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call bfloat @llvm.maximumnum.bf16(bfloat %x, bfloat %y)
@@ -14799,44 +14799,44 @@ define <2 x bfloat> @v_maximumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> %
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v4.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v0.h, v1.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.h, v4.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.h, v4.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v4.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v4.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.h, v2.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v0.l, v1.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v1.l, v3.h, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v3.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v3.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.l, v3.h, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v2.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.h, v0.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, s1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v0.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -14853,50 +14853,50 @@ define <2 x bfloat> @v_maximumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> %
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v3 :: v_dual_lshlrev_b32 v5, 16, v0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v0 :: v_dual_lshlrev_b32 v4, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v3, v2 :: v_dual_lshlrev_b32 v7, 16, v1
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_lshlrev_b32 v7, 16, v5
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
@@ -15326,25 +15326,25 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v0.h, v2.h, vcc_lo
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v2.h, v6.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.h, v6.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v6.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v6.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v4.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v1.l, v3.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
@@ -15352,13 +15352,13 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v5.h
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v6.h, v5.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v5.h, s1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v3, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v0.h, v6.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v1.l
@@ -15368,26 +15368,26 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v6
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v2.l, v0.h, s2
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v2.h, s0
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v0, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.h, v0.h, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v6.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, s2
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v4.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v6.h, s1
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v0.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v4.h, s2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v0.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -15405,71 +15405,71 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v4 :: v_dual_lshlrev_b32 v6, 16, v1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v9, 16, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v10, 16, v6
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v7, 16, v0
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v8
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v6, v1 :: v_dual_lshlrev_b32 v2, 16, v6
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v4, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x bfloat> @llvm.maximumnum.v3bf16(<3 x bfloat> %x, <3 x bfloat> %y)
@@ -16025,45 +16025,45 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v6.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v1.h, v3.h, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v3.h, v6.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v5.h, v6.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v6.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.l, v6.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v4.l
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v8, v8
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v0.h, v2.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v2.h, v6.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v7.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v7.h, v6.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v6.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v6.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v5.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v1.l, v3.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
@@ -16071,14 +16071,14 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v8.h
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v8, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v6.h, v8.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v8.h, s2
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v3, v3
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.h, v7.h, s4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v0.h, v6.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v1.l
@@ -16088,17 +16088,17 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v2.l, v0.h, s3
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v0.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v2.h, s0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v0, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.h, v0.h, s2
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v6.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, s3
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v5.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v6.h, s2
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v0.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -16106,9 +16106,9 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v0.h, s1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v3.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -16125,96 +16125,96 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v11
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v5, v4 :: v_dual_and_b32 v9, 0xffff0000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v13, 16, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v6 :: v_dual_lshlrev_b32 v14, 16, v0
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v9, 16, v7
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v5, 16, v6
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v8
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v3, 16, v7
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v6 :: v_dual_lshlrev_b32 v2, 16, v8
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x5040100
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
index 47fafac1b9f54..267f88124941f 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
@@ -44,7 +44,7 @@ define amdgpu_kernel void @flat_last_use_load_1(ptr %in, ptr %out) {
; GFX12-NEXT: s_mov_b32 s2, 0x3ff
; GFX12-NEXT: v_and_b32_e64 v0, v0, s2
; GFX12-NEXT: s_mov_b32 s2, 2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_lshlrev_b32_e64 v1, s2, v0
; GFX12-NEXT: v_mov_b32_e32 v0, 0
; GFX12-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec
@@ -54,9 +54,9 @@ define amdgpu_kernel void @flat_last_use_load_1(ptr %in, ptr %out) {
; GFX12-NEXT: v_mov_b32_e32 v0, v1
; GFX12-NEXT: s_mov_b32 s2, s5
; GFX12-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_add_co_u32 v0, s3, s3, v0
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v2, s2, s2, v1, s3
; GFX12-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec
; GFX12-NEXT: v_mov_b32_e32 v1, v2
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
index 897178eca1dab..4834142e9bd63 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
@@ -491,7 +491,7 @@ define amdgpu_kernel void @flat_nontemporal_load_1(
; GFX12-WGP-NEXT: s_mov_b32 s2, 0x3ff
; GFX12-WGP-NEXT: v_and_b32_e64 v0, v0, s2
; GFX12-WGP-NEXT: s_mov_b32 s2, 2
-; GFX12-WGP-NEXT: s_wait_alu 0xfffe
+; GFX12-WGP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-WGP-NEXT: v_lshlrev_b32_e64 v1, s2, v0
; GFX12-WGP-NEXT: v_mov_b32_e32 v0, 0
; GFX12-WGP-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec
@@ -501,9 +501,9 @@ define amdgpu_kernel void @flat_nontemporal_load_1(
; GFX12-WGP-NEXT: v_mov_b32_e32 v0, v1
; GFX12-WGP-NEXT: s_mov_b32 s2, s5
; GFX12-WGP-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-WGP-NEXT: s_wait_alu 0xfffe
+; GFX12-WGP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-WGP-NEXT: v_add_co_u32 v0, s3, s3, v0
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_add_co_ci_u32_e64 v2, s2, s2, v1, s3
; GFX12-WGP-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec
; GFX12-WGP-NEXT: v_mov_b32_e32 v1, v2
@@ -522,7 +522,7 @@ define amdgpu_kernel void @flat_nontemporal_load_1(
; GFX12-CU-NEXT: s_mov_b32 s2, 0x3ff
; GFX12-CU-NEXT: v_and_b32_e64 v0, v0, s2
; GFX12-CU-NEXT: s_mov_b32 s2, 2
-; GFX12-CU-NEXT: s_wait_alu 0xfffe
+; GFX12-CU-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-CU-NEXT: v_lshlrev_b32_e64 v1, s2, v0
; GFX12-CU-NEXT: v_mov_b32_e32 v0, 0
; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec
@@ -532,9 +532,9 @@ define amdgpu_kernel void @flat_nontemporal_load_1(
; GFX12-CU-NEXT: v_mov_b32_e32 v0, v1
; GFX12-CU-NEXT: s_mov_b32 s2, s5
; GFX12-CU-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-CU-NEXT: s_wait_alu 0xfffe
+; GFX12-CU-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-CU-NEXT: v_add_co_u32 v0, s3, s3, v0
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_add_co_ci_u32_e64 v2, s2, s2, v1, s3
; GFX12-CU-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec
; GFX12-CU-NEXT: v_mov_b32_e32 v1, v2
@@ -1036,10 +1036,10 @@ define amdgpu_kernel void @flat_nontemporal_store_1(
; GFX12-WGP-NEXT: v_mov_b32_e32 v1, s0
; GFX12-WGP-NEXT: flat_load_b32 v2, v[1:2]
; GFX12-WGP-NEXT: s_mov_b32 s0, 0x3ff
-; GFX12-WGP-NEXT: s_wait_alu 0xfffe
+; GFX12-WGP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-WGP-NEXT: v_and_b32_e64 v0, v0, s0
; GFX12-WGP-NEXT: s_mov_b32 s0, 2
-; GFX12-WGP-NEXT: s_wait_alu 0xfffe
+; GFX12-WGP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-WGP-NEXT: v_lshlrev_b32_e64 v3, s0, v0
; GFX12-WGP-NEXT: v_mov_b32_e32 v0, 0
; GFX12-WGP-NEXT: ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec
@@ -1048,9 +1048,9 @@ define amdgpu_kernel void @flat_nontemporal_store_1(
; GFX12-WGP-NEXT: v_mov_b32_e32 v0, v3
; GFX12-WGP-NEXT: s_mov_b32 s0, s3
; GFX12-WGP-NEXT: v_mov_b32_e32 v1, v4
-; GFX12-WGP-NEXT: s_wait_alu 0xfffe
+; GFX12-WGP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-WGP-NEXT: v_add_co_u32 v0, s1, s1, v0
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_add_co_ci_u32_e64 v3, s0, s0, v1, s1
; GFX12-WGP-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec
; GFX12-WGP-NEXT: v_mov_b32_e32 v1, v3
@@ -1067,10 +1067,10 @@ define amdgpu_kernel void @flat_nontemporal_store_1(
; GFX12-CU-NEXT: v_mov_b32_e32 v1, s0
; GFX12-CU-NEXT: flat_load_b32 v2, v[1:2]
; GFX12-CU-NEXT: s_mov_b32 s0, 0x3ff
-; GFX12-CU-NEXT: s_wait_alu 0xfffe
+; GFX12-CU-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-CU-NEXT: v_and_b32_e64 v0, v0, s0
; GFX12-CU-NEXT: s_mov_b32 s0, 2
-; GFX12-CU-NEXT: s_wait_alu 0xfffe
+; GFX12-CU-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-CU-NEXT: v_lshlrev_b32_e64 v3, s0, v0
; GFX12-CU-NEXT: v_mov_b32_e32 v0, 0
; GFX12-CU-NEXT: ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec
@@ -1079,9 +1079,9 @@ define amdgpu_kernel void @flat_nontemporal_store_1(
; GFX12-CU-NEXT: v_mov_b32_e32 v0, v3
; GFX12-CU-NEXT: s_mov_b32 s0, s3
; GFX12-CU-NEXT: v_mov_b32_e32 v1, v4
-; GFX12-CU-NEXT: s_wait_alu 0xfffe
+; GFX12-CU-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-CU-NEXT: v_add_co_u32 v0, s1, s1, v0
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_add_co_ci_u32_e64 v3, s0, s0, v1, s1
; GFX12-CU-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec
; GFX12-CU-NEXT: v_mov_b32_e32 v1, v3
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
index a7ad4f6f9d774..7077f867ff2a2 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
@@ -354,7 +354,7 @@ define amdgpu_kernel void @flat_nontemporal_load_1(
; GFX12-WGP-NEXT: s_mov_b32 s2, 0x3ff
; GFX12-WGP-NEXT: v_and_b32_e64 v0, v0, s2
; GFX12-WGP-NEXT: s_mov_b32 s2, 2
-; GFX12-WGP-NEXT: s_wait_alu 0xfffe
+; GFX12-WGP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-WGP-NEXT: v_lshlrev_b32_e64 v1, s2, v0
; GFX12-WGP-NEXT: v_mov_b32_e32 v0, 0
; GFX12-WGP-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec
@@ -364,9 +364,9 @@ define amdgpu_kernel void @flat_nontemporal_load_1(
; GFX12-WGP-NEXT: v_mov_b32_e32 v0, v1
; GFX12-WGP-NEXT: s_mov_b32 s2, s5
; GFX12-WGP-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-WGP-NEXT: s_wait_alu 0xfffe
+; GFX12-WGP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-WGP-NEXT: v_add_co_u32 v0, s3, s3, v0
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_add_co_ci_u32_e64 v2, s2, s2, v1, s3
; GFX12-WGP-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec
; GFX12-WGP-NEXT: v_mov_b32_e32 v1, v2
@@ -388,7 +388,7 @@ define amdgpu_kernel void @flat_nontemporal_load_1(
; GFX12-CU-NEXT: s_mov_b32 s2, 0x3ff
; GFX12-CU-NEXT: v_and_b32_e64 v0, v0, s2
; GFX12-CU-NEXT: s_mov_b32 s2, 2
-; GFX12-CU-NEXT: s_wait_alu 0xfffe
+; GFX12-CU-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-CU-NEXT: v_lshlrev_b32_e64 v1, s2, v0
; GFX12-CU-NEXT: v_mov_b32_e32 v0, 0
; GFX12-CU-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec
@@ -398,9 +398,9 @@ define amdgpu_kernel void @flat_nontemporal_load_1(
; GFX12-CU-NEXT: v_mov_b32_e32 v0, v1
; GFX12-CU-NEXT: s_mov_b32 s2, s5
; GFX12-CU-NEXT: v_mov_b32_e32 v1, v2
-; GFX12-CU-NEXT: s_wait_alu 0xfffe
+; GFX12-CU-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-CU-NEXT: v_add_co_u32 v0, s3, s3, v0
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_add_co_ci_u32_e64 v2, s2, s2, v1, s3
; GFX12-CU-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec
; GFX12-CU-NEXT: v_mov_b32_e32 v1, v2
@@ -782,10 +782,10 @@ define amdgpu_kernel void @flat_nontemporal_store_1(
; GFX12-WGP-NEXT: v_mov_b32_e32 v1, s0
; GFX12-WGP-NEXT: flat_load_b32 v2, v[1:2]
; GFX12-WGP-NEXT: s_mov_b32 s0, 0x3ff
-; GFX12-WGP-NEXT: s_wait_alu 0xfffe
+; GFX12-WGP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-WGP-NEXT: v_and_b32_e64 v0, v0, s0
; GFX12-WGP-NEXT: s_mov_b32 s0, 2
-; GFX12-WGP-NEXT: s_wait_alu 0xfffe
+; GFX12-WGP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-WGP-NEXT: v_lshlrev_b32_e64 v3, s0, v0
; GFX12-WGP-NEXT: v_mov_b32_e32 v0, 0
; GFX12-WGP-NEXT: ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec
@@ -794,9 +794,9 @@ define amdgpu_kernel void @flat_nontemporal_store_1(
; GFX12-WGP-NEXT: v_mov_b32_e32 v0, v3
; GFX12-WGP-NEXT: s_mov_b32 s0, s3
; GFX12-WGP-NEXT: v_mov_b32_e32 v1, v4
-; GFX12-WGP-NEXT: s_wait_alu 0xfffe
+; GFX12-WGP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-WGP-NEXT: v_add_co_u32 v0, s1, s1, v0
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_add_co_ci_u32_e64 v3, s0, s0, v1, s1
; GFX12-WGP-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec
; GFX12-WGP-NEXT: v_mov_b32_e32 v1, v3
@@ -818,10 +818,10 @@ define amdgpu_kernel void @flat_nontemporal_store_1(
; GFX12-CU-NEXT: v_mov_b32_e32 v1, s0
; GFX12-CU-NEXT: flat_load_b32 v2, v[1:2]
; GFX12-CU-NEXT: s_mov_b32 s0, 0x3ff
-; GFX12-CU-NEXT: s_wait_alu 0xfffe
+; GFX12-CU-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-CU-NEXT: v_and_b32_e64 v0, v0, s0
; GFX12-CU-NEXT: s_mov_b32 s0, 2
-; GFX12-CU-NEXT: s_wait_alu 0xfffe
+; GFX12-CU-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-CU-NEXT: v_lshlrev_b32_e64 v3, s0, v0
; GFX12-CU-NEXT: v_mov_b32_e32 v0, 0
; GFX12-CU-NEXT: ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec
@@ -830,9 +830,9 @@ define amdgpu_kernel void @flat_nontemporal_store_1(
; GFX12-CU-NEXT: v_mov_b32_e32 v0, v3
; GFX12-CU-NEXT: s_mov_b32 s0, s3
; GFX12-CU-NEXT: v_mov_b32_e32 v1, v4
-; GFX12-CU-NEXT: s_wait_alu 0xfffe
+; GFX12-CU-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-CU-NEXT: v_add_co_u32 v0, s1, s1, v0
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_add_co_ci_u32_e64 v3, s0, s0, v1, s1
; GFX12-CU-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec
; GFX12-CU-NEXT: v_mov_b32_e32 v1, v3
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
index 3a014f3e61c66..5de773e7c84b6 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
@@ -44,7 +44,7 @@ define amdgpu_kernel void @global_last_use_load_1(ptr addrspace(1) %in, ptr addr
; GFX12-NEXT: s_mov_b32 s4, 0x3ff
; GFX12-NEXT: v_and_b32_e64 v1, v1, s4
; GFX12-NEXT: s_mov_b32 s4, 2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_lshlrev_b32_e64 v1, s4, v1
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v1, v1, s[2:3] th:TH_LOAD_LU
@@ -117,7 +117,7 @@ define amdgpu_kernel void @global_last_use_and_nontemporal_load(ptr addrspace(1)
; GFX12-NEXT: s_mov_b32 s4, 0x3ff
; GFX12-NEXT: v_and_b32_e64 v1, v1, s4
; GFX12-NEXT: s_mov_b32 s4, 2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_lshlrev_b32_e64 v1, s4, v1
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_b32 v1, v1, s[2:3] th:TH_LOAD_LU
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
index 5cbafe9f385e4..f15dbf058adfe 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
@@ -432,7 +432,7 @@ define amdgpu_kernel void @global_nontemporal_load_1(
; GFX12-WGP-NEXT: s_mov_b32 s4, 0x3ff
; GFX12-WGP-NEXT: v_and_b32_e64 v1, v1, s4
; GFX12-WGP-NEXT: s_mov_b32 s4, 2
-; GFX12-WGP-NEXT: s_wait_alu 0xfffe
+; GFX12-WGP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-WGP-NEXT: v_lshlrev_b32_e64 v1, s4, v1
; GFX12-WGP-NEXT: s_wait_kmcnt 0x0
; GFX12-WGP-NEXT: global_load_b32 v1, v1, s[2:3] th:TH_LOAD_NT
@@ -449,7 +449,7 @@ define amdgpu_kernel void @global_nontemporal_load_1(
; GFX12-CU-NEXT: s_mov_b32 s4, 0x3ff
; GFX12-CU-NEXT: v_and_b32_e64 v1, v1, s4
; GFX12-CU-NEXT: s_mov_b32 s4, 2
-; GFX12-CU-NEXT: s_wait_alu 0xfffe
+; GFX12-CU-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-CU-NEXT: v_lshlrev_b32_e64 v1, s4, v1
; GFX12-CU-NEXT: s_wait_kmcnt 0x0
; GFX12-CU-NEXT: global_load_b32 v1, v1, s[2:3] th:TH_LOAD_NT
@@ -875,7 +875,7 @@ define amdgpu_kernel void @global_nontemporal_store_1(
; GFX12-WGP-NEXT: s_mov_b32 s3, 0x3ff
; GFX12-WGP-NEXT: v_and_b32_e64 v0, v0, s3
; GFX12-WGP-NEXT: s_mov_b32 s3, 2
-; GFX12-WGP-NEXT: s_wait_alu 0xfffe
+; GFX12-WGP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-WGP-NEXT: v_lshlrev_b32_e64 v0, s3, v0
; GFX12-WGP-NEXT: s_wait_kmcnt 0x0
; GFX12-WGP-NEXT: v_mov_b32_e32 v1, s2
@@ -891,7 +891,7 @@ define amdgpu_kernel void @global_nontemporal_store_1(
; GFX12-CU-NEXT: s_mov_b32 s3, 0x3ff
; GFX12-CU-NEXT: v_and_b32_e64 v0, v0, s3
; GFX12-CU-NEXT: s_mov_b32 s3, 2
-; GFX12-CU-NEXT: s_wait_alu 0xfffe
+; GFX12-CU-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-CU-NEXT: v_lshlrev_b32_e64 v0, s3, v0
; GFX12-CU-NEXT: s_wait_kmcnt 0x0
; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
index 521d6cc669e2d..f9e1e320e14f3 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
@@ -325,7 +325,7 @@ define amdgpu_kernel void @global_volatile_load_1(
; GFX12-WGP-NEXT: s_mov_b32 s4, 0x3ff
; GFX12-WGP-NEXT: v_and_b32_e64 v1, v1, s4
; GFX12-WGP-NEXT: s_mov_b32 s4, 2
-; GFX12-WGP-NEXT: s_wait_alu 0xfffe
+; GFX12-WGP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-WGP-NEXT: v_lshlrev_b32_e64 v1, s4, v1
; GFX12-WGP-NEXT: s_wait_kmcnt 0x0
; GFX12-WGP-NEXT: global_load_b32 v1, v1, s[2:3] scope:SCOPE_SYS
@@ -344,7 +344,7 @@ define amdgpu_kernel void @global_volatile_load_1(
; GFX12-CU-NEXT: s_mov_b32 s4, 0x3ff
; GFX12-CU-NEXT: v_and_b32_e64 v1, v1, s4
; GFX12-CU-NEXT: s_mov_b32 s4, 2
-; GFX12-CU-NEXT: s_wait_alu 0xfffe
+; GFX12-CU-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-CU-NEXT: v_lshlrev_b32_e64 v1, s4, v1
; GFX12-CU-NEXT: s_wait_kmcnt 0x0
; GFX12-CU-NEXT: global_load_b32 v1, v1, s[2:3] scope:SCOPE_SYS
@@ -693,7 +693,7 @@ define amdgpu_kernel void @global_volatile_store_1(
; GFX12-WGP-NEXT: s_mov_b32 s3, 0x3ff
; GFX12-WGP-NEXT: v_and_b32_e64 v0, v0, s3
; GFX12-WGP-NEXT: s_mov_b32 s3, 2
-; GFX12-WGP-NEXT: s_wait_alu 0xfffe
+; GFX12-WGP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-WGP-NEXT: v_lshlrev_b32_e64 v0, s3, v0
; GFX12-WGP-NEXT: s_wait_kmcnt 0x0
; GFX12-WGP-NEXT: v_mov_b32_e32 v1, s2
@@ -715,7 +715,7 @@ define amdgpu_kernel void @global_volatile_store_1(
; GFX12-CU-NEXT: s_mov_b32 s3, 0x3ff
; GFX12-CU-NEXT: v_and_b32_e64 v0, v0, s3
; GFX12-CU-NEXT: s_mov_b32 s3, 2
-; GFX12-CU-NEXT: s_wait_alu 0xfffe
+; GFX12-CU-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-CU-NEXT: v_lshlrev_b32_e64 v0, s3, v0
; GFX12-CU-NEXT: s_wait_kmcnt 0x0
; GFX12-CU-NEXT: v_mov_b32_e32 v1, s2
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
index f520943983b3a..9c12338f17d4c 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
@@ -3375,7 +3375,7 @@ define amdgpu_kernel void @private_agent_monotonic_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -3389,7 +3389,7 @@ define amdgpu_kernel void @private_agent_monotonic_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -3645,7 +3645,7 @@ define amdgpu_kernel void @private_agent_acquire_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -3659,7 +3659,7 @@ define amdgpu_kernel void @private_agent_acquire_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -3917,7 +3917,7 @@ define amdgpu_kernel void @private_agent_release_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -3931,7 +3931,7 @@ define amdgpu_kernel void @private_agent_release_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -4190,7 +4190,7 @@ define amdgpu_kernel void @private_agent_acq_rel_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -4204,7 +4204,7 @@ define amdgpu_kernel void @private_agent_acq_rel_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -4465,7 +4465,7 @@ define amdgpu_kernel void @private_agent_seq_cst_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -4479,7 +4479,7 @@ define amdgpu_kernel void @private_agent_seq_cst_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -4740,7 +4740,7 @@ define amdgpu_kernel void @private_agent_monotonic_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -4754,7 +4754,7 @@ define amdgpu_kernel void @private_agent_monotonic_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -5012,7 +5012,7 @@ define amdgpu_kernel void @private_agent_acquire_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -5026,7 +5026,7 @@ define amdgpu_kernel void @private_agent_acquire_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -5284,7 +5284,7 @@ define amdgpu_kernel void @private_agent_release_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -5298,7 +5298,7 @@ define amdgpu_kernel void @private_agent_release_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -5559,7 +5559,7 @@ define amdgpu_kernel void @private_agent_acq_rel_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -5573,7 +5573,7 @@ define amdgpu_kernel void @private_agent_acq_rel_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -5834,7 +5834,7 @@ define amdgpu_kernel void @private_agent_seq_cst_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -5848,7 +5848,7 @@ define amdgpu_kernel void @private_agent_seq_cst_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -6109,7 +6109,7 @@ define amdgpu_kernel void @private_agent_monotonic_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -6123,7 +6123,7 @@ define amdgpu_kernel void @private_agent_monotonic_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -6384,7 +6384,7 @@ define amdgpu_kernel void @private_agent_acquire_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -6398,7 +6398,7 @@ define amdgpu_kernel void @private_agent_acquire_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -6659,7 +6659,7 @@ define amdgpu_kernel void @private_agent_release_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -6673,7 +6673,7 @@ define amdgpu_kernel void @private_agent_release_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -6934,7 +6934,7 @@ define amdgpu_kernel void @private_agent_acq_rel_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -6948,7 +6948,7 @@ define amdgpu_kernel void @private_agent_acq_rel_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -7209,7 +7209,7 @@ define amdgpu_kernel void @private_agent_seq_cst_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -7223,7 +7223,7 @@ define amdgpu_kernel void @private_agent_seq_cst_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -7510,7 +7510,7 @@ define amdgpu_kernel void @private_agent_monotonic_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -7525,7 +7525,7 @@ define amdgpu_kernel void @private_agent_monotonic_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -7812,7 +7812,7 @@ define amdgpu_kernel void @private_agent_acquire_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -7827,7 +7827,7 @@ define amdgpu_kernel void @private_agent_acquire_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -8115,7 +8115,7 @@ define amdgpu_kernel void @private_agent_release_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -8130,7 +8130,7 @@ define amdgpu_kernel void @private_agent_release_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -8420,7 +8420,7 @@ define amdgpu_kernel void @private_agent_acq_rel_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -8435,7 +8435,7 @@ define amdgpu_kernel void @private_agent_acq_rel_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -8726,7 +8726,7 @@ define amdgpu_kernel void @private_agent_seq_cst_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -8741,7 +8741,7 @@ define amdgpu_kernel void @private_agent_seq_cst_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -9032,7 +9032,7 @@ define amdgpu_kernel void @private_agent_monotonic_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -9047,7 +9047,7 @@ define amdgpu_kernel void @private_agent_monotonic_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -9335,7 +9335,7 @@ define amdgpu_kernel void @private_agent_acquire_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -9350,7 +9350,7 @@ define amdgpu_kernel void @private_agent_acquire_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -9638,7 +9638,7 @@ define amdgpu_kernel void @private_agent_release_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -9653,7 +9653,7 @@ define amdgpu_kernel void @private_agent_release_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -9944,7 +9944,7 @@ define amdgpu_kernel void @private_agent_acq_rel_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -9959,7 +9959,7 @@ define amdgpu_kernel void @private_agent_acq_rel_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -10250,7 +10250,7 @@ define amdgpu_kernel void @private_agent_seq_cst_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -10265,7 +10265,7 @@ define amdgpu_kernel void @private_agent_seq_cst_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -10556,7 +10556,7 @@ define amdgpu_kernel void @private_agent_monotonic_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -10571,7 +10571,7 @@ define amdgpu_kernel void @private_agent_monotonic_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -10862,7 +10862,7 @@ define amdgpu_kernel void @private_agent_acquire_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -10877,7 +10877,7 @@ define amdgpu_kernel void @private_agent_acquire_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -11168,7 +11168,7 @@ define amdgpu_kernel void @private_agent_release_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -11183,7 +11183,7 @@ define amdgpu_kernel void @private_agent_release_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -11474,7 +11474,7 @@ define amdgpu_kernel void @private_agent_acq_rel_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -11489,7 +11489,7 @@ define amdgpu_kernel void @private_agent_acq_rel_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -11780,7 +11780,7 @@ define amdgpu_kernel void @private_agent_seq_cst_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -11795,7 +11795,7 @@ define amdgpu_kernel void @private_agent_seq_cst_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -15218,7 +15218,7 @@ define amdgpu_kernel void @private_agent_one_as_monotonic_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -15232,7 +15232,7 @@ define amdgpu_kernel void @private_agent_one_as_monotonic_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -15488,7 +15488,7 @@ define amdgpu_kernel void @private_agent_one_as_acquire_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -15502,7 +15502,7 @@ define amdgpu_kernel void @private_agent_one_as_acquire_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -15760,7 +15760,7 @@ define amdgpu_kernel void @private_agent_one_as_release_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -15774,7 +15774,7 @@ define amdgpu_kernel void @private_agent_one_as_release_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -16033,7 +16033,7 @@ define amdgpu_kernel void @private_agent_one_as_acq_rel_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -16047,7 +16047,7 @@ define amdgpu_kernel void @private_agent_one_as_acq_rel_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -16308,7 +16308,7 @@ define amdgpu_kernel void @private_agent_one_as_seq_cst_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -16322,7 +16322,7 @@ define amdgpu_kernel void @private_agent_one_as_seq_cst_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -16583,7 +16583,7 @@ define amdgpu_kernel void @private_agent_one_as_monotonic_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -16597,7 +16597,7 @@ define amdgpu_kernel void @private_agent_one_as_monotonic_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -16855,7 +16855,7 @@ define amdgpu_kernel void @private_agent_one_as_acquire_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -16869,7 +16869,7 @@ define amdgpu_kernel void @private_agent_one_as_acquire_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -17127,7 +17127,7 @@ define amdgpu_kernel void @private_agent_one_as_release_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -17141,7 +17141,7 @@ define amdgpu_kernel void @private_agent_one_as_release_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -17402,7 +17402,7 @@ define amdgpu_kernel void @private_agent_one_as_acq_rel_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -17416,7 +17416,7 @@ define amdgpu_kernel void @private_agent_one_as_acq_rel_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -17677,7 +17677,7 @@ define amdgpu_kernel void @private_agent_one_as_seq_cst_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -17691,7 +17691,7 @@ define amdgpu_kernel void @private_agent_one_as_seq_cst_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -17952,7 +17952,7 @@ define amdgpu_kernel void @private_agent_one_as_monotonic_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -17966,7 +17966,7 @@ define amdgpu_kernel void @private_agent_one_as_monotonic_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -18227,7 +18227,7 @@ define amdgpu_kernel void @private_agent_one_as_acquire_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -18241,7 +18241,7 @@ define amdgpu_kernel void @private_agent_one_as_acquire_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -18502,7 +18502,7 @@ define amdgpu_kernel void @private_agent_one_as_release_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -18516,7 +18516,7 @@ define amdgpu_kernel void @private_agent_one_as_release_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -18777,7 +18777,7 @@ define amdgpu_kernel void @private_agent_one_as_acq_rel_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -18791,7 +18791,7 @@ define amdgpu_kernel void @private_agent_one_as_acq_rel_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -19052,7 +19052,7 @@ define amdgpu_kernel void @private_agent_one_as_seq_cst_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -19066,7 +19066,7 @@ define amdgpu_kernel void @private_agent_one_as_seq_cst_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -19353,7 +19353,7 @@ define amdgpu_kernel void @private_agent_one_as_monotonic_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -19368,7 +19368,7 @@ define amdgpu_kernel void @private_agent_one_as_monotonic_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -19655,7 +19655,7 @@ define amdgpu_kernel void @private_agent_one_as_acquire_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -19670,7 +19670,7 @@ define amdgpu_kernel void @private_agent_one_as_acquire_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -19959,7 +19959,7 @@ define amdgpu_kernel void @private_agent_one_as_acq_rel_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -19974,7 +19974,7 @@ define amdgpu_kernel void @private_agent_one_as_acq_rel_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -20266,7 +20266,7 @@ define amdgpu_kernel void @private_agent_one_as_seq_cst_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -20281,7 +20281,7 @@ define amdgpu_kernel void @private_agent_one_as_seq_cst_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -20573,7 +20573,7 @@ define amdgpu_kernel void @private_agent_one_as_monotonic_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -20588,7 +20588,7 @@ define amdgpu_kernel void @private_agent_one_as_monotonic_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -20877,7 +20877,7 @@ define amdgpu_kernel void @private_agent_one_as_acquire_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -20892,7 +20892,7 @@ define amdgpu_kernel void @private_agent_one_as_acquire_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -21181,7 +21181,7 @@ define amdgpu_kernel void @private_agent_one_as_release_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -21196,7 +21196,7 @@ define amdgpu_kernel void @private_agent_one_as_release_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -21488,7 +21488,7 @@ define amdgpu_kernel void @private_agent_one_as_acq_rel_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -21503,7 +21503,7 @@ define amdgpu_kernel void @private_agent_one_as_acq_rel_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -21795,7 +21795,7 @@ define amdgpu_kernel void @private_agent_one_as_seq_cst_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -21810,7 +21810,7 @@ define amdgpu_kernel void @private_agent_one_as_seq_cst_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -22102,7 +22102,7 @@ define amdgpu_kernel void @private_agent_one_as_monotonic_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -22117,7 +22117,7 @@ define amdgpu_kernel void @private_agent_one_as_monotonic_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -22409,7 +22409,7 @@ define amdgpu_kernel void @private_agent_one_as_acquire_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -22424,7 +22424,7 @@ define amdgpu_kernel void @private_agent_one_as_acquire_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -22716,7 +22716,7 @@ define amdgpu_kernel void @private_agent_one_as_release_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -22731,7 +22731,7 @@ define amdgpu_kernel void @private_agent_one_as_release_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -23023,7 +23023,7 @@ define amdgpu_kernel void @private_agent_one_as_acq_rel_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -23038,7 +23038,7 @@ define amdgpu_kernel void @private_agent_one_as_acq_rel_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -23330,7 +23330,7 @@ define amdgpu_kernel void @private_agent_one_as_seq_cst_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -23345,7 +23345,7 @@ define amdgpu_kernel void @private_agent_one_as_seq_cst_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
index 24f9fe0297c63..5d0b7878c6b81 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
@@ -3368,7 +3368,7 @@ define amdgpu_kernel void @private_cluster_monotonic_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -3382,7 +3382,7 @@ define amdgpu_kernel void @private_cluster_monotonic_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -3638,7 +3638,7 @@ define amdgpu_kernel void @private_cluster_acquire_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -3652,7 +3652,7 @@ define amdgpu_kernel void @private_cluster_acquire_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -3910,7 +3910,7 @@ define amdgpu_kernel void @private_cluster_release_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -3924,7 +3924,7 @@ define amdgpu_kernel void @private_cluster_release_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -4182,7 +4182,7 @@ define amdgpu_kernel void @private_cluster_acq_rel_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -4196,7 +4196,7 @@ define amdgpu_kernel void @private_cluster_acq_rel_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -4456,7 +4456,7 @@ define amdgpu_kernel void @private_cluster_seq_cst_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -4470,7 +4470,7 @@ define amdgpu_kernel void @private_cluster_seq_cst_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -4730,7 +4730,7 @@ define amdgpu_kernel void @private_cluster_monotonic_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -4744,7 +4744,7 @@ define amdgpu_kernel void @private_cluster_monotonic_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -5002,7 +5002,7 @@ define amdgpu_kernel void @private_cluster_acquire_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -5016,7 +5016,7 @@ define amdgpu_kernel void @private_cluster_acquire_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -5274,7 +5274,7 @@ define amdgpu_kernel void @private_cluster_release_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -5288,7 +5288,7 @@ define amdgpu_kernel void @private_cluster_release_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -5548,7 +5548,7 @@ define amdgpu_kernel void @private_cluster_acq_rel_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -5562,7 +5562,7 @@ define amdgpu_kernel void @private_cluster_acq_rel_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -5822,7 +5822,7 @@ define amdgpu_kernel void @private_cluster_seq_cst_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -5836,7 +5836,7 @@ define amdgpu_kernel void @private_cluster_seq_cst_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -6096,7 +6096,7 @@ define amdgpu_kernel void @private_cluster_monotonic_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -6110,7 +6110,7 @@ define amdgpu_kernel void @private_cluster_monotonic_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -6370,7 +6370,7 @@ define amdgpu_kernel void @private_cluster_acquire_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -6384,7 +6384,7 @@ define amdgpu_kernel void @private_cluster_acquire_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -6644,7 +6644,7 @@ define amdgpu_kernel void @private_cluster_release_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -6658,7 +6658,7 @@ define amdgpu_kernel void @private_cluster_release_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -6918,7 +6918,7 @@ define amdgpu_kernel void @private_cluster_acq_rel_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -6932,7 +6932,7 @@ define amdgpu_kernel void @private_cluster_acq_rel_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -7192,7 +7192,7 @@ define amdgpu_kernel void @private_cluster_seq_cst_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -7206,7 +7206,7 @@ define amdgpu_kernel void @private_cluster_seq_cst_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -7492,7 +7492,7 @@ define amdgpu_kernel void @private_cluster_monotonic_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -7507,7 +7507,7 @@ define amdgpu_kernel void @private_cluster_monotonic_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -7794,7 +7794,7 @@ define amdgpu_kernel void @private_cluster_acquire_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -7809,7 +7809,7 @@ define amdgpu_kernel void @private_cluster_acquire_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -8097,7 +8097,7 @@ define amdgpu_kernel void @private_cluster_release_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -8112,7 +8112,7 @@ define amdgpu_kernel void @private_cluster_release_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -8401,7 +8401,7 @@ define amdgpu_kernel void @private_cluster_acq_rel_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -8416,7 +8416,7 @@ define amdgpu_kernel void @private_cluster_acq_rel_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -8706,7 +8706,7 @@ define amdgpu_kernel void @private_cluster_seq_cst_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -8721,7 +8721,7 @@ define amdgpu_kernel void @private_cluster_seq_cst_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -9011,7 +9011,7 @@ define amdgpu_kernel void @private_cluster_monotonic_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -9026,7 +9026,7 @@ define amdgpu_kernel void @private_cluster_monotonic_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -9314,7 +9314,7 @@ define amdgpu_kernel void @private_cluster_acquire_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -9329,7 +9329,7 @@ define amdgpu_kernel void @private_cluster_acquire_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -9617,7 +9617,7 @@ define amdgpu_kernel void @private_cluster_release_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -9632,7 +9632,7 @@ define amdgpu_kernel void @private_cluster_release_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -9922,7 +9922,7 @@ define amdgpu_kernel void @private_cluster_acq_rel_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -9937,7 +9937,7 @@ define amdgpu_kernel void @private_cluster_acq_rel_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -10227,7 +10227,7 @@ define amdgpu_kernel void @private_cluster_seq_cst_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -10242,7 +10242,7 @@ define amdgpu_kernel void @private_cluster_seq_cst_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -10532,7 +10532,7 @@ define amdgpu_kernel void @private_cluster_monotonic_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -10547,7 +10547,7 @@ define amdgpu_kernel void @private_cluster_monotonic_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -10837,7 +10837,7 @@ define amdgpu_kernel void @private_cluster_acquire_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -10852,7 +10852,7 @@ define amdgpu_kernel void @private_cluster_acquire_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -11142,7 +11142,7 @@ define amdgpu_kernel void @private_cluster_release_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -11157,7 +11157,7 @@ define amdgpu_kernel void @private_cluster_release_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -11447,7 +11447,7 @@ define amdgpu_kernel void @private_cluster_acq_rel_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -11462,7 +11462,7 @@ define amdgpu_kernel void @private_cluster_acq_rel_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -11752,7 +11752,7 @@ define amdgpu_kernel void @private_cluster_seq_cst_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -11767,7 +11767,7 @@ define amdgpu_kernel void @private_cluster_seq_cst_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -15182,7 +15182,7 @@ define amdgpu_kernel void @private_cluster_one_as_monotonic_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -15196,7 +15196,7 @@ define amdgpu_kernel void @private_cluster_one_as_monotonic_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -15452,7 +15452,7 @@ define amdgpu_kernel void @private_cluster_one_as_acquire_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -15466,7 +15466,7 @@ define amdgpu_kernel void @private_cluster_one_as_acquire_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -15724,7 +15724,7 @@ define amdgpu_kernel void @private_cluster_one_as_release_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -15738,7 +15738,7 @@ define amdgpu_kernel void @private_cluster_one_as_release_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -15996,7 +15996,7 @@ define amdgpu_kernel void @private_cluster_one_as_acq_rel_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -16010,7 +16010,7 @@ define amdgpu_kernel void @private_cluster_one_as_acq_rel_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -16270,7 +16270,7 @@ define amdgpu_kernel void @private_cluster_one_as_seq_cst_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -16284,7 +16284,7 @@ define amdgpu_kernel void @private_cluster_one_as_seq_cst_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -16544,7 +16544,7 @@ define amdgpu_kernel void @private_cluster_one_as_monotonic_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -16558,7 +16558,7 @@ define amdgpu_kernel void @private_cluster_one_as_monotonic_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -16816,7 +16816,7 @@ define amdgpu_kernel void @private_cluster_one_as_acquire_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -16830,7 +16830,7 @@ define amdgpu_kernel void @private_cluster_one_as_acquire_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -17088,7 +17088,7 @@ define amdgpu_kernel void @private_cluster_one_as_release_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -17102,7 +17102,7 @@ define amdgpu_kernel void @private_cluster_one_as_release_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -17362,7 +17362,7 @@ define amdgpu_kernel void @private_cluster_one_as_acq_rel_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -17376,7 +17376,7 @@ define amdgpu_kernel void @private_cluster_one_as_acq_rel_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -17636,7 +17636,7 @@ define amdgpu_kernel void @private_cluster_one_as_seq_cst_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -17650,7 +17650,7 @@ define amdgpu_kernel void @private_cluster_one_as_seq_cst_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -17910,7 +17910,7 @@ define amdgpu_kernel void @private_cluster_one_as_monotonic_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -17924,7 +17924,7 @@ define amdgpu_kernel void @private_cluster_one_as_monotonic_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -18184,7 +18184,7 @@ define amdgpu_kernel void @private_cluster_one_as_acquire_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -18198,7 +18198,7 @@ define amdgpu_kernel void @private_cluster_one_as_acquire_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -18458,7 +18458,7 @@ define amdgpu_kernel void @private_cluster_one_as_release_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -18472,7 +18472,7 @@ define amdgpu_kernel void @private_cluster_one_as_release_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -18732,7 +18732,7 @@ define amdgpu_kernel void @private_cluster_one_as_acq_rel_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -18746,7 +18746,7 @@ define amdgpu_kernel void @private_cluster_one_as_acq_rel_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -19006,7 +19006,7 @@ define amdgpu_kernel void @private_cluster_one_as_seq_cst_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -19020,7 +19020,7 @@ define amdgpu_kernel void @private_cluster_one_as_seq_cst_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -19306,7 +19306,7 @@ define amdgpu_kernel void @private_cluster_one_as_monotonic_monotonic_ret_cmpxch
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -19321,7 +19321,7 @@ define amdgpu_kernel void @private_cluster_one_as_monotonic_monotonic_ret_cmpxch
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -19608,7 +19608,7 @@ define amdgpu_kernel void @private_cluster_one_as_acquire_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -19623,7 +19623,7 @@ define amdgpu_kernel void @private_cluster_one_as_acquire_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -19912,7 +19912,7 @@ define amdgpu_kernel void @private_cluster_one_as_acq_rel_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -19927,7 +19927,7 @@ define amdgpu_kernel void @private_cluster_one_as_acq_rel_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -20218,7 +20218,7 @@ define amdgpu_kernel void @private_cluster_one_as_seq_cst_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -20233,7 +20233,7 @@ define amdgpu_kernel void @private_cluster_one_as_seq_cst_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -20524,7 +20524,7 @@ define amdgpu_kernel void @private_cluster_one_as_monotonic_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -20539,7 +20539,7 @@ define amdgpu_kernel void @private_cluster_one_as_monotonic_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -20828,7 +20828,7 @@ define amdgpu_kernel void @private_cluster_one_as_acquire_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -20843,7 +20843,7 @@ define amdgpu_kernel void @private_cluster_one_as_acquire_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -21132,7 +21132,7 @@ define amdgpu_kernel void @private_cluster_one_as_release_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -21147,7 +21147,7 @@ define amdgpu_kernel void @private_cluster_one_as_release_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -21438,7 +21438,7 @@ define amdgpu_kernel void @private_cluster_one_as_acq_rel_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -21453,7 +21453,7 @@ define amdgpu_kernel void @private_cluster_one_as_acq_rel_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -21744,7 +21744,7 @@ define amdgpu_kernel void @private_cluster_one_as_seq_cst_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -21759,7 +21759,7 @@ define amdgpu_kernel void @private_cluster_one_as_seq_cst_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -22050,7 +22050,7 @@ define amdgpu_kernel void @private_cluster_one_as_monotonic_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -22065,7 +22065,7 @@ define amdgpu_kernel void @private_cluster_one_as_monotonic_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -22356,7 +22356,7 @@ define amdgpu_kernel void @private_cluster_one_as_acquire_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -22371,7 +22371,7 @@ define amdgpu_kernel void @private_cluster_one_as_acquire_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -22662,7 +22662,7 @@ define amdgpu_kernel void @private_cluster_one_as_release_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -22677,7 +22677,7 @@ define amdgpu_kernel void @private_cluster_one_as_release_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -22968,7 +22968,7 @@ define amdgpu_kernel void @private_cluster_one_as_acq_rel_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -22983,7 +22983,7 @@ define amdgpu_kernel void @private_cluster_one_as_acq_rel_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -23274,7 +23274,7 @@ define amdgpu_kernel void @private_cluster_one_as_seq_cst_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -23289,7 +23289,7 @@ define amdgpu_kernel void @private_cluster_one_as_seq_cst_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
index dfbcaaf01bfd4..8759ef2dc32c3 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
@@ -42,7 +42,7 @@ define amdgpu_kernel void @private_last_use_load_1(ptr addrspace(5) %in, ptr add
; GFX12-NEXT: s_mov_b32 s3, 0x3ff
; GFX12-NEXT: v_and_b32_e64 v1, v1, s3
; GFX12-NEXT: s_mov_b32 s3, 2
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_lshlrev_b32_e64 v1, s3, v1
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: scratch_load_b32 v1, v1, s2 th:TH_LOAD_LU
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
index 07602f10d21a7..40f91a5ff3976 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
@@ -427,7 +427,7 @@ define amdgpu_kernel void @private_nontemporal_load_1(
; GFX12-WGP-NEXT: s_mov_b32 s3, 0x3ff
; GFX12-WGP-NEXT: v_and_b32_e64 v1, v1, s3
; GFX12-WGP-NEXT: s_mov_b32 s3, 2
-; GFX12-WGP-NEXT: s_wait_alu 0xfffe
+; GFX12-WGP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-WGP-NEXT: v_lshlrev_b32_e64 v1, s3, v1
; GFX12-WGP-NEXT: s_wait_kmcnt 0x0
; GFX12-WGP-NEXT: scratch_load_b32 v1, v1, s2 th:TH_LOAD_NT
@@ -444,7 +444,7 @@ define amdgpu_kernel void @private_nontemporal_load_1(
; GFX12-CU-NEXT: s_mov_b32 s3, 0x3ff
; GFX12-CU-NEXT: v_and_b32_e64 v1, v1, s3
; GFX12-CU-NEXT: s_mov_b32 s3, 2
-; GFX12-CU-NEXT: s_wait_alu 0xfffe
+; GFX12-CU-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-CU-NEXT: v_lshlrev_b32_e64 v1, s3, v1
; GFX12-CU-NEXT: s_wait_kmcnt 0x0
; GFX12-CU-NEXT: scratch_load_b32 v1, v1, s2 th:TH_LOAD_NT
@@ -840,7 +840,7 @@ define amdgpu_kernel void @private_nontemporal_store_1(
; GFX12-WGP-NEXT: s_mov_b32 s2, 0x3ff
; GFX12-WGP-NEXT: v_and_b32_e64 v0, v0, s2
; GFX12-WGP-NEXT: s_mov_b32 s2, 2
-; GFX12-WGP-NEXT: s_wait_alu 0xfffe
+; GFX12-WGP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-WGP-NEXT: v_lshlrev_b32_e64 v1, s2, v0
; GFX12-WGP-NEXT: s_wait_kmcnt 0x0
; GFX12-WGP-NEXT: v_mov_b32_e32 v0, s1
@@ -856,7 +856,7 @@ define amdgpu_kernel void @private_nontemporal_store_1(
; GFX12-CU-NEXT: s_mov_b32 s2, 0x3ff
; GFX12-CU-NEXT: v_and_b32_e64 v0, v0, s2
; GFX12-CU-NEXT: s_mov_b32 s2, 2
-; GFX12-CU-NEXT: s_wait_alu 0xfffe
+; GFX12-CU-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-CU-NEXT: v_lshlrev_b32_e64 v1, s2, v0
; GFX12-CU-NEXT: s_wait_kmcnt 0x0
; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
index 583eaeb38870b..56bd75944361b 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
@@ -3341,7 +3341,7 @@ define amdgpu_kernel void @private_singlethread_monotonic_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -3355,7 +3355,7 @@ define amdgpu_kernel void @private_singlethread_monotonic_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -3611,7 +3611,7 @@ define amdgpu_kernel void @private_singlethread_acquire_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -3625,7 +3625,7 @@ define amdgpu_kernel void @private_singlethread_acquire_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -3881,7 +3881,7 @@ define amdgpu_kernel void @private_singlethread_release_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -3895,7 +3895,7 @@ define amdgpu_kernel void @private_singlethread_release_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -4151,7 +4151,7 @@ define amdgpu_kernel void @private_singlethread_acq_rel_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -4165,7 +4165,7 @@ define amdgpu_kernel void @private_singlethread_acq_rel_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -4421,7 +4421,7 @@ define amdgpu_kernel void @private_singlethread_seq_cst_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -4435,7 +4435,7 @@ define amdgpu_kernel void @private_singlethread_seq_cst_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -4691,7 +4691,7 @@ define amdgpu_kernel void @private_singlethread_monotonic_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -4705,7 +4705,7 @@ define amdgpu_kernel void @private_singlethread_monotonic_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -4961,7 +4961,7 @@ define amdgpu_kernel void @private_singlethread_acquire_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -4975,7 +4975,7 @@ define amdgpu_kernel void @private_singlethread_acquire_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -5231,7 +5231,7 @@ define amdgpu_kernel void @private_singlethread_release_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -5245,7 +5245,7 @@ define amdgpu_kernel void @private_singlethread_release_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -5501,7 +5501,7 @@ define amdgpu_kernel void @private_singlethread_acq_rel_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -5515,7 +5515,7 @@ define amdgpu_kernel void @private_singlethread_acq_rel_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -5771,7 +5771,7 @@ define amdgpu_kernel void @private_singlethread_seq_cst_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -5785,7 +5785,7 @@ define amdgpu_kernel void @private_singlethread_seq_cst_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -6041,7 +6041,7 @@ define amdgpu_kernel void @private_singlethread_monotonic_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -6055,7 +6055,7 @@ define amdgpu_kernel void @private_singlethread_monotonic_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -6311,7 +6311,7 @@ define amdgpu_kernel void @private_singlethread_acquire_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -6325,7 +6325,7 @@ define amdgpu_kernel void @private_singlethread_acquire_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -6581,7 +6581,7 @@ define amdgpu_kernel void @private_singlethread_release_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -6595,7 +6595,7 @@ define amdgpu_kernel void @private_singlethread_release_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -6851,7 +6851,7 @@ define amdgpu_kernel void @private_singlethread_acq_rel_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -6865,7 +6865,7 @@ define amdgpu_kernel void @private_singlethread_acq_rel_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -7121,7 +7121,7 @@ define amdgpu_kernel void @private_singlethread_seq_cst_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -7135,7 +7135,7 @@ define amdgpu_kernel void @private_singlethread_seq_cst_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -7417,7 +7417,7 @@ define amdgpu_kernel void @private_singlethread_monotonic_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -7432,7 +7432,7 @@ define amdgpu_kernel void @private_singlethread_monotonic_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -7719,7 +7719,7 @@ define amdgpu_kernel void @private_singlethread_acquire_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -7734,7 +7734,7 @@ define amdgpu_kernel void @private_singlethread_acquire_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -8021,7 +8021,7 @@ define amdgpu_kernel void @private_singlethread_release_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -8036,7 +8036,7 @@ define amdgpu_kernel void @private_singlethread_release_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -8323,7 +8323,7 @@ define amdgpu_kernel void @private_singlethread_acq_rel_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -8338,7 +8338,7 @@ define amdgpu_kernel void @private_singlethread_acq_rel_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -8625,7 +8625,7 @@ define amdgpu_kernel void @private_singlethread_seq_cst_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -8640,7 +8640,7 @@ define amdgpu_kernel void @private_singlethread_seq_cst_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -8927,7 +8927,7 @@ define amdgpu_kernel void @private_singlethread_monotonic_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -8942,7 +8942,7 @@ define amdgpu_kernel void @private_singlethread_monotonic_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -9229,7 +9229,7 @@ define amdgpu_kernel void @private_singlethread_acquire_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -9244,7 +9244,7 @@ define amdgpu_kernel void @private_singlethread_acquire_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -9531,7 +9531,7 @@ define amdgpu_kernel void @private_singlethread_release_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -9546,7 +9546,7 @@ define amdgpu_kernel void @private_singlethread_release_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -9833,7 +9833,7 @@ define amdgpu_kernel void @private_singlethread_acq_rel_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -9848,7 +9848,7 @@ define amdgpu_kernel void @private_singlethread_acq_rel_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -10135,7 +10135,7 @@ define amdgpu_kernel void @private_singlethread_seq_cst_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -10150,7 +10150,7 @@ define amdgpu_kernel void @private_singlethread_seq_cst_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -10437,7 +10437,7 @@ define amdgpu_kernel void @private_singlethread_monotonic_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -10452,7 +10452,7 @@ define amdgpu_kernel void @private_singlethread_monotonic_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -10739,7 +10739,7 @@ define amdgpu_kernel void @private_singlethread_acquire_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -10754,7 +10754,7 @@ define amdgpu_kernel void @private_singlethread_acquire_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -11041,7 +11041,7 @@ define amdgpu_kernel void @private_singlethread_release_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -11056,7 +11056,7 @@ define amdgpu_kernel void @private_singlethread_release_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -11343,7 +11343,7 @@ define amdgpu_kernel void @private_singlethread_acq_rel_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -11358,7 +11358,7 @@ define amdgpu_kernel void @private_singlethread_acq_rel_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -11645,7 +11645,7 @@ define amdgpu_kernel void @private_singlethread_seq_cst_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -11660,7 +11660,7 @@ define amdgpu_kernel void @private_singlethread_seq_cst_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -15040,7 +15040,7 @@ define amdgpu_kernel void @private_singlethread_one_as_monotonic_monotonic_cmpxc
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -15054,7 +15054,7 @@ define amdgpu_kernel void @private_singlethread_one_as_monotonic_monotonic_cmpxc
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -15310,7 +15310,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acquire_monotonic_cmpxchg
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -15324,7 +15324,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acquire_monotonic_cmpxchg
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -15580,7 +15580,7 @@ define amdgpu_kernel void @private_singlethread_one_as_release_monotonic_cmpxchg
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -15594,7 +15594,7 @@ define amdgpu_kernel void @private_singlethread_one_as_release_monotonic_cmpxchg
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -15850,7 +15850,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acq_rel_monotonic_cmpxchg
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -15864,7 +15864,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acq_rel_monotonic_cmpxchg
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -16120,7 +16120,7 @@ define amdgpu_kernel void @private_singlethread_one_as_seq_cst_monotonic_cmpxchg
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -16134,7 +16134,7 @@ define amdgpu_kernel void @private_singlethread_one_as_seq_cst_monotonic_cmpxchg
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -16390,7 +16390,7 @@ define amdgpu_kernel void @private_singlethread_one_as_monotonic_acquire_cmpxchg
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -16404,7 +16404,7 @@ define amdgpu_kernel void @private_singlethread_one_as_monotonic_acquire_cmpxchg
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -16660,7 +16660,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acquire_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -16674,7 +16674,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acquire_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -16930,7 +16930,7 @@ define amdgpu_kernel void @private_singlethread_one_as_release_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -16944,7 +16944,7 @@ define amdgpu_kernel void @private_singlethread_one_as_release_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -17200,7 +17200,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acq_rel_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -17214,7 +17214,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acq_rel_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -17470,7 +17470,7 @@ define amdgpu_kernel void @private_singlethread_one_as_seq_cst_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -17484,7 +17484,7 @@ define amdgpu_kernel void @private_singlethread_one_as_seq_cst_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -17740,7 +17740,7 @@ define amdgpu_kernel void @private_singlethread_one_as_monotonic_seq_cst_cmpxchg
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -17754,7 +17754,7 @@ define amdgpu_kernel void @private_singlethread_one_as_monotonic_seq_cst_cmpxchg
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -18010,7 +18010,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acquire_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -18024,7 +18024,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acquire_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -18280,7 +18280,7 @@ define amdgpu_kernel void @private_singlethread_one_as_release_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -18294,7 +18294,7 @@ define amdgpu_kernel void @private_singlethread_one_as_release_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -18550,7 +18550,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acq_rel_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -18564,7 +18564,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acq_rel_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -18820,7 +18820,7 @@ define amdgpu_kernel void @private_singlethread_one_as_seq_cst_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -18834,7 +18834,7 @@ define amdgpu_kernel void @private_singlethread_one_as_seq_cst_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -19116,7 +19116,7 @@ define amdgpu_kernel void @private_singlethread_one_as_monotonic_monotonic_ret_c
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -19131,7 +19131,7 @@ define amdgpu_kernel void @private_singlethread_one_as_monotonic_monotonic_ret_c
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -19418,7 +19418,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acquire_monotonic_ret_cmp
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -19433,7 +19433,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acquire_monotonic_ret_cmp
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -19720,7 +19720,7 @@ define amdgpu_kernel void @private_singlethread_one_as_release_monotonic_ret_cmp
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -19735,7 +19735,7 @@ define amdgpu_kernel void @private_singlethread_one_as_release_monotonic_ret_cmp
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -20022,7 +20022,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acq_rel_monotonic_ret_cmp
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -20037,7 +20037,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acq_rel_monotonic_ret_cmp
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -20324,7 +20324,7 @@ define amdgpu_kernel void @private_singlethread_one_as_seq_cst_monotonic_ret_cmp
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -20339,7 +20339,7 @@ define amdgpu_kernel void @private_singlethread_one_as_seq_cst_monotonic_ret_cmp
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -20626,7 +20626,7 @@ define amdgpu_kernel void @private_singlethread_one_as_monotonic_acquire_ret_cmp
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -20641,7 +20641,7 @@ define amdgpu_kernel void @private_singlethread_one_as_monotonic_acquire_ret_cmp
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -20928,7 +20928,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acquire_acquire_ret_cmpxc
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -20943,7 +20943,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acquire_acquire_ret_cmpxc
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -21230,7 +21230,7 @@ define amdgpu_kernel void @private_singlethread_one_as_release_acquire_ret_cmpxc
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -21245,7 +21245,7 @@ define amdgpu_kernel void @private_singlethread_one_as_release_acquire_ret_cmpxc
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -21532,7 +21532,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acq_rel_acquire_ret_cmpxc
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -21547,7 +21547,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acq_rel_acquire_ret_cmpxc
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -21834,7 +21834,7 @@ define amdgpu_kernel void @private_singlethread_one_as_seq_cst_acquire_ret_cmpxc
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -21849,7 +21849,7 @@ define amdgpu_kernel void @private_singlethread_one_as_seq_cst_acquire_ret_cmpxc
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -22136,7 +22136,7 @@ define amdgpu_kernel void @private_singlethread_one_as_monotonic_seq_cst_ret_cmp
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -22151,7 +22151,7 @@ define amdgpu_kernel void @private_singlethread_one_as_monotonic_seq_cst_ret_cmp
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -22438,7 +22438,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acquire_seq_cst_ret_cmpxc
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -22453,7 +22453,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acquire_seq_cst_ret_cmpxc
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -22740,7 +22740,7 @@ define amdgpu_kernel void @private_singlethread_one_as_release_seq_cst_ret_cmpxc
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -22755,7 +22755,7 @@ define amdgpu_kernel void @private_singlethread_one_as_release_seq_cst_ret_cmpxc
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -23042,7 +23042,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acq_rel_seq_cst_ret_cmpxc
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -23057,7 +23057,7 @@ define amdgpu_kernel void @private_singlethread_one_as_acq_rel_seq_cst_ret_cmpxc
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -23344,7 +23344,7 @@ define amdgpu_kernel void @private_singlethread_one_as_seq_cst_seq_cst_ret_cmpxc
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -23359,7 +23359,7 @@ define amdgpu_kernel void @private_singlethread_one_as_seq_cst_seq_cst_ret_cmpxc
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
index 1bf9db321fa0c..2634e7c9dcd3d 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
@@ -3375,7 +3375,7 @@ define amdgpu_kernel void @private_system_monotonic_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -3389,7 +3389,7 @@ define amdgpu_kernel void @private_system_monotonic_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -3645,7 +3645,7 @@ define amdgpu_kernel void @private_system_acquire_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -3659,7 +3659,7 @@ define amdgpu_kernel void @private_system_acquire_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -3917,7 +3917,7 @@ define amdgpu_kernel void @private_system_release_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -3931,7 +3931,7 @@ define amdgpu_kernel void @private_system_release_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -4190,7 +4190,7 @@ define amdgpu_kernel void @private_system_acq_rel_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -4204,7 +4204,7 @@ define amdgpu_kernel void @private_system_acq_rel_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -4465,7 +4465,7 @@ define amdgpu_kernel void @private_system_seq_cst_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -4479,7 +4479,7 @@ define amdgpu_kernel void @private_system_seq_cst_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -4740,7 +4740,7 @@ define amdgpu_kernel void @private_system_monotonic_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -4754,7 +4754,7 @@ define amdgpu_kernel void @private_system_monotonic_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -5012,7 +5012,7 @@ define amdgpu_kernel void @private_system_acquire_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -5026,7 +5026,7 @@ define amdgpu_kernel void @private_system_acquire_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -5284,7 +5284,7 @@ define amdgpu_kernel void @private_system_release_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -5298,7 +5298,7 @@ define amdgpu_kernel void @private_system_release_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -5559,7 +5559,7 @@ define amdgpu_kernel void @private_system_acq_rel_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -5573,7 +5573,7 @@ define amdgpu_kernel void @private_system_acq_rel_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -5834,7 +5834,7 @@ define amdgpu_kernel void @private_system_seq_cst_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -5848,7 +5848,7 @@ define amdgpu_kernel void @private_system_seq_cst_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -6109,7 +6109,7 @@ define amdgpu_kernel void @private_system_seq_cst_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -6123,7 +6123,7 @@ define amdgpu_kernel void @private_system_seq_cst_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -6410,7 +6410,7 @@ define amdgpu_kernel void @private_system_monotonic_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -6425,7 +6425,7 @@ define amdgpu_kernel void @private_system_monotonic_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -6712,7 +6712,7 @@ define amdgpu_kernel void @private_system_acquire_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -6727,7 +6727,7 @@ define amdgpu_kernel void @private_system_acquire_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -7015,7 +7015,7 @@ define amdgpu_kernel void @private_system_acq_rel_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -7030,7 +7030,7 @@ define amdgpu_kernel void @private_system_acq_rel_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -7321,7 +7321,7 @@ define amdgpu_kernel void @private_system_seq_cst_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -7336,7 +7336,7 @@ define amdgpu_kernel void @private_system_seq_cst_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -7627,7 +7627,7 @@ define amdgpu_kernel void @private_system_monotonic_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -7642,7 +7642,7 @@ define amdgpu_kernel void @private_system_monotonic_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -7930,7 +7930,7 @@ define amdgpu_kernel void @private_system_acquire_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -7945,7 +7945,7 @@ define amdgpu_kernel void @private_system_acquire_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -8233,7 +8233,7 @@ define amdgpu_kernel void @private_system_release_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -8248,7 +8248,7 @@ define amdgpu_kernel void @private_system_release_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -8539,7 +8539,7 @@ define amdgpu_kernel void @private_system_acq_rel_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -8554,7 +8554,7 @@ define amdgpu_kernel void @private_system_acq_rel_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -8845,7 +8845,7 @@ define amdgpu_kernel void @private_system_seq_cst_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -8860,7 +8860,7 @@ define amdgpu_kernel void @private_system_seq_cst_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -9151,7 +9151,7 @@ define amdgpu_kernel void @private_system_monotonic_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -9166,7 +9166,7 @@ define amdgpu_kernel void @private_system_monotonic_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -9457,7 +9457,7 @@ define amdgpu_kernel void @private_system_acquire_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -9472,7 +9472,7 @@ define amdgpu_kernel void @private_system_acquire_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -9763,7 +9763,7 @@ define amdgpu_kernel void @private_system_relese_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -9778,7 +9778,7 @@ define amdgpu_kernel void @private_system_relese_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -10069,7 +10069,7 @@ define amdgpu_kernel void @private_system_acq_rel_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -10084,7 +10084,7 @@ define amdgpu_kernel void @private_system_acq_rel_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -10375,7 +10375,7 @@ define amdgpu_kernel void @private_system_seq_cst_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -10390,7 +10390,7 @@ define amdgpu_kernel void @private_system_seq_cst_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -13813,7 +13813,7 @@ define amdgpu_kernel void @private_system_one_as_monotonic_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -13827,7 +13827,7 @@ define amdgpu_kernel void @private_system_one_as_monotonic_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -14083,7 +14083,7 @@ define amdgpu_kernel void @private_system_one_as_acquire_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -14097,7 +14097,7 @@ define amdgpu_kernel void @private_system_one_as_acquire_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -14355,7 +14355,7 @@ define amdgpu_kernel void @private_system_one_as_release_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -14369,7 +14369,7 @@ define amdgpu_kernel void @private_system_one_as_release_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -14628,7 +14628,7 @@ define amdgpu_kernel void @private_system_one_as_acq_rel_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -14642,7 +14642,7 @@ define amdgpu_kernel void @private_system_one_as_acq_rel_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -14903,7 +14903,7 @@ define amdgpu_kernel void @private_system_one_as_seq_cst_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -14917,7 +14917,7 @@ define amdgpu_kernel void @private_system_one_as_seq_cst_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -15178,7 +15178,7 @@ define amdgpu_kernel void @private_system_one_as_monotonic_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -15192,7 +15192,7 @@ define amdgpu_kernel void @private_system_one_as_monotonic_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -15450,7 +15450,7 @@ define amdgpu_kernel void @private_system_one_as_acquire_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -15464,7 +15464,7 @@ define amdgpu_kernel void @private_system_one_as_acquire_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -15722,7 +15722,7 @@ define amdgpu_kernel void @private_system_one_as_release_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -15736,7 +15736,7 @@ define amdgpu_kernel void @private_system_one_as_release_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -15997,7 +15997,7 @@ define amdgpu_kernel void @private_system_one_as_acq_rel_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -16011,7 +16011,7 @@ define amdgpu_kernel void @private_system_one_as_acq_rel_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -16272,7 +16272,7 @@ define amdgpu_kernel void @private_system_one_as_seq_cst_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -16286,7 +16286,7 @@ define amdgpu_kernel void @private_system_one_as_seq_cst_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -16547,7 +16547,7 @@ define amdgpu_kernel void @private_system_one_as_monotonic_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -16561,7 +16561,7 @@ define amdgpu_kernel void @private_system_one_as_monotonic_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -16822,7 +16822,7 @@ define amdgpu_kernel void @private_system_one_as_acquire_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -16836,7 +16836,7 @@ define amdgpu_kernel void @private_system_one_as_acquire_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -17097,7 +17097,7 @@ define amdgpu_kernel void @private_system_one_as_release_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -17111,7 +17111,7 @@ define amdgpu_kernel void @private_system_one_as_release_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -17372,7 +17372,7 @@ define amdgpu_kernel void @private_system_one_as_acq_rel_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -17386,7 +17386,7 @@ define amdgpu_kernel void @private_system_one_as_acq_rel_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -17647,7 +17647,7 @@ define amdgpu_kernel void @private_system_one_as_seq_cst_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -17661,7 +17661,7 @@ define amdgpu_kernel void @private_system_one_as_seq_cst_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -17948,7 +17948,7 @@ define amdgpu_kernel void @private_system_one_as_monotonic_monotonic_ret_cmpxchg
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -17963,7 +17963,7 @@ define amdgpu_kernel void @private_system_one_as_monotonic_monotonic_ret_cmpxchg
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -18250,7 +18250,7 @@ define amdgpu_kernel void @private_system_one_as_acquire_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -18265,7 +18265,7 @@ define amdgpu_kernel void @private_system_one_as_acquire_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -18554,7 +18554,7 @@ define amdgpu_kernel void @private_system_one_as_release_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -18569,7 +18569,7 @@ define amdgpu_kernel void @private_system_one_as_release_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -18859,7 +18859,7 @@ define amdgpu_kernel void @private_system_one_as_acq_rel_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -18874,7 +18874,7 @@ define amdgpu_kernel void @private_system_one_as_acq_rel_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -19166,7 +19166,7 @@ define amdgpu_kernel void @private_system_one_as_seq_cst_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -19181,7 +19181,7 @@ define amdgpu_kernel void @private_system_one_as_seq_cst_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -19473,7 +19473,7 @@ define amdgpu_kernel void @private_system_one_as_monotonic_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -19488,7 +19488,7 @@ define amdgpu_kernel void @private_system_one_as_monotonic_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -19777,7 +19777,7 @@ define amdgpu_kernel void @private_system_one_as_acquire_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -19792,7 +19792,7 @@ define amdgpu_kernel void @private_system_one_as_acquire_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -20081,7 +20081,7 @@ define amdgpu_kernel void @private_system_one_as_release_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -20096,7 +20096,7 @@ define amdgpu_kernel void @private_system_one_as_release_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -20388,7 +20388,7 @@ define amdgpu_kernel void @private_system_one_as_acq_rel_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -20403,7 +20403,7 @@ define amdgpu_kernel void @private_system_one_as_acq_rel_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -20695,7 +20695,7 @@ define amdgpu_kernel void @private_system_one_as_seq_cst_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -20710,7 +20710,7 @@ define amdgpu_kernel void @private_system_one_as_seq_cst_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -21002,7 +21002,7 @@ define amdgpu_kernel void @private_system_one_as_monotonic_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -21017,7 +21017,7 @@ define amdgpu_kernel void @private_system_one_as_monotonic_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -21309,7 +21309,7 @@ define amdgpu_kernel void @private_system_one_as_acquire_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -21324,7 +21324,7 @@ define amdgpu_kernel void @private_system_one_as_acquire_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -21616,7 +21616,7 @@ define amdgpu_kernel void @private_system_one_as_release_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -21631,7 +21631,7 @@ define amdgpu_kernel void @private_system_one_as_release_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -21923,7 +21923,7 @@ define amdgpu_kernel void @private_system_one_as_acq_rel_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -21938,7 +21938,7 @@ define amdgpu_kernel void @private_system_one_as_acq_rel_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -22230,7 +22230,7 @@ define amdgpu_kernel void @private_system_one_as_seq_cst_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -22245,7 +22245,7 @@ define amdgpu_kernel void @private_system_one_as_seq_cst_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
index 83ccf4537459b..c7adf2aeaaaf5 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
@@ -322,7 +322,7 @@ define amdgpu_kernel void @private_volatile_load_1(
; GFX12-WGP-NEXT: s_mov_b32 s3, 0x3ff
; GFX12-WGP-NEXT: v_and_b32_e64 v1, v1, s3
; GFX12-WGP-NEXT: s_mov_b32 s3, 2
-; GFX12-WGP-NEXT: s_wait_alu 0xfffe
+; GFX12-WGP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-WGP-NEXT: v_lshlrev_b32_e64 v1, s3, v1
; GFX12-WGP-NEXT: s_wait_kmcnt 0x0
; GFX12-WGP-NEXT: scratch_load_b32 v1, v1, s2 scope:SCOPE_SYS
@@ -341,7 +341,7 @@ define amdgpu_kernel void @private_volatile_load_1(
; GFX12-CU-NEXT: s_mov_b32 s3, 0x3ff
; GFX12-CU-NEXT: v_and_b32_e64 v1, v1, s3
; GFX12-CU-NEXT: s_mov_b32 s3, 2
-; GFX12-CU-NEXT: s_wait_alu 0xfffe
+; GFX12-CU-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-CU-NEXT: v_lshlrev_b32_e64 v1, s3, v1
; GFX12-CU-NEXT: s_wait_kmcnt 0x0
; GFX12-CU-NEXT: scratch_load_b32 v1, v1, s2 scope:SCOPE_SYS
@@ -666,7 +666,7 @@ define amdgpu_kernel void @private_volatile_store_1(
; GFX12-WGP-NEXT: s_mov_b32 s2, 0x3ff
; GFX12-WGP-NEXT: v_and_b32_e64 v0, v0, s2
; GFX12-WGP-NEXT: s_mov_b32 s2, 2
-; GFX12-WGP-NEXT: s_wait_alu 0xfffe
+; GFX12-WGP-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-WGP-NEXT: v_lshlrev_b32_e64 v1, s2, v0
; GFX12-WGP-NEXT: s_wait_kmcnt 0x0
; GFX12-WGP-NEXT: v_mov_b32_e32 v0, s1
@@ -688,7 +688,7 @@ define amdgpu_kernel void @private_volatile_store_1(
; GFX12-CU-NEXT: s_mov_b32 s2, 0x3ff
; GFX12-CU-NEXT: v_and_b32_e64 v0, v0, s2
; GFX12-CU-NEXT: s_mov_b32 s2, 2
-; GFX12-CU-NEXT: s_wait_alu 0xfffe
+; GFX12-CU-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-CU-NEXT: v_lshlrev_b32_e64 v1, s2, v0
; GFX12-CU-NEXT: s_wait_kmcnt 0x0
; GFX12-CU-NEXT: v_mov_b32_e32 v0, s1
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
index a9c163a87df61..ffd097912c370 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
@@ -3341,7 +3341,7 @@ define amdgpu_kernel void @private_wavefront_monotonic_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -3355,7 +3355,7 @@ define amdgpu_kernel void @private_wavefront_monotonic_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -3611,7 +3611,7 @@ define amdgpu_kernel void @private_wavefront_acquire_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -3625,7 +3625,7 @@ define amdgpu_kernel void @private_wavefront_acquire_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -3881,7 +3881,7 @@ define amdgpu_kernel void @private_wavefront_release_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -3895,7 +3895,7 @@ define amdgpu_kernel void @private_wavefront_release_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -4151,7 +4151,7 @@ define amdgpu_kernel void @private_wavefront_acq_rel_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -4165,7 +4165,7 @@ define amdgpu_kernel void @private_wavefront_acq_rel_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -4421,7 +4421,7 @@ define amdgpu_kernel void @private_wavefront_seq_cst_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -4435,7 +4435,7 @@ define amdgpu_kernel void @private_wavefront_seq_cst_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -4691,7 +4691,7 @@ define amdgpu_kernel void @private_wavefront_monotonic_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -4705,7 +4705,7 @@ define amdgpu_kernel void @private_wavefront_monotonic_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -4961,7 +4961,7 @@ define amdgpu_kernel void @private_wavefront_acquire_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -4975,7 +4975,7 @@ define amdgpu_kernel void @private_wavefront_acquire_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -5231,7 +5231,7 @@ define amdgpu_kernel void @private_wavefront_release_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -5245,7 +5245,7 @@ define amdgpu_kernel void @private_wavefront_release_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -5501,7 +5501,7 @@ define amdgpu_kernel void @private_wavefront_acq_rel_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -5515,7 +5515,7 @@ define amdgpu_kernel void @private_wavefront_acq_rel_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -5771,7 +5771,7 @@ define amdgpu_kernel void @private_wavefront_seq_cst_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -5785,7 +5785,7 @@ define amdgpu_kernel void @private_wavefront_seq_cst_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -6041,7 +6041,7 @@ define amdgpu_kernel void @private_wavefront_monotonic_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -6055,7 +6055,7 @@ define amdgpu_kernel void @private_wavefront_monotonic_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -6311,7 +6311,7 @@ define amdgpu_kernel void @private_wavefront_acquire_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -6325,7 +6325,7 @@ define amdgpu_kernel void @private_wavefront_acquire_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -6581,7 +6581,7 @@ define amdgpu_kernel void @private_wavefront_release_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -6595,7 +6595,7 @@ define amdgpu_kernel void @private_wavefront_release_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -6851,7 +6851,7 @@ define amdgpu_kernel void @private_wavefront_acq_rel_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -6865,7 +6865,7 @@ define amdgpu_kernel void @private_wavefront_acq_rel_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -7121,7 +7121,7 @@ define amdgpu_kernel void @private_wavefront_seq_cst_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -7135,7 +7135,7 @@ define amdgpu_kernel void @private_wavefront_seq_cst_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -7417,7 +7417,7 @@ define amdgpu_kernel void @private_wavefront_monotonic_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -7432,7 +7432,7 @@ define amdgpu_kernel void @private_wavefront_monotonic_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -7719,7 +7719,7 @@ define amdgpu_kernel void @private_wavefront_acquire_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -7734,7 +7734,7 @@ define amdgpu_kernel void @private_wavefront_acquire_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -8021,7 +8021,7 @@ define amdgpu_kernel void @private_wavefront_release_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -8036,7 +8036,7 @@ define amdgpu_kernel void @private_wavefront_release_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -8323,7 +8323,7 @@ define amdgpu_kernel void @private_wavefront_acq_rel_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -8338,7 +8338,7 @@ define amdgpu_kernel void @private_wavefront_acq_rel_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -8625,7 +8625,7 @@ define amdgpu_kernel void @private_wavefront_seq_cst_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -8640,7 +8640,7 @@ define amdgpu_kernel void @private_wavefront_seq_cst_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -8927,7 +8927,7 @@ define amdgpu_kernel void @private_wavefront_monotonic_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -8942,7 +8942,7 @@ define amdgpu_kernel void @private_wavefront_monotonic_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -9229,7 +9229,7 @@ define amdgpu_kernel void @private_wavefront_acquire_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -9244,7 +9244,7 @@ define amdgpu_kernel void @private_wavefront_acquire_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -9531,7 +9531,7 @@ define amdgpu_kernel void @private_wavefront_release_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -9546,7 +9546,7 @@ define amdgpu_kernel void @private_wavefront_release_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -9833,7 +9833,7 @@ define amdgpu_kernel void @private_wavefront_acq_rel_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -9848,7 +9848,7 @@ define amdgpu_kernel void @private_wavefront_acq_rel_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -10135,7 +10135,7 @@ define amdgpu_kernel void @private_wavefront_seq_cst_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -10150,7 +10150,7 @@ define amdgpu_kernel void @private_wavefront_seq_cst_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -10437,7 +10437,7 @@ define amdgpu_kernel void @private_wavefront_monotonic_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -10452,7 +10452,7 @@ define amdgpu_kernel void @private_wavefront_monotonic_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -10739,7 +10739,7 @@ define amdgpu_kernel void @private_wavefront_acquire_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -10754,7 +10754,7 @@ define amdgpu_kernel void @private_wavefront_acquire_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -11041,7 +11041,7 @@ define amdgpu_kernel void @private_wavefront_release_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -11056,7 +11056,7 @@ define amdgpu_kernel void @private_wavefront_release_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -11343,7 +11343,7 @@ define amdgpu_kernel void @private_wavefront_acq_rel_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -11358,7 +11358,7 @@ define amdgpu_kernel void @private_wavefront_acq_rel_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -11645,7 +11645,7 @@ define amdgpu_kernel void @private_wavefront_seq_cst_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -11660,7 +11660,7 @@ define amdgpu_kernel void @private_wavefront_seq_cst_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -15040,7 +15040,7 @@ define amdgpu_kernel void @private_wavefront_one_as_monotonic_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -15054,7 +15054,7 @@ define amdgpu_kernel void @private_wavefront_one_as_monotonic_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -15310,7 +15310,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acquire_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -15324,7 +15324,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acquire_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -15580,7 +15580,7 @@ define amdgpu_kernel void @private_wavefront_one_as_release_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -15594,7 +15594,7 @@ define amdgpu_kernel void @private_wavefront_one_as_release_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -15850,7 +15850,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acq_rel_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -15864,7 +15864,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acq_rel_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -16120,7 +16120,7 @@ define amdgpu_kernel void @private_wavefront_one_as_seq_cst_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -16134,7 +16134,7 @@ define amdgpu_kernel void @private_wavefront_one_as_seq_cst_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -16390,7 +16390,7 @@ define amdgpu_kernel void @private_wavefront_one_as_monotonic_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -16404,7 +16404,7 @@ define amdgpu_kernel void @private_wavefront_one_as_monotonic_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -16660,7 +16660,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acquire_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -16674,7 +16674,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acquire_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -16930,7 +16930,7 @@ define amdgpu_kernel void @private_wavefront_one_as_release_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -16944,7 +16944,7 @@ define amdgpu_kernel void @private_wavefront_one_as_release_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -17200,7 +17200,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acq_rel_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -17214,7 +17214,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acq_rel_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -17470,7 +17470,7 @@ define amdgpu_kernel void @private_wavefront_one_as_seq_cst_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -17484,7 +17484,7 @@ define amdgpu_kernel void @private_wavefront_one_as_seq_cst_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -17740,7 +17740,7 @@ define amdgpu_kernel void @private_wavefront_one_as_monotonic_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -17754,7 +17754,7 @@ define amdgpu_kernel void @private_wavefront_one_as_monotonic_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -18010,7 +18010,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acquire_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -18024,7 +18024,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acquire_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -18280,7 +18280,7 @@ define amdgpu_kernel void @private_wavefront_one_as_release_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -18294,7 +18294,7 @@ define amdgpu_kernel void @private_wavefront_one_as_release_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -18550,7 +18550,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acq_rel_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -18564,7 +18564,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acq_rel_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -18820,7 +18820,7 @@ define amdgpu_kernel void @private_wavefront_one_as_seq_cst_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -18834,7 +18834,7 @@ define amdgpu_kernel void @private_wavefront_one_as_seq_cst_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -19116,7 +19116,7 @@ define amdgpu_kernel void @private_wavefront_one_as_monotonic_monotonic_ret_cmpx
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -19131,7 +19131,7 @@ define amdgpu_kernel void @private_wavefront_one_as_monotonic_monotonic_ret_cmpx
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -19418,7 +19418,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acquire_monotonic_ret_cmpxch
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -19433,7 +19433,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acquire_monotonic_ret_cmpxch
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -19720,7 +19720,7 @@ define amdgpu_kernel void @private_wavefront_one_as_release_monotonic_ret_cmpxch
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -19735,7 +19735,7 @@ define amdgpu_kernel void @private_wavefront_one_as_release_monotonic_ret_cmpxch
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -20022,7 +20022,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acq_rel_monotonic_ret_cmpxch
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -20037,7 +20037,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acq_rel_monotonic_ret_cmpxch
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -20324,7 +20324,7 @@ define amdgpu_kernel void @private_wavefront_one_as_seq_cst_monotonic_ret_cmpxch
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -20339,7 +20339,7 @@ define amdgpu_kernel void @private_wavefront_one_as_seq_cst_monotonic_ret_cmpxch
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -20626,7 +20626,7 @@ define amdgpu_kernel void @private_wavefront_one_as_monotonic_acquire_ret_cmpxch
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -20641,7 +20641,7 @@ define amdgpu_kernel void @private_wavefront_one_as_monotonic_acquire_ret_cmpxch
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -20928,7 +20928,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acquire_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -20943,7 +20943,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acquire_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -21230,7 +21230,7 @@ define amdgpu_kernel void @private_wavefront_one_as_release_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -21245,7 +21245,7 @@ define amdgpu_kernel void @private_wavefront_one_as_release_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -21532,7 +21532,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acq_rel_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -21547,7 +21547,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acq_rel_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -21834,7 +21834,7 @@ define amdgpu_kernel void @private_wavefront_one_as_seq_cst_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -21849,7 +21849,7 @@ define amdgpu_kernel void @private_wavefront_one_as_seq_cst_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -22136,7 +22136,7 @@ define amdgpu_kernel void @private_wavefront_one_as_monotonic_seq_cst_ret_cmpxch
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -22151,7 +22151,7 @@ define amdgpu_kernel void @private_wavefront_one_as_monotonic_seq_cst_ret_cmpxch
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -22438,7 +22438,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acquire_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -22453,7 +22453,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acquire_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -22740,7 +22740,7 @@ define amdgpu_kernel void @private_wavefront_one_as_release_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -22755,7 +22755,7 @@ define amdgpu_kernel void @private_wavefront_one_as_release_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -23042,7 +23042,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acq_rel_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -23057,7 +23057,7 @@ define amdgpu_kernel void @private_wavefront_one_as_acq_rel_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -23344,7 +23344,7 @@ define amdgpu_kernel void @private_wavefront_one_as_seq_cst_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -23359,7 +23359,7 @@ define amdgpu_kernel void @private_wavefront_one_as_seq_cst_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
index 7561a60518bf8..a1305dafc2825 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
@@ -3360,7 +3360,7 @@ define amdgpu_kernel void @private_workgroup_monotonic_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -3374,7 +3374,7 @@ define amdgpu_kernel void @private_workgroup_monotonic_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -3630,7 +3630,7 @@ define amdgpu_kernel void @private_workgroup_acquire_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -3644,7 +3644,7 @@ define amdgpu_kernel void @private_workgroup_acquire_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -3901,7 +3901,7 @@ define amdgpu_kernel void @private_workgroup_release_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -3915,7 +3915,7 @@ define amdgpu_kernel void @private_workgroup_release_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -4173,7 +4173,7 @@ define amdgpu_kernel void @private_workgroup_acq_rel_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -4187,7 +4187,7 @@ define amdgpu_kernel void @private_workgroup_acq_rel_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -4446,7 +4446,7 @@ define amdgpu_kernel void @private_workgroup_seq_cst_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -4460,7 +4460,7 @@ define amdgpu_kernel void @private_workgroup_seq_cst_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -4719,7 +4719,7 @@ define amdgpu_kernel void @private_workgroup_monotonic_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -4733,7 +4733,7 @@ define amdgpu_kernel void @private_workgroup_monotonic_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -4990,7 +4990,7 @@ define amdgpu_kernel void @private_workgroup_acquire_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -5004,7 +5004,7 @@ define amdgpu_kernel void @private_workgroup_acquire_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -5261,7 +5261,7 @@ define amdgpu_kernel void @private_workgroup_release_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -5275,7 +5275,7 @@ define amdgpu_kernel void @private_workgroup_release_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -5534,7 +5534,7 @@ define amdgpu_kernel void @private_workgroup_acq_rel_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -5548,7 +5548,7 @@ define amdgpu_kernel void @private_workgroup_acq_rel_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -5807,7 +5807,7 @@ define amdgpu_kernel void @private_workgroup_seq_cst_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -5821,7 +5821,7 @@ define amdgpu_kernel void @private_workgroup_seq_cst_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -6080,7 +6080,7 @@ define amdgpu_kernel void @private_workgroup_monotonic_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -6094,7 +6094,7 @@ define amdgpu_kernel void @private_workgroup_monotonic_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -6353,7 +6353,7 @@ define amdgpu_kernel void @private_workgroup_acquire_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -6367,7 +6367,7 @@ define amdgpu_kernel void @private_workgroup_acquire_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -6626,7 +6626,7 @@ define amdgpu_kernel void @private_workgroup_release_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -6640,7 +6640,7 @@ define amdgpu_kernel void @private_workgroup_release_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -6899,7 +6899,7 @@ define amdgpu_kernel void @private_workgroup_acq_rel_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -6913,7 +6913,7 @@ define amdgpu_kernel void @private_workgroup_acq_rel_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -7172,7 +7172,7 @@ define amdgpu_kernel void @private_workgroup_seq_cst_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -7186,7 +7186,7 @@ define amdgpu_kernel void @private_workgroup_seq_cst_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -7471,7 +7471,7 @@ define amdgpu_kernel void @private_workgroup_monotonic_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -7486,7 +7486,7 @@ define amdgpu_kernel void @private_workgroup_monotonic_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -7773,7 +7773,7 @@ define amdgpu_kernel void @private_workgroup_acquire_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -7788,7 +7788,7 @@ define amdgpu_kernel void @private_workgroup_acquire_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -8075,7 +8075,7 @@ define amdgpu_kernel void @private_workgroup_release_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -8090,7 +8090,7 @@ define amdgpu_kernel void @private_workgroup_release_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -8379,7 +8379,7 @@ define amdgpu_kernel void @private_workgroup_acq_rel_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -8394,7 +8394,7 @@ define amdgpu_kernel void @private_workgroup_acq_rel_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -8683,7 +8683,7 @@ define amdgpu_kernel void @private_workgroup_seq_cst_monotonic_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -8698,7 +8698,7 @@ define amdgpu_kernel void @private_workgroup_seq_cst_monotonic_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -8987,7 +8987,7 @@ define amdgpu_kernel void @private_workgroup_monotonic_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -9002,7 +9002,7 @@ define amdgpu_kernel void @private_workgroup_monotonic_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -9289,7 +9289,7 @@ define amdgpu_kernel void @private_workgroup_acquire_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -9304,7 +9304,7 @@ define amdgpu_kernel void @private_workgroup_acquire_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -9591,7 +9591,7 @@ define amdgpu_kernel void @private_workgroup_release_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -9606,7 +9606,7 @@ define amdgpu_kernel void @private_workgroup_release_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -9895,7 +9895,7 @@ define amdgpu_kernel void @private_workgroup_acq_rel_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -9910,7 +9910,7 @@ define amdgpu_kernel void @private_workgroup_acq_rel_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -10199,7 +10199,7 @@ define amdgpu_kernel void @private_workgroup_seq_cst_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -10214,7 +10214,7 @@ define amdgpu_kernel void @private_workgroup_seq_cst_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -10503,7 +10503,7 @@ define amdgpu_kernel void @private_workgroup_monotonic_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -10518,7 +10518,7 @@ define amdgpu_kernel void @private_workgroup_monotonic_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -10807,7 +10807,7 @@ define amdgpu_kernel void @private_workgroup_acquire_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -10822,7 +10822,7 @@ define amdgpu_kernel void @private_workgroup_acquire_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -11111,7 +11111,7 @@ define amdgpu_kernel void @private_workgroup_release_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -11126,7 +11126,7 @@ define amdgpu_kernel void @private_workgroup_release_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -11415,7 +11415,7 @@ define amdgpu_kernel void @private_workgroup_acq_rel_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -11430,7 +11430,7 @@ define amdgpu_kernel void @private_workgroup_acq_rel_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -11719,7 +11719,7 @@ define amdgpu_kernel void @private_workgroup_seq_cst_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -11734,7 +11734,7 @@ define amdgpu_kernel void @private_workgroup_seq_cst_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -15135,7 +15135,7 @@ define amdgpu_kernel void @private_workgroup_one_as_monotonic_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -15149,7 +15149,7 @@ define amdgpu_kernel void @private_workgroup_one_as_monotonic_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -15405,7 +15405,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acquire_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -15419,7 +15419,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acquire_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -15676,7 +15676,7 @@ define amdgpu_kernel void @private_workgroup_one_as_release_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -15690,7 +15690,7 @@ define amdgpu_kernel void @private_workgroup_one_as_release_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -15948,7 +15948,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acq_rel_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -15962,7 +15962,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acq_rel_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -16221,7 +16221,7 @@ define amdgpu_kernel void @private_workgroup_one_as_seq_cst_monotonic_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -16235,7 +16235,7 @@ define amdgpu_kernel void @private_workgroup_one_as_seq_cst_monotonic_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -16494,7 +16494,7 @@ define amdgpu_kernel void @private_workgroup_one_as_monotonic_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -16508,7 +16508,7 @@ define amdgpu_kernel void @private_workgroup_one_as_monotonic_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -16765,7 +16765,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acquire_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -16779,7 +16779,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acquire_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -17036,7 +17036,7 @@ define amdgpu_kernel void @private_workgroup_one_as_release_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -17050,7 +17050,7 @@ define amdgpu_kernel void @private_workgroup_one_as_release_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -17309,7 +17309,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acq_rel_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -17323,7 +17323,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acq_rel_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -17582,7 +17582,7 @@ define amdgpu_kernel void @private_workgroup_one_as_seq_cst_acquire_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -17596,7 +17596,7 @@ define amdgpu_kernel void @private_workgroup_one_as_seq_cst_acquire_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -17855,7 +17855,7 @@ define amdgpu_kernel void @private_workgroup_one_as_monotonic_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -17869,7 +17869,7 @@ define amdgpu_kernel void @private_workgroup_one_as_monotonic_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -18128,7 +18128,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acquire_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -18142,7 +18142,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acquire_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -18401,7 +18401,7 @@ define amdgpu_kernel void @private_workgroup_one_as_release_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -18415,7 +18415,7 @@ define amdgpu_kernel void @private_workgroup_one_as_release_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -18674,7 +18674,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acq_rel_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -18688,7 +18688,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acq_rel_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -18947,7 +18947,7 @@ define amdgpu_kernel void @private_workgroup_one_as_seq_cst_seq_cst_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-WGP-NEXT: s_endpgm
@@ -18961,7 +18961,7 @@ define amdgpu_kernel void @private_workgroup_one_as_seq_cst_seq_cst_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v0, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0 offset:16
; GFX12-CU-NEXT: s_endpgm
@@ -19246,7 +19246,7 @@ define amdgpu_kernel void @private_workgroup_one_as_monotonic_monotonic_ret_cmpx
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -19261,7 +19261,7 @@ define amdgpu_kernel void @private_workgroup_one_as_monotonic_monotonic_ret_cmpx
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -19548,7 +19548,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acquire_monotonic_ret_cmpxch
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -19563,7 +19563,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acquire_monotonic_ret_cmpxch
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -19850,7 +19850,7 @@ define amdgpu_kernel void @private_workgroup_one_as_release_monotonic_ret_cmpxch
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -19865,7 +19865,7 @@ define amdgpu_kernel void @private_workgroup_one_as_release_monotonic_ret_cmpxch
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -20154,7 +20154,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acq_rel_monotonic_ret_cmpxch
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -20169,7 +20169,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acq_rel_monotonic_ret_cmpxch
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -20458,7 +20458,7 @@ define amdgpu_kernel void @private_workgroup_one_as_seq_cst_monotonic_ret_cmpxch
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -20473,7 +20473,7 @@ define amdgpu_kernel void @private_workgroup_one_as_seq_cst_monotonic_ret_cmpxch
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -20762,7 +20762,7 @@ define amdgpu_kernel void @private_workgroup_one_as_monotonic_acquire_ret_cmpxch
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -20777,7 +20777,7 @@ define amdgpu_kernel void @private_workgroup_one_as_monotonic_acquire_ret_cmpxch
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -21064,7 +21064,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acquire_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -21079,7 +21079,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acquire_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -21366,7 +21366,7 @@ define amdgpu_kernel void @private_workgroup_one_as_release_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -21381,7 +21381,7 @@ define amdgpu_kernel void @private_workgroup_one_as_release_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -21670,7 +21670,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acq_rel_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -21685,7 +21685,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acq_rel_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -21974,7 +21974,7 @@ define amdgpu_kernel void @private_workgroup_one_as_seq_cst_acquire_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -21989,7 +21989,7 @@ define amdgpu_kernel void @private_workgroup_one_as_seq_cst_acquire_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -22278,7 +22278,7 @@ define amdgpu_kernel void @private_workgroup_one_as_monotonic_seq_cst_ret_cmpxch
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -22293,7 +22293,7 @@ define amdgpu_kernel void @private_workgroup_one_as_monotonic_seq_cst_ret_cmpxch
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -22582,7 +22582,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acquire_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -22597,7 +22597,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acquire_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -22886,7 +22886,7 @@ define amdgpu_kernel void @private_workgroup_one_as_release_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -22901,7 +22901,7 @@ define amdgpu_kernel void @private_workgroup_one_as_release_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -23190,7 +23190,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acq_rel_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -23205,7 +23205,7 @@ define amdgpu_kernel void @private_workgroup_one_as_acq_rel_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
@@ -23494,7 +23494,7 @@ define amdgpu_kernel void @private_workgroup_one_as_seq_cst_seq_cst_ret_cmpxchg(
; GFX12-WGP-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-WGP-NEXT: s_wait_loadcnt 0x0
; GFX12-WGP-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-WGP-NEXT: s_wait_alu 0xf1ff
+; GFX12-WGP-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-WGP-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-WGP-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-WGP-NEXT: scratch_store_b32 off, v0, s0
@@ -23509,7 +23509,7 @@ define amdgpu_kernel void @private_workgroup_one_as_seq_cst_seq_cst_ret_cmpxchg(
; GFX12-CU-NEXT: scratch_load_b32 v0, off, s0 offset:16
; GFX12-CU-NEXT: s_wait_loadcnt 0x0
; GFX12-CU-NEXT: v_cmp_eq_u32_e64 s2, v0, s2
-; GFX12-CU-NEXT: s_wait_alu 0xf1ff
+; GFX12-CU-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-CU-NEXT: v_cndmask_b32_e64 v1, v0, s1, s2
; GFX12-CU-NEXT: scratch_store_b32 off, v1, s0 offset:16
; GFX12-CU-NEXT: scratch_store_b32 off, v0, s0
diff --git a/llvm/test/CodeGen/AMDGPU/merge-consecutive-wait-alus.mir b/llvm/test/CodeGen/AMDGPU/merge-consecutive-wait-alus.mir
index d8f4c9c8f14b5..10b64b03efe81 100644
--- a/llvm/test/CodeGen/AMDGPU/merge-consecutive-wait-alus.mir
+++ b/llvm/test/CodeGen/AMDGPU/merge-consecutive-wait-alus.mir
@@ -12,7 +12,7 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $sgpr0 = V_CMP_NE_U32_e64 0, $vgpr0, implicit $exec, implicit-def $vcc_lo, implicit-def $vcc_lo
- ; CHECK-NEXT: S_WAITCNT_DEPCTR 61946
+ ; CHECK-NEXT: S_WAITCNT_DEPCTR 61850
; CHECK-NEXT: renamable $vgpr0 = V_CNDMASK_B32_e64 0, -1, 0, killed $vgpr0, killed $sgpr0, implicit $exec, implicit-def $vcc_lo
renamable $sgpr0 = V_CMP_NE_U32_e64 0, $vgpr0, implicit $exec, implicit-def $vcc_lo, implicit-def $vcc
S_WAITCNT_DEPCTR 65530
@@ -32,7 +32,7 @@ body: |
; CHECK-NEXT: bb.1:
; CHECK-NEXT: liveins: $sgpr0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: S_WAITCNT_DEPCTR 61951
+ ; CHECK-NEXT: S_WAITCNT_DEPCTR 61855
; CHECK-NEXT: renamable $vgpr0 = V_CNDMASK_B32_e64 0, -1, 0, killed $vgpr0, killed $sgpr0, implicit $exec, implicit-def $vcc_lo
bb.0:
liveins: $vgpr0
@@ -54,7 +54,7 @@ body: |
; CHECK: renamable $sgpr0 = V_CMP_NE_U32_e64 0, $vgpr0, implicit $exec, implicit-def $vcc_lo, implicit-def $vcc_lo
; CHECK-NEXT: S_WAITCNT_DEPCTR 65530
; CHECK-NEXT: SCHED_BARRIER 0
- ; CHECK-NEXT: S_WAITCNT_DEPCTR 61951
+ ; CHECK-NEXT: S_WAITCNT_DEPCTR 61855
; CHECK-NEXT: renamable $vgpr0 = V_CNDMASK_B32_e64 0, -1, 0, killed $vgpr0, killed $sgpr0, implicit $exec, implicit-def $vcc_lo
renamable $sgpr0 = V_CMP_NE_U32_e64 0, $vgpr0, implicit $exec, implicit-def $vcc_lo, implicit-def $vcc
S_WAITCNT_DEPCTR 65530
@@ -68,7 +68,7 @@ body: |
bb.0:
; CHECK-LABEL: name: debug_instruction
; CHECK: renamable $sgpr0 = V_CMP_NE_U32_e64 0, $vgpr0, implicit $exec, implicit-def $vcc_lo, implicit-def $vcc_lo
- ; CHECK-NEXT: S_WAITCNT_DEPCTR 61946
+ ; CHECK-NEXT: S_WAITCNT_DEPCTR 61850
; CHECK-NEXT: DBG_VALUE $sgpr0
; CHECK-NEXT: renamable $vgpr0 = V_CNDMASK_B32_e64 0, -1, 0, killed $vgpr0, killed $sgpr0, implicit $exec, implicit-def $vcc_lo
renamable $sgpr0 = V_CMP_NE_U32_e64 0, $vgpr0, implicit $exec, implicit-def $vcc_lo, implicit-def $vcc
diff --git a/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll b/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
index 416a601797617..77c45d20296b4 100644
--- a/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
@@ -185,26 +185,26 @@ define bfloat @v_minimumnum_bf16(bfloat %x, bfloat %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v0.l, v0.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v0.h, v1.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v1, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v1.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v1.h, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -218,29 +218,29 @@ define bfloat @v_minimumnum_bf16(bfloat %x, bfloat %y) {
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call bfloat @llvm.minimumnum.bf16(bfloat %x, bfloat %y)
@@ -382,16 +382,16 @@ define bfloat @v_minimumnum_bf16_nnan(bfloat %x, bfloat %y) {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v3, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.l, v0.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v0.l, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -407,17 +407,17 @@ define bfloat @v_minimumnum_bf16_nnan(bfloat %x, bfloat %y) {
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_lshlrev_b32 v3, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -734,44 +734,44 @@ define <2 x bfloat> @v_minimumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v4.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v0.h, v1.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.h, v4.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.h, v4.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v4.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v4.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.h, v2.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v0.l, v1.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v1.l, v3.h, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v3.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v3.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.l, v3.h, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v2.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.h, v0.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, s1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v0.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -788,50 +788,50 @@ define <2 x bfloat> @v_minimumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v3 :: v_dual_lshlrev_b32 v5, 16, v0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v0 :: v_dual_lshlrev_b32 v4, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v3, v2 :: v_dual_lshlrev_b32 v7, 16, v1
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_lshlrev_b32 v7, 16, v5
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
@@ -1069,28 +1069,28 @@ define <2 x bfloat> @v_minimumnum_v2bf16_nnan(<2 x bfloat> %x, <2 x bfloat> %y)
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v3, v2
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v1.l, v0.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v3.h, v0.l, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.h, v0.l, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v1.h, v0.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v0.h, s1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v1.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v0.h, vcc_lo
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1109,31 +1109,31 @@ define <2 x bfloat> @v_minimumnum_v2bf16_nnan(<2 x bfloat> %x, <2 x bfloat> %y)
; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v7, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v3, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
@@ -1566,25 +1566,25 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v0.h, v2.h, vcc_lo
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v2.h, v6.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.h
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.h, v6.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v6.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v6.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v4.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v1.l, v3.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
@@ -1592,13 +1592,13 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v5.h
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v6.h, v5.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v5.h, s1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v3, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v0.h, v6.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v1.l
@@ -1608,26 +1608,26 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v6
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v2.l, v0.h, s2
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v0.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v2.h, s0
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v0, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.h, v0.h, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v6.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, s2
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v4.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v6.h, s1
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v0.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v4.h, s2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v0.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1645,71 +1645,71 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v4 :: v_dual_lshlrev_b32 v6, 16, v1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v9, 16, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v10, 16, v6
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v7, 16, v0
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v7, v8
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v6, v1 :: v_dual_lshlrev_b32 v2, 16, v6
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v4, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x bfloat> @llvm.minimumnum.v3bf16(<3 x bfloat> %x, <3 x bfloat> %y)
@@ -2022,42 +2022,42 @@ define <3 x bfloat> @v_minimumnum_v3bf16_nnan(<3 x bfloat> %x, <3 x bfloat> %y)
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v4
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, 0
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v3.l, v1.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v4.h, v1.l, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v5
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v2
; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v4.h, v1.l, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v2.l, v0.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.h, v0.l, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v4
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.h, v2.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v0.l, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v2.h, v0.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v0.h, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v0.h, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2077,46 +2077,46 @@ define <3 x bfloat> @v_minimumnum_v3bf16_nnan(<3 x bfloat> %x, <3 x bfloat> %y)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v7, v6
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
; GFX12-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v11, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v5, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v6
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v5, v7 :: v_dual_lshlrev_b32 v9, 16, v4
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -2676,45 +2676,45 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v6.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v1.h, v3.h, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v3.h, v6.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v5.h, v6.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v6.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.l, v6.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v4.l
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v8, v8
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v0.h, v2.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v2.h, v6.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v7
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v7.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v7.h, v6.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v6.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v6.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v5.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v1.l, v3.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
@@ -2722,14 +2722,14 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v8.h
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v8, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v6.h, v8.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v8.h, s2
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v3, v3
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.h, v7.h, s4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v0.h, v6.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v1.l
@@ -2739,17 +2739,17 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v2.l, v0.h, s3
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v0.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v2.h, s0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v0, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.h, v0.h, s2
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v6.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, s3
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v5.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v6.h, s2
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v0.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -2757,9 +2757,9 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v0.h, s1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v3.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2776,96 +2776,96 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v11
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v5, v4 :: v_dual_and_b32 v9, 0xffff0000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v13, 16, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v6 :: v_dual_lshlrev_b32 v14, 16, v0
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v9, 16, v7
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v5, 16, v6
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v8
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v3, 16, v7
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v6 :: v_dual_lshlrev_b32 v2, 16, v8
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x5040100
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -3268,56 +3268,56 @@ define <4 x bfloat> @v_minimumnum_v4bf16_nnan(<4 x bfloat> %x, <4 x bfloat> %y)
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v1.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v4
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, 0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v3.l, v1.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v5.h, v1.l, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v4.l, v3.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v7, v6
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.h, v1.l, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v3.h, v1.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.h, v1.h, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v5
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v3.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v4
; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.h, v1.h, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v2.l, v0.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v5.h, v0.l, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v5
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.h, v0.l, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v2.h, v0.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.h, v0.h, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.h, v0.h, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3336,62 +3336,62 @@ define <4 x bfloat> @v_minimumnum_v4bf16_nnan(<4 x bfloat> %x, <4 x bfloat> %y)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v4
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v3 :: v_dual_lshlrev_b32 v10, 16, v0
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v7, v6
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v1 :: v_dual_and_b32 v12, 0xffff0000, v0
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v9
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v6, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v12, v11
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v4, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v7
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v4 :: v_dual_lshlrev_b32 v4, 16, v6
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v9, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
@@ -4203,10 +4203,10 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v9.l
; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
; GFX12-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v2.h, v5.h, vcc_lo
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v5.h, v9.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v9.h
@@ -4215,52 +4215,52 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v8
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v13, v13
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v8.h, v9.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v6.l, v9.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.h, v6.l
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v9.l
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v1.h, v4.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.h, v4.h, v9.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v9.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v10
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v10.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v10.h, v9.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.l, v9.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.h, v7.l
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v9
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v0.h, v3.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v3.h, v9.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v9.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v11
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v11.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v11.h, v9.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v9.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v8.l, v9.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.h, v8.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v2.l, v5.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
@@ -4268,7 +4268,7 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v12.h
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v12, v9
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v9.h, v12.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v9.h
@@ -4276,7 +4276,7 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v5, v5
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v1.h, v9.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.h, v2.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.l, v4.l, s3
@@ -4287,17 +4287,17 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v4.l, v1.h, s4
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v1.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v2.h, v11.h, s7
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v4.h, s0
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v1, v9
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v9.h, v1.h, s3
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v9.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v1.h, s4
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v5, v5
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v7.h, v10.h, s6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v0.h, v9.h, s3
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.h, v1.l
@@ -4308,17 +4308,17 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v3.l, v0.h, s5
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v0.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.h, s3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s4, v0, v9
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v9.h, v0.h, s4
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v9.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, s5
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v8.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v0.h, v9.h, s4
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.h, v0.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -4326,9 +4326,9 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v9
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v6.l, v0.h, s1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s4
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4347,139 +4347,139 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX12-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v5
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX12-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX12-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v10, v9 :: v_dual_lshlrev_b32 v13, 16, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v6
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v12, v13
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v7, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v15, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v15, v12 :: v_dual_lshlrev_b32 v14, 16, v9
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v14
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v12
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v9, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v6, v10, v6 :: v_dual_lshlrev_b32 v13, 16, v11
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v11, v8 :: v_dual_lshlrev_b32 v15, 16, v7
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v14, v15
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v7, v12, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v10, v12, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v2 :: v_dual_lshlrev_b32 v10, 16, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v3 :: v_dual_lshlrev_b32 v11, 16, v2
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v0 :: v_dual_lshlrev_b32 v12, 16, v1
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v5, v2 :: v_dual_lshlrev_b32 v10, 16, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v12, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v4, v1 :: v_dual_lshlrev_b32 v11, 16, v3
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v9, v2 :: v_dual_lshlrev_b32 v13, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v13, v11
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v3, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_lshlrev_b32 v4, 16, v10
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v3 :: v_dual_lshlrev_b32 v3, 16, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v11
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v7, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v1, v8, v1, 0x5040100
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -5536,12 +5536,12 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v12.l
; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v2
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v12.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v3.h, v7.h, vcc_lo
; GFX12-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v4
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v7
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v7.h, v12.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v12.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
@@ -5550,68 +5550,68 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v12, v11
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v17, v17
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v11.h, v12.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v8.l, v12.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.h, v8.l
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v12
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v2.h, v6.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v6.h, v12.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v12.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v12, v13
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v13.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v13.h, v12.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v9.l, v12.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.h, v9.l
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v14, v14
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v12.l
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v12
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v1.h, v5.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v5.h, v12.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v12.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v12, v14
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v14.h, v12.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v12.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.h, v10.l, v12.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v16, v16
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v3
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v12
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v0.h, v4.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v4.h, v12.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v12.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v12, v15
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v15.h, v12.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v12.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v11.l, v12.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.h, v11.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v3.l, v7.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v12
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
@@ -5619,7 +5619,7 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v16.h
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v16, v12
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v12.h, v16.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v12.h
@@ -5627,7 +5627,7 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v7, v7
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v2.h, v12.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.h, v3.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v2.l, v6.l, s4
@@ -5639,10 +5639,10 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v2.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v16, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v6.h, s0
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s4, v2, v12
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v12.h, v2.h, s4
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v12.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -5650,7 +5650,7 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v7, v7
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v9.h, v13.h, s8
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v1.h, v12.h, s4
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.h, v2.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.l, v5.l, s5
@@ -5660,17 +5660,17 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v12
; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v5.l, v1.h, s6
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v1.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.h, s4
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s5, v1, v12
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v12.h, v1.h, s5
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v12.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v1.h, s6
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v7, v7
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v0.h, v12.h, s5
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.h, v1.l
@@ -5680,33 +5680,33 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v12
; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v4.l, v0.h, s7
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v0.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.h, s5
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s6, v0, v12
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0x8000, v12.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v12.h, v0.h, s6
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v11.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, s7
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v8.h, v11.h, s6
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v14.h
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v15.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.h, v12.h, s9
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.h, v0.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v10.h, v14.h, s6
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v15.h, s7
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v8.l, v1.h, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v12
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v10.l, v0.h, s3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v11.l, v5.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s1
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -5725,189 +5725,189 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX12-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v7
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v8 :: v_dual_and_b32 v10, 0xffff0000, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v8
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v12, v11, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v13, v14
; GFX12-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v6
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v9, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v12, v8 :: v_dual_and_b32 v13, 0xffff0000, v1
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v9 :: v_dual_lshlrev_b32 v15, 16, v11
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v14, v15
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v14, v11, v10 :: v_dual_and_b32 v15, 0xffff0000, v5
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v16, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v14, v10 :: v_dual_lshlrev_b32 v13, 16, v12
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v16, v9, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
; GFX12-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v0
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v12, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v15
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v11 :: v_dual_lshlrev_b32 v11, 16, v9
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v12
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v11, v15, v9 :: v_dual_lshlrev_b32 v18, 16, v14
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v12, v17, v16 :: v_dual_lshlrev_b32 v17, 16, v7
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v14, v10 :: v_dual_and_b32 v13, 0xffff0000, v4
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v11, v9 :: v_dual_lshlrev_b32 v14, 16, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v16, v12, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v15
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v15 :: v_dual_lshlrev_b32 v16, 16, v13
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v12
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v16
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v11
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v15, v13, v12 :: v_dual_lshlrev_b32 v16, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v11, v9 :: v_dual_lshlrev_b32 v14, 16, v3
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v11, v15, v12 :: v_dual_lshlrev_b32 v12, 16, v7
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v14, v12
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v7, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v6 :: v_dual_lshlrev_b32 v13, 16, v15
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v12, v3 :: v_dual_lshlrev_b32 v16, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v15, v11, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v6, v6, v2 :: v_dual_lshlrev_b32 v15, 16, v0
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v7 :: v_dual_lshlrev_b32 v14, 16, v6
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v16, v14
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v14, v6, v2 :: v_dual_lshlrev_b32 v7, 16, v12
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v0 :: v_dual_lshlrev_b32 v13, 16, v5
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v14, v2 :: v_dual_lshlrev_b32 v15, 16, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v13
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v14
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v5, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v17, v16
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v4, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v4 :: v_dual_lshlrev_b32 v5, 16, v6
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v14, v2, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v10, v2, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v13
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v11, v0, 0x5040100
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v1, v9, v1, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v3, v8, v3, 0x5040100
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -7963,14 +7963,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v12
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v20, v20
; GFX12-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v7.h, v15.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v16.l
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v21, v21
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v16.l
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v16.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.h, v15.h, v16.h, vcc_lo
; GFX12-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v4
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v22, v22
@@ -7981,13 +7981,13 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v16.l
; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v10
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v16.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.h, v16.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v23, v23
; GFX12-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v2
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v24, v24
; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v17.l, v16.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v17.l
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v18, v18
@@ -7995,7 +7995,7 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v9
; GFX12-TRUE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v0
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v6.h, v14.h, s0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v8
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v29, v29
@@ -8008,7 +8008,7 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v32, v32
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v16, v18
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v14
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.h, v16.h, s0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v32, v32
@@ -8021,7 +8021,7 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v12
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v5.h, v13.h, s1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v32, v32
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v11
@@ -8034,7 +8034,7 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v16, v25
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s17, 0x8000, v25.h
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v32, v32
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v25.h, v16.h, s1
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v9
@@ -8045,13 +8045,13 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v32, v32
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v32.l, v16.l
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v4.h, v12.h, s2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.h, v12.h, v16.h, s3
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v16.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v16, v26
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v26.h, v16.h, s2
; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.h, v21.l, v16.h, s3
@@ -8059,13 +8059,13 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v22, v22
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v3.h, v11.h, s3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.h, v11.h, v16.h, s4
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v16.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v16, v27
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v27.h, v16.h, s3
; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.h, v22.l, v16.h, s4
@@ -8073,13 +8073,13 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v23, v23
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v2.h, v10.h, s4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.h, v10.h, v16.h, s5
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v16.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s4, v16, v28
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v28.h, v16.h, s4
; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.h, v23.l, v16.h, s5
@@ -8087,13 +8087,13 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v24, v24
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v1.h, v9.h, s5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.h, v9.h, v16.h, s6
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v16.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s5, v16, v29
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v29.h, v16.h, s5
; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.h, v24.l, v16.h, s6
@@ -8102,20 +8102,20 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v30.l, v16.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v0.h, v8.h, s6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.h, v8.h, v16.h, s7
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v16.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s6, v16, v30
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v30.h, v16.h, s6
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v31, v31
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v6
; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.l, v15.h, v16.h, s7
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v15.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.l, v15.l, s6
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v16.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
@@ -8124,14 +8124,14 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v7.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s7, v7, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v16.h, v7.h, s7
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v16.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v7.l, v7.h, s8
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v31, v31
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v6.h, v16.h, s7
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v7.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v6.l, v14.l, s8
@@ -8140,18 +8140,18 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s7, 0, v16
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v14.l, v6.h, s9
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0x8000, v6.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v14.h, s7
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s8, v6, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v16.h, v6.h, s8
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v16.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v6.l, v6.h, s9
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v31, v31
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v5.h, v16.h, s8
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v6.l
@@ -8161,18 +8161,18 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v13.l, v5.h, s10
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0x8000, v5.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v13.h, s8
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s9, v5, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v16.h, v5.h, s9
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0x8000, v16.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v5.l, v5.h, s10
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v31, v31
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v4.h, v16.h, s9
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v5.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.l, v12.l, s10
@@ -8181,18 +8181,18 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s9, 0, v16
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v12.l, v4.h, s11
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0x8000, v4.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v12.h, s9
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s10, v4, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v16.h, v4.h, s10
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0x8000, v16.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v4.l, v4.h, s11
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v31, v31
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v3.h, v16.h, s10
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v4.l
@@ -8202,18 +8202,18 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v11.l, v3.h, s12
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0x8000, v3.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v11.h, s10
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s11, v3, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v16.h, v3.h, s11
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0x8000, v16.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.l, v3.h, s12
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v31, v31
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.h, v2.h, v16.h, s11
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v3.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v2.l, v10.l, s12
@@ -8222,18 +8222,18 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s11, 0, v16
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v10.l, v2.h, s13
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0x8000, v2.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v10.h, s11
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s12, v2, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v16.h, v2.h, s12
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0x8000, v16.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v2.l, v2.h, s13
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v31, v31
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v1.h, v16.h, s12
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v2.l
@@ -8245,62 +8245,62 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v31, v31
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0x8000, v1.h
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v8
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v9.h, s12
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s13, v1, v16
; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.h, v0.l, v8.l, s14
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0x8000, v16.h
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v31, v31
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v16.h, v1.h, s13
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0x8000, v17.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v1.h, s15
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v19.l, v17.h, s13
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0x8000, v18.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v20.h, v25.h, s17
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0x8000, v32.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v16.h, s16
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v1.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v17.l, v0.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v19.h, v18.h, s13
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v26.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v20.l, v1.h, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s13, 0, v16
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v8.l, v32.h, s14
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v18.l, v0.h, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v21.h, v26.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v28.h
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v27.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v32, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s13
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v21.l, v0.h, s2
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v29.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v23.h, v28.h, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v16.h, v32.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v16.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v22.h, v27.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v24.h, v29.h, s2
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v30.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v8.l, v32.h, s15
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v23.l, v1.h, s4
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v22.l, v0.h, s3
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v24.l, v8.h, s5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v25.l, v30.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v9.l, v16.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v8.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v15.h, v0.h, s6
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v16
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v8.h, vcc_lo
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -8322,390 +8322,390 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v4
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v1
; GFX12-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v17, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
; GFX12-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v13
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v16
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v16, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v17
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v18, v19
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v17, v16, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v20, v22, v21 :: v_dual_and_b32 v19, 0xffff0000, v14
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v16
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v21, v20, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v17
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v20
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v19
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v17 :: v_dual_lshlrev_b32 v17, 16, v18
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v21, v22
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v13
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v17, v19, v20 :: v_dual_and_b32 v18, 0xffff0000, v5
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v20
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v17, v20, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v22, v21, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
; GFX12-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v4
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v18
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v18, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX12-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v12
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v22, v25, v24 :: v_dual_lshlrev_b32 v25, 16, v21
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v19
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v24, v22, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v23, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v17
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v22
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v23, v21, v18 :: v_dual_lshlrev_b32 v26, 16, v20
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v18
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v23, v18, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v26
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v21
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v18, v18, v21 :: v_dual_lshlrev_b32 v27, 16, v19
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v22
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v19, v22, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v23, v18, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v20
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v20, v22, v20 :: v_dual_and_b32 v23, 0xffff0000, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v21, v26, v25 :: v_dual_and_b32 v22, 0xffff0000, v11
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v25, v21, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
; GFX12-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v24, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v20, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v24, v24, v23 :: v_dual_and_b32 v25, 0xffff0000, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v24
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v20, v26
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v22, v21, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v28, v27, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v23
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v21
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v20, v21, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v29
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v26, v24, v23 :: v_dual_lshlrev_b32 v29, 16, v20
; GFX12-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v9
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v27, v27, v25, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v22
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v21, v21, v22 :: v_dual_lshlrev_b32 v28, 16, v27
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v23
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v22, v26, v23 :: v_dual_lshlrev_b32 v23, 16, v25
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v24
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v24, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v23, v28
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v23, v27, v25 :: v_dual_lshlrev_b32 v24, 16, v26
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v29
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v21, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v21, v26, v22 :: v_dual_and_b32 v24, 0xffff0000, v0
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v25
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v23, v25, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v27
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v27, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v7
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v26, v25, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v23
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v15 :: v_dual_and_b32 v26, 0xffff0000, v8
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v15
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v25, v24, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v15, v15, v7 :: v_dual_lshlrev_b32 v26, 16, v24
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v22, v23, v22 :: v_dual_lshlrev_b32 v27, 16, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v6
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v15
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v27
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v26, v25, v24 :: v_dual_lshlrev_b32 v23, 16, v14
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v29, v28
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v27, v15, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v24
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v24, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v27, v7 :: v_dual_lshlrev_b32 v24, 16, v14
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v25
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v23, v25, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v15
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v26
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v15 :: v_dual_lshlrev_b32 v28, 16, v6
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v28, v24
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v15, v14, v6 :: v_dual_lshlrev_b32 v24, 16, v27
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v23, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v27, v7 :: v_dual_lshlrev_b32 v24, 16, v5
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v14
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_perm_b32 v7, v16, v7, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v13 :: v_dual_lshlrev_b32 v24, 16, v4
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_perm_b32 v6, v17, v6, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v13, v13, v5 :: v_dual_lshlrev_b32 v14, 16, v12
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v24
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v15, v13, v5 :: v_dual_lshlrev_b32 v24, 16, v12
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v11
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v4
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v24
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v11
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v12, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v14, v4 :: v_dual_lshlrev_b32 v13, 16, v15
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v24
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v11, v3, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v18, v5, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v11 :: v_dual_lshlrev_b32 v12, 16, v2
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v10
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v10 :: v_dual_lshlrev_b32 v15, 16, v24
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v15
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0
; GFX12-FAKE16-NEXT: v_perm_b32 v3, v20, v3, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v8 :: v_dual_lshlrev_b32 v11, 16, v9
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v1 :: v_dual_lshlrev_b32 v12, 16, v8
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v10
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v0 :: v_dual_lshlrev_b32 v15, 16, v2
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v9
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v11
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v10, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v24, v12
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v9, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v11, v2 :: v_dual_lshlrev_b32 v15, 16, v8
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v15
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v8, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v12, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v15, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v12
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v15
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v12, v1 :: v_dual_lshlrev_b32 v8, 16, v11
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_perm_b32 v1, v22, v1, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v15, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v23, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v21, v2, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v4, v19, v4, 0x5040100
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -12886,38 +12886,38 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v83.l, v36.l
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s42, v86, v86
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v36.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v96.h, v0.l, v16.l, s42
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s43, 0x8000, v96.h
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v68
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v15.h, v68.h, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v36.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.h, v68.h, v36.h, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v36, v35
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s42, 0x8000, v35.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v35.h, v36.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.h, v31.l, v36.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v31.l
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v32, v32
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v14.h, v30.h, s0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.h, v30.h, v36.h, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v36.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v36, v37
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s44, 0x8000, v37.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v37.h, v36.h, s0
; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.h, v32.l, v36.h, s1
@@ -12925,13 +12925,13 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v33, v33
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v13.h, v29.h, s1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.h, v29.h, v36.h, s2
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v36.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v36, v38
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v38.h, v36.h, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.h, v33.l, v36.h, s2
@@ -12939,13 +12939,13 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v34, v34
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v12.h, v28.h, s2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.h, v28.h, v36.h, s3
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v36.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v36, v39
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v39.h, v36.h, s2
; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.h, v34.l, v36.h, s3
@@ -12954,13 +12954,13 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v48.l, v36.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v11.h, v27.h, s3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.h, v27.h, v36.h, s4
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v36.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v36, v48
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v48.h, v36.h, s3
; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v35.l, v36.h, s4
@@ -12969,13 +12969,13 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v49.l, v36.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v10.h, v26.h, s4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.h, v26.h, v36.h, s5
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v36.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s4, v36, v49
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v49.h, v36.h, s4
; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.l, v38.l, v36.h, s5
@@ -12984,13 +12984,13 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v36.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v9.h, v25.h, s5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v50.h, v25.h, v36.h, s6
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v36.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s5, v36, v50
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.l, v50.h, v36.h, s5
; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.l, v48.l, v36.h, s6
@@ -12999,13 +12999,13 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v36.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v8.h, v24.h, s6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v51.h, v24.h, v36.h, s7
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v36.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s6, v36, v51
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v50.l, v51.h, v36.h, s6
; GFX12-TRUE16-NEXT: v_cndmask_b16 v51.l, v50.l, v36.h, s7
@@ -13014,13 +13014,13 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v36.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v7.h, v23.h, s7
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v52.h, v23.h, v36.h, s8
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v36.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s7, v36, v52
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v52.l, v52.h, v36.h, s7
; GFX12-TRUE16-NEXT: v_cndmask_b16 v69.l, v52.l, v36.h, s8
@@ -13029,13 +13029,13 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v36.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s7, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v6.h, v22.h, s8
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v53.h, v22.h, v36.h, s9
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0x8000, v36.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s8, v36, v53
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v53.l, v53.h, v36.h, s8
; GFX12-TRUE16-NEXT: v_cndmask_b16 v69.h, v53.l, v36.h, s9
@@ -13044,13 +13044,13 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v54.l, v36.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s8, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v5.h, v21.h, s9
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v54.h, v21.h, v36.h, s10
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0x8000, v36.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s9, v36, v54
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v54.l, v54.h, v36.h, s9
; GFX12-TRUE16-NEXT: v_cndmask_b16 v70.l, v54.l, v36.h, s10
@@ -13059,13 +13059,13 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v55.l, v36.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s9, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v4.h, v20.h, s10
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v55.h, v20.h, v36.h, s11
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0x8000, v36.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s10, v36, v55
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v55.l, v55.h, v36.h, s10
; GFX12-TRUE16-NEXT: v_cndmask_b16 v70.h, v55.l, v36.h, s11
@@ -13074,13 +13074,13 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v64.l, v36.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s10, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v3.h, v19.h, s11
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v64.h, v19.h, v36.h, s12
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0x8000, v36.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s11, v36, v64
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v64.l, v64.h, v36.h, s11
; GFX12-TRUE16-NEXT: v_cndmask_b16 v71.l, v64.l, v36.h, s12
@@ -13089,13 +13089,13 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v65.l, v36.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s11, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v2.h, v18.h, s12
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v65.h, v18.h, v36.h, s13
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0x8000, v36.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s12, v36, v65
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v65.l, v65.h, v36.h, s12
; GFX12-TRUE16-NEXT: v_cndmask_b16 v71.h, v65.l, v36.h, s13
@@ -13104,13 +13104,13 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v66.l, v36.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s12, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v1.h, v17.h, s13
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v66.h, v17.h, v36.h, s14
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0x8000, v36.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s13, v36, v66
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v66.l, v66.h, v36.h, s13
; GFX12-TRUE16-NEXT: v_cndmask_b16 v80.l, v66.l, v36.h, s14
@@ -13119,7 +13119,7 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v67.l, v36.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s13, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v0.h, v16.h, s14
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v67.h, v16.h, v36.h, s15
@@ -13127,7 +13127,7 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0x8000, v36.h
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v68
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s14, v36, v67
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v82.h, v15.l, v68.l, s15
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v81, v81
@@ -13138,10 +13138,10 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0x8000, v82.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s14, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v68.l, v82.h, s15
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s15, v82, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v68.l, v36.h, v82.h, s15
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0x8000, v36.h
@@ -13149,7 +13149,7 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s16, v81, v81
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v13
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v29
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.h, v14.h, v36.h, s15
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v68.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v14.l, v30.l, s16
@@ -13165,7 +13165,7 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s16, v14, v36
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v82, v82
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v36.h, v14.h, s16
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0x8000, v36.h
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v26
@@ -13175,7 +13175,7 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v12
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v82, v82
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v25
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.h, v13.h, v36.h, s16
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v14.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v13.l, v29.l, s17
@@ -13189,7 +13189,7 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v82, v82
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v23
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s17, v13, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v29.h, s16
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v82, v82
@@ -13202,7 +13202,7 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v11
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v82, v82
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v21
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.h, v12.h, v36.h, s17
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v13.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v12.l, v28.l, s18
@@ -13216,7 +13216,7 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v82, v82
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v19
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s18, v12, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v28.h, s17
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s28, v82, v82
@@ -13227,7 +13227,7 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v12.l, v12.h, s19
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v81, v81
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v10
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.h, v11.h, v36.h, s18
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v12.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v11.l, v27.l, s19
@@ -13236,18 +13236,18 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v36
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v27.l, v11.h, s20
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s20, 0x8000, v11.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v27.h, s18
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s19, v11, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v36.h, v11.h, s19
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s19, 0x8000, v36.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.h, v11.l, v11.h, s20
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v81, v81
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v9
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.h, v10.h, v36.h, s19
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v11.l
@@ -13257,18 +13257,18 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v26.l, v10.h, s21
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s21, 0x8000, v10.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v26.h, s19
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s20, v10, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v36.h, v10.h, s20
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s20, 0x8000, v36.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v10.l, v10.h, s21
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v81, v81
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v8
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.h, v9.h, v36.h, s20
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v10.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v9.l, v25.l, s21
@@ -13277,18 +13277,18 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v36
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v25.l, v9.h, s22
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s22, 0x8000, v9.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v25.h, s20
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s21, v9, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v36.h, v9.h, s21
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s21, 0x8000, v36.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v9.l, v9.h, s22
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v81, v81
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v7
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.h, v8.h, v36.h, s21
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v9.l
@@ -13298,18 +13298,18 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v24.l, v8.h, s23
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s23, 0x8000, v8.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v24.h, s21
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s22, v8, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v36.h, v8.h, s22
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s22, 0x8000, v36.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v8.l, v8.h, s23
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v81, v81
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.h, v7.h, v36.h, s22
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v8.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.l, v23.l, s23
@@ -13318,18 +13318,18 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v36
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v23.l, v7.h, s24
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s24, 0x8000, v7.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v23.h, s22
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s23, v7, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v36.h, v7.h, s23
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s23, 0x8000, v36.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v7.l, v7.h, s24
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v81, v81
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.h, v6.h, v36.h, s23
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v7.l
@@ -13339,18 +13339,18 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v22.l, v6.h, s25
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s25, 0x8000, v6.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v22.h, s23
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s24, v6, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v36.h, v6.h, s24
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s24, 0x8000, v36.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v6.l, v6.h, s25
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v81, v81
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.h, v5.h, v36.h, s24
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v6.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v5.l, v21.l, s25
@@ -13359,18 +13359,18 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v36
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v21.l, v5.h, s26
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s26, 0x8000, v5.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v21.h, s24
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s25, v5, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v36.h, v5.h, s25
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s25, 0x8000, v36.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v5.l, v5.h, s26
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s26, v81, v81
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.h, v4.h, v36.h, s25
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v5.l
@@ -13380,18 +13380,18 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v20.l, v4.h, s27
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s27, 0x8000, v4.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v20.h, s25
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s26, v4, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v36.h, v4.h, s26
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s26, 0x8000, v36.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v4.l, v4.h, s27
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v81, v81
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v18
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.h, v3.h, v36.h, s26
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v4.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v83.h, v3.l, v19.l, s27
@@ -13405,7 +13405,7 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s41, 0x8000, v83.h
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v36.l
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s27, v83, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v82.h, v2.l, v18.l, s28
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s28, 0x8000, v36.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.h, v1.l, v17.l, s40
@@ -13417,7 +13417,7 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v32.l, v1.l, s0
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, v83.h, s41
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s41, v87, v87
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.h, v36.h, s28
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v3.l
@@ -13427,18 +13427,18 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s45, 0, v36
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v18.l, v82.h, s29
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s29, 0x8000, v38.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v31.l, v0.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v34.h, v39.h, s42
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v48.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s44, v82, v36
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v33.h, v38.h, s29
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v36.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v34.l, v1.h, s2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v37.l, v48.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v36.h, v82.h, s44
; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v33.l, v0.h, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v49.h
@@ -13447,12 +13447,12 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v82.h, s40
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v51.h
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v54.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v49.l, v50.h, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s45
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v36.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v1.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v39.l, v49.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v52.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v51.l, v51.h, s2
@@ -13460,14 +13460,14 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v36
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v17.l, v19.h, s27
; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.h, v38.l, v0.h, s4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v69.l, v52.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v55.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v48.l, v1.h, s5
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v19, v36
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v36.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v69.h, v53.h, s2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v70.h, v55.h, s4
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v66.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v36.h, v19.h, s1
@@ -13477,7 +13477,7 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v52.l, v0.h, s7
; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v16.h, v19.h, s28
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v53.l, v1.h, s8
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v71.h, v65.h, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v54.l, v2.h, s9
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v67.h
@@ -13485,33 +13485,33 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v16.h
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v64.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v65.l, v1.h, s12
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v67.h, s3
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v55.l, v3.h, s10
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v36
; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v16.l, v96.h, s41
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v71.l, v64.h, s0
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v80.l, v66.h, s2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v1.l, v2.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v16.h, v17.l, s4
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v96, v36
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v64.l, v0.h, s11
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v66.l, v16.l, s13
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v67.l, v15.l, s14
; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v68.l, v30.h, s15
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v36.h, v96.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v36.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.h, v16.l, v96.h, s43
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.h, v17.h, v36.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v16.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v36
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v16.l, v17.h, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -13533,7 +13533,7 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v14
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v24
; GFX12-FAKE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v52, v52, v51, s1
; GFX12-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v13
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9
@@ -13545,7 +13545,7 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v22
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v48, v48, v39, s0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14
; GFX12-FAKE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
@@ -13557,494 +13557,494 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v19
; GFX12-FAKE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v36, v36, v35, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v70, v70
; GFX12-FAKE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v29
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18
; GFX12-FAKE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v70, v80, v71, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v82, v82
; GFX12-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v28
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v2
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v80, v84, v83, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86
; GFX12-FAKE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v26
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v17
; GFX12-FAKE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v1
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v27
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v82, v96, v87, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v98
; GFX12-FAKE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v25
; GFX12-FAKE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v11
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v1
; GFX12-FAKE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v84, v100, v99, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v102, v102
; GFX12-FAKE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v24
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v147, 16, v16
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v0
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v54, v54
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v86, v112, v103, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v114, v114
; GFX12-FAKE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v22
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v14
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v26
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v96, v116, v115, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v118, v118
; GFX12-FAKE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v64, v64, v55, s2
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v10
; GFX12-FAKE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v98, v128, v119, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v130, v130
; GFX12-FAKE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v100, v132, v131, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v134, v134
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v102, v144, v135 :: v_dual_and_b32 v133, 0xffff0000, v18
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v146, v146
; GFX12-FAKE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v112, 16, v96
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v147, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54
; GFX12-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v27
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v54, v14, v30 :: v_dual_and_b32 v97, 0xffff0000, v23
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
; GFX12-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v15
; GFX12-FAKE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v39, v48, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v51, v51, v52, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v116, 16, v100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v55, v55, v64 :: v_dual_lshlrev_b32 v130, 16, v51
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v69, v69
; GFX12-FAKE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v10
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v128, 16, v34
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v66, v66
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v68, v68, v67, s3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v67, v67, v68, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v81, v81
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v68
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v80
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v71, v71, v70 :: v_dual_lshlrev_b32 v132, 16, v67
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v85, v85
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v83, v83, v80, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v97, v97
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v30
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v84
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v87, v87, v82 :: v_dual_lshlrev_b32 v134, 16, v83
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v101, v101
; GFX12-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v16
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v99, v99, v84, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v113, v113
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v103, v103, v86 :: v_dual_lshlrev_b32 v144, 16, v99
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v117, v117
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v36
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v113, v115, v96, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v129, v129
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v82
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v115, v119, v98 :: v_dual_lshlrev_b32 v146, 16, v113
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v133, v133
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v48
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v117, v131, v100, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v145, v145
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v86
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v119, v135, v102, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v38, v147, v34 :: v_dual_lshlrev_b32 v49, 16, v52
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e64 s0, v49, v130
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v66, v30, v54 :: v_dual_lshlrev_b32 v53, 16, v64
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v35
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v14, v30
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v70
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v117
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v130, v35, v36 :: v_dual_lshlrev_b32 v129, 16, v39
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v37, v129
-; GFX12-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v129, v51, v52, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v37, v39, v48 :: v_dual_lshlrev_b32 v118, 16, v102
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v131, 16, v55
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v53, v131
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v53, v55, v64 :: v_dual_lshlrev_b32 v50, 16, v15
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v71
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v65, v132
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v65, v67, v68, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v69, v133
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v135, 16, v87
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v69, v71, v70 :: v_dual_lshlrev_b32 v132, 16, v65
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v81, v134
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v81, v83, v80, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v85, v135
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v145, 16, v103
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v85, v87, v82, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v97, v144
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v97, v99, v84 :: v_dual_lshlrev_b32 v114, 16, v98
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v101, v145
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v147, 16, v115
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v101, v103, v86 :: v_dual_lshlrev_b32 v144, 16, v97
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v112, v146
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v112, v113, v96, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v114, v147
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v119
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v38
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v114, v115, v98, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v116, v14
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v116, v117, v100, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v118, v30
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v118, v119, v102, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v128, v49
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v128, v38, v34, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v36
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v130, v36, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v48
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v36, v37, v48, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v52
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v49, v129, v52, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v64
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v52, 16, v129
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v64, v53, v64, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v68
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v68, v65, v68, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v70
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v70, v69, v70, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v80
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v80, v81, v80, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v82
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v82, v85, v82, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v84
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v84, v97, v84, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v86
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v86, v101, v86, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v96
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v96, v112, v96, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v98
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v98, v114, v98 :: v_dual_lshlrev_b32 v131, 16, v53
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v100, v116, v100 :: v_dual_lshlrev_b32 v133, 16, v69
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v35
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v35 :: v_dual_lshlrev_b32 v135, 16, v85
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v102
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v118, v102, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v39
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v36, v36, v39 :: v_dual_lshlrev_b32 v145, 16, v101
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v34
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v34, v128, v34, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v51
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v49, v51, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v55
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v51, 16, v128
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v49, v64, v55, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v67
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v68, v67, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v71
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v64, v70, v71 :: v_dual_lshlrev_b32 v147, 16, v114
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v83
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v67, v80, v83, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v87
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v68, v82, v87, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v99
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v70, v84, v99, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v103
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v71, v86, v103 :: v_dual_lshlrev_b32 v30, 16, v130
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v113
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v37
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v80, v96, v113, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v115
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v82, v98, v115, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v117
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v81
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v83, v100, v117, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v119
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v84, v35, v119, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v38
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v86, v34, v38, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v30
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v130, v14, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v48
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v30, v37, v36, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v52
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v31
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v34, v129, v39, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v131
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v53, v49, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v132
; GFX12-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v31
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v36, v65, v55, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v133
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v37, v69, v64, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v134
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v38, v81, v67, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v135
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v85, v68, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v144
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v48, v97, v70, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v145
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v49, v101, v71, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v15, v31, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v32, 16, v31
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v148, 16, v116
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v55
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v52, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v146, 16, v112
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v33
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v146
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v112, v80, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v52, v52, v33, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v118
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v53, v31, v55 :: v_dual_lshlrev_b32 v64, 16, v52
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v147
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v53
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v31, v114, v82, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v148
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v32, v116, v83, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v50, v64
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v64, v52, v33, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v65, v67
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v64
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v65, v53, v55, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v102
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v65
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v50, v118, v84, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v33
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v33, v64, v33, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v55
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v65, v55, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v52
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v52, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v53
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v53, v55, v53, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v67
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v33, v64, v33, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v52, v128, v86, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v68
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v51, v65, v53, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v66
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v29
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v12
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v13, v13, v29 :: v_dual_lshlrev_b32 v64, 16, v54
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v64, v53
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v53, v66, v54, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v29, v29, v13, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v28
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v29
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v54
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v54, v53, v54, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v28, v28, v12, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v66
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v54, v54, v66, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v65, v64
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v53
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v28
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v55, v29, v13 :: v_dual_lshlrev_b32 v66, 16, v12
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v64
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v53, v53, v54 :: v_dual_lshlrev_b32 v64, 16, v55
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v66, v65
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v27
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_perm_b32 v14, v14, v53, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v54, v28, v12, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v29
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v11
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v54, v12, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v28
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v27, v27, v11 :: v_dual_lshlrev_b32 v28, 16, v54
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v64
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v26
; GFX12-FAKE16-NEXT: v_perm_b32 v13, v30, v13, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v54, v12, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v11
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v26 :: v_dual_lshlrev_b32 v29, 16, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v27
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v54, v28
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v28, v27, v11, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v26, v26, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v25
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v11, v28, v11 :: v_dual_lshlrev_b32 v54, 16, v26
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v25, v9, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v27
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v10
@@ -14053,258 +14053,258 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v55, v54
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v29, v26, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v29
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_perm_b32 v11, v35, v11, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v29, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v55, v54
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v27, v25, v9, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v26
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v27, v9, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v23
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v29, v10, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v25
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v25 :: v_dual_lshlrev_b32 v26, 16, v8
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v7
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v27
; GFX12-FAKE16-NEXT: v_perm_b32 v10, v36, v10, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v26, 16, v24
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v7
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v23, v23, v7 :: v_dual_lshlrev_b32 v26, 16, v24
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v27, v9 :: v_dual_lshlrev_b32 v28, 16, v23
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v8
; GFX12-FAKE16-NEXT: v_perm_b32 v9, v37, v9, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v27, v26
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v26, v24, v8 :: v_dual_lshlrev_b32 v25, 16, v22
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v29, v28
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v27, v23, v7, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v24
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v23
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v24, 16, v26
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v22
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v6
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v28, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v27
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v22, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v21
; GFX12-FAKE16-NEXT: v_perm_b32 v8, v38, v8, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v22
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_perm_b32 v7, v39, v7, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v21 :: v_dual_lshlrev_b32 v24, 16, v4
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v20
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v21
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v24
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v4
; GFX12-FAKE16-NEXT: v_perm_b32 v6, v48, v6, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v23, v21, v5 :: v_dual_lshlrev_b32 v22, 16, v19
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v24
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v19
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v20, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v21
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v22, v4 :: v_dual_lshlrev_b32 v21, 16, v23
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v24
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v19, v3, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v20
; GFX12-FAKE16-NEXT: v_perm_b32 v5, v49, v5, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v19
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v19 :: v_dual_lshlrev_b32 v20, 16, v2
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v18
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v18 :: v_dual_lshlrev_b32 v23, 16, v24
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v0
; GFX12-FAKE16-NEXT: v_perm_b32 v3, v31, v3, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v18, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v17
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v17, v17, v1 :: v_dual_lshlrev_b32 v20, 16, v16
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v0 :: v_dual_lshlrev_b32 v19, 16, v18
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v17
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v23, v19
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v18, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v24, v20
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v17, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v19, v2 :: v_dual_lshlrev_b32 v23, 16, v16
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v25, v23
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v16, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v20, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v18
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v23, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v17
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v20
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v16
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v23
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v20, v1 :: v_dual_lshlrev_b32 v16, 16, v19
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_perm_b32 v1, v50, v1, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v23, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v16
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v52, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v2, v32, v2, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v4, v15, v4, 0x5040100
; GFX12-FAKE16-NEXT: v_perm_b32 v15, v33, v51, 0x5040100
@@ -14489,26 +14489,26 @@ define bfloat @v_minimumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v0.l, v0.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v0.h, v1.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v1, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v1.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v1.h, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, vcc_lo
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -14522,29 +14522,29 @@ define bfloat @v_minimumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 {
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call bfloat @llvm.minimumnum.bf16(bfloat %x, bfloat %y)
@@ -14859,44 +14859,44 @@ define <2 x bfloat> @v_minimumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> %
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v4.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v0.h, v1.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.h, v4.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.h, v4.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v4.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v4.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.h, v2.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v0.l, v1.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v1.l, v3.h, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v3.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v3, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v3.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.l, v3.h, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v2.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.h, v0.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, s1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v0.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -14913,50 +14913,50 @@ define <2 x bfloat> @v_minimumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> %
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v3 :: v_dual_lshlrev_b32 v5, 16, v0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v0 :: v_dual_lshlrev_b32 v4, 16, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v3, v2 :: v_dual_lshlrev_b32 v7, 16, v1
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_lshlrev_b32 v7, 16, v5
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
@@ -15389,25 +15389,25 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v0.h, v2.h, vcc_lo
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v2.h, v6.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.h
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.h, v6.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v6.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v6.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v4.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v1.l, v3.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
@@ -15415,13 +15415,13 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v5.h
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v5, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v6.h, v5.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v5.h, s1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v3, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v0.h, v6.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v1.l
@@ -15431,26 +15431,26 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v6
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v2.l, v0.h, s2
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v0.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v2.h, s0
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v0, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.h, v0.h, s1
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v6.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, s2
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v4.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v6.h, s1
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v0.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v4.h, s2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v0.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -15468,71 +15468,71 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v4 :: v_dual_lshlrev_b32 v6, 16, v1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v9, 16, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v10, 16, v6
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v7, 16, v0
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v7, v8
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v6, v1 :: v_dual_lshlrev_b32 v2, 16, v6
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v4, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x bfloat> @llvm.minimumnum.v3bf16(<3 x bfloat> %x, <3 x bfloat> %y)
@@ -16091,45 +16091,45 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v6.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v1.h, v3.h, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v3.h, v6.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v5
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v5.h, v6.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v6.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.l, v6.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v4.l
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v8, v8
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v0.h, v2.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v2.h, v6.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.h
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v7
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v7.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v7.h, v6.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v6.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v6.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v5.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v1.l, v3.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
@@ -16137,14 +16137,14 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v8.h
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v8, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v6.h, v8.h, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v8.h, s2
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v3, v3
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.h, v7.h, s4
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v0.h, v6.h, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v1.l
@@ -16154,17 +16154,17 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v2.l, v0.h, s3
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v0.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v2.h, s0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v0, v6
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.h, v0.h, s2
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v6.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, s3
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v5.h
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v6.h, s2
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v0.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -16172,9 +16172,9 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v0.h, s1
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v3.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -16191,96 +16191,96 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v3
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v11
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v5, v4 :: v_dual_and_b32 v9, 0xffff0000, v2
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v13, 16, v3
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v6 :: v_dual_lshlrev_b32 v14, 16, v0
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v9, 16, v7
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v5, 16, v6
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v9
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v8
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v10
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v3, 16, v7
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v6 :: v_dual_lshlrev_b32 v2, 16, v8
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo
; GFX12-FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x5040100
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll b/llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
index f9041ffcf0a4f..46d63c87656d9 100644
--- a/llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
+++ b/llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
@@ -51,7 +51,7 @@ define float @mubuf_vgpr(<4 x i32> %i, i32 %c) #0 {
; GFX1010_W32-NEXT: buffer_load_format_x v5, v4, s[8:11], 0 idxen
; GFX1010_W32-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX1010_W32-NEXT: ; implicit-def: $vgpr4
-; GFX1010_W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010_W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010_W32-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX1010_W32-NEXT: s_cbranch_execnz .LBB0_1
; GFX1010_W32-NEXT: ; %bb.2:
@@ -76,7 +76,7 @@ define float @mubuf_vgpr(<4 x i32> %i, i32 %c) #0 {
; GFX1010_W64-NEXT: buffer_load_format_x v5, v4, s[8:11], 0 idxen
; GFX1010_W64-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX1010_W64-NEXT: ; implicit-def: $vgpr4
-; GFX1010_W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010_W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010_W64-NEXT: s_xor_b64 exec, exec, s[4:5]
; GFX1010_W64-NEXT: s_cbranch_execnz .LBB0_1
; GFX1010_W64-NEXT: ; %bb.2:
@@ -305,7 +305,7 @@ define void @mubuf_vgpr_adjacent_in_block(<4 x i32> %i, <4 x i32> %j, i32 %c, pt
; GFX1010_W32-NEXT: s_and_saveexec_b32 s4, s4
; GFX1010_W32-NEXT: buffer_load_format_x v13, v8, s[8:11], 0 idxen
; GFX1010_W32-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
-; GFX1010_W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010_W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010_W32-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX1010_W32-NEXT: s_cbranch_execnz .LBB1_1
; GFX1010_W32-NEXT: ; %bb.2:
@@ -323,7 +323,7 @@ define void @mubuf_vgpr_adjacent_in_block(<4 x i32> %i, <4 x i32> %j, i32 %c, pt
; GFX1010_W32-NEXT: buffer_load_format_x v0, v8, s[8:11], 0 idxen
; GFX1010_W32-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7
; GFX1010_W32-NEXT: ; implicit-def: $vgpr8
-; GFX1010_W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010_W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010_W32-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX1010_W32-NEXT: s_cbranch_execnz .LBB1_3
; GFX1010_W32-NEXT: ; %bb.4:
@@ -351,7 +351,7 @@ define void @mubuf_vgpr_adjacent_in_block(<4 x i32> %i, <4 x i32> %j, i32 %c, pt
; GFX1010_W64-NEXT: s_and_saveexec_b64 s[4:5], s[4:5]
; GFX1010_W64-NEXT: buffer_load_format_x v13, v8, s[8:11], 0 idxen
; GFX1010_W64-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
-; GFX1010_W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010_W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010_W64-NEXT: s_xor_b64 exec, exec, s[4:5]
; GFX1010_W64-NEXT: s_cbranch_execnz .LBB1_1
; GFX1010_W64-NEXT: ; %bb.2:
@@ -369,7 +369,7 @@ define void @mubuf_vgpr_adjacent_in_block(<4 x i32> %i, <4 x i32> %j, i32 %c, pt
; GFX1010_W64-NEXT: buffer_load_format_x v0, v8, s[8:11], 0 idxen
; GFX1010_W64-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7
; GFX1010_W64-NEXT: ; implicit-def: $vgpr8
-; GFX1010_W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010_W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010_W64-NEXT: s_xor_b64 exec, exec, s[4:5]
; GFX1010_W64-NEXT: s_cbranch_execnz .LBB1_3
; GFX1010_W64-NEXT: ; %bb.4:
@@ -784,7 +784,7 @@ define void @mubuf_vgpr_outside_entry(<4 x i32> %i, <4 x i32> %j, i32 %c, ptr ad
; GFX1010_W32-NEXT: buffer_load_format_x v9, v8, s[8:11], 0 idxen
; GFX1010_W32-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX1010_W32-NEXT: ; implicit-def: $vgpr8
-; GFX1010_W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010_W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010_W32-NEXT: s_xor_b32 exec_lo, exec_lo, s5
; GFX1010_W32-NEXT: s_cbranch_execnz .LBB2_1
; GFX1010_W32-NEXT: ; %bb.2:
@@ -808,7 +808,7 @@ define void @mubuf_vgpr_outside_entry(<4 x i32> %i, <4 x i32> %j, i32 %c, ptr ad
; GFX1010_W32-NEXT: buffer_load_format_x v9, v0, s[8:11], 0 idxen
; GFX1010_W32-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7
; GFX1010_W32-NEXT: ; implicit-def: $vgpr0
-; GFX1010_W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010_W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010_W32-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX1010_W32-NEXT: s_cbranch_execnz .LBB2_4
; GFX1010_W32-NEXT: ; %bb.5:
@@ -840,7 +840,7 @@ define void @mubuf_vgpr_outside_entry(<4 x i32> %i, <4 x i32> %j, i32 %c, ptr ad
; GFX1010_W64-NEXT: buffer_load_format_x v9, v8, s[8:11], 0 idxen
; GFX1010_W64-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX1010_W64-NEXT: ; implicit-def: $vgpr8
-; GFX1010_W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010_W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010_W64-NEXT: s_xor_b64 exec, exec, s[6:7]
; GFX1010_W64-NEXT: s_cbranch_execnz .LBB2_1
; GFX1010_W64-NEXT: ; %bb.2:
@@ -864,7 +864,7 @@ define void @mubuf_vgpr_outside_entry(<4 x i32> %i, <4 x i32> %j, i32 %c, ptr ad
; GFX1010_W64-NEXT: buffer_load_format_x v9, v0, s[8:11], 0 idxen
; GFX1010_W64-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7
; GFX1010_W64-NEXT: ; implicit-def: $vgpr0
-; GFX1010_W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010_W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010_W64-NEXT: s_xor_b64 exec, exec, s[4:5]
; GFX1010_W64-NEXT: s_cbranch_execnz .LBB2_4
; GFX1010_W64-NEXT: ; %bb.5:
diff --git a/llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll b/llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
index 6368030b445fe..b7947de7d5836 100644
--- a/llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
+++ b/llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
@@ -50,7 +50,7 @@ define float @mubuf_vgpr(ptr addrspace(8) %i, i32 %c) #0 {
; GFX1010_W32-NEXT: buffer_load_format_x v5, v4, s[8:11], 0 idxen
; GFX1010_W32-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX1010_W32-NEXT: ; implicit-def: $vgpr4
-; GFX1010_W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010_W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010_W32-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX1010_W32-NEXT: s_cbranch_execnz .LBB0_1
; GFX1010_W32-NEXT: ; %bb.2:
@@ -75,7 +75,7 @@ define float @mubuf_vgpr(ptr addrspace(8) %i, i32 %c) #0 {
; GFX1010_W64-NEXT: buffer_load_format_x v5, v4, s[8:11], 0 idxen
; GFX1010_W64-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX1010_W64-NEXT: ; implicit-def: $vgpr4
-; GFX1010_W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010_W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010_W64-NEXT: s_xor_b64 exec, exec, s[4:5]
; GFX1010_W64-NEXT: s_cbranch_execnz .LBB0_1
; GFX1010_W64-NEXT: ; %bb.2:
@@ -311,7 +311,7 @@ define void @mubuf_vgpr_adjacent_in_block(ptr addrspace(8) %i, ptr addrspace(8)
; GFX1010_W32-NEXT: s_and_saveexec_b32 s4, s4
; GFX1010_W32-NEXT: buffer_load_format_x v13, v8, s[8:11], 0 idxen
; GFX1010_W32-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
-; GFX1010_W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010_W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010_W32-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX1010_W32-NEXT: s_cbranch_execnz .LBB1_1
; GFX1010_W32-NEXT: ; %bb.2:
@@ -329,7 +329,7 @@ define void @mubuf_vgpr_adjacent_in_block(ptr addrspace(8) %i, ptr addrspace(8)
; GFX1010_W32-NEXT: buffer_load_format_x v0, v8, s[8:11], 0 idxen
; GFX1010_W32-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7
; GFX1010_W32-NEXT: ; implicit-def: $vgpr8
-; GFX1010_W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010_W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010_W32-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX1010_W32-NEXT: s_cbranch_execnz .LBB1_3
; GFX1010_W32-NEXT: ; %bb.4:
@@ -357,7 +357,7 @@ define void @mubuf_vgpr_adjacent_in_block(ptr addrspace(8) %i, ptr addrspace(8)
; GFX1010_W64-NEXT: s_and_saveexec_b64 s[4:5], s[4:5]
; GFX1010_W64-NEXT: buffer_load_format_x v13, v8, s[8:11], 0 idxen
; GFX1010_W64-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
-; GFX1010_W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010_W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010_W64-NEXT: s_xor_b64 exec, exec, s[4:5]
; GFX1010_W64-NEXT: s_cbranch_execnz .LBB1_1
; GFX1010_W64-NEXT: ; %bb.2:
@@ -375,7 +375,7 @@ define void @mubuf_vgpr_adjacent_in_block(ptr addrspace(8) %i, ptr addrspace(8)
; GFX1010_W64-NEXT: buffer_load_format_x v0, v8, s[8:11], 0 idxen
; GFX1010_W64-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7
; GFX1010_W64-NEXT: ; implicit-def: $vgpr8
-; GFX1010_W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010_W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010_W64-NEXT: s_xor_b64 exec, exec, s[4:5]
; GFX1010_W64-NEXT: s_cbranch_execnz .LBB1_3
; GFX1010_W64-NEXT: ; %bb.4:
@@ -801,7 +801,7 @@ define void @mubuf_vgpr_outside_entry(ptr addrspace(8) %i, ptr addrspace(8) %j,
; GFX1010_W32-NEXT: buffer_load_format_x v9, v8, s[8:11], 0 idxen
; GFX1010_W32-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX1010_W32-NEXT: ; implicit-def: $vgpr8
-; GFX1010_W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010_W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010_W32-NEXT: s_xor_b32 exec_lo, exec_lo, s5
; GFX1010_W32-NEXT: s_cbranch_execnz .LBB2_1
; GFX1010_W32-NEXT: ; %bb.2:
@@ -825,7 +825,7 @@ define void @mubuf_vgpr_outside_entry(ptr addrspace(8) %i, ptr addrspace(8) %j,
; GFX1010_W32-NEXT: buffer_load_format_x v9, v0, s[8:11], 0 idxen
; GFX1010_W32-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7
; GFX1010_W32-NEXT: ; implicit-def: $vgpr0
-; GFX1010_W32-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010_W32-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010_W32-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GFX1010_W32-NEXT: s_cbranch_execnz .LBB2_4
; GFX1010_W32-NEXT: ; %bb.5:
@@ -857,7 +857,7 @@ define void @mubuf_vgpr_outside_entry(ptr addrspace(8) %i, ptr addrspace(8) %j,
; GFX1010_W64-NEXT: buffer_load_format_x v9, v8, s[8:11], 0 idxen
; GFX1010_W64-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX1010_W64-NEXT: ; implicit-def: $vgpr8
-; GFX1010_W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010_W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010_W64-NEXT: s_xor_b64 exec, exec, s[6:7]
; GFX1010_W64-NEXT: s_cbranch_execnz .LBB2_1
; GFX1010_W64-NEXT: ; %bb.2:
@@ -881,7 +881,7 @@ define void @mubuf_vgpr_outside_entry(ptr addrspace(8) %i, ptr addrspace(8) %j,
; GFX1010_W64-NEXT: buffer_load_format_x v9, v0, s[8:11], 0 idxen
; GFX1010_W64-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7
; GFX1010_W64-NEXT: ; implicit-def: $vgpr0
-; GFX1010_W64-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1010_W64-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1010_W64-NEXT: s_xor_b64 exec, exec, s[4:5]
; GFX1010_W64-NEXT: s_cbranch_execnz .LBB2_4
; GFX1010_W64-NEXT: ; %bb.5:
diff --git a/llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll b/llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll
index 587e454da884c..aff07787a2fb7 100644
--- a/llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll
+++ b/llvm/test/CodeGen/AMDGPU/no-folding-imm-to-inst-with-fi.ll
@@ -26,7 +26,7 @@ define protected amdgpu_kernel void @no_folding_imm_to_inst_with_fi(<4 x i64> %v
; CHECK-NEXT: v_dual_mov_b32 v16, s20 :: v_dual_mov_b32 v17, s21
; CHECK-NEXT: s_add_nc_u64 s[20:21], s[34:35], 0x50
; CHECK-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
-; CHECK-NEXT: s_wait_alu 0xfffe
+; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0)
; CHECK-NEXT: v_dual_mov_b32 v22, s24 :: v_dual_mov_b32 v23, s25
; CHECK-NEXT: v_dual_mov_b32 v18, s22 :: v_dual_mov_b32 v19, s23
; CHECK-NEXT: v_dual_mov_b32 v25, s21 :: v_dual_mov_b32 v24, s20
@@ -45,7 +45,7 @@ define protected amdgpu_kernel void @no_folding_imm_to_inst_with_fi(<4 x i64> %v
; CHECK-NEXT: v_dual_mov_b32 v0, s16 :: v_dual_mov_b32 v1, s17
; CHECK-NEXT: v_dual_mov_b32 v2, s18 :: v_dual_mov_b32 v3, s19
; CHECK-NEXT: v_dual_mov_b32 v6, s14 :: v_dual_mov_b32 v7, s15
-; CHECK-NEXT: s_wait_alu 0xfffe
+; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0)
; CHECK-NEXT: v_dual_mov_b32 v29, s13 :: v_dual_mov_b32 v28, s12
; CHECK-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9
; CHECK-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11
diff --git a/llvm/test/CodeGen/AMDGPU/nor-divergent-lanemask.ll b/llvm/test/CodeGen/AMDGPU/nor-divergent-lanemask.ll
index 97c2bdceb31a8..a9c9db6d9aef5 100644
--- a/llvm/test/CodeGen/AMDGPU/nor-divergent-lanemask.ll
+++ b/llvm/test/CodeGen/AMDGPU/nor-divergent-lanemask.ll
@@ -13,7 +13,7 @@ define amdgpu_ps i64 @test_nor(i64 inreg %a, i64 inreg %b) {
; SDAG-W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; SDAG-W64-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; SDAG-W64-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v0
-; SDAG-W64-NEXT: s_waitcnt_depctr 0xf1ff
+; SDAG-W64-NEXT: s_waitcnt_depctr depctr_va_sdst(0)
; SDAG-W64-NEXT: ; return to shader part epilog
;
; GISEL-W64-LABEL: test_nor:
@@ -53,12 +53,12 @@ define amdgpu_ps i64 @test_or_two_uses(i64 inreg %a, i64 inreg %b) {
; SDAG-W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; SDAG-W64-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; SDAG-W64-NEXT: s_xor_b64 s[0:1], s[0:1], -1
-; SDAG-W64-NEXT: s_waitcnt_depctr 0xfffe
+; SDAG-W64-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; SDAG-W64-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; SDAG-W64-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SDAG-W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
; SDAG-W64-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v1
-; SDAG-W64-NEXT: s_waitcnt_depctr 0xf1ff
+; SDAG-W64-NEXT: s_waitcnt_depctr depctr_va_sdst(0)
; SDAG-W64-NEXT: s_and_b64 s[0:1], s[0:1], vcc
; SDAG-W64-NEXT: ; return to shader part epilog
;
@@ -105,4 +105,4 @@ define amdgpu_ps i64 @test_or_two_uses(i64 inreg %a, i64 inreg %b) {
%r1 = call i64 @llvm.amdgcn.ballot.i64(i1 %or)
%r = and i64 %r0, %r1
ret i64 %r
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/AMDGPU/offset-split-flat.ll b/llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
index 4d189d7a9673d..6551a955d314e 100644
--- a/llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
+++ b/llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
@@ -1087,7 +1087,7 @@ define i8 @flat_inst_valu_offset_2x_24bit_max(ptr %p) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: flat_load_d16_u8 v0, v[0:1] offset:8388606
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1101,7 +1101,7 @@ define i8 @flat_inst_valu_offset_2x_24bit_max(ptr %p) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: flat_load_u8 v0, v[0:1] offset:8388606
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1134,7 +1134,7 @@ define i8 @flat_inst_valu_offset_2x_24bit_max(ptr %p) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffffe, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1449,7 +1449,7 @@ define i8 @flat_inst_valu_offset_2x_neg_24bit_max(ptr %p) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xff800000, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: flat_load_d16_u8 v0, v[0:1] offset:-8388607
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1463,7 +1463,7 @@ define i8 @flat_inst_valu_offset_2x_neg_24bit_max(ptr %p) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xff800000, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: flat_load_u8 v0, v[0:1] offset:-8388607
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1487,7 +1487,7 @@ define i8 @flat_inst_valu_offset_2x_neg_24bit_max(ptr %p) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0xff000001, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1545,7 +1545,7 @@ define i8 @flat_inst_valu_offset_64bit_11bit_split0(ptr %p) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: flat_load_d16_u8 v0, v[0:1] offset:2047
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1559,7 +1559,7 @@ define i8 @flat_inst_valu_offset_64bit_11bit_split0(ptr %p) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: flat_load_u8 v0, v[0:1] offset:2047
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1592,7 +1592,7 @@ define i8 @flat_inst_valu_offset_64bit_11bit_split0(ptr %p) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x7ff, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1650,7 +1650,7 @@ define i8 @flat_inst_valu_offset_64bit_11bit_split1(ptr %p) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: flat_load_d16_u8 v0, v[0:1] offset:2048
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1664,7 +1664,7 @@ define i8 @flat_inst_valu_offset_64bit_11bit_split1(ptr %p) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: flat_load_u8 v0, v[0:1] offset:2048
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1697,7 +1697,7 @@ define i8 @flat_inst_valu_offset_64bit_11bit_split1(ptr %p) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1755,7 +1755,7 @@ define i8 @flat_inst_valu_offset_64bit_12bit_split0(ptr %p) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: flat_load_d16_u8 v0, v[0:1] offset:4095
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1769,7 +1769,7 @@ define i8 @flat_inst_valu_offset_64bit_12bit_split0(ptr %p) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: flat_load_u8 v0, v[0:1] offset:4095
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1802,7 +1802,7 @@ define i8 @flat_inst_valu_offset_64bit_12bit_split0(ptr %p) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0xfff, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1860,7 +1860,7 @@ define i8 @flat_inst_valu_offset_64bit_12bit_split1(ptr %p) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: flat_load_d16_u8 v0, v[0:1] offset:4096
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1874,7 +1874,7 @@ define i8 @flat_inst_valu_offset_64bit_12bit_split1(ptr %p) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: flat_load_u8 v0, v[0:1] offset:4096
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1898,7 +1898,7 @@ define i8 @flat_inst_valu_offset_64bit_12bit_split1(ptr %p) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1956,7 +1956,7 @@ define i8 @flat_inst_valu_offset_64bit_13bit_split0(ptr %p) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: flat_load_d16_u8 v0, v[0:1] offset:8191
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1970,7 +1970,7 @@ define i8 @flat_inst_valu_offset_64bit_13bit_split0(ptr %p) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: flat_load_u8 v0, v[0:1] offset:8191
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2003,7 +2003,7 @@ define i8 @flat_inst_valu_offset_64bit_13bit_split0(ptr %p) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x1fff, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2061,7 +2061,7 @@ define i8 @flat_inst_valu_offset_64bit_13bit_split1(ptr %p) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: flat_load_d16_u8 v0, v[0:1] offset:8192
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2075,7 +2075,7 @@ define i8 @flat_inst_valu_offset_64bit_13bit_split1(ptr %p) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: flat_load_u8 v0, v[0:1] offset:8192
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2099,7 +2099,7 @@ define i8 @flat_inst_valu_offset_64bit_13bit_split1(ptr %p) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2158,7 +2158,7 @@ define i8 @flat_inst_valu_offset_64bit_11bit_neg_high_split0(ptr %p) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: flat_load_d16_u8 v0, v[0:1] offset:-8386561
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2172,7 +2172,7 @@ define i8 @flat_inst_valu_offset_64bit_11bit_neg_high_split0(ptr %p) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: flat_load_u8 v0, v[0:1] offset:-8386561
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2206,7 +2206,7 @@ define i8 @flat_inst_valu_offset_64bit_11bit_neg_high_split0(ptr %p) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x7ff, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2265,7 +2265,7 @@ define i8 @flat_inst_valu_offset_64bit_11bit_neg_high_split1(ptr %p) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: flat_load_d16_u8 v0, v[0:1] offset:-8386560
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2279,7 +2279,7 @@ define i8 @flat_inst_valu_offset_64bit_11bit_neg_high_split1(ptr %p) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: flat_load_u8 v0, v[0:1] offset:-8386560
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2313,7 +2313,7 @@ define i8 @flat_inst_valu_offset_64bit_11bit_neg_high_split1(ptr %p) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2372,7 +2372,7 @@ define i8 @flat_inst_valu_offset_64bit_12bit_neg_high_split0(ptr %p) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: flat_load_d16_u8 v0, v[0:1] offset:-8384513
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2386,7 +2386,7 @@ define i8 @flat_inst_valu_offset_64bit_12bit_neg_high_split0(ptr %p) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: flat_load_u8 v0, v[0:1] offset:-8384513
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2420,7 +2420,7 @@ define i8 @flat_inst_valu_offset_64bit_12bit_neg_high_split0(ptr %p) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0xfff, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2479,7 +2479,7 @@ define i8 @flat_inst_valu_offset_64bit_12bit_neg_high_split1(ptr %p) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: flat_load_d16_u8 v0, v[0:1] offset:-8384512
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2493,7 +2493,7 @@ define i8 @flat_inst_valu_offset_64bit_12bit_neg_high_split1(ptr %p) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: flat_load_u8 v0, v[0:1] offset:-8384512
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2527,7 +2527,7 @@ define i8 @flat_inst_valu_offset_64bit_12bit_neg_high_split1(ptr %p) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2586,7 +2586,7 @@ define i8 @flat_inst_valu_offset_64bit_13bit_neg_high_split0(ptr %p) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: flat_load_d16_u8 v0, v[0:1] offset:-8380417
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2600,7 +2600,7 @@ define i8 @flat_inst_valu_offset_64bit_13bit_neg_high_split0(ptr %p) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: flat_load_u8 v0, v[0:1] offset:-8380417
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2634,7 +2634,7 @@ define i8 @flat_inst_valu_offset_64bit_13bit_neg_high_split0(ptr %p) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x1fff, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2693,7 +2693,7 @@ define i8 @flat_inst_valu_offset_64bit_13bit_neg_high_split1(ptr %p) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: flat_load_d16_u8 v0, v[0:1] offset:-8380416
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2707,7 +2707,7 @@ define i8 @flat_inst_valu_offset_64bit_13bit_neg_high_split1(ptr %p) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: flat_load_u8 v0, v[0:1] offset:-8380416
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2741,7 +2741,7 @@ define i8 @flat_inst_valu_offset_64bit_13bit_neg_high_split1(ptr %p) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-GISEL-NEXT: flat_load_u8 v0, v[0:1]
; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -4175,7 +4175,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_11bit_split0(ptr %p) {
; GFX12-SDAG-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0
; GFX12-SDAG-TRUE16-NEXT: flat_load_d16_u8 v0, v[0:1] offset:2047 scope:SCOPE_SYS
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -4187,7 +4187,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_11bit_split0(ptr %p) {
; GFX12-SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0
; GFX12-SDAG-FAKE16-NEXT: flat_load_u8 v0, v[0:1] offset:2047 scope:SCOPE_SYS
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -4294,7 +4294,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_11bit_split1(ptr %p) {
; GFX12-SDAG-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0
; GFX12-SDAG-TRUE16-NEXT: flat_load_d16_u8 v0, v[0:1] offset:2048 scope:SCOPE_SYS
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -4306,7 +4306,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_11bit_split1(ptr %p) {
; GFX12-SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0
; GFX12-SDAG-FAKE16-NEXT: flat_load_u8 v0, v[0:1] offset:2048 scope:SCOPE_SYS
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -4413,7 +4413,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_12bit_split0(ptr %p) {
; GFX12-SDAG-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0
; GFX12-SDAG-TRUE16-NEXT: flat_load_d16_u8 v0, v[0:1] offset:4095 scope:SCOPE_SYS
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -4425,7 +4425,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_12bit_split0(ptr %p) {
; GFX12-SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0
; GFX12-SDAG-FAKE16-NEXT: flat_load_u8 v0, v[0:1] offset:4095 scope:SCOPE_SYS
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -4533,7 +4533,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_12bit_split1(ptr %p) {
; GFX12-SDAG-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0
; GFX12-SDAG-TRUE16-NEXT: flat_load_d16_u8 v0, v[0:1] offset:4096 scope:SCOPE_SYS
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -4545,7 +4545,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_12bit_split1(ptr %p) {
; GFX12-SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0
; GFX12-SDAG-FAKE16-NEXT: flat_load_u8 v0, v[0:1] offset:4096 scope:SCOPE_SYS
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -4653,7 +4653,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_13bit_split0(ptr %p) {
; GFX12-SDAG-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0
; GFX12-SDAG-TRUE16-NEXT: flat_load_d16_u8 v0, v[0:1] offset:8191 scope:SCOPE_SYS
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -4665,7 +4665,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_13bit_split0(ptr %p) {
; GFX12-SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0
; GFX12-SDAG-FAKE16-NEXT: flat_load_u8 v0, v[0:1] offset:8191 scope:SCOPE_SYS
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -4773,7 +4773,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_13bit_split1(ptr %p) {
; GFX12-SDAG-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0
; GFX12-SDAG-TRUE16-NEXT: flat_load_d16_u8 v0, v[0:1] offset:8192 scope:SCOPE_SYS
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -4785,7 +4785,7 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_13bit_split1(ptr %p) {
; GFX12-SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0
; GFX12-SDAG-FAKE16-NEXT: flat_load_u8 v0, v[0:1] offset:8192 scope:SCOPE_SYS
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/offset-split-global.ll b/llvm/test/CodeGen/AMDGPU/offset-split-global.ll
index ef9d4aff3065e..60743d2cc18c6 100644
--- a/llvm/test/CodeGen/AMDGPU/offset-split-global.ll
+++ b/llvm/test/CodeGen/AMDGPU/offset-split-global.ll
@@ -1102,7 +1102,7 @@ define i8 @global_inst_valu_offset_2x_24bit_max(ptr addrspace(1) %p) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffffe, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-GISEL-NEXT: global_load_u8 v0, v[0:1], off
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
@@ -1154,7 +1154,7 @@ define i8 @global_inst_valu_offset_2x_24bit_max(ptr addrspace(1) %p) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: global_load_d16_u8 v0, v[0:1], off offset:8388606
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -1168,7 +1168,7 @@ define i8 @global_inst_valu_offset_2x_24bit_max(ptr addrspace(1) %p) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: global_load_u8 v0, v[0:1], off offset:8388606
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
@@ -1462,7 +1462,7 @@ define i8 @global_inst_valu_offset_2x_neg_24bit_max(ptr addrspace(1) %p) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0xff000001, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-GISEL-NEXT: global_load_u8 v0, v[0:1], off
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
@@ -1514,7 +1514,7 @@ define i8 @global_inst_valu_offset_2x_neg_24bit_max(ptr addrspace(1) %p) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xff800000, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: global_load_d16_u8 v0, v[0:1], off offset:-8388607
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -1528,7 +1528,7 @@ define i8 @global_inst_valu_offset_2x_neg_24bit_max(ptr addrspace(1) %p) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0xff800000, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: global_load_u8 v0, v[0:1], off offset:-8388607
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
@@ -1577,7 +1577,7 @@ define i8 @global_inst_valu_offset_64bit_11bit_split0(ptr addrspace(1) %p) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x7ff, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-GISEL-NEXT: global_load_u8 v0, v[0:1], off
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
@@ -1629,7 +1629,7 @@ define i8 @global_inst_valu_offset_64bit_11bit_split0(ptr addrspace(1) %p) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: global_load_d16_u8 v0, v[0:1], off offset:2047
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -1643,7 +1643,7 @@ define i8 @global_inst_valu_offset_64bit_11bit_split0(ptr addrspace(1) %p) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: global_load_u8 v0, v[0:1], off offset:2047
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
@@ -1691,7 +1691,7 @@ define i8 @global_inst_valu_offset_64bit_11bit_split1(ptr addrspace(1) %p) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-GISEL-NEXT: global_load_u8 v0, v[0:1], off
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
@@ -1734,7 +1734,7 @@ define i8 @global_inst_valu_offset_64bit_11bit_split1(ptr addrspace(1) %p) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: global_load_d16_u8 v0, v[0:1], off offset:2048
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -1748,7 +1748,7 @@ define i8 @global_inst_valu_offset_64bit_11bit_split1(ptr addrspace(1) %p) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: global_load_u8 v0, v[0:1], off offset:2048
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
@@ -1796,7 +1796,7 @@ define i8 @global_inst_valu_offset_64bit_12bit_split0(ptr addrspace(1) %p) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0xfff, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-GISEL-NEXT: global_load_u8 v0, v[0:1], off
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
@@ -1848,7 +1848,7 @@ define i8 @global_inst_valu_offset_64bit_12bit_split0(ptr addrspace(1) %p) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: global_load_d16_u8 v0, v[0:1], off offset:4095
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -1862,7 +1862,7 @@ define i8 @global_inst_valu_offset_64bit_12bit_split0(ptr addrspace(1) %p) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: global_load_u8 v0, v[0:1], off offset:4095
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
@@ -1910,7 +1910,7 @@ define i8 @global_inst_valu_offset_64bit_12bit_split1(ptr addrspace(1) %p) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-GISEL-NEXT: global_load_u8 v0, v[0:1], off
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
@@ -1944,7 +1944,7 @@ define i8 @global_inst_valu_offset_64bit_12bit_split1(ptr addrspace(1) %p) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: global_load_d16_u8 v0, v[0:1], off offset:4096
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -1958,7 +1958,7 @@ define i8 @global_inst_valu_offset_64bit_12bit_split1(ptr addrspace(1) %p) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: global_load_u8 v0, v[0:1], off offset:4096
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
@@ -2006,7 +2006,7 @@ define i8 @global_inst_valu_offset_64bit_13bit_split0(ptr addrspace(1) %p) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x1fff, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-GISEL-NEXT: global_load_u8 v0, v[0:1], off
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
@@ -2058,7 +2058,7 @@ define i8 @global_inst_valu_offset_64bit_13bit_split0(ptr addrspace(1) %p) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: global_load_d16_u8 v0, v[0:1], off offset:8191
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -2072,7 +2072,7 @@ define i8 @global_inst_valu_offset_64bit_13bit_split0(ptr addrspace(1) %p) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: global_load_u8 v0, v[0:1], off offset:8191
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
@@ -2120,7 +2120,7 @@ define i8 @global_inst_valu_offset_64bit_13bit_split1(ptr addrspace(1) %p) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-GISEL-NEXT: global_load_u8 v0, v[0:1], off
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
@@ -2154,7 +2154,7 @@ define i8 @global_inst_valu_offset_64bit_13bit_split1(ptr addrspace(1) %p) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: global_load_d16_u8 v0, v[0:1], off offset:8192
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -2168,7 +2168,7 @@ define i8 @global_inst_valu_offset_64bit_13bit_split1(ptr addrspace(1) %p) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: global_load_u8 v0, v[0:1], off offset:8192
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
@@ -2217,7 +2217,7 @@ define i8 @global_inst_valu_offset_64bit_11bit_neg_high_split0(ptr addrspace(1)
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x7ff, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-GISEL-NEXT: global_load_u8 v0, v[0:1], off
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
@@ -2270,7 +2270,7 @@ define i8 @global_inst_valu_offset_64bit_11bit_neg_high_split0(ptr addrspace(1)
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: global_load_d16_u8 v0, v[0:1], off offset:-8386561
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -2284,7 +2284,7 @@ define i8 @global_inst_valu_offset_64bit_11bit_neg_high_split0(ptr addrspace(1)
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: global_load_u8 v0, v[0:1], off offset:-8386561
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
@@ -2333,7 +2333,7 @@ define i8 @global_inst_valu_offset_64bit_11bit_neg_high_split1(ptr addrspace(1)
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-GISEL-NEXT: global_load_u8 v0, v[0:1], off
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
@@ -2377,7 +2377,7 @@ define i8 @global_inst_valu_offset_64bit_11bit_neg_high_split1(ptr addrspace(1)
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: global_load_d16_u8 v0, v[0:1], off offset:-8386560
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -2391,7 +2391,7 @@ define i8 @global_inst_valu_offset_64bit_11bit_neg_high_split1(ptr addrspace(1)
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: global_load_u8 v0, v[0:1], off offset:-8386560
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
@@ -2440,7 +2440,7 @@ define i8 @global_inst_valu_offset_64bit_12bit_neg_high_split0(ptr addrspace(1)
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0xfff, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-GISEL-NEXT: global_load_u8 v0, v[0:1], off
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
@@ -2493,7 +2493,7 @@ define i8 @global_inst_valu_offset_64bit_12bit_neg_high_split0(ptr addrspace(1)
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: global_load_d16_u8 v0, v[0:1], off offset:-8384513
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -2507,7 +2507,7 @@ define i8 @global_inst_valu_offset_64bit_12bit_neg_high_split0(ptr addrspace(1)
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: global_load_u8 v0, v[0:1], off offset:-8384513
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
@@ -2556,7 +2556,7 @@ define i8 @global_inst_valu_offset_64bit_12bit_neg_high_split1(ptr addrspace(1)
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-GISEL-NEXT: global_load_u8 v0, v[0:1], off
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
@@ -2600,7 +2600,7 @@ define i8 @global_inst_valu_offset_64bit_12bit_neg_high_split1(ptr addrspace(1)
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: global_load_d16_u8 v0, v[0:1], off offset:-8384512
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -2614,7 +2614,7 @@ define i8 @global_inst_valu_offset_64bit_12bit_neg_high_split1(ptr addrspace(1)
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: global_load_u8 v0, v[0:1], off offset:-8384512
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
@@ -2663,7 +2663,7 @@ define i8 @global_inst_valu_offset_64bit_13bit_neg_high_split0(ptr addrspace(1)
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x1fff, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-GISEL-NEXT: global_load_u8 v0, v[0:1], off
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
@@ -2716,7 +2716,7 @@ define i8 @global_inst_valu_offset_64bit_13bit_neg_high_split0(ptr addrspace(1)
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: global_load_d16_u8 v0, v[0:1], off offset:-8380417
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -2730,7 +2730,7 @@ define i8 @global_inst_valu_offset_64bit_13bit_neg_high_split0(ptr addrspace(1)
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: global_load_u8 v0, v[0:1], off offset:-8380417
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
@@ -2779,7 +2779,7 @@ define i8 @global_inst_valu_offset_64bit_13bit_neg_high_split1(ptr addrspace(1)
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-GISEL-NEXT: global_load_u8 v0, v[0:1], off
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
@@ -2823,7 +2823,7 @@ define i8 @global_inst_valu_offset_64bit_13bit_neg_high_split1(ptr addrspace(1)
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: global_load_d16_u8 v0, v[0:1], off offset:-8380416
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -2837,7 +2837,7 @@ define i8 @global_inst_valu_offset_64bit_13bit_neg_high_split1(ptr addrspace(1)
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0x80000000, v1, vcc_lo
; GFX12-SDAG-FAKE16-NEXT: global_load_u8 v0, v[0:1], off offset:-8380416
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
@@ -4155,7 +4155,7 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_11bit_split0(ptr addrsp
; GFX12-SDAG-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0
; GFX12-SDAG-TRUE16-NEXT: global_load_d16_u8 v0, v[0:1], off offset:2047 scope:SCOPE_SYS
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -4167,7 +4167,7 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_11bit_split0(ptr addrsp
; GFX12-SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0
; GFX12-SDAG-FAKE16-NEXT: global_load_u8 v0, v[0:1], off offset:2047 scope:SCOPE_SYS
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
@@ -4272,7 +4272,7 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_11bit_split1(ptr addrsp
; GFX12-SDAG-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0
; GFX12-SDAG-TRUE16-NEXT: global_load_d16_u8 v0, v[0:1], off offset:2048 scope:SCOPE_SYS
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -4284,7 +4284,7 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_11bit_split1(ptr addrsp
; GFX12-SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0
; GFX12-SDAG-FAKE16-NEXT: global_load_u8 v0, v[0:1], off offset:2048 scope:SCOPE_SYS
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
@@ -4389,7 +4389,7 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_12bit_split0(ptr addrsp
; GFX12-SDAG-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0
; GFX12-SDAG-TRUE16-NEXT: global_load_d16_u8 v0, v[0:1], off offset:4095 scope:SCOPE_SYS
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -4401,7 +4401,7 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_12bit_split0(ptr addrsp
; GFX12-SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0
; GFX12-SDAG-FAKE16-NEXT: global_load_u8 v0, v[0:1], off offset:4095 scope:SCOPE_SYS
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
@@ -4506,7 +4506,7 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_12bit_split1(ptr addrsp
; GFX12-SDAG-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0
; GFX12-SDAG-TRUE16-NEXT: global_load_d16_u8 v0, v[0:1], off offset:4096 scope:SCOPE_SYS
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -4518,7 +4518,7 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_12bit_split1(ptr addrsp
; GFX12-SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0
; GFX12-SDAG-FAKE16-NEXT: global_load_u8 v0, v[0:1], off offset:4096 scope:SCOPE_SYS
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
@@ -4623,7 +4623,7 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_13bit_split0(ptr addrsp
; GFX12-SDAG-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0
; GFX12-SDAG-TRUE16-NEXT: global_load_d16_u8 v0, v[0:1], off offset:8191 scope:SCOPE_SYS
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -4635,7 +4635,7 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_13bit_split0(ptr addrsp
; GFX12-SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0
; GFX12-SDAG-FAKE16-NEXT: global_load_u8 v0, v[0:1], off offset:8191 scope:SCOPE_SYS
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
@@ -4740,7 +4740,7 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_13bit_split1(ptr addrsp
; GFX12-SDAG-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0
; GFX12-SDAG-TRUE16-NEXT: global_load_d16_u8 v0, v[0:1], off offset:8192 scope:SCOPE_SYS
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -4752,7 +4752,7 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_13bit_split1(ptr addrsp
; GFX12-SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_add_co_u32 v0, s0, 0, s0
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0
; GFX12-SDAG-FAKE16-NEXT: global_load_u8 v0, v[0:1], off offset:8192 scope:SCOPE_SYS
; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/partial-forwarding-hazards.mir b/llvm/test/CodeGen/AMDGPU/partial-forwarding-hazards.mir
index 5659e70cb7db7..052459a44d341 100644
--- a/llvm/test/CodeGen/AMDGPU/partial-forwarding-hazards.mir
+++ b/llvm/test/CodeGen/AMDGPU/partial-forwarding-hazards.mir
@@ -10,7 +10,7 @@ body: |
; GFX11: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
; GFX11-NEXT: $exec = S_MOV_B64 -1
; GFX11-NEXT: $vgpr1 = V_MOV_B32_e32 0, implicit $exec
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 4095
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 3999
; GFX11-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr0, $vgpr1, implicit $mode, implicit $exec
; GFX11-NEXT: S_ENDPGM 0
;
@@ -46,7 +46,7 @@ body: |
; GFX11-NEXT: $sgpr8 = S_MOV_B32 0
; GFX11-NEXT: $sgpr9 = S_MOV_B32 0
; GFX11-NEXT: $sgpr10 = S_MOV_B32 0
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 4095
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 3999
; GFX11-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr0, $vgpr1, implicit $mode, implicit $exec
; GFX11-NEXT: S_ENDPGM 0
;
@@ -99,7 +99,7 @@ body: |
; GFX11-NEXT: $vgpr13 = V_MOV_B32_e32 0, implicit $exec
; GFX11-NEXT: $vgpr14 = V_MOV_B32_e32 0, implicit $exec
; GFX11-NEXT: $vgpr15 = V_MOV_B32_e32 0, implicit $exec
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 4095
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 3999
; GFX11-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr0, $vgpr1, implicit $mode, implicit $exec
; GFX11-NEXT: S_ENDPGM 0
;
@@ -235,7 +235,7 @@ body: |
; GFX11-NEXT: $vgpr13 = V_MOV_B32_e32 0, implicit $exec
; GFX11-NEXT: $vgpr14 = V_MOV_B32_e32 0, implicit $exec
; GFX11-NEXT: $vgpr15 = V_MOV_B32_e32 0, implicit $exec
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 4095
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 3999
; GFX11-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr0, $vgpr1, implicit $mode, implicit $exec
; GFX11-NEXT: S_ENDPGM 0
;
@@ -309,7 +309,7 @@ body: |
; GFX11-NEXT: $vgpr13 = V_MOV_B32_e32 0, implicit $exec
; GFX11-NEXT: $vgpr14 = V_MOV_B32_e32 0, implicit $exec
; GFX11-NEXT: $vgpr15 = V_MOV_B32_e32 0, implicit $exec
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 4095
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 3999
; GFX11-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr0, $vgpr1, implicit $mode, implicit $exec
; GFX11-NEXT: S_ENDPGM 0
;
@@ -396,7 +396,7 @@ body: |
; GFX11-NEXT: $vgpr13 = V_MOV_B32_e32 0, implicit $exec
; GFX11-NEXT: $vgpr14 = V_MOV_B32_e32 0, implicit $exec
; GFX11-NEXT: $vgpr15 = V_MOV_B32_e32 0, implicit $exec
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 4095
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 3999
; GFX11-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr0, $vgpr1, implicit $mode, implicit $exec
; GFX11-NEXT: S_ENDPGM 0
;
@@ -474,7 +474,7 @@ body: |
; GFX11-NEXT: $vgpr13 = V_MOV_B32_e32 0, implicit $exec
; GFX11-NEXT: $vgpr14 = V_MOV_B32_e32 0, implicit $exec
; GFX11-NEXT: $vgpr15 = V_MOV_B32_e32 0, implicit $exec
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 4095
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 3999
; GFX11-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr0, $vgpr1, implicit $mode, implicit $exec
; GFX11-NEXT: S_ENDPGM 0
;
diff --git a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
index d957aaa8a48ad..328a2dbbd4b0d 100644
--- a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
+++ b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
@@ -14,7 +14,7 @@ define amdgpu_cs float @v_s_exp_f32(float inreg %src) {
; GFX12-SDAG-NEXT: v_s_exp_f32 s0, s0
; GFX12-SDAG-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
; GFX12-SDAG-NEXT: s_mul_f32 s0, s0, s1
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX12-SDAG-NEXT: ; return to shader part epilog
;
@@ -26,7 +26,7 @@ define amdgpu_cs float @v_s_exp_f32(float inreg %src) {
; GFX12-GISEL-NEXT: s_add_f32 s0, s0, s1
; GFX12-GISEL-NEXT: s_cselect_b32 s1, 0xffffffc0, 0
; GFX12-GISEL-NEXT: v_s_exp_f32 s0, s0
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
; GFX12-GISEL-NEXT: v_ldexp_f32 v0, s0, s1
; GFX12-GISEL-NEXT: ; return to shader part epilog
@@ -38,7 +38,7 @@ define amdgpu_cs half @v_s_exp_f16(half inreg %src) {
; GFX12-LABEL: v_s_exp_f16:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_s_exp_f16 s0, s0
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: ; return to shader part epilog
@@ -50,7 +50,7 @@ define amdgpu_cs float @v_s_amdgcn_exp_f32(float inreg %src) {
; GFX12-LABEL: v_s_amdgcn_exp_f32:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_s_exp_f32 s0, s0
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: ; return to shader part epilog
@@ -62,7 +62,7 @@ define amdgpu_cs half @v_s_amdgcn_exp_f16(half inreg %src) {
; GFX12-LABEL: v_s_amdgcn_exp_f16:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_s_exp_f16 s0, s0
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: ; return to shader part epilog
@@ -81,7 +81,7 @@ define amdgpu_cs float @v_s_log_f32(float inreg %src) {
; GFX12-SDAG-NEXT: v_s_log_f32 s0, s0
; GFX12-SDAG-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
; GFX12-SDAG-NEXT: s_sub_f32 s0, s0, s1
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX12-SDAG-NEXT: ; return to shader part epilog
;
@@ -95,7 +95,7 @@ define amdgpu_cs float @v_s_log_f32(float inreg %src) {
; GFX12-GISEL-NEXT: v_ldexp_f32 v0, s0, s2
; GFX12-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
; GFX12-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
; GFX12-GISEL-NEXT: v_subrev_f32_e32 v0, s0, v0
; GFX12-GISEL-NEXT: ; return to shader part epilog
@@ -107,7 +107,7 @@ define amdgpu_cs half @v_s_log_f16(half inreg %src) {
; GFX12-LABEL: v_s_log_f16:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_s_log_f16 s0, s0
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: ; return to shader part epilog
@@ -119,7 +119,7 @@ define amdgpu_cs float @v_s_amdgcn_log_f32(float inreg %src) {
; GFX12-LABEL: v_s_amdgcn_log_f32:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_s_log_f32 s0, s0
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: ; return to shader part epilog
@@ -131,7 +131,7 @@ define amdgpu_cs half @v_s_amdgcn_log_f16(half inreg %src) {
; GFX12-LABEL: v_s_amdgcn_log_f16:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_s_log_f16 s0, s0
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: ; return to shader part epilog
@@ -143,7 +143,7 @@ define amdgpu_cs float @v_s_rcp_f32(float inreg %src) {
; GFX12-LABEL: v_s_rcp_f32:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_s_rcp_f32 s0, s0
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: ; return to shader part epilog
@@ -155,7 +155,7 @@ define amdgpu_cs half @v_s_rcp_f16(half inreg %src) {
; GFX12-LABEL: v_s_rcp_f16:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_s_rcp_f16 s0, s0
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: ; return to shader part epilog
@@ -168,7 +168,7 @@ define amdgpu_cs float @v_s_rsq_f32(float inreg %src) {
; GFX12-SDAG-LABEL: v_s_rsq_f32:
; GFX12-SDAG: ; %bb.0:
; GFX12-SDAG-NEXT: v_s_rsq_f32 s0, s0
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX12-SDAG-NEXT: ; return to shader part epilog
@@ -176,10 +176,10 @@ define amdgpu_cs float @v_s_rsq_f32(float inreg %src) {
; GFX12-GISEL-LABEL: v_s_rsq_f32:
; GFX12-GISEL: ; %bb.0:
; GFX12-GISEL-NEXT: v_s_sqrt_f32 s0, s0
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
; GFX12-GISEL-NEXT: v_s_rcp_f32 s0, s0
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX12-GISEL-NEXT: ; return to shader part epilog
%sqrt = call fast float @llvm.sqrt.f32(float %src)
@@ -191,7 +191,7 @@ define amdgpu_cs half @v_s_rsq_f16(half inreg %src) {
; GFX12-LABEL: v_s_rsq_f16:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_s_rsq_f16 s0, s0
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: ; return to shader part epilog
@@ -228,13 +228,13 @@ define amdgpu_cs float @v_s_sqrt_f32(float inreg %src) {
; GFX12-SDAG-NEXT: s_cmp_lt_f32 s0, 0xf800000
; GFX12-SDAG-NEXT: s_mul_f32 s0, s2, 0x37800000
; GFX12-SDAG-NEXT: v_cmp_class_f32_e64 s3, s1, 0x260
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-SDAG-NEXT: s_cselect_b32 s0, s0, s2
; GFX12-SDAG-NEXT: s_and_b32 s2, s3, exec_lo
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: s_cselect_b32 s0, s1, s0
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX12-SDAG-NEXT: ; return to shader part epilog
;
@@ -263,12 +263,12 @@ define amdgpu_cs float @v_s_sqrt_f32(float inreg %src) {
; GFX12-GISEL-NEXT: s_cselect_b32 s2, s5, s2
; GFX12-GISEL-NEXT: s_cmp_lg_u32 s1, 0
; GFX12-GISEL-NEXT: s_mul_f32 s3, s2, 0x37800000
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: s_cselect_b32 s1, s3, s2
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s1
; GFX12-GISEL-NEXT: v_cmp_class_f32_e64 s1, s0, 0x260
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, s0, s1
; GFX12-GISEL-NEXT: ; return to shader part epilog
%result = call float @llvm.sqrt.f32(float %src)
@@ -279,7 +279,7 @@ define amdgpu_cs half @v_s_sqrt_f16(half inreg %src) {
; GFX12-LABEL: v_s_sqrt_f16:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_s_sqrt_f16 s0, s0
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: ; return to shader part epilog
@@ -291,7 +291,7 @@ define amdgpu_cs float @v_amdgcn_sqrt_f32(float inreg %src) {
; GFX12-LABEL: v_amdgcn_sqrt_f32:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_s_sqrt_f32 s0, s0
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: ; return to shader part epilog
@@ -303,7 +303,7 @@ define amdgpu_cs half @v_amdgcn_sqrt_f16(half inreg %src) {
; GFX12-LABEL: v_amdgcn_sqrt_f16:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_s_sqrt_f16 s0, s0
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: ; return to shader part epilog
@@ -323,7 +323,7 @@ define amdgpu_cs float @srcmods_abs_f32(float inreg %src) {
; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX12-SDAG-NEXT: v_s_log_f32 s0, s0
; GFX12-SDAG-NEXT: s_sub_f32 s0, s0, s1
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX12-SDAG-NEXT: ; return to shader part epilog
@@ -340,7 +340,7 @@ define amdgpu_cs float @srcmods_abs_f32(float inreg %src) {
; GFX12-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
; GFX12-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: v_subrev_f32_e32 v0, s0, v0
; GFX12-GISEL-NEXT: ; return to shader part epilog
%abs = call float @llvm.fabs.f32(float %src)
@@ -360,7 +360,7 @@ define amdgpu_cs float @srcmods_neg_f32(float inreg %src) {
; GFX12-SDAG-NEXT: v_s_log_f32 s0, s0
; GFX12-SDAG-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
; GFX12-SDAG-NEXT: s_sub_f32 s0, s0, s1
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX12-SDAG-NEXT: ; return to shader part epilog
;
@@ -376,7 +376,7 @@ define amdgpu_cs float @srcmods_neg_f32(float inreg %src) {
; GFX12-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
; GFX12-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: v_subrev_f32_e32 v0, s0, v0
; GFX12-GISEL-NEXT: ; return to shader part epilog
%neg = fneg float %src
@@ -388,7 +388,7 @@ define amdgpu_cs half @srcmods_abs_f16(half inreg %src) {
; GFX12-LABEL: srcmods_abs_f16:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_s_log_f16 s0, |s0|
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: ; return to shader part epilog
@@ -401,7 +401,7 @@ define amdgpu_cs half @srcmods_neg_f16(half inreg %src) {
; GFX12-LABEL: srcmods_neg_f16:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_s_log_f16 s0, -s0
-; GFX12-NEXT: s_wait_alu 0xf1ff
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: ; return to shader part epilog
@@ -426,7 +426,7 @@ define amdgpu_cs float @fdiv_f32_i32(float inreg %a, i32 inreg %b) {
; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX12-GISEL-NEXT: v_s_rcp_f32 s1, s1
; GFX12-GISEL-NEXT: s_mul_f32 s0, s0, s1
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX12-GISEL-NEXT: ; return to shader part epilog
diff --git a/llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll b/llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll
index f4f5a78f0e2b6..2e15c37bc19fb 100644
--- a/llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll
+++ b/llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll
@@ -59,11 +59,11 @@ define ptr @gep_as0(ptr %p, i64 %offset) {
; GFX12-NEXT: v_lshlrev_b64_e32 v[2:3], 2, v[2:3]
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, 5
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -214,11 +214,11 @@ define ptr @multi_gep_as0(ptr %p, i64 %offset) {
; GFX12-NEXT: v_lshlrev_b64_e32 v[2:3], 2, v[2:3]
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, 5
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/repeated-divisor.ll b/llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
index d34d2050b157e..624f4480e689a 100644
--- a/llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
+++ b/llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
@@ -69,7 +69,7 @@ define <2 x float> @v_repeat_divisor_f32_x2(float %x, float %y, float %D) #0 {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_rcp_f32_e32 v5, v3
; GFX11-NEXT: v_rcp_f32_e32 v6, v4
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v7, -v3, v5, 1.0
; GFX11-NEXT: v_fma_f32 v8, -v4, v6, 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
@@ -146,7 +146,7 @@ define <2 x float> @v_repeat_divisor_f32_x2_arcp(float %x, float %y, float %D) #
; GFX11-NEXT: v_div_scale_f32 v6, vcc_lo, 1.0, v2, 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f32_e32 v4, v3
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v5, -v3, v4, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v4, v5, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -218,7 +218,7 @@ define <2 x float> @v_repeat_divisor_f32_x2_arcp_daz(float %x, float %y, float %
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f32_e32 v4, v3
; GFX11-NEXT: s_denorm_mode 15
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v6, -v3, v4, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v4, v6, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -280,7 +280,7 @@ define <2 x half> @v_repeat_divisor_f16_x2_arcp(half %x, half %y, half %D) #0 {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_rcp_f16_e32 v2.l, v2.l
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v2.l
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.h, v1.l, v2.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -291,7 +291,7 @@ define <2 x half> @v_repeat_divisor_f16_x2_arcp(half %x, half %y, half %D) #0 {
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_rcp_f16_e32 v2, v2
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v2
; GFX11-FAKE16-NEXT: v_mul_f16_e32 v1, v1, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -352,7 +352,7 @@ define <2 x double> @v_repeat_divisor_f64_x2_arcp(double %x, double %y, double %
; GFX11-NEXT: v_div_scale_f64 v[12:13], vcc_lo, 1.0, v[4:5], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f64_e32 v[8:9], v[6:7]
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
; GFX11-NEXT: v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -421,7 +421,7 @@ define <3 x float> @v_repeat_divisor_f32_x3_arcp(float %x, float %y, float %z, f
; GFX11-NEXT: v_div_scale_f32 v7, vcc_lo, 1.0, v3, 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f32_e32 v5, v4
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v6, -v4, v5, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -495,7 +495,7 @@ define <4 x float> @v_repeat_divisor_f32_x4_arcp(float %x, float %y, float %z, f
; GFX11-NEXT: v_div_scale_f32 v8, vcc_lo, 1.0, v4, 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f32_e32 v6, v5
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v7, -v5, v6, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v6, v7, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -566,7 +566,7 @@ define <3 x half> @v_repeat_divisor_f16_x3_arcp(half %x, half %y, half %z, half
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_rcp_f16_e32 v3.l, v3.l
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v3.l
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.h, v1.l, v3.l
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v1.l, v2.l, v3.l
@@ -578,7 +578,7 @@ define <3 x half> @v_repeat_divisor_f16_x3_arcp(half %x, half %y, half %z, half
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_rcp_f16_e32 v3, v3
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v3
; GFX11-FAKE16-NEXT: v_mul_f16_e32 v1, v1, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -667,7 +667,7 @@ define <4 x float> @v_repeat_divisor_v2f32_x2(<2 x float> %x, <2 x float> %y, <2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_rcp_f32_e32 v8, v6
; GFX11-NEXT: v_rcp_f32_e32 v9, v7
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_fma_f32 v10, -v6, v8, 1.0
; GFX11-NEXT: v_fma_f32 v11, -v7, v9, 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
@@ -737,7 +737,7 @@ define <2 x float> @v_repeat_divisor_f32_x2_ulp25(float %x, float %y, float %D)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f32_e32 v3, v3
; GFX11-NEXT: v_sub_nc_u32_e32 v2, 0, v2
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_ldexp_f32 v2, v3, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v2
@@ -771,7 +771,7 @@ define <2 x float> @v_repeat_divisor_f32_x2_daz_ulp25(float %x, float %y, float
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_rcp_f32_e32 v2, v2
-; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX11-NEXT: v_mul_f32_e32 v1, v1, v2
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -841,7 +841,7 @@ define <4 x half> @v_repeat_divisor_v2f16_x2(<2 x half> %x, <2 x half> %y, <2 x
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_rcp_f16_e32 v2.h, v2.h
; GFX11-TRUE16-NEXT: v_rcp_f16_e32 v2.l, v2.l
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_pack_b32_f16 v2, v2.l, v2.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_pk_mul_f16 v0, v0, v2
@@ -855,7 +855,7 @@ define <4 x half> @v_repeat_divisor_v2f16_x2(<2 x half> %x, <2 x half> %y, <2 x
; GFX11-FAKE16-NEXT: v_rcp_f16_e32 v2, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_rcp_f16_e32 v3, v3
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v2, v2, v3
; GFX11-FAKE16-NEXT: v_pk_mul_f16 v0, v0, v2
; GFX11-FAKE16-NEXT: v_pk_mul_f16 v1, v1, v2
@@ -952,7 +952,7 @@ define <6 x half> @v_repeat_divisor_v3f16_x2(<3 x half> %x, <3 x half> %y, <3 x
; GFX11-TRUE16-NEXT: v_rcp_f16_e32 v4.h, v4.h
; GFX11-TRUE16-NEXT: v_rcp_f16_e32 v5.l, v5.l
; GFX11-TRUE16-NEXT: v_rcp_f16_e32 v4.l, v4.l
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_pack_b32_f16 v5, v5.l, 0x7e00
; GFX11-TRUE16-NEXT: v_pack_b32_f16 v4, v4.l, v4.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -975,7 +975,7 @@ define <6 x half> @v_repeat_divisor_v3f16_x2(<3 x half> %x, <3 x half> %y, <3 x
; GFX11-FAKE16-NEXT: v_rcp_f16_e32 v5, v5
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_rcp_f16_e32 v6, v6
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v5, v5, 0x7e00
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v4, v4, v6
; GFX11-FAKE16-NEXT: v_pk_mul_f16 v1, v1, v5
diff --git a/llvm/test/CodeGen/AMDGPU/s-barrier.ll b/llvm/test/CodeGen/AMDGPU/s-barrier.ll
index 4c7cef9cc1a0f..6e51c870cd487 100644
--- a/llvm/test/CodeGen/AMDGPU/s-barrier.ll
+++ b/llvm/test/CodeGen/AMDGPU/s-barrier.ll
@@ -118,10 +118,10 @@ define amdgpu_kernel void @kernel1(ptr addrspace(1) %out, ptr addrspace(3) %in)
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX12-SDAG-NEXT: s_getpc_b64 s[2:3]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: s_sext_i32_i16 s3, s3
; GFX12-SDAG-NEXT: s_add_co_u32 s2, s2, func2 at gotpcrel32@lo+12
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: s_add_co_ci_u32 s3, s3, func2 at gotpcrel32@hi+24
; GFX12-SDAG-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
@@ -178,10 +178,10 @@ define amdgpu_kernel void @kernel1(ptr addrspace(1) %out, ptr addrspace(3) %in)
; GFX12-GISEL-NEXT: s_add_co_u32 s8, s12, 48
; GFX12-GISEL-NEXT: s_add_co_ci_u32 s9, s13, 0
; GFX12-GISEL-NEXT: s_getpc_b64 s[0:1]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: s_sext_i32_i16 s1, s1
; GFX12-GISEL-NEXT: s_add_co_u32 s0, s0, func2 at gotpcrel32@lo+12
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s1, func2 at gotpcrel32@hi+24
; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll b/llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
index dba10f19eb500..9d8a54b4cc178 100644
--- a/llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
+++ b/llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
@@ -63,11 +63,11 @@ define void @test_remat_s_getpc_b64() {
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_store_b32 off, v2, s32 ; 4-byte Folded Spill
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: v_writelane_b32 v2, s30, 0
; GFX12-NEXT: s_getpc_b64 s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_sext_i32_i16 s1, s1
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ;;#ASMEND
@@ -75,16 +75,16 @@ define void @test_remat_s_getpc_b64() {
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ;;#ASMEND
; GFX12-NEXT: s_getpc_b64 s[0:1]
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_sext_i32_i16 s1, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-NEXT: v_readlane_b32 s31, v2, 1
; GFX12-NEXT: v_readlane_b32 s30, v2, 0
; GFX12-NEXT: global_store_b64 v[0:1], v[0:1], off
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_load_b32 v2, off, s32 ; 4-byte Folded Reload
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll b/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
index 1b7112ef4ddca..09f7e7a926376 100644
--- a/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
@@ -31,7 +31,7 @@ define float @v_test_fmin_legacy_ule_f32_safe(float %a, float %b) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v1
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ule float %a, %b
@@ -61,7 +61,7 @@ define float @v_test_fmin_legacy_ule_f32_nnan_flag(float %a, float %b) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v1
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ule float %a, %b
@@ -91,7 +91,7 @@ define float @v_test_fmin_legacy_ule_f32_nsz_flag(float %a, float %b) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v1
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ule float %a, %b
@@ -148,7 +148,7 @@ define float @v_test_fmax_legacy_uge_f32_safe(float %a, float %b) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v1
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp uge float %a, %b
@@ -178,7 +178,7 @@ define float @v_test_fmax_legacy_uge_f32_nnan_flag(float %a, float %b) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v1
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp uge float %a, %b
@@ -208,7 +208,7 @@ define float @v_test_fmax_legacy_uge_f32_nsz_flag(float %a, float %b) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v1
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp uge float %a, %b
@@ -268,10 +268,10 @@ define <2 x float> @v_test_fmin_legacy_ule_v2f32_safe(<2 x float> %a, <2 x float
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v1, v3
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ule <2 x float> %a, %b
@@ -304,10 +304,10 @@ define <2 x float> @v_test_fmin_legacy_ule_v2f32_nnan_flag(<2 x float> %a, <2 x
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v1, v3
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ule <2 x float> %a, %b
@@ -340,10 +340,10 @@ define <2 x float> @v_test_fmin_legacy_ule_v2f32_nsz_flag(<2 x float> %a, <2 x f
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v1, v3
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ule <2 x float> %a, %b
@@ -405,10 +405,10 @@ define <2 x float> @v_test_fmax_legacy_uge_v2f32_safe(<2 x float> %a, <2 x float
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v1, v3
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp uge <2 x float> %a, %b
@@ -441,10 +441,10 @@ define <2 x float> @v_test_fmax_legacy_uge_v2f32_nnan_flag(<2 x float> %a, <2 x
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v1, v3
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp uge <2 x float> %a, %b
@@ -477,10 +477,10 @@ define <2 x float> @v_test_fmax_legacy_uge_v2f32_nsz_flag(<2 x float> %a, <2 x f
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v1, v3
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp uge <2 x float> %a, %b
@@ -543,7 +543,7 @@ define half @v_test_fmin_legacy_ule_f16_safe(half %a, half %b) {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.l, v1.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -555,7 +555,7 @@ define half @v_test_fmin_legacy_ule_f16_safe(half %a, half %b) {
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ule half %a, %b
@@ -589,7 +589,7 @@ define half @v_test_fmin_legacy_ule_f16_nnan_flag(half %a, half %b) {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.l, v1.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -601,7 +601,7 @@ define half @v_test_fmin_legacy_ule_f16_nnan_flag(half %a, half %b) {
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ule half %a, %b
@@ -635,7 +635,7 @@ define half @v_test_fmin_legacy_ule_f16_nsz_flag(half %a, half %b) {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.l, v1.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -647,7 +647,7 @@ define half @v_test_fmin_legacy_ule_f16_nsz_flag(half %a, half %b) {
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ule half %a, %b
@@ -722,7 +722,7 @@ define half @v_test_fmax_legacy_uge_f16_safe(half %a, half %b) {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.l, v1.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -734,7 +734,7 @@ define half @v_test_fmax_legacy_uge_f16_safe(half %a, half %b) {
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp uge half %a, %b
@@ -768,7 +768,7 @@ define half @v_test_fmax_legacy_uge_f16_nnan_flag(half %a, half %b) {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.l, v1.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -780,7 +780,7 @@ define half @v_test_fmax_legacy_uge_f16_nnan_flag(half %a, half %b) {
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp uge half %a, %b
@@ -814,7 +814,7 @@ define half @v_test_fmax_legacy_uge_f16_nsz_flag(half %a, half %b) {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.l, v1.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -826,7 +826,7 @@ define half @v_test_fmax_legacy_uge_f16_nsz_flag(half %a, half %b) {
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp uge half %a, %b
@@ -913,9 +913,9 @@ define <2 x half> @v_test_fmin_legacy_ule_v2f16_safe(<2 x half> %a, <2 x half> %
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.h, v1.h
; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.l, v1.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -931,10 +931,10 @@ define <2 x half> @v_test_fmin_legacy_ule_v2f16_safe(<2 x half> %a, <2 x half> %
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
@@ -982,9 +982,9 @@ define <2 x half> @v_test_fmin_legacy_ule_v2f16_nnan_flag(<2 x half> %a, <2 x ha
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.h, v1.h
; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.l, v1.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1000,10 +1000,10 @@ define <2 x half> @v_test_fmin_legacy_ule_v2f16_nnan_flag(<2 x half> %a, <2 x ha
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
@@ -1051,9 +1051,9 @@ define <2 x half> @v_test_fmin_legacy_ule_v2f16_nsz_flag(<2 x half> %a, <2 x hal
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.h, v1.h
; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.l, v1.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1069,10 +1069,10 @@ define <2 x half> @v_test_fmin_legacy_ule_v2f16_nsz_flag(<2 x half> %a, <2 x hal
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
@@ -1156,9 +1156,9 @@ define <2 x half> @v_test_fmax_legacy_uge_v2f16_safe(<2 x half> %a, <2 x half> %
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.h, v1.h
; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v0.l, v1.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1174,10 +1174,10 @@ define <2 x half> @v_test_fmax_legacy_uge_v2f16_safe(<2 x half> %a, <2 x half> %
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
@@ -1225,9 +1225,9 @@ define <2 x half> @v_test_fmax_legacy_uge_v2f16_nnan_flag(<2 x half> %a, <2 x ha
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.h, v1.h
; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v0.l, v1.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1243,10 +1243,10 @@ define <2 x half> @v_test_fmax_legacy_uge_v2f16_nnan_flag(<2 x half> %a, <2 x ha
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
@@ -1294,9 +1294,9 @@ define <2 x half> @v_test_fmax_legacy_uge_v2f16_nsz_flag(<2 x half> %a, <2 x hal
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.h, v1.h
; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v0.l, v1.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1312,10 +1312,10 @@ define <2 x half> @v_test_fmax_legacy_uge_v2f16_nsz_flag(<2 x half> %a, <2 x hal
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
@@ -1418,9 +1418,9 @@ define <4 x half> @v_test_fmin_legacy_ule_v4f16_safe(<4 x half> %a, <4 x half> %
; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.h, v2.h
; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v0.l, v2.l
; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s2, v1.l, v3.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
@@ -1439,16 +1439,16 @@ define <4 x half> @v_test_fmin_legacy_ule_v4f16_safe(<4 x half> %a, <4 x half> %
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v5, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v7, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
@@ -1516,9 +1516,9 @@ define <4 x half> @v_test_fmin_legacy_ule_v4f16_nnan_flag(<4 x half> %a, <4 x ha
; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.h, v2.h
; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v0.l, v2.l
; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s2, v1.l, v3.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
@@ -1537,16 +1537,16 @@ define <4 x half> @v_test_fmin_legacy_ule_v4f16_nnan_flag(<4 x half> %a, <4 x ha
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v5, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v7, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
@@ -1614,9 +1614,9 @@ define <4 x half> @v_test_fmin_legacy_ule_v4f16_nsz_flag(<4 x half> %a, <4 x hal
; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.h, v2.h
; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v0.l, v2.l
; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s2, v1.l, v3.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
@@ -1635,16 +1635,16 @@ define <4 x half> @v_test_fmin_legacy_ule_v4f16_nsz_flag(<4 x half> %a, <4 x hal
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v5, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v7, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
@@ -1760,9 +1760,9 @@ define <4 x half> @v_test_fmax_legacy_uge_v4f16_safe(<4 x half> %a, <4 x half> %
; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v0.h, v2.h
; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s1, v0.l, v2.l
; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s2, v1.l, v3.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
@@ -1781,16 +1781,16 @@ define <4 x half> @v_test_fmax_legacy_uge_v4f16_safe(<4 x half> %a, <4 x half> %
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v5, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v7, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v1, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
@@ -1858,9 +1858,9 @@ define <4 x half> @v_test_fmax_legacy_uge_v4f16_nnan_flag(<4 x half> %a, <4 x ha
; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v0.h, v2.h
; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s1, v0.l, v2.l
; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s2, v1.l, v3.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
@@ -1879,16 +1879,16 @@ define <4 x half> @v_test_fmax_legacy_uge_v4f16_nnan_flag(<4 x half> %a, <4 x ha
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v5, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v7, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v1, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
@@ -1956,9 +1956,9 @@ define <4 x half> @v_test_fmax_legacy_uge_v4f16_nsz_flag(<4 x half> %a, <4 x hal
; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v0.h, v2.h
; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s1, v0.l, v2.l
; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s2, v1.l, v3.l
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffd
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu 0xf1ff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
@@ -1977,16 +1977,16 @@ define <4 x half> @v_test_fmax_legacy_uge_v4f16_nsz_flag(<4 x half> %a, <4 x hal
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v5, v4
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v7, v6
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v1, v3
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffd
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
diff --git a/llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll b/llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
index 5c90957edd9f5..25eb8f01b210c 100644
--- a/llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
+++ b/llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
@@ -25,7 +25,7 @@ define amdgpu_cs void @if_then(ptr addrspace(8) inreg %input, ptr addrspace(8) i
; GCN-NEXT: v_mov_b32_e32 v3, 0
; GCN-NEXT: buffer_store_dword v4, v0, s[4:7], 0 offen
; GCN-NEXT: .LBB0_4: ; %.end
-; GCN-NEXT: s_waitcnt_depctr 0xffe3
+; GCN-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GCN-NEXT: v_mov_b32_e32 v0, -1
; GCN-NEXT: buffer_store_dword v0, v3, s[4:7], 0 offen
diff --git a/llvm/test/CodeGen/AMDGPU/should-not-hoist-set-inactive.ll b/llvm/test/CodeGen/AMDGPU/should-not-hoist-set-inactive.ll
index 98c4868e213db..d3cb529933b95 100644
--- a/llvm/test/CodeGen/AMDGPU/should-not-hoist-set-inactive.ll
+++ b/llvm/test/CodeGen/AMDGPU/should-not-hoist-set-inactive.ll
@@ -11,7 +11,7 @@ define amdgpu_cs void @should_not_hoist_set_inactive(<4 x i32> inreg %i14, i32 i
; GCN-NEXT: s_branch .LBB0_2
; GCN-NEXT: .LBB0_1: ; %bb4
; GCN-NEXT: ; in Loop: Header=BB0_2 Depth=1
-; GCN-NEXT: s_waitcnt_depctr 0xffe3
+; GCN-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s8
; GCN-NEXT: s_and_b32 s8, exec_lo, s6
; GCN-NEXT: s_or_b32 s7, s8, s7
diff --git a/llvm/test/CodeGen/AMDGPU/skip-if-dead.ll b/llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
index e836366fd8dbf..4b4fe73826e01 100644
--- a/llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
+++ b/llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
@@ -1239,7 +1239,7 @@ define amdgpu_ps void @phi_use_def_before_kill(float inreg %x, i32 inreg %y) #0
; GFX11-NEXT: v_cmp_lt_f32_e32 vcc, 0, v1
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc
; GFX11-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfffd
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX11-NEXT: s_and_not1_b64 exec, exec, vcc
; GFX11-NEXT: s_cbranch_scc0 .LBB11_6
; GFX11-NEXT: ; %bb.1: ; %bb
@@ -2067,7 +2067,7 @@ define amdgpu_ps void @scc_use_after_kill_inst(float inreg %x, i32 inreg %y) #0
; GFX11-NEXT: v_cmp_lt_f32_e32 vcc, 0, v1
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc
; GFX11-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v1
-; GFX11-NEXT: s_waitcnt_depctr 0xfffd
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
; GFX11-NEXT: s_and_not1_b64 s[2:3], s[2:3], vcc
; GFX11-NEXT: s_cbranch_scc0 .LBB17_6
; GFX11-NEXT: ; %bb.1: ; %bb
diff --git a/llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll b/llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll
index bfadfd860edf6..291d6ca12d9f7 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll
+++ b/llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll
@@ -12,7 +12,7 @@ define i32 @non_entry_func(i32 %x) {
; CHECK-NEXT: s_wait_kmcnt 0x0
; CHECK-NEXT: s_xor_saveexec_b32 s0, -1
; CHECK-NEXT: scratch_store_b32 off, v2, s32 offset:100 ; 4-byte Folded Spill
-; CHECK-NEXT: s_wait_alu 0xfffe
+; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0)
; CHECK-NEXT: s_mov_b32 exec_lo, s0
; CHECK-NEXT: v_writelane_b32 v2, s48, 0
; CHECK-NEXT: s_mov_b32 m0, 0x110003
@@ -37,7 +37,7 @@ define i32 @non_entry_func(i32 %x) {
; CHECK-NEXT: v_readlane_b32 s48, v2, 0
; CHECK-NEXT: s_xor_saveexec_b32 s0, -1
; CHECK-NEXT: scratch_load_b32 v2, off, s32 offset:100 ; 4-byte Folded Reload
-; CHECK-NEXT: s_wait_alu 0xfffe
+; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0)
; CHECK-NEXT: s_mov_b32 exec_lo, s0
; CHECK-NEXT: s_wait_loadcnt 0x0
; CHECK-NEXT: s_setpc_b64 s[30:31]
@@ -66,7 +66,7 @@ define amdgpu_kernel void @entry_func(i32 %x) {
; GISEL-NEXT: s_wait_kmcnt 0x0
; GISEL-NEXT: v_mov_b32_e32 v0, s6
; GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GISEL-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll b/llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
index c84c49ee1a41d..d33e94809b326 100644
--- a/llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
+++ b/llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
@@ -70,7 +70,7 @@ define amdgpu_kernel void @kernel_background_evaluate(ptr addrspace(5) %kg, ptr
; FLATSCR-NEXT: ; %bb.1: ; %if.then4.i
; FLATSCR-NEXT: s_movk_i32 s0, 0x4000
; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s0 offset:4
-; FLATSCR-NEXT: s_waitcnt_depctr 0xffe3
+; FLATSCR-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; FLATSCR-NEXT: s_mov_b32 s0, 0x41c64e6d
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: v_add_nc_u32_e32 v0, v1, v0
diff --git a/llvm/test/CodeGen/AMDGPU/sub.ll b/llvm/test/CodeGen/AMDGPU/sub.ll
index 0a5160145fbd8..d10ef709f8e33 100644
--- a/llvm/test/CodeGen/AMDGPU/sub.ll
+++ b/llvm/test/CodeGen/AMDGPU/sub.ll
@@ -876,7 +876,7 @@ define amdgpu_kernel void @v_test_sub_v2i64(ptr addrspace(1) %out, ptr addrspace
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_sub_co_ci_u32_e64 v3, null, v3, v7, vcc_lo
; GFX12-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v4
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_sub_co_ci_u32_e64 v1, null, v1, v5, vcc_lo
; GFX12-NEXT: global_store_b128 v8, v[0:3], s[0:1]
; GFX12-NEXT: s_endpgm
@@ -1010,13 +1010,13 @@ define amdgpu_kernel void @v_test_sub_v4i64(ptr addrspace(1) %out, ptr addrspace
; GFX12-NEXT: v_sub_co_ci_u32_e64 v3, null, v7, v3, vcc_lo
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: v_sub_co_u32 v10, vcc_lo, v10, v14
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_sub_co_ci_u32_e64 v11, null, v11, v15, vcc_lo
; GFX12-NEXT: v_sub_co_u32 v8, vcc_lo, v8, v12
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_sub_co_ci_u32_e64 v9, null, v9, v13, vcc_lo
; GFX12-NEXT: v_sub_co_u32 v0, vcc_lo, v4, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_sub_co_ci_u32_e64 v1, null, v5, v1, vcc_lo
; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: global_store_b128 v16, v[8:11], s[0:1] offset:16
diff --git a/llvm/test/CodeGen/AMDGPU/sub.v2i16.ll b/llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
index 82ef28f7339b8..4923aef29c6c6 100644
--- a/llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
@@ -58,7 +58,7 @@ define amdgpu_kernel void @v_test_sub_v2i16(ptr addrspace(1) %out, ptr addrspace
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_load_dword v2, v0, s[6:7] glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 s3, 0x31016000
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: v_pk_sub_i16 v0, v1, v2
@@ -303,7 +303,7 @@ define amdgpu_kernel void @v_test_sub_v2i16_constant(ptr addrspace(1) %out, ptr
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_load_dword v0, v0, s[2:3] glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 s3, 0x31016000
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: v_pk_sub_i16 v0, v0, 0x1c8007b
@@ -375,7 +375,7 @@ define amdgpu_kernel void @v_test_sub_v2i16_neg_constant(ptr addrspace(1) %out,
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_load_dword v0, v0, s[2:3] glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 s3, 0x31016000
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: v_pk_sub_i16 v0, v0, 0xfc21fcb3
@@ -445,7 +445,7 @@ define amdgpu_kernel void @v_test_sub_v2i16_inline_neg1(ptr addrspace(1) %out, p
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_load_dword v0, v0, s[2:3] glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 s3, 0x31016000
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: v_pk_sub_i16 v0, v0, -1
@@ -514,7 +514,7 @@ define amdgpu_kernel void @v_test_sub_v2i16_inline_lo_zero_hi(ptr addrspace(1) %
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_load_dword v0, v0, s[2:3] glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 s3, 0x31016000
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: v_pk_sub_i16 v0, v0, 32
@@ -584,7 +584,7 @@ define amdgpu_kernel void @v_test_sub_v2i16_inline_fp_split(ptr addrspace(1) %ou
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_load_dword v0, v0, s[2:3] glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 s3, 0x31016000
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: v_pk_sub_i16 v0, v0, 1.0
@@ -668,7 +668,7 @@ define amdgpu_kernel void @v_test_sub_v2i16_zext_to_v2i32(ptr addrspace(1) %out,
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_load_dword v2, v0, s[6:7] glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 s3, 0x31016000
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: v_pk_sub_i16 v0, v1, v2
@@ -791,7 +791,7 @@ define amdgpu_kernel void @v_test_sub_v2i16_zext_to_v2i64(ptr addrspace(1) %out,
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_load_dword v2, v0, s[6:7] glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 s3, 0x31016000
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: v_pk_sub_i16 v0, v1, v2
@@ -917,7 +917,7 @@ define amdgpu_kernel void @v_test_sub_v2i16_sext_to_v2i32(ptr addrspace(1) %out,
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_load_dword v2, v0, s[6:7] glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 s3, 0x31016000
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: v_pk_sub_i16 v0, v1, v2
@@ -1017,7 +1017,7 @@ define amdgpu_kernel void @v_test_sub_v2i16_sext_to_v2i64(ptr addrspace(1) %out,
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_dword v1, v0, s[2:3]
; GFX10-NEXT: global_load_dword v2, v0, s[6:7]
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 s3, 0x31016000
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/sub_i1.ll b/llvm/test/CodeGen/AMDGPU/sub_i1.ll
index 08ca8482d8c40..3ef1cece538ed 100644
--- a/llvm/test/CodeGen/AMDGPU/sub_i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/sub_i1.ll
@@ -171,7 +171,7 @@ define amdgpu_kernel void @sub_i1_cf(ptr addrspace(1) %out, ptr addrspace(1) %a,
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3] glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_andn2_b32 s2, s4, exec_lo
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
diff --git a/llvm/test/CodeGen/AMDGPU/trans-forwarding-hazards.mir b/llvm/test/CodeGen/AMDGPU/trans-forwarding-hazards.mir
index 2843d83d3a2f2..6c7e70f5455aa 100644
--- a/llvm/test/CodeGen/AMDGPU/trans-forwarding-hazards.mir
+++ b/llvm/test/CodeGen/AMDGPU/trans-forwarding-hazards.mir
@@ -9,7 +9,7 @@ body: |
; GFX11-LABEL: name: trans_use_1_hazard
; GFX11: $vgpr1 = V_SQRT_F32_e32 $vgpr0, implicit $mode, implicit $exec
; GFX11-NEXT: $vgpr2 = V_MOV_B32_e32 0, implicit $exec
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 4095
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 3999
; GFX11-NEXT: $vgpr3 = V_ADD_F32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec
; GFX11-NEXT: S_ENDPGM 0
;
@@ -59,7 +59,7 @@ body: |
; GFX11-NEXT: $sgpr8 = S_MOV_B32 0
; GFX11-NEXT: $sgpr9 = S_MOV_B32 0
; GFX11-NEXT: $sgpr10 = S_MOV_B32 0
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 4095
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 3999
; GFX11-NEXT: $vgpr3 = V_ADD_F32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec
; GFX11-NEXT: S_ENDPGM 0
;
@@ -107,7 +107,7 @@ body: |
; GFX11-NEXT: $vgpr11 = V_MOV_B32_e32 0, implicit $exec
; GFX11-NEXT: $vgpr12 = V_MOV_B32_e32 0, implicit $exec
; GFX11-NEXT: $vgpr13 = V_MOV_B32_e32 0, implicit $exec
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 4095
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 3999
; GFX11-NEXT: $vgpr3 = V_ADD_F32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec
; GFX11-NEXT: S_ENDPGM 0
;
@@ -206,7 +206,7 @@ body: |
; GFX11-LABEL: name: trans_use_4_one_depctr_1
; GFX11: $vgpr1 = V_SQRT_F32_e32 $vgpr0, implicit $mode, implicit $exec
; GFX11-NEXT: $vgpr3 = V_SQRT_F32_e32 $vgpr2, implicit $mode, implicit $exec
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 4095
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 3999
; GFX11-NEXT: $vgpr5 = V_ADD_F32_e32 $vgpr1, $vgpr4, implicit $mode, implicit $exec
; GFX11-NEXT: $vgpr7 = V_ADD_F32_e32 $vgpr3, $vgpr6, implicit $mode, implicit $exec
; GFX11-NEXT: S_ENDPGM 0
@@ -231,7 +231,7 @@ body: |
; GFX11-LABEL: name: trans_use_4_one_depctr_2
; GFX11: $vgpr1 = V_SQRT_F32_e32 $vgpr0, implicit $mode, implicit $exec
; GFX11-NEXT: $vgpr3 = V_SQRT_F32_e32 $vgpr2, implicit $mode, implicit $exec
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 4095
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 3999
; GFX11-NEXT: $vgpr5 = V_ADD_F32_e32 $vgpr3, $vgpr4, implicit $mode, implicit $exec
; GFX11-NEXT: $vgpr7 = V_ADD_F32_e32 $vgpr1, $vgpr6, implicit $mode, implicit $exec
; GFX11-NEXT: S_ENDPGM 0
@@ -257,7 +257,7 @@ body: |
; GFX11: $vgpr1 = V_SQRT_F32_e32 $vgpr0, implicit $mode, implicit $exec
; GFX11-NEXT: $vgpr10 = V_SQRT_F32_e32 $vgpr11, implicit $mode, implicit $exec
; GFX11-NEXT: $vgpr2 = V_MOV_B32_e32 0, implicit $exec
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 4095
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 3999
; GFX11-NEXT: $vgpr3 = V_ADD_F32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec
; GFX11-NEXT: S_ENDPGM 0
;
@@ -296,7 +296,7 @@ body: |
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: bb.2:
; GFX11-NEXT: $vgpr3 = V_MOV_B32_e32 0, implicit $exec
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 4095
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 3999
; GFX11-NEXT: $vgpr4 = V_ADD_F32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec
; GFX11-NEXT: S_ENDPGM 0
;
@@ -357,7 +357,7 @@ body: |
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: bb.2:
; GFX11-NEXT: $vgpr3 = V_MOV_B32_e32 0, implicit $exec
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 4095
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 3999
; GFX11-NEXT: $vgpr4 = V_ADD_F32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec
; GFX11-NEXT: S_ENDPGM 0
;
diff --git a/llvm/test/CodeGen/AMDGPU/v_cndmask.ll b/llvm/test/CodeGen/AMDGPU/v_cndmask.ll
index 53525c93f5b89..ca93fcf3f55a2 100644
--- a/llvm/test/CodeGen/AMDGPU/v_cndmask.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_cndmask.ll
@@ -64,7 +64,7 @@ define amdgpu_kernel void @v_cnd_nan_nosgpr(ptr addrspace(1) %out, i32 %c, ptr a
; GFX10-NEXT: global_load_dword v0, v0, s[0:1]
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_cmp_eq_u32 s2, 0
@@ -561,7 +561,7 @@ define amdgpu_kernel void @fcmp_sgprX_k0_select_k0_vgprZ_f32(ptr addrspace(1) %o
; GFX10-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_cmp_nlg_f32_e64 vcc, s2, 0
@@ -663,7 +663,7 @@ define amdgpu_kernel void @fcmp_sgprX_k0_select_k1_vgprZ_f32(ptr addrspace(1) %o
; GFX10-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_cmp_nlg_f32_e64 vcc, s2, 0
@@ -2216,7 +2216,7 @@ define amdgpu_kernel void @v_cndmask_abs_neg_f16(ptr addrspace(1) %out, i32 %c,
; GFX10-NEXT: global_load_ushort v0, v0, s[0:1]
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_cmp_lg_u32 s2, 0
@@ -2377,7 +2377,7 @@ define amdgpu_kernel void @v_cndmask_abs_neg_f32(ptr addrspace(1) %out, i32 %c,
; GFX10-NEXT: global_load_dword v0, v0, s[0:1]
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_cmp_lg_u32 s2, 0
@@ -2491,7 +2491,7 @@ define amdgpu_kernel void @v_cndmask_abs_neg_f64(ptr addrspace(1) %out, i32 %c,
; GFX10-NEXT: global_load_dwordx2 v[0:1], v0, s[0:1]
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_cmp_lg_u32 s2, 0
diff --git a/llvm/test/CodeGen/AMDGPU/v_swap_b16.ll b/llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
index 490046ce5b856..55986328491ec 100644
--- a/llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
@@ -62,9 +62,9 @@ define half @swap(half %a, half %b, i32 %i) {
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
; GFX12-TRUE16-NEXT: v_swap_b16 v0.l, v0.h
; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB0_1
; GFX12-TRUE16-NEXT: ; %bb.2: ; %ret
@@ -85,9 +85,9 @@ define half @swap(half %a, half %b, i32 %i) {
; GFX12-FAKE16-NEXT: v_swap_b32 v1, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB0_1
; GFX12-FAKE16-NEXT: ; %bb.2: ; %ret
diff --git a/llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard-true16.mir b/llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard-true16.mir
index 9c8e0a48b114b..4d74ccebacab3 100644
--- a/llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard-true16.mir
+++ b/llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard-true16.mir
@@ -8,7 +8,7 @@ body: |
; GCN-LABEL: name: mask_hazard_cndmask_t16_dpp4
; GCN: $vgpr0_lo16 = V_CNDMASK_B16_t16_e64_dpp $vgpr0_lo16, 0, $vgpr1_lo16, 0, $vgpr2_lo16, $sgpr2_sgpr3, 0, 1, 15, 15, 1, implicit $exec
; GCN-NEXT: $sgpr2_sgpr3 = S_CSELECT_B64 -1, 0, implicit $scc
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: S_ENDPGM 0
$vgpr0_lo16 = V_CNDMASK_B16_t16_e64_dpp $vgpr0_lo16, 0, $vgpr1_lo16, 0, $vgpr2_lo16, $sgpr2_sgpr3, 0, 1, 15, 15, 1, implicit $exec
$sgpr2_sgpr3 = S_CSELECT_B64 -1, 0, implicit $scc
diff --git a/llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir b/llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
index 514eeca7ac4c7..03da77e586eaf 100644
--- a/llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
+++ b/llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
@@ -66,7 +66,7 @@ body: |
; GCN-LABEL: name: mask_hazard_getpc1
; GCN: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0_sgpr1, implicit $exec
; GCN-NEXT: $sgpr0_sgpr1 = S_GETPC_B64
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0
$vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0_sgpr1, implicit $exec
@@ -83,7 +83,7 @@ body: |
; GCN: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0_sgpr1, implicit $exec
; GCN-NEXT: BUNDLE implicit-def $sgpr0_sgpr1 {
; GCN-NEXT: $sgpr0_sgpr1 = S_GETPC_B64
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, target-flags(amdgpu-rel32-lo) @mem + 8, implicit-def $scc
; GCN-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, target-flags(amdgpu-rel32-lo) @mem + 16, implicit-def $scc, implicit $scc
; GCN-NEXT: }
@@ -104,7 +104,7 @@ body: |
; GFX11-LABEL: name: mask_hazard_vcc1
; GFX11: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr2_sgpr3, implicit $exec
; GFX11-NEXT: $sgpr2_sgpr3 = S_CSELECT_B64 -1, 0, implicit $scc
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_vcc1
@@ -123,7 +123,7 @@ body: |
; GFX11-LABEL: name: mask_hazard_vcc2
; GFX11: $vgpr1 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec
; GFX11-NEXT: $vcc = S_CSELECT_B64 -1, 0, implicit $scc
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_vcc2
@@ -142,7 +142,7 @@ body: |
; GFX11-LABEL: name: mask_hazard_cndmask_dpp1
; GFX11: $vgpr0 = V_CNDMASK_B32_dpp $vgpr0, 0, $vgpr1, 0, $vgpr2, 1, 15, 15, 1, implicit $vcc, implicit $exec
; GFX11-NEXT: $vcc = S_CSELECT_B64 -1, 0, implicit $scc
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_cndmask_dpp1
@@ -161,7 +161,7 @@ body: |
; GFX11-LABEL: name: mask_hazard_cndmask_dpp2
; GFX11: $vgpr0 = V_CNDMASK_B32_e64_dpp $vgpr0, 0, $vgpr1, 0, $vgpr2, $sgpr2_sgpr3, 1, 15, 15, 1, implicit $exec
; GFX11-NEXT: $sgpr2_sgpr3 = S_CSELECT_B64 -1, 0, implicit $scc
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_cndmask_dpp2
@@ -180,7 +180,7 @@ body: |
; GFX11-LABEL: name: mask_hazard_cndmask_dpp3
; GFX11: $vgpr0 = V_CNDMASK_B16_fake16_e64_dpp $vgpr0, 0, $vgpr1, 0, $vgpr2, $sgpr2_sgpr3, 1, 15, 15, 1, implicit $exec
; GFX11-NEXT: $sgpr2_sgpr3 = S_CSELECT_B64 -1, 0, implicit $scc
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_cndmask_dpp3
@@ -199,7 +199,7 @@ body: |
; GFX11-LABEL: name: mask_hazard_addc1
; GFX11: $vgpr1, $vcc = V_ADDC_U32_e64 0, $vgpr1, $sgpr2_sgpr3, 0, implicit $exec
; GFX11-NEXT: $sgpr2_sgpr3 = S_CSELECT_B64 -1, 0, implicit $scc
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_addc1
@@ -218,7 +218,7 @@ body: |
; GFX11-LABEL: name: mask_hazard_addc2
; GFX11: $vgpr1 = V_ADDC_U32_e32 0, $vgpr1, implicit-def $vcc, implicit $vcc, implicit $exec
; GFX11-NEXT: $vcc = S_CSELECT_B64 -1, 0, implicit $scc
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_addc2
@@ -237,7 +237,7 @@ body: |
; GFX11-LABEL: name: mask_hazard_addc3
; GFX11: $vgpr0 = V_ADDC_U32_dpp $vgpr0, $vgpr1, $vgpr2, 1, 15, 15, 1, implicit-def $vcc, implicit $vcc, implicit $exec
; GFX11-NEXT: $vcc = S_CSELECT_B64 -1, 0, implicit $scc
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_addc3
@@ -256,7 +256,7 @@ body: |
; GFX11-LABEL: name: mask_hazard_addc4
; GFX11: $vgpr0, $sgpr2_sgpr3 = V_ADDC_U32_e64_dpp $vgpr0, $vgpr1, $vgpr2, $sgpr2_sgpr3, 0, 1, 15, 15, 1, implicit $exec
; GFX11-NEXT: $sgpr2_sgpr3 = S_CSELECT_B64 -1, 0, implicit $scc
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_addc4
@@ -275,7 +275,7 @@ body: |
; GFX11-LABEL: name: mask_hazard_subb1
; GFX11: $vgpr1, $vcc = V_SUBB_U32_e64 0, $vgpr1, $sgpr2_sgpr3, 0, implicit $exec
; GFX11-NEXT: $sgpr2_sgpr3 = S_CSELECT_B64 -1, 0, implicit $scc
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_subb1
@@ -294,7 +294,7 @@ body: |
; GFX11-LABEL: name: mask_hazard_subb2
; GFX11: $vgpr1 = V_SUBB_U32_e32 0, $vgpr1, implicit-def $vcc, implicit $vcc, implicit $exec
; GFX11-NEXT: $vcc = S_CSELECT_B64 -1, 0, implicit $scc
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_subb2
@@ -313,7 +313,7 @@ body: |
; GFX11-LABEL: name: mask_hazard_subb3
; GFX11: $vgpr0 = V_SUBB_U32_dpp $vgpr0, $vgpr1, $vgpr2, 1, 15, 15, 1, implicit-def $vcc, implicit $vcc, implicit $exec
; GFX11-NEXT: $vcc = S_CSELECT_B64 -1, 0, implicit $scc
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_subb3
@@ -332,7 +332,7 @@ body: |
; GFX11-LABEL: name: mask_hazard_subb4
; GFX11: $vgpr0, $sgpr2_sgpr3 = V_SUBB_U32_e64_dpp $vgpr0, $vgpr1, $vgpr2, $sgpr2_sgpr3, 0, 1, 15, 15, 1, implicit $exec
; GFX11-NEXT: $sgpr2_sgpr3 = S_CSELECT_B64 -1, 0, implicit $scc
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_subb4
@@ -351,7 +351,7 @@ body: |
; GFX11-LABEL: name: mask_hazard_subbrev1
; GFX11: $vgpr1, $vcc = V_SUBBREV_U32_e64 0, $vgpr1, $sgpr2_sgpr3, 0, implicit $exec
; GFX11-NEXT: $sgpr2_sgpr3 = S_CSELECT_B64 -1, 0, implicit $scc
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_subbrev1
@@ -370,7 +370,7 @@ body: |
; GFX11-LABEL: name: mask_hazard_subbrev2
; GFX11: $vgpr1 = V_SUBBREV_U32_e32 0, $vgpr1, implicit-def $vcc, implicit $vcc, implicit $exec
; GFX11-NEXT: $vcc = S_CSELECT_B64 -1, 0, implicit $scc
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_subbrev2
@@ -389,7 +389,7 @@ body: |
; GFX11-LABEL: name: mask_hazard_subbrev3
; GFX11: $vgpr0 = V_SUBBREV_U32_dpp $vgpr0, $vgpr1, $vgpr2, 1, 15, 15, 1, implicit-def $vcc, implicit $vcc, implicit $exec
; GFX11-NEXT: $vcc = S_CSELECT_B64 -1, 0, implicit $scc
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_subbrev3
@@ -408,7 +408,7 @@ body: |
; GFX11-LABEL: name: mask_hazard_subbrev4
; GFX11: $vgpr0, $sgpr2_sgpr3 = V_SUBBREV_U32_e64_dpp $vgpr0, $vgpr1, $vgpr2, $sgpr2_sgpr3, 0, 1, 15, 15, 1, implicit $exec
; GFX11-NEXT: $sgpr2_sgpr3 = S_CSELECT_B64 -1, 0, implicit $scc
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_subbrev4
@@ -427,7 +427,7 @@ body: |
; GFX11-LABEL: name: mask_hazard_div_fmas_f32
; GFX11: $vgpr0 = V_DIV_FMAS_F32_e64 0, $vgpr1, 0, $vgpr2, 0, $vgpr3, 0, 0, implicit $mode, implicit $vcc, implicit $exec
; GFX11-NEXT: $vcc = S_CSELECT_B64 -1, 0, implicit $scc
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_div_fmas_f32
@@ -446,7 +446,7 @@ body: |
; GFX11-LABEL: name: mask_hazard_div_fmas_f64
; GFX11: $vgpr0_vgpr1 = V_DIV_FMAS_F64_e64 0, $vgpr0_vgpr1, 0, $vgpr2_vgpr3, 0, $vgpr4_vgpr5, 0, 0, implicit $mode, implicit $vcc, implicit $exec
; GFX11-NEXT: $vcc = S_CSELECT_B64 -1, 0, implicit $scc
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_div_fmas_f64
@@ -466,7 +466,7 @@ body: |
; GFX11-LABEL: name: mask_hazard_subreg1
; GFX11: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr2_sgpr3, implicit $exec
; GFX11-NEXT: $sgpr2 = S_MOV_B32 0
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_subreg1
@@ -486,7 +486,7 @@ body: |
; GFX11-LABEL: name: mask_hazard_subreg2
; GFX11: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr2_sgpr3, implicit $exec
; GFX11-NEXT: $sgpr3 = S_MOV_B32 0
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_subreg2
@@ -507,7 +507,7 @@ body: |
; GFX11: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr2_sgpr3, implicit $exec
; GFX11-NEXT: $sgpr2 = S_MOV_B32 0
; GFX11-NEXT: $sgpr3 = S_MOV_B32 0
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_subreg3
@@ -529,7 +529,7 @@ body: |
; GCN-LABEL: name: mask_hazard_subreg4
; GCN: $vgpr1 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec
; GCN-NEXT: $vcc_lo = S_MOV_B32 0
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr2 = S_MOV_B32 $vcc_lo
; GCN-NEXT: S_ENDPGM 0
$vgpr1 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec
@@ -546,7 +546,7 @@ body: |
; GCN-LABEL: name: mask_hazard_subreg5
; GCN: $vgpr1 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec
; GCN-NEXT: $vcc_hi = S_MOV_B32 0
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr2 = S_MOV_B32 $vcc_hi
; GCN-NEXT: S_ENDPGM 0
$vgpr1 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec
@@ -564,7 +564,7 @@ body: |
; GCN: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0_sgpr1, implicit $exec
; GCN-NEXT: S_WAITCNT 0
; GCN-NEXT: $sgpr0_sgpr1 = S_GETPC_B64
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0
$vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0_sgpr1, implicit $exec
@@ -584,7 +584,7 @@ body: |
; GCN-NEXT: $vgpr2 = V_MOV_B32_e32 0, implicit $exec
; GCN-NEXT: $vgpr3 = V_MOV_B32_e32 0, implicit $exec
; GCN-NEXT: $sgpr0_sgpr1 = S_GETPC_B64
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0
$vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0_sgpr1, implicit $exec
@@ -604,7 +604,7 @@ body: |
; GCN: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0_sgpr1, implicit $exec
; GCN-NEXT: $vgpr2 = V_MOV_B32_e32 0, implicit $exec, implicit $mode
; GCN-NEXT: $sgpr0_sgpr1 = S_GETPC_B64
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0
$vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0_sgpr1, implicit $exec
@@ -623,7 +623,7 @@ body: |
; GCN: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0_sgpr1, implicit $exec
; GCN-NEXT: $vgpr2 = V_WRITELANE_B32 $exec_lo, 0, $vgpr2
; GCN-NEXT: $sgpr0_sgpr1 = S_GETPC_B64
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0
$vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0_sgpr1, implicit $exec
@@ -683,7 +683,7 @@ body: |
; GCN: $vgpr1 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec
; GCN-NEXT: $vcc_lo = S_MOV_B32 0
; GCN-NEXT: $vcc_hi = S_MOV_B32 0
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr0 = S_MOV_B32 $vcc_lo
; GCN-NEXT: $vcc = S_MOV_B64 1
; GCN-NEXT: S_ENDPGM 0
@@ -702,7 +702,7 @@ body: |
; GCN-LABEL: name: mask_hazard_cancel_hazard2
; GCN: $vgpr1 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec
; GCN-NEXT: $vcc = S_MOV_B64 0
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr0 = S_MOV_B32 $vcc_lo
; GCN-NEXT: $vcc = S_MOV_B64 1
; GCN-NEXT: S_ENDPGM 0
@@ -720,7 +720,7 @@ body: |
; GCN-LABEL: name: mask_hazard_cancel_hazard3
; GCN: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0_sgpr1, implicit $exec
; GCN-NEXT: $sgpr0_sgpr1 = S_MOV_B64 0
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr4 = S_MOV_B32 $sgpr0
; GCN-NEXT: $sgpr0_sgpr1 = S_MOV_B64 1
; GCN-NEXT: S_ENDPGM 0
@@ -739,7 +739,7 @@ body: |
; GCN: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0_sgpr1, implicit $exec
; GCN-NEXT: $sgpr0 = S_MOV_B32 0
; GCN-NEXT: $sgpr1 = S_MOV_B32 0
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr4 = S_MOV_B32 $sgpr0
; GCN-NEXT: $sgpr0_sgpr1 = S_MOV_B64 1
; GCN-NEXT: S_ENDPGM 0
@@ -758,16 +758,16 @@ body: |
; GFX11-LABEL: name: mask_hazard_partial_cancel1
; GFX11: $vgpr1 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec
; GFX11-NEXT: $vcc_lo = S_MOV_B32 0
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: $sgpr0 = S_MOV_B32 $vcc_lo
; GFX11-NEXT: $vcc = S_MOV_B64 1
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_partial_cancel1
; GFX12: $vgpr1 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec
; GFX12-NEXT: $vcc_lo = S_MOV_B32 0
- ; GFX12-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX12-NEXT: S_WAITCNT_DEPCTR 65438
; GFX12-NEXT: $sgpr0 = S_MOV_B32 $vcc_lo
; GFX12-NEXT: $vcc = S_MOV_B64 1
; GFX12-NEXT: S_ENDPGM 0
@@ -785,16 +785,16 @@ body: |
; GFX11-LABEL: name: mask_hazard_partial_cancel2
; GFX11: $vgpr1 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec
; GFX11-NEXT: $vcc_hi = S_MOV_B32 0
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: $sgpr0 = S_MOV_B32 $vcc_lo
; GFX11-NEXT: $vcc = S_MOV_B64 1
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_partial_cancel2
; GFX12: $vgpr1 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec
; GFX12-NEXT: $vcc_hi = S_MOV_B32 0
- ; GFX12-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX12-NEXT: S_WAITCNT_DEPCTR 65438
; GFX12-NEXT: $sgpr0 = S_MOV_B32 $vcc_lo
; GFX12-NEXT: $vcc = S_MOV_B64 1
; GFX12-NEXT: S_ENDPGM 0
@@ -812,16 +812,16 @@ body: |
; GFX11-LABEL: name: mask_hazard_partial_cancel3
; GFX11: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0_sgpr1, implicit $exec
; GFX11-NEXT: $sgpr0 = S_MOV_B32 0
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: $sgpr3 = S_MOV_B32 $sgpr0
; GFX11-NEXT: $sgpr0_sgpr1 = S_MOV_B64 1
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_partial_cancel3
; GFX12: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0_sgpr1, implicit $exec
; GFX12-NEXT: $sgpr0 = S_MOV_B32 0
- ; GFX12-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX12-NEXT: S_WAITCNT_DEPCTR 65438
; GFX12-NEXT: $sgpr3 = S_MOV_B32 $sgpr0
; GFX12-NEXT: $sgpr0_sgpr1 = S_MOV_B64 1
; GFX12-NEXT: S_ENDPGM 0
@@ -839,16 +839,16 @@ body: |
; GFX11-LABEL: name: mask_hazard_partial_cancel4
; GFX11: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0_sgpr1, implicit $exec
; GFX11-NEXT: $sgpr1 = S_MOV_B32 0
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: $sgpr3 = S_MOV_B32 $sgpr1
; GFX11-NEXT: $sgpr0_sgpr1 = S_MOV_B64 1
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65438
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_partial_cancel4
; GFX12: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0_sgpr1, implicit $exec
; GFX12-NEXT: $sgpr1 = S_MOV_B32 0
- ; GFX12-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GFX12-NEXT: S_WAITCNT_DEPCTR 65438
; GFX12-NEXT: $sgpr3 = S_MOV_B32 $sgpr1
; GFX12-NEXT: $sgpr0_sgpr1 = S_MOV_B64 1
; GFX12-NEXT: S_ENDPGM 0
@@ -866,7 +866,7 @@ body: |
; GFX11-LABEL: name: mask_hazard_valu_readlane1
; GFX11: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr2_sgpr3, implicit $exec
; GFX11-NEXT: $sgpr2 = V_READLANE_B32 $vgpr3, 0
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 61951
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 61855
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_valu_readlane1
@@ -885,7 +885,7 @@ body: |
; GFX11-LABEL: name: mask_hazard_valu_readlane2
; GFX11: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr2_sgpr3, implicit $exec
; GFX11-NEXT: $sgpr3 = V_READLANE_B32 $vgpr3, 1
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 61951
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 61855
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_valu_readlane2
@@ -905,7 +905,7 @@ body: |
; GFX11: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr2_sgpr3, implicit $exec
; GFX11-NEXT: $sgpr2 = V_READLANE_B32 $vgpr3, 0
; GFX11-NEXT: $sgpr3 = V_READLANE_B32 $vgpr3, 1
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 61951
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 61855
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_valu_readlane3
@@ -926,7 +926,7 @@ body: |
; GFX11-LABEL: name: mask_hazard_valu_readfirstlane
; GFX11: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr2_sgpr3, implicit $exec
; GFX11-NEXT: $sgpr2 = V_READFIRSTLANE_B32 $vgpr3, implicit $exec
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 61951
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 61855
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_valu_readfirstlane
@@ -945,7 +945,7 @@ body: |
; GFX11-LABEL: name: mask_hazard_valu_vcmp_vcc
; GFX11: $vgpr1 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec
; GFX11-NEXT: V_CMP_NE_U32_e32 0, $vgpr5, implicit-def $vcc, implicit $exec
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65533
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65437
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_valu_vcmp_vcc
@@ -964,7 +964,7 @@ body: |
; GFX11-LABEL: name: mask_hazard_valu_vcmp_sgpr
; GFX11: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr2_sgpr3, implicit $exec
; GFX11-NEXT: $sgpr2_sgpr3 = V_CMP_EQ_U32_e64 3, $vgpr5, implicit $exec
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 61951
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 61855
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_valu_vcmp_sgpr
@@ -988,7 +988,7 @@ body: |
; GFX11-NEXT: $sgpr0 = S_MOV_B32 0
; GFX11-NEXT: $sgpr1 = S_MOV_B32 0
; GFX11-NEXT: $sgpr2_sgpr3 = V_CMP_EQ_U32_e64 3, $vgpr5, implicit $exec
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 61948
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 61852
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_combine1
@@ -1020,10 +1020,10 @@ body: |
; GFX11-NEXT: $vgpr5 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr2_sgpr3, implicit $exec
; GFX11-NEXT: V_CMP_NE_U32_e32 0, $vgpr5, implicit-def $vcc, implicit $exec
; GFX11-NEXT: $sgpr0 = S_MOV_B32 0
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 65532
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 65436
; GFX11-NEXT: $sgpr1 = S_MOV_B32 $sgpr4
; GFX11-NEXT: $sgpr2_sgpr3 = V_CMP_EQ_U32_e64 3, $vgpr5, implicit $exec
- ; GFX11-NEXT: S_WAITCNT_DEPCTR 61950
+ ; GFX11-NEXT: S_WAITCNT_DEPCTR 61854
; GFX11-NEXT: S_ENDPGM 0
;
; GFX12-LABEL: name: mask_hazard_combine2
diff --git a/llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard-attrs.mir b/llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard-attrs.mir
index fe3cb30793390..3d241b0037fd9 100644
--- a/llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard-attrs.mir
+++ b/llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard-attrs.mir
@@ -44,7 +44,7 @@ body: |
; GCN-LABEL: name: hazard_enable
; GCN: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0, implicit $exec
; GCN-NEXT: $sgpr0_sgpr1 = S_GETPC_B64
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr3 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0
$vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0, implicit $exec
@@ -83,7 +83,7 @@ body: |
; GCN-NEXT: DS_NOP implicit $m0, implicit $exec
; GCN-NEXT: DS_NOP implicit $m0, implicit $exec
; GCN-NEXT: DS_NOP implicit $m0, implicit $exec
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: S_SETPC_B64 $sgpr0_sgpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.3:
@@ -92,7 +92,7 @@ body: |
; GCN-NEXT: DS_NOP implicit $m0, implicit $exec
; GCN-NEXT: DS_NOP implicit $m0, implicit $exec
; GCN-NEXT: DS_NOP implicit $m0, implicit $exec
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: S_SETPC_B64_return $sgpr0_sgpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.4:
@@ -104,7 +104,7 @@ body: |
; GCN-NEXT: DS_NOP implicit $m0, implicit $exec
; GCN-NEXT: DS_NOP implicit $m0, implicit $exec
; GCN-NEXT: DS_NOP implicit $m0, implicit $exec
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr4_sgpr5 = S_SWAPPC_B64 $sgpr2_sgpr3
; GCN-NEXT: $sgpr4 = S_ADD_U32 $sgpr4, 0, implicit-def $scc
; GCN-NEXT: {{ $}}
@@ -172,7 +172,7 @@ body: |
; GCN-LABEL: name: hazard_callee2
; GCN: $vgpr1, $sgpr0 = V_ADDC_U32_e64 0, $vgpr1, $sgpr0, 0, implicit $exec
; GCN-NEXT: $sgpr1 = S_CSELECT_B32 -1, 0, implicit $scc
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr2 = S_ADD_U32 $sgpr1, 0, implicit-def $scc
; GCN-NEXT: DS_NOP implicit $m0, implicit $exec
; GCN-NEXT: DS_NOP implicit $m0, implicit $exec
@@ -292,7 +292,7 @@ body: |
; GCN-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD $vgpr0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: S_WAIT_LOADCNT 0
; GCN-NEXT: $sgpr0_sgpr1 = S_GETPC_B64
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr3 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0
$vgpr1, $sgpr0 = V_ADDC_U32_e64 0, $vgpr1, $sgpr0, 0, implicit $exec
@@ -335,7 +335,7 @@ body: |
; GCN-NEXT: $vgpr0 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: S_WAIT_LOADCNT 0
; GCN-NEXT: $sgpr0_sgpr1 = S_GETPC_B64
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr3 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0
$vgpr1, $sgpr0 = V_ADDC_U32_e64 0, $vgpr1, $sgpr0, 0, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard.mir b/llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard.mir
index 04f7e480764e6..babc64a67bc1a 100644
--- a/llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard.mir
+++ b/llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard.mir
@@ -54,7 +54,7 @@ body: |
; GCN-LABEL: name: hazard_getpc1
; GCN: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0, implicit $exec
; GCN-NEXT: $sgpr0_sgpr1 = S_GETPC_B64
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr3 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0
$vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0, implicit $exec
@@ -70,7 +70,7 @@ body: |
; GCN-LABEL: name: hazard_getpc2
; GCN: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr1, implicit $exec
; GCN-NEXT: $sgpr0_sgpr1 = S_GETPC_B64
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr3 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0
$vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr1, implicit $exec
@@ -87,7 +87,7 @@ body: |
; GCN: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0, implicit $exec
; GCN-NEXT: BUNDLE implicit-def $sgpr0_sgpr1 {
; GCN-NEXT: $sgpr0_sgpr1 = S_GETPC_B64
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, target-flags(amdgpu-rel32-lo) @mem + 8, implicit-def $scc
; GCN-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, target-flags(amdgpu-rel32-hi) @mem + 16, implicit-def $scc, implicit $scc
; GCN-NEXT: }
@@ -109,10 +109,10 @@ body: |
; GCN: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0, implicit $exec
; GCN-NEXT: BUNDLE implicit-def $sgpr0_sgpr1 {
; GCN-NEXT: $sgpr0_sgpr1 = S_GETPC_B64
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr1 = S_SEXT_I32_I16 $sgpr1
; GCN-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, target-flags(amdgpu-rel32-lo) @mem + 12, implicit-def $scc
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, target-flags(amdgpu-rel32-hi) @mem + 24, implicit-def $scc, implicit $scc
; GCN-NEXT: }
; GCN-NEXT: S_ENDPGM 0
@@ -133,7 +133,7 @@ body: |
; GCN-LABEL: name: hazard_vcc1
; GCN: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr2, implicit $exec
; GCN-NEXT: $sgpr3 = S_CSELECT_B32 -1, 0, implicit $scc
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr4 = S_ADD_U32 $sgpr3, 0, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0
$vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr2, implicit $exec
@@ -149,7 +149,7 @@ body: |
; GCN-LABEL: name: hazard_vcc2
; GCN: $vgpr1 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $vcc_lo, implicit $exec
; GCN-NEXT: $vcc_lo = S_CSELECT_B32 -1, 0, implicit $scc
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr4 = S_ADD_U32 $vcc_lo, 0, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0
$vgpr1 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec
@@ -165,7 +165,7 @@ body: |
; GCN-LABEL: name: hazard_vcc3
; GCN: $vgpr1 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $vcc_lo, implicit $exec
; GCN-NEXT: $vcc_lo = S_CSELECT_B32 -1, 0, implicit $scc
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $vgpr3 = V_CNDMASK_B32_e32 $vgpr4, $vgpr5, implicit $vcc_lo, implicit $exec
; GCN-NEXT: S_ENDPGM 0
$vgpr1 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec
@@ -198,7 +198,7 @@ body: |
; GCN-NEXT: S_BRANCH %bb.3
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.3:
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65532
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65436
; GCN-NEXT: $vgpr3 = V_CNDMASK_B32_e32 $vgpr4, $vgpr5, implicit $vcc_lo, implicit $exec
; GCN-NEXT: S_ENDPGM 0
bb.0:
@@ -223,7 +223,7 @@ body: |
; GCN-LABEL: name: hazard_addc1
; GCN: $vgpr1, $vcc_lo = V_ADDC_U32_e64 0, $vgpr1, $sgpr0, 0, implicit $exec
; GCN-NEXT: $sgpr0 = S_CSELECT_B32 -1, 0, implicit $scc
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr2 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0
$vgpr1, $vcc_lo = V_ADDC_U32_e64 0, $vgpr1, $sgpr0, 0, implicit $exec
@@ -239,7 +239,7 @@ body: |
; GCN-LABEL: name: hazard_addc2
; GCN: $vgpr1, $vcc_lo = V_ADDC_U32_e64 0, $vgpr1, $sgpr1, 0, implicit $exec
; GCN-NEXT: $sgpr0 = S_CSELECT_B32 -1, 0, implicit $scc
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr2 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0
$vgpr1, $vcc_lo = V_ADDC_U32_e64 0, $vgpr1, $sgpr1, 0, implicit $exec
@@ -255,7 +255,7 @@ body: |
; GCN-LABEL: name: hazard_addc3
; GCN: $vgpr1, $vcc_lo = V_ADDC_U32_e64 0, $vgpr1, $sgpr0, 0, implicit $exec
; GCN-NEXT: $sgpr1 = S_CSELECT_B32 -1, 0, implicit $scc
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr2 = S_ADD_U32 $sgpr1, 0, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0
$vgpr1, $vcc_lo = V_ADDC_U32_e64 0, $vgpr1, $sgpr0, 0, implicit $exec
@@ -271,7 +271,7 @@ body: |
; GCN-LABEL: name: hazard_addc4
; GCN: $vgpr1, $vcc_lo = V_ADDC_U32_e64 0, $vgpr1, $sgpr3, 0, implicit $exec
; GCN-NEXT: $sgpr3 = S_CSELECT_B32 -1, 0, implicit $scc
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr2 = S_ADD_U32 $sgpr3, 0, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0
$vgpr1, $vcc_lo = V_ADDC_U32_e64 0, $vgpr1, $sgpr3, 0, implicit $exec
@@ -289,7 +289,7 @@ body: |
; GCN-NEXT: $sgpr16 = S_MOV_B32 0
; GCN-NEXT: $sgpr32 = S_MOV_B32 0
; GCN-NEXT: $sgpr1 = S_CSELECT_B32 -1, 0, implicit $scc
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr2 = S_ADD_U32 $sgpr1, 0, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0
$vgpr1, $vcc_lo = V_ADDC_U32_e64 0, $vgpr1, $sgpr0, 0, implicit $exec
@@ -312,7 +312,7 @@ body: |
; GCN-NEXT: $sgpr80 = S_MOV_B32 0
; GCN-NEXT: $sgpr96 = S_MOV_B32 0
; GCN-NEXT: $sgpr1 = S_CSELECT_B32 -1, 0, implicit $scc
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr2 = S_ADD_U32 $sgpr1, 0, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0
$vgpr1, $vcc_lo = V_ADDC_U32_e64 0, $vgpr1, $sgpr0, 0, implicit $exec
@@ -333,7 +333,7 @@ body: |
; GCN-LABEL: name: hazard_vaddc1
; GCN: $vgpr1, $vcc_lo = V_ADDC_U32_e64 0, $vgpr1, $sgpr0, 0, implicit $exec
; GCN-NEXT: $sgpr1 = S_CSELECT_B32 -1, 0, implicit $scc
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $vgpr2, $vcc_lo = V_ADDC_U32_e64 0, $vgpr1, $sgpr1, 0, implicit $exec
; GCN-NEXT: S_ENDPGM 0
$vgpr1, $vcc_lo = V_ADDC_U32_e64 0, $vgpr1, $sgpr0, 0, implicit $exec
@@ -357,7 +357,7 @@ body: |
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: $sgpr1 = S_CSELECT_B32 -1, 0, implicit $scc
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr2 = S_ADD_U32 $sgpr1, 0, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0
$vgpr1, $vcc_lo = V_ADDC_U32_e64 0, $vgpr1, $sgpr0, 0, implicit $exec
@@ -389,7 +389,7 @@ body: |
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr2 = S_ADD_U32 $sgpr1, 0, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0
$vgpr1, $vcc_lo = V_ADDC_U32_e64 0, $vgpr1, $sgpr0, 0, implicit $exec
@@ -420,7 +420,7 @@ body: |
; GCN-NEXT: $sgpr12 = S_ADD_U32 $sgpr11, 0, implicit-def $scc
; GCN-NEXT: $sgpr14 = S_ADD_U32 $sgpr13, 0, implicit-def $scc
; GCN-NEXT: $sgpr16 = S_ADD_U32 $sgpr15, 0, implicit-def $scc
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr2 = S_ADD_U32 $sgpr1, 0, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0
$vgpr1, $vcc_lo = V_ADDC_U32_e64 0, $vgpr1, $sgpr0, 0, implicit $exec
@@ -453,7 +453,7 @@ body: |
; GCN-NEXT: $sgpr18 = S_ADD_U32 $sgpr17, 0, implicit-def $scc
; GCN-NEXT: $sgpr20 = S_ADD_U32 $sgpr19, 0, implicit-def $scc
; GCN-NEXT: $sgpr22 = S_ADD_U32 $sgpr21, 0, implicit-def $scc
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr2 = S_ADD_U32 $sgpr1, 0, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0
$vgpr1, $vcc_lo = V_ADDC_U32_e64 0, $vgpr1, $sgpr0, 0, implicit $exec
@@ -539,7 +539,7 @@ body: |
; GCN-NEXT: successors: %bb.2(0x80000000)
; GCN-NEXT: {{ $}}
; GCN-NEXT: $sgpr0_sgpr1 = S_GETPC_B64
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr3 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
@@ -591,12 +591,12 @@ body: |
; NOBC-NEXT: {{ $}}
; NOBC-NEXT: bb.2:
; NOBC-NEXT: $sgpr16 = S_MOV_B32 0
- ; NOBC-NEXT: S_WAITCNT_DEPCTR 65534
+ ; NOBC-NEXT: S_WAITCNT_DEPCTR 65438
; NOBC-NEXT: S_SETPC_B64 $sgpr0_sgpr1
; NOBC-NEXT: {{ $}}
; NOBC-NEXT: bb.3:
; NOBC-NEXT: $sgpr18 = S_MOV_B32 0
- ; NOBC-NEXT: S_WAITCNT_DEPCTR 65534
+ ; NOBC-NEXT: S_WAITCNT_DEPCTR 65438
; NOBC-NEXT: S_SETPC_B64_return $sgpr0_sgpr1
; NOBC-NEXT: {{ $}}
; NOBC-NEXT: bb.4:
@@ -604,19 +604,19 @@ body: |
; NOBC-NEXT: {{ $}}
; NOBC-NEXT: $vcc_lo = S_MOV_B32 0
; NOBC-NEXT: $sgpr20 = S_MOV_B32 0
- ; NOBC-NEXT: S_WAITCNT_DEPCTR 65534
+ ; NOBC-NEXT: S_WAITCNT_DEPCTR 65438
; NOBC-NEXT: $sgpr4_sgpr5 = S_SWAPPC_B64 $sgpr2_sgpr3
- ; NOBC-NEXT: S_WAITCNT_DEPCTR 65534
+ ; NOBC-NEXT: S_WAITCNT_DEPCTR 65438
; NOBC-NEXT: $sgpr4 = S_ADD_U32 $sgpr4, 0, implicit-def $scc
; NOBC-NEXT: {{ $}}
; NOBC-NEXT: bb.5:
; NOBC-NEXT: successors: %bb.6(0x80000000)
; NOBC-NEXT: {{ $}}
- ; NOBC-NEXT: S_WAITCNT_DEPCTR 65534
+ ; NOBC-NEXT: S_WAITCNT_DEPCTR 65438
; NOBC-NEXT: $sgpr8_sgpr9 = S_CALL_B64 0
; NOBC-NEXT: {{ $}}
; NOBC-NEXT: bb.6:
- ; NOBC-NEXT: S_WAITCNT_DEPCTR 65534
+ ; NOBC-NEXT: S_WAITCNT_DEPCTR 65438
; NOBC-NEXT: $sgpr22 = S_MOV_B32 $sgpr8
; NOBC-NEXT: S_ENDPGM 0
;
@@ -645,7 +645,7 @@ body: |
; BC-NEXT: DS_NOP implicit $m0, implicit $exec
; BC-NEXT: DS_NOP implicit $m0, implicit $exec
; BC-NEXT: DS_NOP implicit $m0, implicit $exec
- ; BC-NEXT: S_WAITCNT_DEPCTR 65534
+ ; BC-NEXT: S_WAITCNT_DEPCTR 65438
; BC-NEXT: S_SETPC_B64 $sgpr0_sgpr1
; BC-NEXT: {{ $}}
; BC-NEXT: bb.3:
@@ -654,7 +654,7 @@ body: |
; BC-NEXT: DS_NOP implicit $m0, implicit $exec
; BC-NEXT: DS_NOP implicit $m0, implicit $exec
; BC-NEXT: DS_NOP implicit $m0, implicit $exec
- ; BC-NEXT: S_WAITCNT_DEPCTR 65534
+ ; BC-NEXT: S_WAITCNT_DEPCTR 65438
; BC-NEXT: S_SETPC_B64_return $sgpr0_sgpr1
; BC-NEXT: {{ $}}
; BC-NEXT: bb.4:
@@ -666,7 +666,7 @@ body: |
; BC-NEXT: DS_NOP implicit $m0, implicit $exec
; BC-NEXT: DS_NOP implicit $m0, implicit $exec
; BC-NEXT: DS_NOP implicit $m0, implicit $exec
- ; BC-NEXT: S_WAITCNT_DEPCTR 65534
+ ; BC-NEXT: S_WAITCNT_DEPCTR 65438
; BC-NEXT: $sgpr4_sgpr5 = S_SWAPPC_B64 $sgpr2_sgpr3
; BC-NEXT: $sgpr4 = S_ADD_U32 $sgpr4, 0, implicit-def $scc
; BC-NEXT: {{ $}}
@@ -720,9 +720,9 @@ body: |
bb.0:
; NOBC-LABEL: name: hazard_callee1
; NOBC: $sgpr1 = S_CSELECT_B32 -1, 0, implicit $scc
- ; NOBC-NEXT: S_WAITCNT_DEPCTR 65534
+ ; NOBC-NEXT: S_WAITCNT_DEPCTR 65438
; NOBC-NEXT: $sgpr2 = S_ADD_U32 $sgpr1, 0, implicit-def $scc
- ; NOBC-NEXT: S_WAITCNT_DEPCTR 65534
+ ; NOBC-NEXT: S_WAITCNT_DEPCTR 65438
; NOBC-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
;
; BC-LABEL: name: hazard_callee1
@@ -741,15 +741,15 @@ body: |
; NOBC-LABEL: name: hazard_callee2
; NOBC: $vgpr1, $sgpr0 = V_ADDC_U32_e64 0, $vgpr1, $sgpr0, 0, implicit $exec
; NOBC-NEXT: $sgpr1 = S_CSELECT_B32 -1, 0, implicit $scc
- ; NOBC-NEXT: S_WAITCNT_DEPCTR 65534
+ ; NOBC-NEXT: S_WAITCNT_DEPCTR 65438
; NOBC-NEXT: $sgpr2 = S_ADD_U32 $sgpr1, 0, implicit-def $scc
- ; NOBC-NEXT: S_WAITCNT_DEPCTR 65534
+ ; NOBC-NEXT: S_WAITCNT_DEPCTR 65438
; NOBC-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
;
; BC-LABEL: name: hazard_callee2
; BC: $vgpr1, $sgpr0 = V_ADDC_U32_e64 0, $vgpr1, $sgpr0, 0, implicit $exec
; BC-NEXT: $sgpr1 = S_CSELECT_B32 -1, 0, implicit $scc
- ; BC-NEXT: S_WAITCNT_DEPCTR 65534
+ ; BC-NEXT: S_WAITCNT_DEPCTR 65438
; BC-NEXT: $sgpr2 = S_ADD_U32 $sgpr1, 0, implicit-def $scc
; BC-NEXT: DS_NOP implicit $m0, implicit $exec
; BC-NEXT: DS_NOP implicit $m0, implicit $exec
@@ -769,7 +769,7 @@ body: |
; GCN-LABEL: name: hazard_carry_vcc
; GCN: $vgpr1, $sgpr0 = V_ADDC_U32_e64 0, $vgpr1, $vcc_lo, 0, implicit $exec
; GCN-NEXT: $vgpr0 = V_ADD_CO_U32_e32 $vgpr0, $vgpr1, implicit-def $vcc_lo, implicit $exec
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65533
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65437
; GCN-NEXT: $vgpr1 = V_ADDC_U32_e32 $vgpr2, $vgpr3, implicit-def $vcc_lo, implicit $vcc_lo, implicit $exec
; GCN-NEXT: S_ENDPGM 0
$vgpr1, $sgpr0 = V_ADDC_U32_e64 0, $vgpr1, $vcc_lo, 0, implicit $exec
@@ -802,7 +802,7 @@ body: |
; GCN-LABEL: name: hazard_carry_sgpr
; GCN: $vgpr1, $sgpr0 = V_ADDC_U32_e64 0, $vgpr1, $sgpr0, 0, implicit $exec
; GCN-NEXT: $vgpr0, $sgpr0 = V_ADD_CO_U32_e64 $vgpr0, $vgpr1, 0, implicit $exec
- ; GCN-NEXT: S_WAITCNT_DEPCTR 61951
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 61855
; GCN-NEXT: $vgpr1, $sgpr1 = V_ADDC_U32_e64 $vgpr2, $vgpr3, $sgpr0, 0, implicit $exec
; GCN-NEXT: S_ENDPGM 0
$vgpr1, $sgpr0 = V_ADDC_U32_e64 0, $vgpr1, $sgpr0, 0, implicit $exec
@@ -871,7 +871,7 @@ body: |
; NOMEMC-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8, 0, 0, 0, implicit $exec
; NOMEMC-NEXT: S_WAIT_LOADCNT 0
; NOMEMC-NEXT: $sgpr0_sgpr1 = S_GETPC_B64
- ; NOMEMC-NEXT: S_WAITCNT_DEPCTR 65534
+ ; NOMEMC-NEXT: S_WAITCNT_DEPCTR 65438
; NOMEMC-NEXT: $sgpr3 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
; NOMEMC-NEXT: S_ENDPGM 0
;
@@ -903,7 +903,7 @@ body: |
; NOMEMC-NEXT: $vgpr10 = IMAGE_SAMPLE_LZ_V1_V2_gfx12 $vgpr3, $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 1, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128))
; NOMEMC-NEXT: S_WAIT_SAMPLECNT 0
; NOMEMC-NEXT: $sgpr0_sgpr1 = S_GETPC_B64
- ; NOMEMC-NEXT: S_WAITCNT_DEPCTR 65534
+ ; NOMEMC-NEXT: S_WAITCNT_DEPCTR 65438
; NOMEMC-NEXT: $sgpr3 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
; NOMEMC-NEXT: S_ENDPGM 0
;
@@ -935,7 +935,7 @@ body: |
; NOMEMC-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMAGE_BVH_INTERSECT_RAY_sa_gfx11 $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14, renamable $sgpr0_sgpr1_sgpr2_sgpr3, 0, implicit $exec :: (dereferenceable load (s128), addrspace 7)
; NOMEMC-NEXT: S_WAIT_BVHCNT 0
; NOMEMC-NEXT: $sgpr0_sgpr1 = S_GETPC_B64
- ; NOMEMC-NEXT: S_WAITCNT_DEPCTR 65534
+ ; NOMEMC-NEXT: S_WAITCNT_DEPCTR 65438
; NOMEMC-NEXT: $sgpr3 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
; NOMEMC-NEXT: S_ENDPGM 0
;
@@ -967,7 +967,7 @@ body: |
; GCN-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD $vgpr0, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: S_WAIT_LOADCNT 0
; GCN-NEXT: $sgpr0_sgpr1 = S_GETPC_B64
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr3 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0
$vgpr1, $sgpr0 = V_ADDC_U32_e64 0, $vgpr1, $sgpr0, 0, implicit $exec
@@ -987,7 +987,7 @@ body: |
; NOMEMC-NEXT: $vgpr0 = GLOBAL_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec
; NOMEMC-NEXT: S_WAIT_LOADCNT 0
; NOMEMC-NEXT: $sgpr0_sgpr1 = S_GETPC_B64
- ; NOMEMC-NEXT: S_WAITCNT_DEPCTR 65534
+ ; NOMEMC-NEXT: S_WAITCNT_DEPCTR 65438
; NOMEMC-NEXT: $sgpr3 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
; NOMEMC-NEXT: S_ENDPGM 0
;
@@ -1019,7 +1019,7 @@ body: |
; GCN-NEXT: $vgpr0 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr
; GCN-NEXT: S_WAIT_LOADCNT 0
; GCN-NEXT: $sgpr0_sgpr1 = S_GETPC_B64
- ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+ ; GCN-NEXT: S_WAITCNT_DEPCTR 65438
; GCN-NEXT: $sgpr3 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
; GCN-NEXT: S_ENDPGM 0
$vgpr1, $sgpr0 = V_ADDC_U32_e64 0, $vgpr1, $sgpr0, 0, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir b/llvm/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir
index e97c518da1e3c..1794a9c555bca 100644
--- a/llvm/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir
+++ b/llvm/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir
@@ -3,7 +3,7 @@
# GCN-LABEL: name: hazard_vcmpx_smov_exec_lo
# GCN: $sgpr0 = S_MOV_B32 $exec_lo
-# GFX10-NEXT: S_WAITCNT_DEPCTR 65534
+# GFX10-NEXT: S_WAITCNT_DEPCTR 65310
# GCN-NEXT: V_CMPX_LE_F32_nosdst_e32
---
name: hazard_vcmpx_smov_exec_lo
@@ -21,7 +21,7 @@ body: |
# GCN-LABEL: name: hazard_vcmpx_smov_exec
# GCN: $sgpr0_sgpr1 = S_MOV_B64 $exec
-# GFX10-NEXT: S_WAITCNT_DEPCTR 65534
+# GFX10-NEXT: S_WAITCNT_DEPCTR 65310
# GCN-NEXT: V_CMPX_LE_F32_nosdst_e32
---
name: hazard_vcmpx_smov_exec
@@ -129,7 +129,7 @@ body: |
# GCN-LABEL: name: hazard_vcmpx_smov_exec_lo_depctr_ffff
# GCN: $sgpr0 = S_MOV_B32 $exec_lo
# GCN-NEXT: S_WAITCNT_DEPCTR 65535
-# GFX10-NEXT: S_WAITCNT_DEPCTR 65534
+# GFX10-NEXT: S_WAITCNT_DEPCTR 65310
# GCN-NEXT: V_CMPX_LE_F32_nosdst_e32
---
name: hazard_vcmpx_smov_exec_lo_depctr_ffff
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
index 334215125f58a..4f4e2115810c6 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
@@ -2413,7 +2413,7 @@ define i64 @test_vector_reduce_add_v2i64(<2 x i64> %v) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -2486,11 +2486,11 @@ define i64 @test_vector_reduce_add_v3i64(<3 x i64> %v) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v5, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -2621,14 +2621,14 @@ define i64 @test_vector_reduce_add_v4i64(<4 x i64> %v) {
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_add_co_u32 v2, vcc_lo, v2, v6
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v7, vcc_lo
; GFX12-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v5, vcc_lo
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2640,14 +2640,14 @@ define i64 @test_vector_reduce_add_v4i64(<4 x i64> %v) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v5, vcc_lo
; GFX12-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v6
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v7, vcc_lo
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -2864,26 +2864,26 @@ define i64 @test_vector_reduce_add_v8i64(<8 x i64> %v) {
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_add_co_u32 v4, vcc_lo, v4, v12
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v13, vcc_lo
; GFX12-SDAG-NEXT: v_add_co_u32 v6, vcc_lo, v6, v14
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v15, vcc_lo
; GFX12-SDAG-NEXT: v_add_co_u32 v2, vcc_lo, v2, v10
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v11, vcc_lo
; GFX12-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, v0, v8
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v9, vcc_lo
; GFX12-SDAG-NEXT: v_add_co_u32 v2, vcc_lo, v2, v6
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v7, vcc_lo
; GFX12-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v5, vcc_lo
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2895,26 +2895,26 @@ define i64 @test_vector_reduce_add_v8i64(<8 x i64> %v) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v8
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v9, vcc_lo
; GFX12-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v10
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v11, vcc_lo
; GFX12-GISEL-NEXT: v_add_co_u32 v4, vcc_lo, v4, v12
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v13, vcc_lo
; GFX12-GISEL-NEXT: v_add_co_u32 v6, vcc_lo, v6, v14
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v15, vcc_lo
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v5, vcc_lo
; GFX12-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v6
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v7, vcc_lo
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -3320,51 +3320,51 @@ define i64 @test_vector_reduce_add_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: scratch_load_b32 v31, off, s32
; GFX12-SDAG-NEXT: v_add_co_u32 v10, vcc_lo, v10, v26
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v11, null, v11, v27, vcc_lo
; GFX12-SDAG-NEXT: v_add_co_u32 v2, vcc_lo, v2, v18
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v19, vcc_lo
; GFX12-SDAG-NEXT: v_add_co_u32 v6, vcc_lo, v6, v22
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v23, vcc_lo
; GFX12-SDAG-NEXT: v_add_co_u32 v8, vcc_lo, v8, v24
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v9, null, v9, v25, vcc_lo
; GFX12-SDAG-NEXT: v_add_co_u32 v12, vcc_lo, v12, v28
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v13, null, v13, v29, vcc_lo
; GFX12-SDAG-NEXT: v_add_co_u32 v4, vcc_lo, v4, v20
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v21, vcc_lo
; GFX12-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, v0, v16
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v17, vcc_lo
; GFX12-SDAG-NEXT: v_add_co_u32 v4, vcc_lo, v4, v12
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v13, vcc_lo
; GFX12-SDAG-NEXT: v_add_co_u32 v12, vcc_lo, v14, v30
; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v13, null, v15, v31, vcc_lo
; GFX12-SDAG-NEXT: v_add_co_u32 v2, vcc_lo, v2, v10
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v11, vcc_lo
; GFX12-SDAG-NEXT: v_add_co_u32 v6, vcc_lo, v6, v12
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v13, vcc_lo
; GFX12-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, v0, v8
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v9, vcc_lo
; GFX12-SDAG-NEXT: v_add_co_u32 v2, vcc_lo, v2, v6
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v7, vcc_lo
; GFX12-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v5, vcc_lo
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3377,51 +3377,51 @@ define i64 @test_vector_reduce_add_v16i64(<16 x i64> %v) {
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: scratch_load_b32 v31, off, s32
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v16
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v17, vcc_lo
; GFX12-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v18
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v19, vcc_lo
; GFX12-GISEL-NEXT: v_add_co_u32 v4, vcc_lo, v4, v20
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v21, vcc_lo
; GFX12-GISEL-NEXT: v_add_co_u32 v6, vcc_lo, v6, v22
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v23, vcc_lo
; GFX12-GISEL-NEXT: v_add_co_u32 v8, vcc_lo, v8, v24
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v9, null, v9, v25, vcc_lo
; GFX12-GISEL-NEXT: v_add_co_u32 v10, vcc_lo, v10, v26
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v11, null, v11, v27, vcc_lo
; GFX12-GISEL-NEXT: v_add_co_u32 v12, vcc_lo, v12, v28
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v13, null, v13, v29, vcc_lo
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v8
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v9, vcc_lo
; GFX12-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v10
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v11, vcc_lo
; GFX12-GISEL-NEXT: v_add_co_u32 v8, vcc_lo, v14, v30
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v9, null, v15, v31, vcc_lo
; GFX12-GISEL-NEXT: v_add_co_u32 v4, vcc_lo, v4, v12
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, v5, v13, vcc_lo
; GFX12-GISEL-NEXT: v_add_co_u32 v6, vcc_lo, v6, v8
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v7, null, v7, v9, vcc_lo
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v5, vcc_lo
; GFX12-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v6
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v7, vcc_lo
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
index 1a81e82607aa7..9c54c30daefe0 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
@@ -200,7 +200,7 @@ define half @test_vector_reduce_fmaximum_v3half(<3 x half> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_mov_b32 s0, 0xfc00
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-FAKE16-NEXT: v_perm_b32 v1, s0, v1, 0x5040100
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_pk_maximum_f16 v0, v0, v1
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
index 6414f73c22b31..9d3a4f387bfc8 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
@@ -224,7 +224,7 @@ define half @test_vector_reduce_fminimum_v3half(<3 x half> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x7c00
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-FAKE16-NEXT: v_perm_b32 v1, s0, v1, 0x5040100
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_pk_minimum_f16 v0, v0, v1
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
index 8d0e00383d692..43430dc132f0e 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
@@ -572,7 +572,7 @@ define i8 @test_vector_reduce_smax_v4i8(<4 x i8> %v) {
; GFX12-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-GISEL-NEXT: v_max_i16 v1, v1, v3
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: v_max_i16 v4, v2, s0
; GFX12-GISEL-NEXT: v_max_i16 v3, v3, s0
; GFX12-GISEL-NEXT: v_max_i16 v0, v0, v2
@@ -994,7 +994,7 @@ define i8 @test_vector_reduce_smax_v8i8(<8 x i8> %v) {
; GFX12-GISEL-NEXT: v_max_i16 v1, v1, v3
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-GISEL-NEXT: v_max_i16 v0, v0, v4
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: v_max_i16 v3, v3, s0
; GFX12-GISEL-NEXT: v_max_i16 v4, v2, s0
; GFX12-GISEL-NEXT: v_max_i16 v5, v1, s0
@@ -1603,7 +1603,7 @@ define i8 @test_vector_reduce_smax_v16i8(<16 x i8> %v) {
; GFX12-GISEL-NEXT: s_sext_i32_i8 s0, s0
; GFX12-GISEL-NEXT: v_max_i16 v1, v1, v3
; GFX12-GISEL-NEXT: v_max_i16 v2, v2, v5
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: v_max_i16 v3, v3, s0
; GFX12-GISEL-NEXT: v_max_i16 v0, v0, v4
; GFX12-GISEL-NEXT: v_max_i16 v4, v1, s0
@@ -1875,7 +1875,7 @@ define i16 @test_vector_reduce_smax_v3i16(<3 x i16> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x8000
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-FAKE16-NEXT: v_perm_b32 v1, s0, v1, 0x5040100
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_pk_max_i16 v0, v0, v1
@@ -3230,7 +3230,7 @@ define i64 @test_vector_reduce_smax_v2i64(<2 x i64> %v) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -3359,11 +3359,11 @@ define i64 @test_vector_reduce_smax_v3i64(<3 x i64> %v) {
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v3, v1 :: v_dual_cndmask_b32 v0, v2, v0
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3375,11 +3375,11 @@ define i64 @test_vector_reduce_smax_v3i64(<3 x i64> %v) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -3541,14 +3541,14 @@ define i64 @test_vector_reduce_smax_v4i64(<4 x i64> %v) {
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[6:7]
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v2, v6, v2
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3561,14 +3561,14 @@ define i64 @test_vector_reduce_smax_v4i64(<4 x i64> %v) {
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[6:7]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -3859,27 +3859,27 @@ define i64 @test_vector_reduce_smax_v8i64(<8 x i64> %v) {
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[4:5], v[12:13]
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[6:7], v[14:15]
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s1, v[2:3], v[10:11]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_cndmask_b32 v4, v12, v4
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s1
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s1
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v9, v1 :: v_dual_cndmask_b32 v0, v8, v0
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[6:7]
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v2, v6, v2
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3893,27 +3893,27 @@ define i64 @test_vector_reduce_smax_v8i64(<8 x i64> %v) {
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[8:9]
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[10:11]
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e64 s1, v[4:5], v[12:13]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s1
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s1
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[6:7]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -4460,9 +4460,9 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[0:1], v[16:17]
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s1, v[12:13], v[28:29]
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s2, v[6:7], v[22:23]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v9, v25, v9 :: v_dual_cndmask_b32 v8, v24, v8
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v17, v1, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v16, v0, s0
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[10:11], v[26:27]
@@ -4471,9 +4471,9 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v12, v28, v12, s1
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s1, v[4:5], v[20:21]
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v7, v23, v7, s2
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v11, v27, v11 :: v_dual_cndmask_b32 v10, v26, v10
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v19, v3, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v18, v2, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v5, v21, v5, s1
@@ -4481,7 +4481,7 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v6, v22, v6, s2
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s1, v[0:1], v[8:9]
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[10:11]
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s1
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
@@ -4489,27 +4489,27 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s1
; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[14:15], v[30:31]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v15, v31, v15 :: v_dual_cndmask_b32 v14, v30, v14
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[4:5], v[12:13]
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[6:7], v[14:15]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_cndmask_b32 v4, v12, v4
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s0
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[6:7]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -4524,60 +4524,60 @@ define i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[16:17]
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[18:19]
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e64 s1, v[4:5], v[20:21]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v16, v0 :: v_dual_cndmask_b32 v1, v17, v1
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[6:7], v[22:23]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v18, v2, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v19, v3, s0
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e64 s0, v[8:9], v[24:25]
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, v20, v4, s1
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v5, v21, v5, s1
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v22, v6 :: v_dual_cndmask_b32 v7, v23, v7
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[10:11], v[26:27]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v8, v24, v8, s0
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e64 s1, v[12:13], v[28:29]
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v9, v25, v9, s0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v10, v26, v10 :: v_dual_cndmask_b32 v11, v27, v11
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v12, v28, v12, s1
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v13, v29, v13, s1
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e64 s1, v[4:5], v[12:13]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s1
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s1
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e64 s0, v[14:15], v[30:31]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v14, v30, v14, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v15, v31, v15, s0
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[10:11]
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e64 s0, v[2:3], v[6:7]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
; GFX12-GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
index f15ecf014ab0b..94de3bc7241c1 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
@@ -572,7 +572,7 @@ define i8 @test_vector_reduce_smin_v4i8(<4 x i8> %v) {
; GFX12-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-GISEL-NEXT: v_min_i16 v1, v1, v3
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: v_min_i16 v4, v2, s0
; GFX12-GISEL-NEXT: v_min_i16 v3, v3, s0
; GFX12-GISEL-NEXT: v_min_i16 v0, v0, v2
@@ -994,7 +994,7 @@ define i8 @test_vector_reduce_smin_v8i8(<8 x i8> %v) {
; GFX12-GISEL-NEXT: v_min_i16 v1, v1, v3
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-GISEL-NEXT: v_min_i16 v0, v0, v4
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: v_min_i16 v3, v3, s0
; GFX12-GISEL-NEXT: v_min_i16 v4, v2, s0
; GFX12-GISEL-NEXT: v_min_i16 v5, v1, s0
@@ -1603,7 +1603,7 @@ define i8 @test_vector_reduce_smin_v16i8(<16 x i8> %v) {
; GFX12-GISEL-NEXT: s_sext_i32_i8 s0, s0
; GFX12-GISEL-NEXT: v_min_i16 v1, v1, v3
; GFX12-GISEL-NEXT: v_min_i16 v2, v2, v5
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: v_min_i16 v3, v3, s0
; GFX12-GISEL-NEXT: v_min_i16 v0, v0, v4
; GFX12-GISEL-NEXT: v_min_i16 v4, v1, s0
@@ -1875,7 +1875,7 @@ define i16 @test_vector_reduce_smin_v3i16(<3 x i16> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x7fff
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-FAKE16-NEXT: v_perm_b32 v1, s0, v1, 0x5040100
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_pk_min_i16 v0, v0, v1
@@ -3229,7 +3229,7 @@ define i64 @test_vector_reduce_smin_v2i64(<2 x i64> %v) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -3358,11 +3358,11 @@ define i64 @test_vector_reduce_smin_v3i64(<3 x i64> %v) {
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v3, v1 :: v_dual_cndmask_b32 v0, v2, v0
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3374,11 +3374,11 @@ define i64 @test_vector_reduce_smin_v3i64(<3 x i64> %v) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -3540,14 +3540,14 @@ define i64 @test_vector_reduce_smin_v4i64(<4 x i64> %v) {
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[6:7]
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v2, v6, v2
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3560,14 +3560,14 @@ define i64 @test_vector_reduce_smin_v4i64(<4 x i64> %v) {
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[6:7]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -3858,27 +3858,27 @@ define i64 @test_vector_reduce_smin_v8i64(<8 x i64> %v) {
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[12:13]
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[6:7], v[14:15]
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s1, v[2:3], v[10:11]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_cndmask_b32 v4, v12, v4
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s1
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s1
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v9, v1 :: v_dual_cndmask_b32 v0, v8, v0
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[6:7]
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v2, v6, v2
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3892,27 +3892,27 @@ define i64 @test_vector_reduce_smin_v8i64(<8 x i64> %v) {
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[8:9]
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[10:11]
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e64 s1, v[4:5], v[12:13]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s1
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s1
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[6:7]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -4459,9 +4459,9 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[0:1], v[16:17]
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s1, v[12:13], v[28:29]
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s2, v[6:7], v[22:23]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v9, v25, v9 :: v_dual_cndmask_b32 v8, v24, v8
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v17, v1, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v16, v0, s0
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[10:11], v[26:27]
@@ -4470,9 +4470,9 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v12, v28, v12, s1
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s1, v[4:5], v[20:21]
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v7, v23, v7, s2
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v11, v27, v11 :: v_dual_cndmask_b32 v10, v26, v10
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v19, v3, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v18, v2, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v5, v21, v5, s1
@@ -4480,7 +4480,7 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v6, v22, v6, s2
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s1, v[0:1], v[8:9]
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[10:11]
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s1
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
@@ -4488,27 +4488,27 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s1
; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[14:15], v[30:31]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v15, v31, v15 :: v_dual_cndmask_b32 v14, v30, v14
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[12:13]
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[6:7], v[14:15]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_cndmask_b32 v4, v12, v4
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s0
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[6:7]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
; GFX12-SDAG-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -4523,60 +4523,60 @@ define i64 @test_vector_reduce_smin_v16i64(<16 x i64> %v) {
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[16:17]
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[18:19]
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e64 s1, v[4:5], v[20:21]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v16, v0 :: v_dual_cndmask_b32 v1, v17, v1
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[22:23]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v18, v2, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v19, v3, s0
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e64 s0, v[8:9], v[24:25]
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, v20, v4, s1
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v5, v21, v5, s1
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v22, v6 :: v_dual_cndmask_b32 v7, v23, v7
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[10:11], v[26:27]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v8, v24, v8, s0
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e64 s1, v[12:13], v[28:29]
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v9, v25, v9, s0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v10, v26, v10 :: v_dual_cndmask_b32 v11, v27, v11
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v12, v28, v12, s1
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v13, v29, v13, s1
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e64 s1, v[4:5], v[12:13]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s1
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s1
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e64 s0, v[14:15], v[30:31]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v14, v30, v14, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v15, v31, v15, s0
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[10:11]
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e64 s0, v[2:3], v[6:7]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
; GFX12-GISEL-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
index e62165cb933c5..87b1e78f73da7 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
@@ -3106,7 +3106,7 @@ define i64 @test_vector_reduce_umax_v2i64(<2 x i64> %v) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -3235,11 +3235,11 @@ define i64 @test_vector_reduce_umax_v3i64(<3 x i64> %v) {
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v3, v1 :: v_dual_cndmask_b32 v0, v2, v0
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3251,11 +3251,11 @@ define i64 @test_vector_reduce_umax_v3i64(<3 x i64> %v) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -3417,14 +3417,14 @@ define i64 @test_vector_reduce_umax_v4i64(<4 x i64> %v) {
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[6:7]
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v2, v6, v2
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3437,14 +3437,14 @@ define i64 @test_vector_reduce_umax_v4i64(<4 x i64> %v) {
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[6:7]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -3735,27 +3735,27 @@ define i64 @test_vector_reduce_umax_v8i64(<8 x i64> %v) {
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[4:5], v[12:13]
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[6:7], v[14:15]
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s1, v[2:3], v[10:11]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_cndmask_b32 v4, v12, v4
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s1
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s1
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v9, v1 :: v_dual_cndmask_b32 v0, v8, v0
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[6:7]
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v2, v6, v2
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3769,27 +3769,27 @@ define i64 @test_vector_reduce_umax_v8i64(<8 x i64> %v) {
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[8:9]
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[10:11]
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e64 s1, v[4:5], v[12:13]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s1
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s1
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[6:7]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -4336,9 +4336,9 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[0:1], v[16:17]
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s1, v[12:13], v[28:29]
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s2, v[6:7], v[22:23]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v9, v25, v9 :: v_dual_cndmask_b32 v8, v24, v8
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v17, v1, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v16, v0, s0
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[10:11], v[26:27]
@@ -4347,9 +4347,9 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v12, v28, v12, s1
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s1, v[4:5], v[20:21]
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v7, v23, v7, s2
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v11, v27, v11 :: v_dual_cndmask_b32 v10, v26, v10
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v19, v3, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v18, v2, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v5, v21, v5, s1
@@ -4357,7 +4357,7 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v6, v22, v6, s2
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s1, v[0:1], v[8:9]
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[10:11]
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s1
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
@@ -4365,27 +4365,27 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s1
; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[14:15], v[30:31]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v15, v31, v15 :: v_dual_cndmask_b32 v14, v30, v14
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[4:5], v[12:13]
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[6:7], v[14:15]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_cndmask_b32 v4, v12, v4
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s0
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[6:7]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -4400,60 +4400,60 @@ define i64 @test_vector_reduce_umax_v16i64(<16 x i64> %v) {
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[16:17]
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[18:19]
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e64 s1, v[4:5], v[20:21]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v16, v0 :: v_dual_cndmask_b32 v1, v17, v1
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[6:7], v[22:23]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v18, v2, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v19, v3, s0
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e64 s0, v[8:9], v[24:25]
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, v20, v4, s1
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v5, v21, v5, s1
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v22, v6 :: v_dual_cndmask_b32 v7, v23, v7
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[10:11], v[26:27]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v8, v24, v8, s0
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e64 s1, v[12:13], v[28:29]
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v9, v25, v9, s0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v10, v26, v10 :: v_dual_cndmask_b32 v11, v27, v11
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v12, v28, v12, s1
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v13, v29, v13, s1
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e64 s1, v[4:5], v[12:13]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s1
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s1
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e64 s0, v[14:15], v[30:31]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v14, v30, v14, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v15, v31, v15, s0
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[10:11]
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e64 s0, v[2:3], v[6:7]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
; GFX12-GISEL-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
index 83ecaaa7e0846..2dd549c191ce9 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
@@ -2842,7 +2842,7 @@ define i64 @test_vector_reduce_umin_v2i64(<2 x i64> %v) {
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -2971,11 +2971,11 @@ define i64 @test_vector_reduce_umin_v3i64(<3 x i64> %v) {
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v3, v1 :: v_dual_cndmask_b32 v0, v2, v0
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -2987,11 +2987,11 @@ define i64 @test_vector_reduce_umin_v3i64(<3 x i64> %v) {
; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -3153,14 +3153,14 @@ define i64 @test_vector_reduce_umin_v4i64(<4 x i64> %v) {
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[6:7]
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v2, v6, v2
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3173,14 +3173,14 @@ define i64 @test_vector_reduce_umin_v4i64(<4 x i64> %v) {
; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[6:7]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -3471,27 +3471,27 @@ define i64 @test_vector_reduce_umin_v8i64(<8 x i64> %v) {
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[12:13]
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[6:7], v[14:15]
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s1, v[2:3], v[10:11]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_cndmask_b32 v4, v12, v4
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s1
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, v2, s1
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v9, v1 :: v_dual_cndmask_b32 v0, v8, v0
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[6:7]
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[0:1], v[4:5]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v2, v6, v2
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -3505,27 +3505,27 @@ define i64 @test_vector_reduce_umin_v8i64(<8 x i64> %v) {
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[8:9]
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[10:11]
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e64 s1, v[4:5], v[12:13]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s1
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s1
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[6:7]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -4072,9 +4072,9 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[0:1], v[16:17]
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s1, v[12:13], v[28:29]
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s2, v[6:7], v[22:23]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v9, v25, v9 :: v_dual_cndmask_b32 v8, v24, v8
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v17, v1, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v16, v0, s0
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[10:11], v[26:27]
@@ -4083,9 +4083,9 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v12, v28, v12, s1
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s1, v[4:5], v[20:21]
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v7, v23, v7, s2
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v11, v27, v11 :: v_dual_cndmask_b32 v10, v26, v10
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v19, v3, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v18, v2, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v5, v21, v5, s1
@@ -4093,7 +4093,7 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v6, v22, v6, s2
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s1, v[0:1], v[8:9]
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[10:11]
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s1
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
@@ -4101,27 +4101,27 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s1
; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[14:15], v[30:31]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v15, v31, v15 :: v_dual_cndmask_b32 v14, v30, v14
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[12:13]
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[6:7], v[14:15]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v5, v13, v5 :: v_dual_cndmask_b32 v4, v12, v4
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v7, v15, v7, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v6, v14, v6, s0
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[6:7]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v0, v4, v0
-; GFX12-SDAG-NEXT: s_wait_alu 0xf1ff
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-SDAG-NEXT: s_wait_alu 0xfffd
+; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -4136,60 +4136,60 @@ define i64 @test_vector_reduce_umin_v16i64(<16 x i64> %v) {
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[16:17]
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[18:19]
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e64 s1, v[4:5], v[20:21]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v16, v0 :: v_dual_cndmask_b32 v1, v17, v1
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[22:23]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v18, v2, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v19, v3, s0
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e64 s0, v[8:9], v[24:25]
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, v20, v4, s1
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v5, v21, v5, s1
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v22, v6 :: v_dual_cndmask_b32 v7, v23, v7
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[10:11], v[26:27]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v8, v24, v8, s0
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e64 s1, v[12:13], v[28:29]
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v9, v25, v9, s0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v10, v26, v10 :: v_dual_cndmask_b32 v11, v27, v11
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[8:9]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v12, v28, v12, s1
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v13, v29, v13, s1
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v8, v0 :: v_dual_cndmask_b32 v1, v9, v1
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e64 s1, v[4:5], v[12:13]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s1
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v5, v13, v5, s1
; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e64 s0, v[14:15], v[30:31]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v14, v30, v14, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v15, v31, v15, s0
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[10:11]
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[14:15]
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v10, v2, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v11, v3, s0
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v6, v14, v6 :: v_dual_cndmask_b32 v7, v15, v7
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[4:5]
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e64 s0, v[2:3], v[6:7]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
-; GFX12-GISEL-NEXT: s_wait_alu 0xf1ff
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
; GFX12-GISEL-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
-; GFX12-GISEL-NEXT: s_wait_alu 0xfffd
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll b/llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
index d15db230524e0..a69dba90a9640 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
@@ -28,7 +28,7 @@ define void @vgpr_descriptor_waterfall_loop_idom_update(ptr %arg) #0 {
; GCN-NEXT: s_and_saveexec_b32 s4, s4
; GCN-NEXT: buffer_store_dword v0, v0, s[8:11], 0 offen
; GCN-NEXT: ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5
-; GCN-NEXT: s_waitcnt_depctr 0xffe3
+; GCN-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GCN-NEXT: s_xor_b32 exec_lo, exec_lo, s4
; GCN-NEXT: s_cbranch_execnz .LBB0_2
; GCN-NEXT: ; %bb.3: ; in Loop: Header=BB0_1 Depth=1
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll b/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
index 14f222a8c8e17..ae998e4c420ba 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
@@ -70,7 +70,7 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s5, -1
; GFX10-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s5
; GFX10-NEXT: v_mov_b32_e32 v36, v16
; GFX10-NEXT: v_mov_b32_e32 v35, v15
@@ -104,7 +104,7 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
; GFX10-NEXT: v_mov_b32_e32 v1, v41
; GFX10-NEXT: v_mov_b32_e32 v2, v42
; GFX10-NEXT: v_mov_b32_e32 v3, v43
-; GFX10-NEXT: s_clause 0x3
+; GFX10-NEXT: s_clause 0x3 ; 16-byte Folded Reload
; GFX10-NEXT: buffer_load_dword v43, off, s[0:3], s33
; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:4
; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:8
@@ -115,7 +115,7 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
; GFX10-NEXT: v_readlane_b32 s4, v44, 2
; GFX10-NEXT: s_or_saveexec_b32 s5, -1
; GFX10-NEXT: buffer_load_dword v44, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s5
; GFX10-NEXT: s_mov_b32 s33, s4
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -132,7 +132,7 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
; GFX11-NEXT: v_dual_mov_b32 v36, v16 :: v_dual_mov_b32 v35, v15
; GFX11-NEXT: v_dual_mov_b32 v34, v14 :: v_dual_mov_b32 v33, v13
; GFX11-NEXT: v_mov_b32_e32 v32, v12
-; GFX11-NEXT: s_clause 0x3
+; GFX11-NEXT: s_clause 0x3 ; 16-byte Folded Spill
; GFX11-NEXT: scratch_store_b32 off, v40, s33 offset:12
; GFX11-NEXT: scratch_store_b32 off, v41, s33 offset:8
; GFX11-NEXT: scratch_store_b32 off, v42, s33 offset:4
@@ -158,7 +158,7 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: v_dual_mov_b32 v0, v40 :: v_dual_mov_b32 v1, v41
; GFX11-NEXT: v_dual_mov_b32 v2, v42 :: v_dual_mov_b32 v3, v43
-; GFX11-NEXT: s_clause 0x3
+; GFX11-NEXT: s_clause 0x3 ; 16-byte Folded Reload
; GFX11-NEXT: scratch_load_b32 v43, off, s33
; GFX11-NEXT: scratch_load_b32 v42, off, s33 offset:4
; GFX11-NEXT: scratch_load_b32 v41, off, s33 offset:8
@@ -254,7 +254,7 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_or_saveexec_b32 s5, -1
; GFX10-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s5
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
@@ -280,7 +280,7 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX10-NEXT: image_gather4_c_b_cl v[0:3], [v44, v43, v42, v41, v40], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
-; GFX10-NEXT: s_clause 0x4
+; GFX10-NEXT: s_clause 0x4 ; 20-byte Folded Reload
; GFX10-NEXT: buffer_load_dword v44, off, s[0:3], s33
; GFX10-NEXT: buffer_load_dword v43, off, s[0:3], s33 offset:4
; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8
@@ -292,7 +292,7 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
; GFX10-NEXT: v_readlane_b32 s4, v45, 2
; GFX10-NEXT: s_or_saveexec_b32 s5, -1
; GFX10-NEXT: buffer_load_dword v45, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
+; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_mov_b32 exec_lo, s5
; GFX10-NEXT: s_mov_b32 s33, s4
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -306,7 +306,7 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-NEXT: scratch_store_b32 off, v45, s33 offset:20 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-NEXT: s_clause 0x4
+; GFX11-NEXT: s_clause 0x4 ; 20-byte Folded Spill
; GFX11-NEXT: scratch_store_b32 off, v40, s33 offset:16
; GFX11-NEXT: scratch_store_b32 off, v41, s33 offset:12
; GFX11-NEXT: scratch_store_b32 off, v42, s33 offset:8
@@ -329,7 +329,7 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: image_gather4_c_b_cl v[0:3], [v44, v43, v42, v41, v40], s[0:7], s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_2D
-; GFX11-NEXT: s_clause 0x4
+; GFX11-NEXT: s_clause 0x4 ; 20-byte Folded Reload
; GFX11-NEXT: scratch_load_b32 v44, off, s33
; GFX11-NEXT: scratch_load_b32 v43, off, s33 offset:4
; GFX11-NEXT: scratch_load_b32 v42, off, s33 offset:8
diff --git a/llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir b/llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
index 27e4d6e9d8032..84ecc5929b9fb 100644
--- a/llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
+++ b/llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
@@ -3,7 +3,7 @@
# GCN-LABEL: name: vmem_write_sgpr
# GCN: BUFFER_LOAD_DWORD_OFFEN
-# GFX10-NEXT: S_WAITCNT_DEPCTR 65507
+# GFX10-NEXT: S_WAITCNT_DEPCTR 65283
# GCN-NEXT: S_MOV_B32
---
name: vmem_write_sgpr
@@ -17,7 +17,7 @@ body: |
...
# GCN-LABEL: name: vmem_write_exec
# GCN: BUFFER_STORE_DWORD_OFFEN_exact
-# GFX10-NEXT: S_WAITCNT_DEPCTR 65507
+# GFX10-NEXT: S_WAITCNT_DEPCTR 65283
# GCN-NEXT: S_MOV_B32
---
name: vmem_write_exec
@@ -36,7 +36,7 @@ body: |
# GCN-NEXT: S_MOV_B32
# GCN-NEXT: S_MOV_B32
# GCN-NEXT: S_MOV_B32
-# GFX10-NEXT: S_WAITCNT_DEPCTR 65507
+# GFX10-NEXT: S_WAITCNT_DEPCTR 65283
# GCN-NEXT: S_MOV_B32
---
name: vmem_write_sgpr_chain
@@ -55,7 +55,7 @@ body: |
...
# GCN-LABEL: name: vmem_smem_write_sgpr
# GCN: BUFFER_LOAD_DWORD_OFFEN
-# GFX10-NEXT: S_WAITCNT_DEPCTR 65507
+# GFX10-NEXT: S_WAITCNT_DEPCTR 65283
# GCN-NEXT: S_LOAD_DWORD_IMM
---
name: vmem_smem_write_sgpr
@@ -70,7 +70,7 @@ body: |
# GCN-LABEL: name: vmem_snop_write_sgpr
# GCN: BUFFER_LOAD_DWORD_OFFEN
# GCN-NEXT: S_NOP
-# GFX10-NEXT: S_WAITCNT_DEPCTR 65507
+# GFX10-NEXT: S_WAITCNT_DEPCTR 65283
# GCN-NEXT: S_MOV_B32
---
name: vmem_snop_write_sgpr
@@ -116,7 +116,7 @@ body: |
# GCN-LABEL: name: vmem_swait_any_write_sgpr
# GCN: BUFFER_LOAD_DWORD_OFFEN
# GCN-NEXT: S_WAITCNT
-# GFX10-NEXT: S_WAITCNT_DEPCTR 65507
+# GFX10-NEXT: S_WAITCNT_DEPCTR 65283
# GCN-NEXT: S_MOV_B32
---
name: vmem_swait_any_write_sgpr
@@ -131,7 +131,7 @@ body: |
...
# GCN-LABEL: name: vmem_write_exec_impread
# GCN: BUFFER_LOAD_DWORD_OFFEN
-# GFX10-NEXT: S_WAITCNT_DEPCTR 65507
+# GFX10-NEXT: S_WAITCNT_DEPCTR 65283
# GCN-NEXT: S_MOV_B64
---
name: vmem_write_exec_impread
@@ -145,7 +145,7 @@ body: |
...
# GCN-LABEL: name: vmem_write_exec_expread
# GCN: BUFFER_LOAD_DWORD_OFFEN
-# GFX10-NEXT: S_WAITCNT_DEPCTR 65507
+# GFX10-NEXT: S_WAITCNT_DEPCTR 65283
# GCN-NEXT: S_MOV_B64
---
name: vmem_write_exec_expread
@@ -158,7 +158,7 @@ body: |
...
# GCN-LABEL: name: ds_write_m0
# GCN: DS_READ_B32
-# GFX10-NEXT: S_WAITCNT_DEPCTR 65507
+# GFX10-NEXT: S_WAITCNT_DEPCTR 65283
# GCN-NEXT: S_MOV_B32
---
name: ds_write_m0
@@ -173,7 +173,7 @@ body: |
# GCN-LABEL: name: vmem_write_sgpr_fall_through
# GCN: BUFFER_LOAD_DWORD_OFFEN
# GCN: bb.1:
-# GFX10-NEXT: S_WAITCNT_DEPCTR 65507
+# GFX10-NEXT: S_WAITCNT_DEPCTR 65283
# GCN-NEXT: S_MOV_B32
---
name: vmem_write_sgpr_fall_through
@@ -192,7 +192,7 @@ body: |
# GCN: BUFFER_LOAD_DWORD_OFFEN
# GCN-NEXT: S_BRANCH
# GCN: bb.1:
-# GFX10-NEXT: S_WAITCNT_DEPCTR 65507
+# GFX10-NEXT: S_WAITCNT_DEPCTR 65283
# GCN-NEXT: S_MOV_B32
---
name: vmem_write_sgpr_branch
@@ -212,7 +212,7 @@ body: |
# GCN: BUFFER_LOAD_DWORD_OFFEN
# GCN-NEXT: S_BRANCH
# GCN: bb.2:
-# GFX10-NEXT: S_WAITCNT_DEPCTR 65507
+# GFX10-NEXT: S_WAITCNT_DEPCTR 65283
# GCN-NEXT: S_MOV_B32
---
name: vmem_write_sgpr_branch_around
@@ -240,7 +240,7 @@ body: |
# GCN: S_WAITCNT
# GCN: V_ADD_CO_U32
# GCN: bb.2:
-# GFX10-NEXT: S_WAITCNT_DEPCTR 65507
+# GFX10-NEXT: S_WAITCNT_DEPCTR 65283
# GCN-NEXT: S_MOV_B32
---
name: vmem_write_sgpr_cbranch_around
@@ -265,7 +265,7 @@ body: |
...
# GCN-LABEL: name: vmem_write_sgpr_branch_backedge
# GCN: $vgpr0 = IMPLICIT_DEF
-# GFX10-NEXT: S_WAITCNT_DEPCTR 65507
+# GFX10-NEXT: S_WAITCNT_DEPCTR 65283
# GCN-NEXT: S_MOV_B32
---
name: vmem_write_sgpr_branch_backedge
@@ -283,7 +283,7 @@ body: |
...
# GCN-LABEL: name: ds_write_exec
# GCN: DS_WRITE_B32_gfx9
-# GFX10-NEXT: S_WAITCNT_DEPCTR 65507
+# GFX10-NEXT: S_WAITCNT_DEPCTR 65283
# GCN-NEXT: S_MOV_B32
---
name: ds_write_exec
@@ -296,7 +296,7 @@ body: |
...
# GCN-LABEL: name: vmem_scratch_exec
# GCN: SCRATCH_LOAD_DWORD
-# GFX10-NEXT: S_WAITCNT_DEPCTR 65507
+# GFX10-NEXT: S_WAITCNT_DEPCTR 65283
# GCN-NEXT: S_MOV_B32
---
name: vmem_scratch_exec
@@ -308,7 +308,7 @@ body: |
...
# GCN-LABEL: name: vmem_flat_exec
# GCN: FLAT_LOAD_DWORD
-# GFX10-NEXT: S_WAITCNT_DEPCTR 65507
+# GFX10-NEXT: S_WAITCNT_DEPCTR 65283
# GCN-NEXT: S_MOV_B32
---
name: vmem_flat_exec
@@ -321,7 +321,7 @@ body: |
...
# GCN-LABEL: name: vmem_global_exec
# GCN: GLOBAL_LOAD_DWORD
-# GFX10-NEXT: S_WAITCNT_DEPCTR 65507
+# GFX10-NEXT: S_WAITCNT_DEPCTR 65283
# GCN-NEXT: S_MOV_B32
---
name: vmem_global_exec
@@ -334,7 +334,7 @@ body: |
...
# GCN-LABEL: name: vmem_global_atomic_exec
# GCN: GLOBAL_ATOMIC_ADD_RTN
-# GFX10-NEXT: S_WAITCNT_DEPCTR 65507
+# GFX10-NEXT: S_WAITCNT_DEPCTR 65283
# GCN-NEXT: S_MOV_B32
---
name: vmem_global_atomic_exec
diff --git a/llvm/test/CodeGen/AMDGPU/wave32.ll b/llvm/test/CodeGen/AMDGPU/wave32.ll
index 28c6b40554bb6..0ae31be32ed51 100644
--- a/llvm/test/CodeGen/AMDGPU/wave32.ll
+++ b/llvm/test/CodeGen/AMDGPU/wave32.ll
@@ -362,7 +362,7 @@ define amdgpu_kernel void @test_loop_with_if(ptr addrspace(1) %arg) #0 {
; GFX1032-NEXT: s_branch .LBB10_2
; GFX1032-NEXT: .LBB10_1: ; %bb13
; GFX1032-NEXT: ; in Loop: Header=BB10_2 Depth=1
-; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX1032-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0xfe, v4
; GFX1032-NEXT: v_add_nc_u32_e32 v1, 1, v4
@@ -424,7 +424,7 @@ define amdgpu_kernel void @test_loop_with_if(ptr addrspace(1) %arg) #0 {
; GFX1064-NEXT: s_branch .LBB10_2
; GFX1064-NEXT: .LBB10_1: ; %bb13
; GFX1064-NEXT: ; in Loop: Header=BB10_2 Depth=1
-; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX1064-NEXT: v_cmp_lt_i32_e32 vcc, 0xfe, v4
; GFX1064-NEXT: v_add_nc_u32_e32 v1, 1, v4
@@ -1262,7 +1262,7 @@ define amdgpu_kernel void @test_div_fmas_f32_i1_phi_vcc(ptr addrspace(1) %out, p
; GFX1032-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX1032-NEXT: s_and_b32 vcc_lo, vcc_lo, exec_lo
; GFX1032-NEXT: .LBB22_2: ; %exit
-; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GFX1032-NEXT: v_mov_b32_e32 v0, 0
; GFX1032-NEXT: s_waitcnt vmcnt(0)
@@ -1289,7 +1289,7 @@ define amdgpu_kernel void @test_div_fmas_f32_i1_phi_vcc(ptr addrspace(1) %out, p
; GFX1064-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX1064-NEXT: s_and_b64 vcc, vcc, exec
; GFX1064-NEXT: .LBB22_2: ; %exit
-; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX1064-NEXT: v_mov_b32_e32 v0, 0
; GFX1064-NEXT: s_waitcnt vmcnt(0)
@@ -3074,7 +3074,7 @@ define void @callee_no_stack_with_call() #1 {
; GFX1032-NEXT: s_mov_b32 s33, s32
; GFX1032-NEXT: s_or_saveexec_b32 s17, -1
; GFX1032-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032-NEXT: s_mov_b32 exec_lo, s17
; GFX1032-NEXT: s_addk_i32 s32, 0x200
; GFX1032-NEXT: v_writelane_b32 v40, s16, 2
@@ -3092,7 +3092,7 @@ define void @callee_no_stack_with_call() #1 {
; GFX1032-NEXT: v_readlane_b32 s4, v40, 2
; GFX1032-NEXT: s_or_saveexec_b32 s5, -1
; GFX1032-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1032-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1032-NEXT: s_mov_b32 exec_lo, s5
; GFX1032-NEXT: s_mov_b32 s33, s4
; GFX1032-NEXT: s_waitcnt vmcnt(0)
@@ -3105,7 +3105,7 @@ define void @callee_no_stack_with_call() #1 {
; GFX1064-NEXT: s_mov_b32 s33, s32
; GFX1064-NEXT: s_or_saveexec_b64 s[18:19], -1
; GFX1064-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064-NEXT: s_mov_b64 exec, s[18:19]
; GFX1064-NEXT: s_addk_i32 s32, 0x400
; GFX1064-NEXT: v_writelane_b32 v40, s16, 2
@@ -3123,7 +3123,7 @@ define void @callee_no_stack_with_call() #1 {
; GFX1064-NEXT: v_readlane_b32 s4, v40, 2
; GFX1064-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX1064-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
+; GFX1064-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX1064-NEXT: s_mov_b64 exec, s[6:7]
; GFX1064-NEXT: s_mov_b32 s33, s4
; GFX1064-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll b/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
index 49031e1d818f0..bfad131dc4413 100644
--- a/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+++ b/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
@@ -22,7 +22,7 @@ define amdgpu_gfx_whole_wave i32 @basic_test(i1 %active, i32 %a, i32 %b) {
; DAGISEL-NEXT: scratch_store_b32 off, v0, s32
; DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4
; DAGISEL-NEXT: s_mov_b32 exec_lo, -1
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: v_dual_cndmask_b32 v0, 5, v0 :: v_dual_cndmask_b32 v1, 3, v1
; DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; DAGISEL-NEXT: v_mov_b32_dpp v0, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
@@ -46,7 +46,7 @@ define amdgpu_gfx_whole_wave i32 @basic_test(i1 %active, i32 %a, i32 %b) {
; GISEL-NEXT: scratch_store_b32 off, v0, s32
; GISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4
; GISEL-NEXT: s_mov_b32 exec_lo, -1
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: v_dual_cndmask_b32 v0, 5, v0 :: v_dual_cndmask_b32 v1, 3, v1
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-NEXT: v_mov_b32_dpp v0, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
@@ -70,7 +70,7 @@ define amdgpu_gfx_whole_wave i32 @basic_test(i1 %active, i32 %a, i32 %b) {
; DAGISEL64-NEXT: scratch_store_b32 off, v0, s32
; DAGISEL64-NEXT: scratch_store_b32 off, v1, s32 offset:4
; DAGISEL64-NEXT: s_mov_b64 exec, -1
-; DAGISEL64-NEXT: s_wait_alu 0xfffe
+; DAGISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL64-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
; DAGISEL64-NEXT: v_cndmask_b32_e32 v1, 3, v1, vcc
; DAGISEL64-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -95,7 +95,7 @@ define amdgpu_gfx_whole_wave i32 @basic_test(i1 %active, i32 %a, i32 %b) {
; GISEL64-NEXT: scratch_store_b32 off, v0, s32
; GISEL64-NEXT: scratch_store_b32 off, v1, s32 offset:4
; GISEL64-NEXT: s_mov_b64 exec, -1
-; GISEL64-NEXT: s_wait_alu 0xfffe
+; GISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL64-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
; GISEL64-NEXT: v_cndmask_b32_e32 v1, 3, v1, vcc
; GISEL64-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -149,7 +149,7 @@ define amdgpu_gfx_whole_wave i32 @single_use_of_active(i1 %active, i32 %a, i32 %
; DAGISEL-NEXT: scratch_store_b32 off, v0, s32
; DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4
; DAGISEL-NEXT: s_mov_b32 exec_lo, -1
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: v_cndmask_b32_e32 v1, 17, v1, vcc_lo
; DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; DAGISEL-NEXT: v_mov_b32_dpp v0, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
@@ -173,7 +173,7 @@ define amdgpu_gfx_whole_wave i32 @single_use_of_active(i1 %active, i32 %a, i32 %
; GISEL-NEXT: scratch_store_b32 off, v0, s32
; GISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4
; GISEL-NEXT: s_mov_b32 exec_lo, -1
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: v_cndmask_b32_e32 v1, 17, v1, vcc_lo
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-NEXT: v_mov_b32_dpp v0, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
@@ -197,7 +197,7 @@ define amdgpu_gfx_whole_wave i32 @single_use_of_active(i1 %active, i32 %a, i32 %
; DAGISEL64-NEXT: scratch_store_b32 off, v0, s32
; DAGISEL64-NEXT: scratch_store_b32 off, v1, s32 offset:4
; DAGISEL64-NEXT: s_mov_b64 exec, -1
-; DAGISEL64-NEXT: s_wait_alu 0xfffe
+; DAGISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL64-NEXT: v_cndmask_b32_e32 v1, 17, v1, vcc
; DAGISEL64-NEXT: s_delay_alu instid0(VALU_DEP_1)
; DAGISEL64-NEXT: v_mov_b32_dpp v0, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
@@ -221,7 +221,7 @@ define amdgpu_gfx_whole_wave i32 @single_use_of_active(i1 %active, i32 %a, i32 %
; GISEL64-NEXT: scratch_store_b32 off, v0, s32
; GISEL64-NEXT: scratch_store_b32 off, v1, s32 offset:4
; GISEL64-NEXT: s_mov_b64 exec, -1
-; GISEL64-NEXT: s_wait_alu 0xfffe
+; GISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL64-NEXT: v_cndmask_b32_e32 v1, 17, v1, vcc
; GISEL64-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL64-NEXT: v_mov_b32_dpp v0, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
@@ -272,7 +272,7 @@ define amdgpu_gfx_whole_wave i32 @unused_active(i1 %active, i32 %a, i32 %b) {
; DAGISEL-NEXT: scratch_store_b32 off, v0, s32 ; 4-byte Folded Spill
; DAGISEL-NEXT: s_mov_b32 exec_lo, -1
; DAGISEL-NEXT: v_mov_b32_e32 v0, 14
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: s_xor_b32 exec_lo, s0, -1
; DAGISEL-NEXT: scratch_load_b32 v0, off, s32 ; 4-byte Folded Reload
; DAGISEL-NEXT: s_mov_b32 exec_lo, s0
@@ -290,7 +290,7 @@ define amdgpu_gfx_whole_wave i32 @unused_active(i1 %active, i32 %a, i32 %b) {
; GISEL-NEXT: scratch_store_b32 off, v0, s32 ; 4-byte Folded Spill
; GISEL-NEXT: s_mov_b32 exec_lo, -1
; GISEL-NEXT: v_mov_b32_e32 v0, 14
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: s_xor_b32 exec_lo, s0, -1
; GISEL-NEXT: scratch_load_b32 v0, off, s32 ; 4-byte Folded Reload
; GISEL-NEXT: s_mov_b32 exec_lo, s0
@@ -308,7 +308,7 @@ define amdgpu_gfx_whole_wave i32 @unused_active(i1 %active, i32 %a, i32 %b) {
; DAGISEL64-NEXT: scratch_store_b32 off, v0, s32 ; 4-byte Folded Spill
; DAGISEL64-NEXT: s_mov_b64 exec, -1
; DAGISEL64-NEXT: v_mov_b32_e32 v0, 14
-; DAGISEL64-NEXT: s_wait_alu 0xfffe
+; DAGISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL64-NEXT: s_xor_b64 exec, s[0:1], -1
; DAGISEL64-NEXT: scratch_load_b32 v0, off, s32 ; 4-byte Folded Reload
; DAGISEL64-NEXT: s_mov_b64 exec, s[0:1]
@@ -326,7 +326,7 @@ define amdgpu_gfx_whole_wave i32 @unused_active(i1 %active, i32 %a, i32 %b) {
; GISEL64-NEXT: scratch_store_b32 off, v0, s32 ; 4-byte Folded Spill
; GISEL64-NEXT: s_mov_b64 exec, -1
; GISEL64-NEXT: v_mov_b32_e32 v0, 14
-; GISEL64-NEXT: s_wait_alu 0xfffe
+; GISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL64-NEXT: s_xor_b64 exec, s[0:1], -1
; GISEL64-NEXT: scratch_load_b32 v0, off, s32 ; 4-byte Folded Reload
; GISEL64-NEXT: s_mov_b64 exec, s[0:1]
@@ -377,7 +377,7 @@ define amdgpu_gfx_whole_wave i32 @csr(i1 %active, i32 %a, i32 %b) {
; DAGISEL-NEXT: ; clobber non-CSR
; DAGISEL-NEXT: ;;#ASMEND
; DAGISEL-NEXT: scratch_load_b32 v40, off, s32 offset:12 ; 4-byte Folded Reload
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: v_dual_cndmask_b32 v0, 5, v0 :: v_dual_cndmask_b32 v1, 3, v1
; DAGISEL-NEXT: v_readlane_b32 s20, v2, 0
; DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -390,7 +390,7 @@ define amdgpu_gfx_whole_wave i32 @csr(i1 %active, i32 %a, i32 %b) {
; DAGISEL-NEXT: scratch_load_b32 v49, off, s32 offset:16
; DAGISEL-NEXT: s_mov_b32 exec_lo, vcc_lo
; DAGISEL-NEXT: s_wait_loadcnt 0x0
-; DAGISEL-NEXT: s_wait_alu 0xf1ff
+; DAGISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; DAGISEL-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-LABEL: csr:
@@ -416,7 +416,7 @@ define amdgpu_gfx_whole_wave i32 @csr(i1 %active, i32 %a, i32 %b) {
; GISEL-NEXT: ; clobber non-CSR
; GISEL-NEXT: ;;#ASMEND
; GISEL-NEXT: scratch_load_b32 v40, off, s32 offset:12 ; 4-byte Folded Reload
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: v_dual_cndmask_b32 v0, 5, v0 :: v_dual_cndmask_b32 v1, 3, v1
; GISEL-NEXT: v_readlane_b32 s20, v2, 0
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -429,7 +429,7 @@ define amdgpu_gfx_whole_wave i32 @csr(i1 %active, i32 %a, i32 %b) {
; GISEL-NEXT: scratch_load_b32 v49, off, s32 offset:16
; GISEL-NEXT: s_mov_b32 exec_lo, vcc_lo
; GISEL-NEXT: s_wait_loadcnt 0x0
-; GISEL-NEXT: s_wait_alu 0xf1ff
+; GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GISEL-NEXT: s_setpc_b64 s[30:31]
;
; DAGISEL64-LABEL: csr:
@@ -455,7 +455,7 @@ define amdgpu_gfx_whole_wave i32 @csr(i1 %active, i32 %a, i32 %b) {
; DAGISEL64-NEXT: ; clobber non-CSR
; DAGISEL64-NEXT: ;;#ASMEND
; DAGISEL64-NEXT: scratch_load_b32 v40, off, s32 offset:12 ; 4-byte Folded Reload
-; DAGISEL64-NEXT: s_wait_alu 0xfffe
+; DAGISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL64-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
; DAGISEL64-NEXT: v_cndmask_b32_e32 v1, 3, v1, vcc
; DAGISEL64-NEXT: v_readlane_b32 s20, v2, 0
@@ -469,7 +469,7 @@ define amdgpu_gfx_whole_wave i32 @csr(i1 %active, i32 %a, i32 %b) {
; DAGISEL64-NEXT: scratch_load_b32 v49, off, s32 offset:16
; DAGISEL64-NEXT: s_mov_b64 exec, vcc
; DAGISEL64-NEXT: s_wait_loadcnt 0x0
-; DAGISEL64-NEXT: s_wait_alu 0xf1ff
+; DAGISEL64-NEXT: s_wait_alu depctr_va_sdst(0)
; DAGISEL64-NEXT: s_setpc_b64 s[30:31]
;
; GISEL64-LABEL: csr:
@@ -495,7 +495,7 @@ define amdgpu_gfx_whole_wave i32 @csr(i1 %active, i32 %a, i32 %b) {
; GISEL64-NEXT: ; clobber non-CSR
; GISEL64-NEXT: ;;#ASMEND
; GISEL64-NEXT: scratch_load_b32 v40, off, s32 offset:12 ; 4-byte Folded Reload
-; GISEL64-NEXT: s_wait_alu 0xfffe
+; GISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL64-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
; GISEL64-NEXT: v_cndmask_b32_e32 v1, 3, v1, vcc
; GISEL64-NEXT: v_readlane_b32 s20, v2, 0
@@ -509,7 +509,7 @@ define amdgpu_gfx_whole_wave i32 @csr(i1 %active, i32 %a, i32 %b) {
; GISEL64-NEXT: scratch_load_b32 v49, off, s32 offset:16
; GISEL64-NEXT: s_mov_b64 exec, vcc
; GISEL64-NEXT: s_wait_loadcnt 0x0
-; GISEL64-NEXT: s_wait_alu 0xf1ff
+; GISEL64-NEXT: s_wait_alu depctr_va_sdst(0)
; GISEL64-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-DAGISEL-LABEL: csr:
@@ -572,7 +572,7 @@ define amdgpu_gfx_whole_wave void @csr_vgpr_only(i1 %active, i32 %a, i32 %b) {
; DAGISEL-NEXT: ; clobber CSR VGPR
; DAGISEL-NEXT: ;;#ASMEND
; DAGISEL-NEXT: scratch_load_b32 v40, off, s32 ; 4-byte Folded Reload
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: s_mov_b32 exec_lo, s0
; DAGISEL-NEXT: s_wait_loadcnt 0x0
; DAGISEL-NEXT: s_setpc_b64 s[30:31]
@@ -590,7 +590,7 @@ define amdgpu_gfx_whole_wave void @csr_vgpr_only(i1 %active, i32 %a, i32 %b) {
; GISEL-NEXT: ; clobber CSR VGPR
; GISEL-NEXT: ;;#ASMEND
; GISEL-NEXT: scratch_load_b32 v40, off, s32 ; 4-byte Folded Reload
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: s_mov_b32 exec_lo, s0
; GISEL-NEXT: s_wait_loadcnt 0x0
; GISEL-NEXT: s_setpc_b64 s[30:31]
@@ -608,7 +608,7 @@ define amdgpu_gfx_whole_wave void @csr_vgpr_only(i1 %active, i32 %a, i32 %b) {
; DAGISEL64-NEXT: ; clobber CSR VGPR
; DAGISEL64-NEXT: ;;#ASMEND
; DAGISEL64-NEXT: scratch_load_b32 v40, off, s32 ; 4-byte Folded Reload
-; DAGISEL64-NEXT: s_wait_alu 0xfffe
+; DAGISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL64-NEXT: s_mov_b64 exec, s[0:1]
; DAGISEL64-NEXT: s_wait_loadcnt 0x0
; DAGISEL64-NEXT: s_setpc_b64 s[30:31]
@@ -626,7 +626,7 @@ define amdgpu_gfx_whole_wave void @csr_vgpr_only(i1 %active, i32 %a, i32 %b) {
; GISEL64-NEXT: ; clobber CSR VGPR
; GISEL64-NEXT: ;;#ASMEND
; GISEL64-NEXT: scratch_load_b32 v40, off, s32 ; 4-byte Folded Reload
-; GISEL64-NEXT: s_wait_alu 0xfffe
+; GISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL64-NEXT: s_mov_b64 exec, s[0:1]
; GISEL64-NEXT: s_wait_loadcnt 0x0
; GISEL64-NEXT: s_setpc_b64 s[30:31]
@@ -667,7 +667,7 @@ define amdgpu_gfx_whole_wave void @sgpr_spill_only(i1 %active, i32 %a, i32 %b) {
; DAGISEL-NEXT: ;;#ASMEND
; DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; DAGISEL-NEXT: v_readlane_b32 s68, v0, 0
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: s_xor_b32 exec_lo, s0, -1
; DAGISEL-NEXT: scratch_load_b32 v0, off, s32 ; 4-byte Folded Reload
; DAGISEL-NEXT: s_mov_b32 exec_lo, s0
@@ -690,7 +690,7 @@ define amdgpu_gfx_whole_wave void @sgpr_spill_only(i1 %active, i32 %a, i32 %b) {
; GISEL-NEXT: ;;#ASMEND
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-NEXT: v_readlane_b32 s68, v0, 0
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: s_xor_b32 exec_lo, s0, -1
; GISEL-NEXT: scratch_load_b32 v0, off, s32 ; 4-byte Folded Reload
; GISEL-NEXT: s_mov_b32 exec_lo, s0
@@ -713,7 +713,7 @@ define amdgpu_gfx_whole_wave void @sgpr_spill_only(i1 %active, i32 %a, i32 %b) {
; DAGISEL64-NEXT: ;;#ASMEND
; DAGISEL64-NEXT: s_delay_alu instid0(VALU_DEP_1)
; DAGISEL64-NEXT: v_readlane_b32 s68, v0, 0
-; DAGISEL64-NEXT: s_wait_alu 0xfffe
+; DAGISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL64-NEXT: s_xor_b64 exec, s[0:1], -1
; DAGISEL64-NEXT: scratch_load_b32 v0, off, s32 ; 4-byte Folded Reload
; DAGISEL64-NEXT: s_mov_b64 exec, s[0:1]
@@ -736,7 +736,7 @@ define amdgpu_gfx_whole_wave void @sgpr_spill_only(i1 %active, i32 %a, i32 %b) {
; GISEL64-NEXT: ;;#ASMEND
; GISEL64-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL64-NEXT: v_readlane_b32 s68, v0, 0
-; GISEL64-NEXT: s_wait_alu 0xfffe
+; GISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL64-NEXT: s_xor_b64 exec, s[0:1], -1
; GISEL64-NEXT: scratch_load_b32 v0, off, s32 ; 4-byte Folded Reload
; GISEL64-NEXT: s_mov_b64 exec, s[0:1]
@@ -777,7 +777,7 @@ define amdgpu_gfx_whole_wave void @realign_stack(i1 %active, i32 %x) {
; DAGISEL-NEXT: s_wait_kmcnt 0x0
; DAGISEL-NEXT: s_mov_b32 s1, s33
; DAGISEL-NEXT: s_add_co_i32 s33, s32, 0x3ff
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: s_and_b32 s33, s33, 0xfffffc00
; DAGISEL-NEXT: s_xor_saveexec_b32 s0, -1
; DAGISEL-NEXT: s_mov_b32 s2, s34
@@ -786,12 +786,12 @@ define amdgpu_gfx_whole_wave void @realign_stack(i1 %active, i32 %x) {
; DAGISEL-NEXT: s_wait_storecnt 0x0
; DAGISEL-NEXT: scratch_store_b32 off, v0, s33 scope:SCOPE_SYS
; DAGISEL-NEXT: s_wait_storecnt 0x0
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: s_mov_b32 s32, s34
; DAGISEL-NEXT: s_mov_b32 s34, s2
; DAGISEL-NEXT: s_mov_b32 exec_lo, s0
; DAGISEL-NEXT: s_mov_b32 s33, s1
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-LABEL: realign_stack:
@@ -803,7 +803,7 @@ define amdgpu_gfx_whole_wave void @realign_stack(i1 %active, i32 %x) {
; GISEL-NEXT: s_wait_kmcnt 0x0
; GISEL-NEXT: s_mov_b32 s1, s33
; GISEL-NEXT: s_add_co_i32 s33, s32, 0x3ff
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: s_and_b32 s33, s33, 0xfffffc00
; GISEL-NEXT: s_xor_saveexec_b32 s0, -1
; GISEL-NEXT: s_mov_b32 s2, s34
@@ -812,12 +812,12 @@ define amdgpu_gfx_whole_wave void @realign_stack(i1 %active, i32 %x) {
; GISEL-NEXT: s_wait_storecnt 0x0
; GISEL-NEXT: scratch_store_b32 off, v0, s33 scope:SCOPE_SYS
; GISEL-NEXT: s_wait_storecnt 0x0
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: s_mov_b32 s32, s34
; GISEL-NEXT: s_mov_b32 s34, s2
; GISEL-NEXT: s_mov_b32 exec_lo, s0
; GISEL-NEXT: s_mov_b32 s33, s1
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: s_setpc_b64 s[30:31]
;
; DAGISEL64-LABEL: realign_stack:
@@ -829,7 +829,7 @@ define amdgpu_gfx_whole_wave void @realign_stack(i1 %active, i32 %x) {
; DAGISEL64-NEXT: s_wait_kmcnt 0x0
; DAGISEL64-NEXT: s_mov_b32 s2, s33
; DAGISEL64-NEXT: s_add_co_i32 s33, s32, 0x3ff
-; DAGISEL64-NEXT: s_wait_alu 0xfffe
+; DAGISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL64-NEXT: s_and_b32 s33, s33, 0xfffffc00
; DAGISEL64-NEXT: s_xor_saveexec_b64 s[0:1], -1
; DAGISEL64-NEXT: s_mov_b32 s3, s34
@@ -838,12 +838,12 @@ define amdgpu_gfx_whole_wave void @realign_stack(i1 %active, i32 %x) {
; DAGISEL64-NEXT: s_wait_storecnt 0x0
; DAGISEL64-NEXT: scratch_store_b32 off, v0, s33 scope:SCOPE_SYS
; DAGISEL64-NEXT: s_wait_storecnt 0x0
-; DAGISEL64-NEXT: s_wait_alu 0xfffe
+; DAGISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL64-NEXT: s_mov_b32 s32, s34
; DAGISEL64-NEXT: s_mov_b32 s34, s3
; DAGISEL64-NEXT: s_mov_b64 exec, s[0:1]
; DAGISEL64-NEXT: s_mov_b32 s33, s2
-; DAGISEL64-NEXT: s_wait_alu 0xfffe
+; DAGISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL64-NEXT: s_setpc_b64 s[30:31]
;
; GISEL64-LABEL: realign_stack:
@@ -855,7 +855,7 @@ define amdgpu_gfx_whole_wave void @realign_stack(i1 %active, i32 %x) {
; GISEL64-NEXT: s_wait_kmcnt 0x0
; GISEL64-NEXT: s_mov_b32 s2, s33
; GISEL64-NEXT: s_add_co_i32 s33, s32, 0x3ff
-; GISEL64-NEXT: s_wait_alu 0xfffe
+; GISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL64-NEXT: s_and_b32 s33, s33, 0xfffffc00
; GISEL64-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GISEL64-NEXT: s_mov_b32 s3, s34
@@ -864,12 +864,12 @@ define amdgpu_gfx_whole_wave void @realign_stack(i1 %active, i32 %x) {
; GISEL64-NEXT: s_wait_storecnt 0x0
; GISEL64-NEXT: scratch_store_b32 off, v0, s33 scope:SCOPE_SYS
; GISEL64-NEXT: s_wait_storecnt 0x0
-; GISEL64-NEXT: s_wait_alu 0xfffe
+; GISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL64-NEXT: s_mov_b32 s32, s34
; GISEL64-NEXT: s_mov_b32 s34, s3
; GISEL64-NEXT: s_mov_b64 exec, s[0:1]
; GISEL64-NEXT: s_mov_b32 s33, s2
-; GISEL64-NEXT: s_wait_alu 0xfffe
+; GISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL64-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-DAGISEL-LABEL: realign_stack:
@@ -916,7 +916,7 @@ define amdgpu_gfx_whole_wave i32 @multiple_blocks(i1 %active, i32 %a, i32 %b) {
; DAGISEL-NEXT: ; %bb.1: ; %if.then
; DAGISEL-NEXT: v_add_nc_u32_e32 v1, v0, v1
; DAGISEL-NEXT: ; %bb.2: ; %if.end
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: s_or_b32 exec_lo, exec_lo, s1
; DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; DAGISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
@@ -946,7 +946,7 @@ define amdgpu_gfx_whole_wave i32 @multiple_blocks(i1 %active, i32 %a, i32 %b) {
; GISEL-NEXT: ; %bb.1: ; %if.then
; GISEL-NEXT: v_add_nc_u32_e32 v1, v0, v1
; GISEL-NEXT: ; %bb.2: ; %if.end
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s1
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
@@ -976,7 +976,7 @@ define amdgpu_gfx_whole_wave i32 @multiple_blocks(i1 %active, i32 %a, i32 %b) {
; DAGISEL64-NEXT: ; %bb.1: ; %if.then
; DAGISEL64-NEXT: v_add_nc_u32_e32 v1, v0, v1
; DAGISEL64-NEXT: ; %bb.2: ; %if.end
-; DAGISEL64-NEXT: s_wait_alu 0xfffe
+; DAGISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL64-NEXT: s_or_b64 exec, exec, s[2:3]
; DAGISEL64-NEXT: s_delay_alu instid0(VALU_DEP_1)
; DAGISEL64-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -1006,7 +1006,7 @@ define amdgpu_gfx_whole_wave i32 @multiple_blocks(i1 %active, i32 %a, i32 %b) {
; GISEL64-NEXT: ; %bb.1: ; %if.then
; GISEL64-NEXT: v_add_nc_u32_e32 v1, v0, v1
; GISEL64-NEXT: ; %bb.2: ; %if.end
-; GISEL64-NEXT: s_wait_alu 0xfffe
+; GISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL64-NEXT: s_or_b64 exec, exec, s[2:3]
; GISEL64-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL64-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
@@ -1073,7 +1073,7 @@ define amdgpu_gfx_whole_wave i64 @ret_64(i1 %active, i64 %a, i64 %b) {
; DAGISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8
; DAGISEL-NEXT: scratch_store_b32 off, v3, s32 offset:12
; DAGISEL-NEXT: s_mov_b32 exec_lo, -1
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 5, v0
; DAGISEL-NEXT: v_dual_cndmask_b32 v2, 3, v2 :: v_dual_cndmask_b32 v3, 0, v3
; DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -1103,7 +1103,7 @@ define amdgpu_gfx_whole_wave i64 @ret_64(i1 %active, i64 %a, i64 %b) {
; GISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8
; GISEL-NEXT: scratch_store_b32 off, v3, s32 offset:12
; GISEL-NEXT: s_mov_b32 exec_lo, -1
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: v_dual_cndmask_b32 v0, 5, v0 :: v_dual_cndmask_b32 v1, 0, v1
; GISEL-NEXT: v_dual_cndmask_b32 v2, 3, v2 :: v_dual_cndmask_b32 v3, 0, v3
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -1133,7 +1133,7 @@ define amdgpu_gfx_whole_wave i64 @ret_64(i1 %active, i64 %a, i64 %b) {
; DAGISEL64-NEXT: scratch_store_b32 off, v2, s32 offset:8
; DAGISEL64-NEXT: scratch_store_b32 off, v3, s32 offset:12
; DAGISEL64-NEXT: s_mov_b64 exec, -1
-; DAGISEL64-NEXT: s_wait_alu 0xfffe
+; DAGISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL64-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; DAGISEL64-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
; DAGISEL64-NEXT: v_cndmask_b32_e32 v2, 3, v2, vcc
@@ -1165,7 +1165,7 @@ define amdgpu_gfx_whole_wave i64 @ret_64(i1 %active, i64 %a, i64 %b) {
; GISEL64-NEXT: scratch_store_b32 off, v2, s32 offset:8
; GISEL64-NEXT: scratch_store_b32 off, v3, s32 offset:12
; GISEL64-NEXT: s_mov_b64 exec, -1
-; GISEL64-NEXT: s_wait_alu 0xfffe
+; GISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL64-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc
; GISEL64-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GISEL64-NEXT: v_cndmask_b32_e32 v2, 3, v2, vcc
@@ -1240,7 +1240,7 @@ define amdgpu_gfx_whole_wave void @inreg_args(i1 %active, i32 inreg %i32, <4 x i
; DAGISEL-NEXT: s_clause 0x1
; DAGISEL-NEXT: scratch_store_b128 off, v[0:3], s11
; DAGISEL-NEXT: scratch_store_b32 off, v5, s11
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: s_xor_b32 exec_lo, s0, -1
; DAGISEL-NEXT: s_clause 0x5 ; 24-byte Folded Reload
; DAGISEL-NEXT: scratch_load_b32 v0, off, s32
@@ -1274,7 +1274,7 @@ define amdgpu_gfx_whole_wave void @inreg_args(i1 %active, i32 inreg %i32, <4 x i
; GISEL-NEXT: s_mov_b32 s2, s7
; GISEL-NEXT: s_mov_b32 s3, s8
; GISEL-NEXT: v_mov_b32_e32 v4, s4
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
; GISEL-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
; GISEL-NEXT: v_mov_b32_e32 v5, s9
@@ -1320,7 +1320,7 @@ define amdgpu_gfx_whole_wave void @inreg_args(i1 %active, i32 inreg %i32, <4 x i
; DAGISEL64-NEXT: s_clause 0x1
; DAGISEL64-NEXT: scratch_store_b128 off, v[0:3], s11
; DAGISEL64-NEXT: scratch_store_b32 off, v5, s11
-; DAGISEL64-NEXT: s_wait_alu 0xfffe
+; DAGISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL64-NEXT: s_xor_b64 exec, s[0:1], -1
; DAGISEL64-NEXT: s_clause 0x5 ; 24-byte Folded Reload
; DAGISEL64-NEXT: scratch_load_b32 v0, off, s32
@@ -1354,7 +1354,7 @@ define amdgpu_gfx_whole_wave void @inreg_args(i1 %active, i32 inreg %i32, <4 x i
; GISEL64-NEXT: s_mov_b32 s2, s7
; GISEL64-NEXT: s_mov_b32 s3, s8
; GISEL64-NEXT: v_mov_b32_e32 v4, s4
-; GISEL64-NEXT: s_wait_alu 0xfffe
+; GISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL64-NEXT: v_mov_b32_e32 v0, s0
; GISEL64-NEXT: v_mov_b32_e32 v1, s1
; GISEL64-NEXT: v_mov_b32_e32 v2, s2
@@ -1580,7 +1580,7 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2
; DAGISEL-NEXT: scratch_store_b32 off, v247, s33 offset:576
; DAGISEL-NEXT: s_mov_b32 exec_lo, -1
; DAGISEL-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: v_writelane_b32 v40, s0, 3
; DAGISEL-NEXT: v_mov_b32_e32 v2, v0
; DAGISEL-NEXT: v_swap_b32 v0, v1
@@ -1590,7 +1590,7 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2
; DAGISEL-NEXT: s_addk_co_i32 s32, 0x250
; DAGISEL-NEXT: v_writelane_b32 v40, s30, 1
; DAGISEL-NEXT: v_writelane_b32 v40, s31, 2
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
; DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; DAGISEL-NEXT: v_readlane_b32 s31, v40, 2
@@ -1752,7 +1752,7 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2
; DAGISEL-NEXT: s_mov_b32 exec_lo, s4
; DAGISEL-NEXT: s_mov_b32 s33, s0
; DAGISEL-NEXT: s_wait_loadcnt 0x0
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-LABEL: call_gfx_from_whole_wave:
@@ -1916,7 +1916,7 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2
; GISEL-NEXT: scratch_store_b32 off, v247, s33 offset:576
; GISEL-NEXT: s_mov_b32 exec_lo, -1
; GISEL-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: v_writelane_b32 v40, s0, 3
; GISEL-NEXT: v_mov_b32_e32 v2, v0
; GISEL-NEXT: v_swap_b32 v0, v1
@@ -1926,7 +1926,7 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2
; GISEL-NEXT: s_addk_co_i32 s32, 0x250
; GISEL-NEXT: v_writelane_b32 v40, s30, 1
; GISEL-NEXT: v_writelane_b32 v40, s31, 2
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-NEXT: v_readlane_b32 s31, v40, 2
@@ -2088,7 +2088,7 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2
; GISEL-NEXT: s_mov_b32 exec_lo, s4
; GISEL-NEXT: s_mov_b32 s33, s0
; GISEL-NEXT: s_wait_loadcnt 0x0
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: s_setpc_b64 s[30:31]
;
; DAGISEL64-LABEL: call_gfx_from_whole_wave:
@@ -2252,7 +2252,7 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2
; DAGISEL64-NEXT: scratch_store_b32 off, v247, s33 offset:576
; DAGISEL64-NEXT: s_mov_b64 exec, -1
; DAGISEL64-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
-; DAGISEL64-NEXT: s_wait_alu 0xfffe
+; DAGISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL64-NEXT: v_writelane_b32 v40, s0, 4
; DAGISEL64-NEXT: v_mov_b32_e32 v2, v0
; DAGISEL64-NEXT: v_swap_b32 v0, v1
@@ -2263,7 +2263,7 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2
; DAGISEL64-NEXT: v_writelane_b32 v40, s5, 1
; DAGISEL64-NEXT: v_writelane_b32 v40, s30, 2
; DAGISEL64-NEXT: v_writelane_b32 v40, s31, 3
-; DAGISEL64-NEXT: s_wait_alu 0xfffe
+; DAGISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL64-NEXT: s_swappc_b64 s[30:31], s[0:1]
; DAGISEL64-NEXT: s_delay_alu instid0(VALU_DEP_1)
; DAGISEL64-NEXT: v_readlane_b32 s31, v40, 3
@@ -2426,7 +2426,7 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2
; DAGISEL64-NEXT: s_mov_b64 exec, s[4:5]
; DAGISEL64-NEXT: s_mov_b32 s33, s0
; DAGISEL64-NEXT: s_wait_loadcnt 0x0
-; DAGISEL64-NEXT: s_wait_alu 0xfffe
+; DAGISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL64-NEXT: s_setpc_b64 s[30:31]
;
; GISEL64-LABEL: call_gfx_from_whole_wave:
@@ -2590,7 +2590,7 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2
; GISEL64-NEXT: scratch_store_b32 off, v247, s33 offset:576
; GISEL64-NEXT: s_mov_b64 exec, -1
; GISEL64-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
-; GISEL64-NEXT: s_wait_alu 0xfffe
+; GISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL64-NEXT: v_writelane_b32 v40, s0, 4
; GISEL64-NEXT: v_mov_b32_e32 v2, v0
; GISEL64-NEXT: v_swap_b32 v0, v1
@@ -2601,7 +2601,7 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2
; GISEL64-NEXT: v_writelane_b32 v40, s5, 1
; GISEL64-NEXT: v_writelane_b32 v40, s30, 2
; GISEL64-NEXT: v_writelane_b32 v40, s31, 3
-; GISEL64-NEXT: s_wait_alu 0xfffe
+; GISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL64-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GISEL64-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL64-NEXT: v_readlane_b32 s31, v40, 3
@@ -2764,7 +2764,7 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2
; GISEL64-NEXT: s_mov_b64 exec, s[4:5]
; GISEL64-NEXT: s_mov_b32 s33, s0
; GISEL64-NEXT: s_wait_loadcnt 0x0
-; GISEL64-NEXT: s_wait_alu 0xfffe
+; GISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL64-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-DAGISEL-LABEL: call_gfx_from_whole_wave:
@@ -4831,7 +4831,7 @@ define amdgpu_gfx_whole_wave <2 x half> @tail_call_gfx_from_whole_wave(i1 %activ
; DAGISEL-NEXT: s_mov_b32 s37, gfx_callee at abs32@hi
; DAGISEL-NEXT: s_mov_b32 s36, gfx_callee at abs32@lo
; DAGISEL-NEXT: v_swap_b32 v0, v1
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: s_xor_b32 exec_lo, s0, -1
; DAGISEL-NEXT: s_clause 0x1f ; 128-byte Folded Reload
; DAGISEL-NEXT: scratch_load_b32 v0, off, s32
@@ -5147,7 +5147,7 @@ define amdgpu_gfx_whole_wave <2 x half> @tail_call_gfx_from_whole_wave(i1 %activ
; GISEL-NEXT: v_swap_b32 v0, v1
; GISEL-NEXT: s_mov_b32 s36, gfx_callee at abs32@lo
; GISEL-NEXT: s_mov_b32 s37, gfx_callee at abs32@hi
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: s_xor_b32 exec_lo, s0, -1
; GISEL-NEXT: s_clause 0x1f ; 128-byte Folded Reload
; GISEL-NEXT: scratch_load_b32 v0, off, s32
@@ -5463,7 +5463,7 @@ define amdgpu_gfx_whole_wave <2 x half> @tail_call_gfx_from_whole_wave(i1 %activ
; DAGISEL64-NEXT: s_mov_b32 s37, gfx_callee at abs32@hi
; DAGISEL64-NEXT: s_mov_b32 s36, gfx_callee at abs32@lo
; DAGISEL64-NEXT: v_swap_b32 v0, v1
-; DAGISEL64-NEXT: s_wait_alu 0xfffe
+; DAGISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL64-NEXT: s_xor_b64 exec, s[0:1], -1
; DAGISEL64-NEXT: s_clause 0x1f ; 128-byte Folded Reload
; DAGISEL64-NEXT: scratch_load_b32 v0, off, s32
@@ -5779,7 +5779,7 @@ define amdgpu_gfx_whole_wave <2 x half> @tail_call_gfx_from_whole_wave(i1 %activ
; GISEL64-NEXT: v_swap_b32 v0, v1
; GISEL64-NEXT: s_mov_b32 s36, gfx_callee at abs32@lo
; GISEL64-NEXT: s_mov_b32 s37, gfx_callee at abs32@hi
-; GISEL64-NEXT: s_wait_alu 0xfffe
+; GISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL64-NEXT: s_xor_b64 exec, s[0:1], -1
; GISEL64-NEXT: s_clause 0x1f ; 128-byte Folded Reload
; GISEL64-NEXT: scratch_load_b32 v0, off, s32
@@ -8037,7 +8037,7 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float>
; DAGISEL-NEXT: scratch_store_b32 off, v42, s33
; DAGISEL-NEXT: scratch_store_b32 off, v40, s33 offset:164
; DAGISEL-NEXT: scratch_store_b32 off, v41, s33 offset:168
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: v_writelane_b32 v42, s0, 3
; DAGISEL-NEXT: s_mov_b32 s1, callee at abs32@hi
; DAGISEL-NEXT: s_mov_b32 s0, callee at abs32@lo
@@ -8046,7 +8046,7 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float>
; DAGISEL-NEXT: v_writelane_b32 v42, s4, 0
; DAGISEL-NEXT: v_writelane_b32 v42, s30, 1
; DAGISEL-NEXT: v_writelane_b32 v42, s31, 2
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
; DAGISEL-NEXT: flat_store_b32 v[40:41], v0
; DAGISEL-NEXT: v_readlane_b32 s31, v42, 2
@@ -8211,7 +8211,7 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float>
; DAGISEL-NEXT: s_mov_b32 exec_lo, s4
; DAGISEL-NEXT: s_mov_b32 s33, s0
; DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; DAGISEL-NEXT: s_wait_alu 0xfffe
+; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-LABEL: call_from_whole_wave:
@@ -8378,7 +8378,7 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float>
; GISEL-NEXT: scratch_store_b32 off, v42, s33
; GISEL-NEXT: scratch_store_b32 off, v40, s33 offset:164
; GISEL-NEXT: scratch_store_b32 off, v41, s33 offset:168
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: v_writelane_b32 v42, s0, 3
; GISEL-NEXT: s_mov_b32 s0, callee at abs32@lo
; GISEL-NEXT: s_mov_b32 s1, callee at abs32@hi
@@ -8387,7 +8387,7 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float>
; GISEL-NEXT: v_writelane_b32 v42, s4, 0
; GISEL-NEXT: v_writelane_b32 v42, s30, 1
; GISEL-NEXT: v_writelane_b32 v42, s31, 2
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GISEL-NEXT: flat_store_b32 v[40:41], v0
; GISEL-NEXT: v_readlane_b32 s31, v42, 2
@@ -8552,7 +8552,7 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float>
; GISEL-NEXT: s_mov_b32 exec_lo, s4
; GISEL-NEXT: s_mov_b32 s33, s0
; GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GISEL-NEXT: s_wait_alu 0xfffe
+; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-NEXT: s_setpc_b64 s[30:31]
;
; DAGISEL64-LABEL: call_from_whole_wave:
@@ -8719,7 +8719,7 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float>
; DAGISEL64-NEXT: scratch_store_b32 off, v42, s33
; DAGISEL64-NEXT: scratch_store_b32 off, v40, s33 offset:164
; DAGISEL64-NEXT: scratch_store_b32 off, v41, s33 offset:168
-; DAGISEL64-NEXT: s_wait_alu 0xfffe
+; DAGISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL64-NEXT: v_writelane_b32 v42, s0, 4
; DAGISEL64-NEXT: s_mov_b32 s1, callee at abs32@hi
; DAGISEL64-NEXT: s_mov_b32 s0, callee at abs32@lo
@@ -8730,7 +8730,7 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float>
; DAGISEL64-NEXT: v_writelane_b32 v42, s5, 1
; DAGISEL64-NEXT: v_writelane_b32 v42, s30, 2
; DAGISEL64-NEXT: v_writelane_b32 v42, s31, 3
-; DAGISEL64-NEXT: s_wait_alu 0xfffe
+; DAGISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL64-NEXT: s_swappc_b64 s[30:31], s[0:1]
; DAGISEL64-NEXT: flat_store_b32 v[40:41], v0
; DAGISEL64-NEXT: v_readlane_b32 s31, v42, 3
@@ -8896,7 +8896,7 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float>
; DAGISEL64-NEXT: s_mov_b64 exec, s[4:5]
; DAGISEL64-NEXT: s_mov_b32 s33, s0
; DAGISEL64-NEXT: s_wait_loadcnt_dscnt 0x0
-; DAGISEL64-NEXT: s_wait_alu 0xfffe
+; DAGISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL64-NEXT: s_setpc_b64 s[30:31]
;
; GISEL64-LABEL: call_from_whole_wave:
@@ -9063,7 +9063,7 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float>
; GISEL64-NEXT: scratch_store_b32 off, v42, s33
; GISEL64-NEXT: scratch_store_b32 off, v40, s33 offset:164
; GISEL64-NEXT: scratch_store_b32 off, v41, s33 offset:168
-; GISEL64-NEXT: s_wait_alu 0xfffe
+; GISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL64-NEXT: v_writelane_b32 v42, s0, 4
; GISEL64-NEXT: s_mov_b32 s0, callee at abs32@lo
; GISEL64-NEXT: s_mov_b32 s1, callee at abs32@hi
@@ -9074,7 +9074,7 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float>
; GISEL64-NEXT: v_writelane_b32 v42, s5, 1
; GISEL64-NEXT: v_writelane_b32 v42, s30, 2
; GISEL64-NEXT: v_writelane_b32 v42, s31, 3
-; GISEL64-NEXT: s_wait_alu 0xfffe
+; GISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL64-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GISEL64-NEXT: flat_store_b32 v[40:41], v0
; GISEL64-NEXT: v_readlane_b32 s31, v42, 3
@@ -9240,7 +9240,7 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float>
; GISEL64-NEXT: s_mov_b64 exec, s[4:5]
; GISEL64-NEXT: s_mov_b32 s33, s0
; GISEL64-NEXT: s_wait_loadcnt_dscnt 0x0
-; GISEL64-NEXT: s_wait_alu 0xfffe
+; GISEL64-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL64-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-DAGISEL-LABEL: call_from_whole_wave:
diff --git a/llvm/test/CodeGen/AMDGPU/workitem-intrinsic-opts.ll b/llvm/test/CodeGen/AMDGPU/workitem-intrinsic-opts.ll
index 4445383bd0ace..d0c7b2441968a 100644
--- a/llvm/test/CodeGen/AMDGPU/workitem-intrinsic-opts.ll
+++ b/llvm/test/CodeGen/AMDGPU/workitem-intrinsic-opts.ll
@@ -36,7 +36,7 @@ define i1 @workitem_zero() {
; DAGISEL-GFX12-NEXT: v_and_b32_e32 v0, 0x3fffffff, v31
; DAGISEL-GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; DAGISEL-GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; DAGISEL-GFX12-NEXT: s_wait_alu 0xfffd
+; DAGISEL-GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; DAGISEL-GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; DAGISEL-GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -77,7 +77,7 @@ define i1 @workitem_zero() {
; GISEL-GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GISEL-GFX12-NEXT: v_or3_b32 v0, v0, v1, v2
; GISEL-GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GISEL-GFX12-NEXT: s_wait_alu 0xfffd
+; GISEL-GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GISEL-GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GISEL-GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -119,7 +119,7 @@ define i1 @workitem_nonzero() {
; DAGISEL-GFX12-NEXT: v_and_b32_e32 v0, 0x3fffffff, v31
; DAGISEL-GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; DAGISEL-GFX12-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; DAGISEL-GFX12-NEXT: s_wait_alu 0xfffd
+; DAGISEL-GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; DAGISEL-GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; DAGISEL-GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -160,7 +160,7 @@ define i1 @workitem_nonzero() {
; GISEL-GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GISEL-GFX12-NEXT: v_or3_b32 v0, v0, v1, v2
; GISEL-GFX12-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GISEL-GFX12-NEXT: s_wait_alu 0xfffd
+; GISEL-GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GISEL-GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GISEL-GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -203,15 +203,15 @@ define i1 @workgroup_zero() {
; DAGISEL-GFX12-NEXT: s_wait_bvhcnt 0x0
; DAGISEL-GFX12-NEXT: s_wait_kmcnt 0x0
; DAGISEL-GFX12-NEXT: s_and_b32 s0, ttmp7, 0xffff
-; DAGISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; DAGISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-GFX12-NEXT: s_lshr_b32 s1, ttmp7, 16
; DAGISEL-GFX12-NEXT: s_or_b32 s0, ttmp9, s0
-; DAGISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; DAGISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-GFX12-NEXT: s_or_b32 s0, s0, s1
-; DAGISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; DAGISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-GFX12-NEXT: s_cmp_eq_u32 s0, 0
; DAGISEL-GFX12-NEXT: s_cselect_b32 s0, -1, 0
-; DAGISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; DAGISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; DAGISEL-GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -243,15 +243,15 @@ define i1 @workgroup_zero() {
; GISEL-GFX12-NEXT: s_wait_bvhcnt 0x0
; GISEL-GFX12-NEXT: s_wait_kmcnt 0x0
; GISEL-GFX12-NEXT: s_and_b32 s0, ttmp7, 0xffff
-; GISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; GISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX12-NEXT: s_lshr_b32 s1, ttmp7, 16
; GISEL-GFX12-NEXT: s_or_b32 s0, ttmp9, s0
-; GISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; GISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX12-NEXT: s_or_b32 s0, s0, s1
-; GISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; GISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX12-NEXT: s_cmp_eq_u32 s0, 0
; GISEL-GFX12-NEXT: s_cselect_b32 s0, 1, 0
-; GISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; GISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX12-NEXT: v_mov_b32_e32 v0, s0
; GISEL-GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -292,13 +292,13 @@ define i1 @workgroup_nonzero() {
; DAGISEL-GFX12-NEXT: s_wait_bvhcnt 0x0
; DAGISEL-GFX12-NEXT: s_wait_kmcnt 0x0
; DAGISEL-GFX12-NEXT: s_and_b32 s0, ttmp7, 0xffff
-; DAGISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; DAGISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-GFX12-NEXT: s_lshr_b32 s1, ttmp7, 16
; DAGISEL-GFX12-NEXT: s_or_b32 s0, ttmp9, s0
-; DAGISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; DAGISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-GFX12-NEXT: s_or_b32 s0, s0, s1
; DAGISEL-GFX12-NEXT: s_cselect_b32 s0, -1, 0
-; DAGISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; DAGISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; DAGISEL-GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -328,13 +328,13 @@ define i1 @workgroup_nonzero() {
; GISEL-GFX12-NEXT: s_wait_bvhcnt 0x0
; GISEL-GFX12-NEXT: s_wait_kmcnt 0x0
; GISEL-GFX12-NEXT: s_and_b32 s0, ttmp7, 0xffff
-; GISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; GISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX12-NEXT: s_lshr_b32 s1, ttmp7, 16
; GISEL-GFX12-NEXT: s_or_b32 s0, ttmp9, s0
-; GISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; GISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX12-NEXT: s_or_b32 s0, s0, s1
; GISEL-GFX12-NEXT: s_cselect_b32 s0, 1, 0
-; GISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; GISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX12-NEXT: v_mov_b32_e32 v0, s0
; GISEL-GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -385,16 +385,16 @@ define i1 @workitem_workgroup_zero() {
; GFX12-NEXT: s_and_b32 s0, ttmp7, 0xffff
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v31
; GFX12-NEXT: v_bfe_u32 v1, v31, 10, 10
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_lshr_b32 s1, ttmp7, 16
; GFX12-NEXT: s_or_b32 s0, ttmp9, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_or_b32 s0, s0, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_or3_b32 v0, s0, v0, v1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -454,17 +454,17 @@ define i1 @workitem_workgroup_nonzero() {
; DAGISEL-GFX12-NEXT: s_wait_kmcnt 0x0
; DAGISEL-GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v31
; DAGISEL-GFX12-NEXT: s_and_b32 s0, ttmp7, 0xffff
-; DAGISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; DAGISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-GFX12-NEXT: s_lshr_b32 s1, ttmp7, 16
; DAGISEL-GFX12-NEXT: s_or_b32 s0, ttmp9, s0
; DAGISEL-GFX12-NEXT: v_bfe_u32 v1, v31, 20, 10
; DAGISEL-GFX12-NEXT: v_bfe_u32 v2, v31, 10, 10
-; DAGISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; DAGISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL-GFX12-NEXT: v_or3_b32 v0, s0, s1, v0
; DAGISEL-GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; DAGISEL-GFX12-NEXT: v_or3_b32 v0, v0, v2, v1
; DAGISEL-GFX12-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; DAGISEL-GFX12-NEXT: s_wait_alu 0xfffd
+; DAGISEL-GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; DAGISEL-GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; DAGISEL-GFX12-NEXT: s_setpc_b64 s[30:31]
;
@@ -491,19 +491,19 @@ define i1 @workitem_workgroup_nonzero() {
; GISEL-GFX12-NEXT: s_wait_bvhcnt 0x0
; GISEL-GFX12-NEXT: s_wait_kmcnt 0x0
; GISEL-GFX12-NEXT: s_and_b32 s0, ttmp7, 0xffff
-; GISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; GISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX12-NEXT: s_lshr_b32 s1, ttmp7, 16
; GISEL-GFX12-NEXT: s_or_b32 s0, ttmp9, s0
; GISEL-GFX12-NEXT: v_bfe_u32 v0, v31, 10, 10
-; GISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; GISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX12-NEXT: s_or_b32 s0, s0, s1
; GISEL-GFX12-NEXT: v_bfe_u32 v1, v31, 20, 10
-; GISEL-GFX12-NEXT: s_wait_alu 0xfffe
+; GISEL-GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX12-NEXT: v_and_or_b32 v2, 0x3ff, v31, s0
; GISEL-GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GISEL-GFX12-NEXT: v_or3_b32 v0, v2, v0, v1
; GISEL-GFX12-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GISEL-GFX12-NEXT: s_wait_alu 0xfffd
+; GISEL-GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GISEL-GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GISEL-GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
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