[llvm] [AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu (PR #169378)

[Carl Ritson via llvm-commits]

perlfu wrote:

 > We could but that would break SP3 compatibility in the sense that e.g. `s_waitcnt_depctr depctr_va_vdst(0)` would start assembling to BFA30FFF instead of BFA30F9F.

OK, sorry, I see what you mean. Other SP3 tooling is expecting reserve bits to be 0.

https://github.com/llvm/llvm-project/pull/169378