[llvm] [VPlan] Improve code in VPInstruction::generate (NFC) (PR #169470)

[David Sherwood via llvm-commits]

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@@ -900,7 +897,7 @@ Value *VPInstruction::generate(VPTransformState &State) {
     // each part of the reduction.
     unsigned UF = getNumOperands() - 1;
     VectorParts RdxParts(UF);
-    for (unsigned Part = 0; Part < UF; ++Part)
+    for (unsigned Part : seq<unsigned>(UF))
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david-arm wrote:

Is this part of a plan to change all code in the loop vectoriser/plan to use seq? I imagine there are 100s of examples and it will start to look inconsistent if we use different styles throughout LV. @fhahn any thoughts?

I wonder if it's worth committing these changes separately?

https://github.com/llvm/llvm-project/pull/169470