[llvm] Use umin for x != 0 when +cssc is enabled (PR #169159)

[Benjamin Maxwell via llvm-commits]

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@@ -26417,6 +26418,12 @@ static SDValue performSETCCCombine(SDNode *N,
       return DAG.getNode(ISD::SETCC, DL, VT, TST, RHS, N->getOperand(2));
     }
   }
+  if (Subtarget->hasCSSC() && Cond == ISD::SETNE && isNullConstant(RHS) &&
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MacDue wrote:

After ` AfterLegalizeTypes` would be fine too (only i32 and i64 should be legal then). This the above generated at that stage? When I tested locally, replacing `SETCC` with `UMIN` before type legalization seemed not the improve the codegen. 

https://github.com/llvm/llvm-project/pull/169159