[llvm] [RISCV][ISelLowering] Use Zicond for FP selects on Zfinx/Zdinx (PR #169299)

[via llvm-commits]

fennecJ wrote:

I have updated the selection logic to skip cases requiring register splitting (e.g., f64 on RV32).

Consequently, the output for select_f64_fcmp
```asm
define double @select_f64_fcmp(double %a, double %b, double %c, double %d) nounwind {
entry:
  %cmp = fcmp ogt double %a, %b
  %sel = select i1 %cmp, double %c, double %d
  ret double %sel
}
```
is now identical for both `RV32ZDINX_ZICOND` and `RV32ZDINX_NOZICOND`:

```asm
; RV32ZDINX_ZICOND-LABEL: select_f64_fcmp:
; RV32ZDINX_ZICOND:       # %bb.0: # %entry
; RV32ZDINX_ZICOND-NEXT:    flt.d a0, a2, a0
; RV32ZDINX_ZICOND-NEXT:    bnez a0, .LBB2_2
; RV32ZDINX_ZICOND-NEXT:  # %bb.1: # %entry
; RV32ZDINX_ZICOND-NEXT:    mv a4, a6
; RV32ZDINX_ZICOND-NEXT:    mv a5, a7
; RV32ZDINX_ZICOND-NEXT:  .LBB2_2: # %entry
; RV32ZDINX_ZICOND-NEXT:    mv a0, a4
; RV32ZDINX_ZICOND-NEXT:    mv a1, a5
; RV32ZDINX_ZICOND-NEXT:    ret
;
; RV32ZDINX_NOZICOND-LABEL: select_f64_fcmp:
; RV32ZDINX_NOZICOND:       # %bb.0: # %entry
; RV32ZDINX_NOZICOND-NEXT:    flt.d a0, a2, a0
; RV32ZDINX_NOZICOND-NEXT:    bnez a0, .LBB2_2
; RV32ZDINX_NOZICOND-NEXT:  # %bb.1: # %entry
; RV32ZDINX_NOZICOND-NEXT:    mv a4, a6
; RV32ZDINX_NOZICOND-NEXT:    mv a5, a7
; RV32ZDINX_NOZICOND-NEXT:  .LBB2_2: # %entry
; RV32ZDINX_NOZICOND-NEXT:    mv a0, a4
; RV32ZDINX_NOZICOND-NEXT:    mv a1, a5
; RV32ZDINX_NOZICOND-NEXT:    ret
```
Note: For `RV32ZFINX_ZICOND`, the czero instructions seem to be pre-existing/unrelated, as they remain even if I remove the whole FP ISel logic.

```
; RV32ZFINX_ZICOND-LABEL: select_f64_fcmp:
; RV32ZFINX_ZICOND:       # %bb.0: # %entry
; RV32ZFINX_ZICOND-NEXT:    addi sp, sp, -32
; RV32ZFINX_ZICOND-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
; RV32ZFINX_ZICOND-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
; RV32ZFINX_ZICOND-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
; RV32ZFINX_ZICOND-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
; RV32ZFINX_ZICOND-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
; RV32ZFINX_ZICOND-NEXT:    mv s0, a7
; RV32ZFINX_ZICOND-NEXT:    mv s1, a6
; RV32ZFINX_ZICOND-NEXT:    mv s2, a5
; RV32ZFINX_ZICOND-NEXT:    mv s3, a4
; RV32ZFINX_ZICOND-NEXT:    call __gtdf2
; RV32ZFINX_ZICOND-NEXT:    sgtz a0, a0
; RV32ZFINX_ZICOND-NEXT:    czero.nez a1, s1, a0
; RV32ZFINX_ZICOND-NEXT:    czero.eqz a2, s3, a0
; RV32ZFINX_ZICOND-NEXT:    czero.nez a3, s0, a0
; RV32ZFINX_ZICOND-NEXT:    czero.eqz a4, s2, a0
; RV32ZFINX_ZICOND-NEXT:    or a0, a2, a1
; RV32ZFINX_ZICOND-NEXT:    or a1, a4, a3
; RV32ZFINX_ZICOND-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
; RV32ZFINX_ZICOND-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
; RV32ZFINX_ZICOND-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
; RV32ZFINX_ZICOND-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
; RV32ZFINX_ZICOND-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
; RV32ZFINX_ZICOND-NEXT:    addi sp, sp, 32
; RV32ZFINX_ZICOND-NEXT:    ret
```

https://github.com/llvm/llvm-project/pull/169299