[llvm] [RISCV] Propagate SDNode flags when combining `(fmul (fneg X), ...)` (PR #169460)

[Min-Yih Hsu via llvm-commits]

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mshockwave wrote:

context: the issue was originally found in 470.lbm, from which this test was reduced.
The reason this test looks so big and weird in some sense was because the flaw (i.e. missing SDNode flags) can only be revealed when a specific set of FMA DAG combiner patterns were _skipped_ due to hitting some recursion limits.  And this test is written in a way to hit that limit. I have spend lots of time trying other ways to test this but to no avail. An alternative could be directly checking the fast math flags in the SelectionDAG dump but I don't think that's a better idea.

https://github.com/llvm/llvm-project/pull/169460