[llvm] [AMX][NFC] Organize tilerow (PR #168193)
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Mon Nov 24 21:17:58 PST 2025
https://github.com/mahesh-attarde updated https://github.com/llvm/llvm-project/pull/168193
>From 87f0adbcde4dd8cbcc6b2fa3e6689233d16c8d7e Mon Sep 17 00:00:00 2001
From: mattarde <mattarde at intel.com>
Date: Sat, 15 Nov 2025 02:12:14 -0800
Subject: [PATCH 1/4] [AMX][NFC] Organize tilerow
---
llvm/lib/Target/X86/X86ExpandPseudo.cpp | 4 ++--
llvm/lib/Target/X86/X86ISelLowering.cpp | 4 ++--
llvm/lib/Target/X86/X86InstrAMX.td | 16 ++++++++--------
.../MIR2Vec/Inputs/reference_x86_vocab_print.txt | 4 ++--
4 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ExpandPseudo.cpp b/llvm/lib/Target/X86/X86ExpandPseudo.cpp
index e3c44c048f7bf..0bccbe7f9c927 100644
--- a/llvm/lib/Target/X86/X86ExpandPseudo.cpp
+++ b/llvm/lib/Target/X86/X86ExpandPseudo.cpp
@@ -638,10 +638,10 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
Opc = X86::TCVTROWPS2PHLrri;
break;
case X86::PTILEMOVROWrreV:
- Opc = X86::TILEMOVROWrre;
+ Opc = X86::TILEMOVROWrte;
break;
case X86::PTILEMOVROWrriV:
- Opc = X86::TILEMOVROWrri;
+ Opc = X86::TILEMOVROWrti;
break;
default:
llvm_unreachable("Unexpected Opcode");
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index dc84025c166a3..017470908ae55 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -38316,7 +38316,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
Opc = X86::TCVTROWPS2PHLrri;
break;
case X86::PTILEMOVROWrri:
- Opc = X86::TILEMOVROWrri;
+ Opc = X86::TILEMOVROWrti;
break;
}
MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, TII->get(Opc));
@@ -38354,7 +38354,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
Opc = X86::TCVTROWPS2PHLrre;
break;
case X86::PTILEMOVROWrre:
- Opc = X86::TILEMOVROWrre;
+ Opc = X86::TILEMOVROWrte;
break;
}
MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, TII->get(Opc));
diff --git a/llvm/lib/Target/X86/X86InstrAMX.td b/llvm/lib/Target/X86/X86InstrAMX.td
index 522782abd710f..cd3f1fa012f9c 100644
--- a/llvm/lib/Target/X86/X86InstrAMX.td
+++ b/llvm/lib/Target/X86/X86InstrAMX.td
@@ -475,22 +475,22 @@ defm TCVTROWPS2PHL : AMXAVX512_BASE<0x6d, 0x77, "tcvtrowps2phl", PD, XD>;
defm TCVTROWPS2BF16H : AMXAVX512_BASE<0x6d, 0x07, "tcvtrowps2bf16h", XD, XD>;
defm TCVTROWPS2BF16L : AMXAVX512_BASE<0x6d, 0x77, "tcvtrowps2bf16l", XS, XS>;
-multiclass m_tilemovrow {
+multiclass AMXAVX512_TILEMOVE<bits<8> Opcode1, bits<8> Opcode2, string Opstr> {
let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode] in {
let SchedRW = [WriteSystem] in {
- def rri : Ii8<0x7, MRMSrcReg, (outs VR512:$dst),
+ def rti : Ii8<0x7, MRMSrcReg, (outs VR512:$dst),
(ins TILE:$src1, u8imm:$src2),
- "tilemovrow\t{$src2, $src1, $dst|$dst, $src1, $src2}",
- []>, TA,PD, EVEX, EVEX_V512;
- def rre : I<0x4A, MRMSrcReg4VOp3, (outs VR512:$dst),
+ !strconcat(Opstr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ []>, TA, PD, EVEX, EVEX_V512;
+ def rte : I<0x4A, MRMSrcReg4VOp3, (outs VR512:$dst),
(ins TILE:$src1, GR32:$src2),
- "tilemovrow\t{$src2, $src1, $dst|$dst, $src1, $src2}",
- []>, T8,PD, EVEX, VVVV, EVEX_V512;
+ !strconcat(Opstr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ []>, T8, PD, EVEX, VVVV, EVEX_V512;
}
} // HasAMXAVX512, HasAVX10_2, In64BitMode
}
-defm TILEMOVROW : m_tilemovrow;
+defm TILEMOVROW : AMXAVX512_TILEMOVE<0x07, 0x4A, "tilemovrow">;
let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode] in {
let SchedRW = [WriteSystem] in {
diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
index bd26938c93cb7..74ef1e608d4ba 100644
--- a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
+++ b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
@@ -1737,8 +1737,8 @@ Key: TILELOADDRST: [ 0.00 0.00 ]
Key: TILELOADDRS_EVEX: [ 0.00 0.00 ]
Key: TILELOADDT: [ 0.00 0.00 ]
Key: TILELOADD_EVEX: [ 0.00 0.00 ]
-Key: TILEMOVROWrre: [ 0.00 0.00 ]
-Key: TILEMOVROWrri: [ 0.00 0.00 ]
+Key: TILEMOVROWrte: [ 0.00 0.00 ]
+Key: TILEMOVROWrti: [ 0.00 0.00 ]
Key: TILERELEASE: [ 0.00 0.00 ]
Key: TILESTORED: [ 0.00 0.00 ]
Key: TILESTORED_EVEX: [ 0.00 0.00 ]
>From 163a0b2676d12fcca83bac58afaccfe4a9e83b46 Mon Sep 17 00:00:00 2001
From: mattarde <mattarde at intel.com>
Date: Sat, 15 Nov 2025 03:34:29 -0800
Subject: [PATCH 2/4] fix mir2vec
---
.../MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
index a3810c19e584a..1ba4f13e69c92 100644
--- a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
+++ b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
@@ -1737,8 +1737,8 @@ Key: TILELOADDRST: [ 0.00 0.00 ]
Key: TILELOADDRS_EVEX: [ 0.00 0.00 ]
Key: TILELOADDT: [ 0.00 0.00 ]
Key: TILELOADD_EVEX: [ 0.00 0.00 ]
-Key: TILEMOVROWrre: [ 0.00 0.00 ]
-Key: TILEMOVROWrri: [ 0.00 0.00 ]
+Key: TILEMOVROWrte: [ 0.00 0.00 ]
+Key: TILEMOVROWrti: [ 0.00 0.00 ]
Key: TILERELEASE: [ 0.00 0.00 ]
Key: TILESTORED: [ 0.00 0.00 ]
Key: TILESTORED_EVEX: [ 0.00 0.00 ]
>From 42072df7010fcc7328a2d1a30811e21dfa4909e4 Mon Sep 17 00:00:00 2001
From: mattarde <mattarde at intel.com>
Date: Mon, 24 Nov 2025 04:40:49 -0800
Subject: [PATCH 3/4] fix naming convention for real amx instr with mix of
avx512 and amx reg
---
llvm/lib/Target/X86/X86ExpandPseudo.cpp | 20 ++++++++++----------
llvm/lib/Target/X86/X86ISelLowering.cpp | 20 ++++++++++----------
llvm/lib/Target/X86/X86InstrAMX.td | 8 ++++----
3 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ExpandPseudo.cpp b/llvm/lib/Target/X86/X86ExpandPseudo.cpp
index 0bccbe7f9c927..6a18086cae29f 100644
--- a/llvm/lib/Target/X86/X86ExpandPseudo.cpp
+++ b/llvm/lib/Target/X86/X86ExpandPseudo.cpp
@@ -608,34 +608,34 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
Opc = GET_EGPR_IF_ENABLED(X86::TILELOADDT1);
break;
case X86::PTCVTROWD2PSrreV:
- Opc = X86::TCVTROWD2PSrre;
+ Opc = X86::TCVTROWD2PSrte;
break;
case X86::PTCVTROWD2PSrriV:
- Opc = X86::TCVTROWD2PSrri;
+ Opc = X86::TCVTROWD2PSrti;
break;
case X86::PTCVTROWPS2BF16HrreV:
- Opc = X86::TCVTROWPS2BF16Hrre;
+ Opc = X86::TCVTROWPS2BF16Hrte;
break;
case X86::PTCVTROWPS2BF16HrriV:
- Opc = X86::TCVTROWPS2BF16Hrri;
+ Opc = X86::TCVTROWPS2BF16Hrti;
break;
case X86::PTCVTROWPS2BF16LrreV:
- Opc = X86::TCVTROWPS2BF16Lrre;
+ Opc = X86::TCVTROWPS2BF16Lrte;
break;
case X86::PTCVTROWPS2BF16LrriV:
- Opc = X86::TCVTROWPS2BF16Lrri;
+ Opc = X86::TCVTROWPS2BF16Lrti;
break;
case X86::PTCVTROWPS2PHHrreV:
- Opc = X86::TCVTROWPS2PHHrre;
+ Opc = X86::TCVTROWPS2PHHrte;
break;
case X86::PTCVTROWPS2PHHrriV:
- Opc = X86::TCVTROWPS2PHHrri;
+ Opc = X86::TCVTROWPS2PHHrti;
break;
case X86::PTCVTROWPS2PHLrreV:
- Opc = X86::TCVTROWPS2PHLrre;
+ Opc = X86::TCVTROWPS2PHLrte;
break;
case X86::PTCVTROWPS2PHLrriV:
- Opc = X86::TCVTROWPS2PHLrri;
+ Opc = X86::TCVTROWPS2PHLrti;
break;
case X86::PTILEMOVROWrreV:
Opc = X86::TILEMOVROWrte;
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 017470908ae55..0920724da2e44 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -38301,19 +38301,19 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
default:
llvm_unreachable("Unexpected instruction!");
case X86::PTCVTROWD2PSrri:
- Opc = X86::TCVTROWD2PSrri;
+ Opc = X86::TCVTROWD2PSrti;
break;
case X86::PTCVTROWPS2BF16Hrri:
- Opc = X86::TCVTROWPS2BF16Hrri;
+ Opc = X86::TCVTROWPS2BF16Hrti;
break;
case X86::PTCVTROWPS2PHHrri:
- Opc = X86::TCVTROWPS2PHHrri;
+ Opc = X86::TCVTROWPS2PHHrti;
break;
case X86::PTCVTROWPS2BF16Lrri:
- Opc = X86::TCVTROWPS2BF16Lrri;
+ Opc = X86::TCVTROWPS2BF16Lrti;
break;
case X86::PTCVTROWPS2PHLrri:
- Opc = X86::TCVTROWPS2PHLrri;
+ Opc = X86::TCVTROWPS2PHLrti;
break;
case X86::PTILEMOVROWrri:
Opc = X86::TILEMOVROWrti;
@@ -38339,19 +38339,19 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
default:
llvm_unreachable("Unexpected instruction!");
case X86::PTCVTROWD2PSrre:
- Opc = X86::TCVTROWD2PSrre;
+ Opc = X86::TCVTROWD2PSrte;
break;
case X86::PTCVTROWPS2BF16Hrre:
- Opc = X86::TCVTROWPS2BF16Hrre;
+ Opc = X86::TCVTROWPS2BF16Hrte;
break;
case X86::PTCVTROWPS2BF16Lrre:
- Opc = X86::TCVTROWPS2BF16Lrre;
+ Opc = X86::TCVTROWPS2BF16Lrte;
break;
case X86::PTCVTROWPS2PHHrre:
- Opc = X86::TCVTROWPS2PHHrre;
+ Opc = X86::TCVTROWPS2PHHrte;
break;
case X86::PTCVTROWPS2PHLrre:
- Opc = X86::TCVTROWPS2PHLrre;
+ Opc = X86::TCVTROWPS2PHLrte;
break;
case X86::PTILEMOVROWrre:
Opc = X86::TILEMOVROWrte;
diff --git a/llvm/lib/Target/X86/X86InstrAMX.td b/llvm/lib/Target/X86/X86InstrAMX.td
index cd3f1fa012f9c..eaa762acc2940 100644
--- a/llvm/lib/Target/X86/X86InstrAMX.td
+++ b/llvm/lib/Target/X86/X86InstrAMX.td
@@ -370,11 +370,11 @@ let Predicates = [HasAMXMOVRS, In64BitMode], SchedRW = [WriteSystem] in {
multiclass m_tcvtrowd2ps {
let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode] in {
let SchedRW = [WriteSystem] in {
- def rri : Ii8<0x7, MRMSrcReg, (outs VR512:$dst),
+ def rti : Ii8<0x7, MRMSrcReg, (outs VR512:$dst),
(ins TILE:$src1, i32u8imm:$src2),
"tcvtrowd2ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
[]>, TA,XS, EVEX, EVEX_V512;
- def rre : I<0x4A, MRMSrcReg4VOp3, (outs VR512:$dst),
+ def rte : I<0x4A, MRMSrcReg4VOp3, (outs VR512:$dst),
(ins TILE:$src1, GR32:$src2),
"tcvtrowd2ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
[]>, T8,XS, EVEX, VVVV, EVEX_V512;
@@ -450,12 +450,12 @@ multiclass AMXAVX512_BASE<bits<8> Opcode1, bits<8> Opcode2, string Opstr,
Prefix P1, Prefix P2> {
let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode], SchedRW = [WriteSystem] in {
let OpPrefix = P1 in
- def rre : I<Opcode1, MRMSrcReg4VOp3, (outs VR512:$dst),
+ def rte : I<Opcode1, MRMSrcReg4VOp3, (outs VR512:$dst),
(ins TILE:$src1, GR32:$src2),
!strconcat(Opstr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[]>, EVEX, VVVV, EVEX_V512, T8;
let OpPrefix = P2 in
- def rri : Ii8<Opcode2, MRMSrcReg, (outs VR512:$dst),
+ def rti : Ii8<Opcode2, MRMSrcReg, (outs VR512:$dst),
(ins TILE:$src1, i32u8imm:$src2),
!strconcat(Opstr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[]>, EVEX, EVEX_V512, TA;
>From 93bf5f41a33453a4f8675651347d962b44b9da07 Mon Sep 17 00:00:00 2001
From: "Attarde, Mahesh" <mahesh.attarde at intel.com>
Date: Mon, 24 Nov 2025 21:14:43 -0800
Subject: [PATCH 4/4] review comments for opcode
---
llvm/lib/Target/X86/X86InstrAMX.td | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/X86/X86InstrAMX.td b/llvm/lib/Target/X86/X86InstrAMX.td
index eaa762acc2940..6b8b8f720ddd7 100644
--- a/llvm/lib/Target/X86/X86InstrAMX.td
+++ b/llvm/lib/Target/X86/X86InstrAMX.td
@@ -478,11 +478,11 @@ defm TCVTROWPS2BF16L : AMXAVX512_BASE<0x6d, 0x77, "tcvtrowps2bf16l", XS, XS>;
multiclass AMXAVX512_TILEMOVE<bits<8> Opcode1, bits<8> Opcode2, string Opstr> {
let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode] in {
let SchedRW = [WriteSystem] in {
- def rti : Ii8<0x7, MRMSrcReg, (outs VR512:$dst),
+ def rti : Ii8<Opcode1, MRMSrcReg, (outs VR512:$dst),
(ins TILE:$src1, u8imm:$src2),
!strconcat(Opstr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[]>, TA, PD, EVEX, EVEX_V512;
- def rte : I<0x4A, MRMSrcReg4VOp3, (outs VR512:$dst),
+ def rte : I<Opcode2, MRMSrcReg4VOp3, (outs VR512:$dst),
(ins TILE:$src1, GR32:$src2),
!strconcat(Opstr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[]>, T8, PD, EVEX, VVVV, EVEX_V512;
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