[llvm] [RISCV][ISelLowering] Use Zicond for FP selects on Zfinx/Zdinx (PR #169299)

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fennecJ wrote:

> Please can you add an rv32zdinx RUN line? It would be useful to see if/how this works for 64-bit values with that combination.

Thanks for the suggestion! It was actually very helpful because adding the rv32zdinx RUN line revealed a crash when handling f64 values on RV32.

I've updated the implementation to handle f64 on 32-bit targets by splitting it into two 32-bit integer selects. The RUN line has been added and verifies the fix. 


However, I have a concern regarding the performance cost for this specific case: While the static code size difference is negligible (7 vs 8 instructions), the dynamic instruction count is a regression.  

Branch version: Executes 5 or 7 instructions  
```asm
; RV32ZDINX_NOZICOND-LABEL: select_f64_fcmp:
; RV32ZDINX_NOZICOND:       # %bb.0: # %entry
; RV32ZDINX_NOZICOND-NEXT:    flt.d a0, a2, a0
; RV32ZDINX_NOZICOND-NEXT:    bnez a0, .LBB2_2
; RV32ZDINX_NOZICOND-NEXT:  # %bb.1: # %entry
; RV32ZDINX_NOZICOND-NEXT:    mv a4, a6
; RV32ZDINX_NOZICOND-NEXT:    mv a5, a7
; RV32ZDINX_NOZICOND-NEXT:  .LBB2_2: # %entry
; RV32ZDINX_NOZICOND-NEXT:    mv a0, a4
; RV32ZDINX_NOZICOND-NEXT:    mv a1, a5
; RV32ZDINX_NOZICOND-NEXT:    ret
```

Zicond version: Always executes 8 instructions.  
```asm
; RV32ZDINX_ZICOND-LABEL: select_f64_fcmp:
; RV32ZDINX_ZICOND:       # %bb.0: # %entry
; RV32ZDINX_ZICOND-NEXT:    flt.d a0, a2, a0
; RV32ZDINX_ZICOND-NEXT:    czero.nez a1, a6, a0
; RV32ZDINX_ZICOND-NEXT:    czero.eqz a2, a4, a0
; RV32ZDINX_ZICOND-NEXT:    czero.nez a3, a7, a0
; RV32ZDINX_ZICOND-NEXT:    czero.eqz a4, a5, a0
; RV32ZDINX_ZICOND-NEXT:    or a0, a2, a1
; RV32ZDINX_ZICOND-NEXT:    or a1, a4, a3
; RV32ZDINX_ZICOND-NEXT:    ret
```
Should we still prefer the Zicond transformation here, or should I disable it for f64 on RV32?

https://github.com/llvm/llvm-project/pull/169299