[llvm] 26362c6 - [RISCV] Add segmented tunes to tt-ascalon-d8 (#168800)

[via llvm-commits]

Author: Petr Penzin
Date: 2025-11-24T19:50:48-08:00
New Revision: 26362c68579dd4375198aae4651b4d5f8a36c715

URL: https://github.com/llvm/llvm-project/commit/26362c68579dd4375198aae4651b4d5f8a36c715
DIFF: https://github.com/llvm/llvm-project/commit/26362c68579dd4375198aae4651b4d5f8a36c715.diff

LOG: [RISCV] Add segmented tunes to tt-ascalon-d8 (#168800)

Add TuneOptimizedNFnSegmentedLoadStore tune flags to tt-ascalon-d8
processor definition.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVProcessors.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index e86431f78f1ba..07f6a38c77897 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -633,6 +633,13 @@ def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8",
                                                   FeatureUnalignedVectorMem]),
                                                  [TuneNoDefaultUnroll,
                                                   TuneNLogNVRGather,
+                                                  TuneOptimizedNF2SegmentLoadStore,
+                                                  TuneOptimizedNF3SegmentLoadStore,
+                                                  TuneOptimizedNF4SegmentLoadStore,
+                                                  TuneOptimizedNF5SegmentLoadStore,
+                                                  TuneOptimizedNF6SegmentLoadStore,
+                                                  TuneOptimizedNF7SegmentLoadStore,
+                                                  TuneOptimizedNF8SegmentLoadStore,
                                                   TuneOptimizedZeroStrideLoad,
                                                   TunePostRAScheduler]>;