[llvm] f581d8a - AMDGPU: Fix a comment (#169403)

[via llvm-commits]

Author: Nicolai Hähnle
Date: 2025-11-24T20:54:53Z
New Revision: f581d8ad8f0cd08da6465c6843f9c6841d49e522

URL: https://github.com/llvm/llvm-project/commit/f581d8ad8f0cd08da6465c6843f9c6841d49e522
DIFF: https://github.com/llvm/llvm-project/commit/f581d8ad8f0cd08da6465c6843f9c6841d49e522.diff

LOG: AMDGPU: Fix a comment (#169403)

This verifier check will complain if there aren't enough implicit
operands -- so it doesn't *allow* those operands, it *requires* them.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index a7333e3373f38..7504452dc777f 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5518,9 +5518,10 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
         Desc.getNumOperands() + Desc.implicit_uses().size();
     const unsigned NumImplicitOps = IsDst ? 2 : 1;
 
-    // Allow additional implicit operands. This allows a fixup done by the post
-    // RA scheduler where the main implicit operand is killed and implicit-defs
-    // are added for sub-registers that remain live after this instruction.
+    // Require additional implicit operands. This allows a fixup done by the
+    // post RA scheduler where the main implicit operand is killed and
+    // implicit-defs are added for sub-registers that remain live after this
+    // instruction.
     if (MI.getNumOperands() < StaticNumOps + NumImplicitOps) {
       ErrInfo = "missing implicit register operands";
       return false;