[llvm] [DAG][X86] Improve custom i256/i512 AVX512 CTLZ/CTTZ Handling with MVT::i256/i512 (PR #168860)

[Craig Topper via llvm-commits]

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@@ -8,13 +8,13 @@
 // CHECK-NEXT:/*     3*/ OPC_CheckChild0Integer, [[#]],
 // CHECK-NEXT:/*     5*/ OPC_RecordChild1, // #0 = $src
 // CHECK-NEXT:/*     6*/ OPC_Scope, 9, /*->17*/ // 2 children in Scope
-// CHECK-NEXT:/*     8*/  OPC_CheckChild1Type, /*MVT::c64*/126|128,1/*254*/,
+// CHECK-NEXT:/*     8*/  OPC_CheckChild1Type, /*MVT::c64*/0|128,2/*256*/,
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topperc wrote:

Yes, that looks right. Each byte contains 7 bits, the msb is used to indicate if another byte exists for the next 7 bits. This is `(0 | 2 << 7)` which is 256. Previously it was `(126 | 1 << 7)` which is 254

https://github.com/llvm/llvm-project/pull/168860