[llvm] [AArch64][SVE] Add basic support for `@llvm.masked.compressstore` (PR #168350)

[Benjamin Maxwell via llvm-commits]

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@@ -332,6 +332,48 @@ class AArch64TTIImpl final : public BasicTTIImplBase<AArch64TTIImpl> {
     return isLegalMaskedLoadStore(DataType, Alignment);
   }
 
+  bool isElementTypeLegalForCompressStore(Type *Ty) const {
+    if (Ty->isFloatTy() || Ty->isDoubleTy())
+      return true;
+
+    if (Ty->isIntegerTy(8) || Ty->isIntegerTy(16) || Ty->isIntegerTy(32) ||
+        Ty->isIntegerTy(64))
+      return true;
+
+    return false;
+  }
+
+  bool isLegalMaskedCompressStore(Type *DataType,
+                                  Align Alignment) const override {
+    auto VecTy = cast<VectorType>(DataType);
+    Type *ElTy = VecTy->getScalarType();
+    unsigned ElSizeInBits = ElTy->getScalarSizeInBits();
+    TypeSize VecSizeInBits = VecTy->getPrimitiveSizeInBits();
+
+    if (isa<FixedVectorType>(VecTy)) {
+      // Each 128-bit segment must contain 2 or 4 elements (packed).
+      if (ElSizeInBits != 32 && ElSizeInBits != 64)
+        return false;
+      if (VecSizeInBits % 128 != 0 ||
+          VecSizeInBits > std::max(128U, ST->getMinSVEVectorSizeInBits()))
+        return false;
+    } else {
+      // Each segment must contain 2 or 4 elements, but the segments can be
+      // < 128-bits for unpacked vector types.
----------------
MacDue wrote:

I've removed this (and simplified the implementation). Currently, this is only used to decide if we should expand the intrinsic pre-ISEL, but that is only attempted for fixed-length vectors, so currently there's no need to add a check many SVE cases here. 

I've now limited this to only allow supported 32/64-bit types, and splitting is supported. 

https://github.com/llvm/llvm-project/pull/168350