[llvm] [AArch64] Combine vector FNEG+FMA into `FNML[A|S]` (PR #167900)

[Benjamin Maxwell via llvm-commits]

================
@@ -20692,6 +20694,58 @@ static SDValue performFADDCombine(SDNode *N,
   return SDValue();
 }
 
+static SDValue performFMACombine(SDNode *N,
+                                 TargetLowering::DAGCombinerInfo &DCI,
+                                 const AArch64Subtarget *Subtarget) {
+  SelectionDAG &DAG = DCI.DAG;
+  SDValue OpA = N->getOperand(0);
+  SDValue OpB = N->getOperand(1);
+  SDValue OpC = N->getOperand(2);
+  EVT VT = N->getValueType(0);
+  SDLoc DL(N);
+
+  // Convert FMA/FNEG nodes to SVE to enable the following patterns:
+  // fma(a, b, neg(c)) -> fnmls(a, b, c)
+  // fma(neg(a), b, neg(c)) -> fnmla(a, b, c)
+  // fma(a, neg(b), neg(c)) -> fnmla(a, b, c)
+  if (!VT.isVector() || !DAG.getTargetLoweringInfo().isTypeLegal(VT) ||
+      !Subtarget->isSVEorStreamingSVEAvailable() ||
+      OpC.getOpcode() != ISD::FNEG) {
+    return SDValue();
+  }
+
+  SDValue Pg = getPredicateForVector(DAG, DL, VT);
+  EVT ContainerVT =
+      VT.isFixedLengthVector() ? getContainerForFixedLengthVector(DAG, VT) : VT;
----------------
MacDue wrote:

Could this combine be simplified by only handling fixed-length vectors (i.e. bail out if `!VT.isFixedLengthVector()`). We could add extra tablegen patterns for any SVE cases not covered by the existing patterns. 

https://github.com/llvm/llvm-project/pull/167900