[llvm] [VPlan] Set ZeroIsPoison=false for FirstActiveLane (PR #169298)

[Luke Lau via llvm-commits]

lukel97 wrote:

> where we were essentially relying upon a vector full of zero elements returning the element count? It's a problem because theoretically an IR pass could at some point detect that one of the vector is all-zeroes and replace the call with poison. The algorithm relies upon it returning the element count instead.

Yup, and actually on RISC-V this will miscompile today because when ZeroIsPoison=true it will get lowered to an instruction that just returns all ones. 

>  as most platforms generate the same code for both true/false and RISCV for which codegen is different doesn't interleave with tail-folding.

I think RISC-V will disable tail folding w/ a early exit loop. I guess we were just missing test coverage for early exit loops with interleaving on RISC-V? Or maybe something is preventing them from being selected in the cost model. 

https://github.com/llvm/llvm-project/pull/169298