[llvm] [AArch64][SVE] Add basic support for `@llvm.masked.compressstore` (PR #168350)

[Benjamin Maxwell via llvm-commits]

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@@ -30180,6 +30185,36 @@ SDValue AArch64TargetLowering::LowerFixedLengthVectorStoreToSVE(
                             Store->isTruncatingStore());
 }
 
+SDValue AArch64TargetLowering::LowerMSTORE(SDValue Op,
+                                           SelectionDAG &DAG) const {
+  SDLoc DL(Op);
+  auto *Store = cast<MaskedStoreSDNode>(Op);
+  EVT VT = Store->getValue().getValueType();
+  if (VT.isFixedLengthVector())
+    return LowerFixedLengthVectorMStoreToSVE(Op, DAG);
+
+  if (!Store->isCompressingStore())
+    return SDValue();
+
+  EVT MaskVT = Store->getMask().getValueType();
+
+  SDValue Zero = DAG.getConstant(0, DL, MVT::i64);
+  SDValue CntActive =
+      DAG.getNode(ISD::VECREDUCE_ADD, DL, MVT::i64, Store->getMask());
----------------
MacDue wrote:

> but can this be done as a target agnostic expansion?

I think it could, but the setup of the `MSTORE` ISD nodes is not great. It's one ISD node that covers a range of stores (including compressing), so it'd need some extra hooks in `TargetLowering` to determine the right operation action. 

https://github.com/llvm/llvm-project/pull/168350