[llvm] [VPlan] Set ZeroIsPoison=false for FirstActiveLane (PR #169298)

[Florian Hahn via llvm-commits]

https://github.com/fhahn approved this pull request.

LGTM, thanks.

As per https://github.com/llvm/llvm-project/pull/168738#discussion_r2549411124, this fixes an mis-compile when vectorizing early-exit loops + interleaving. It currently does not trigger in practice on most platforms, as most platforms generate the same code for both true/false and RISCV for which codegen is different doesn't interleave with tail-folding.

https://github.com/llvm/llvm-project/pull/169298